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r9a09g057.dtsi
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linux-6.19.14/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2H(P) SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g057"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&gic>; 16 17 audio_extal_clk: audio-clk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by the board */ 21 clock-frequency = <0>; 22 }; 23 24 /* 25 * The default cluster table is based on the assumption that the PLLCA55 clock 26 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 27 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 28 * clocked to 1.8GHz as well). The table below should be overridden in the board 29 * DTS based on the PLLCA55 clock frequency. 30 */ 31 cluster0_opp: opp-table-0 { 32 compatible = "operating-points-v2"; 33 34 opp-1700000000 { 35 opp-hz = /bits/ 64 <1700000000>; 36 opp-microvolt = <900000>; 37 clock-latency-ns = <300000>; 38 }; 39 opp-850000000 { 40 opp-hz = /bits/ 64 <850000000>; 41 opp-microvolt = <800000>; 42 clock-latency-ns = <300000>; 43 }; 44 opp-425000000 { 45 opp-hz = /bits/ 64 <425000000>; 46 opp-microvolt = <800000>; 47 clock-latency-ns = <300000>; 48 }; 49 opp-212500000 { 50 opp-hz = /bits/ 64 <212500000>; 51 opp-microvolt = <800000>; 52 clock-latency-ns = <300000>; 53 opp-suspend; 54 }; 55 }; 56 57 cpus { 58 #address-cells = <1>; 59 #size-cells = <0>; 60 61 cpu0: cpu@0 { 62 compatible = "arm,cortex-a55"; 63 reg = <0>; 64 device_type = "cpu"; 65 next-level-cache = <&L3_CA55>; 66 enable-method = "psci"; 67 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; 68 #cooling-cells = <2>; 69 operating-points-v2 = <&cluster0_opp>; 70 }; 71 72 cpu1: cpu@100 { 73 compatible = "arm,cortex-a55"; 74 reg = <0x100>; 75 device_type = "cpu"; 76 next-level-cache = <&L3_CA55>; 77 enable-method = "psci"; 78 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; 79 #cooling-cells = <2>; 80 operating-points-v2 = <&cluster0_opp>; 81 }; 82 83 cpu2: cpu@200 { 84 compatible = "arm,cortex-a55"; 85 reg = <0x200>; 86 device_type = "cpu"; 87 next-level-cache = <&L3_CA55>; 88 enable-method = "psci"; 89 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; 90 #cooling-cells = <2>; 91 operating-points-v2 = <&cluster0_opp>; 92 }; 93 94 cpu3: cpu@300 { 95 compatible = "arm,cortex-a55"; 96 reg = <0x300>; 97 device_type = "cpu"; 98 next-level-cache = <&L3_CA55>; 99 enable-method = "psci"; 100 clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; 101 #cooling-cells = <2>; 102 operating-points-v2 = <&cluster0_opp>; 103 }; 104 105 L3_CA55: cache-controller-0 { 106 compatible = "cache"; 107 cache-unified; 108 cache-size = <0x100000>; 109 cache-level = <3>; 110 }; 111 }; 112 113 gpu_opp_table: opp-table-1 { 114 compatible = "operating-points-v2"; 115 116 opp-630000000 { 117 opp-hz = /bits/ 64 <630000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-315000000 { 122 opp-hz = /bits/ 64 <315000000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-157500000 { 127 opp-hz = /bits/ 64 <157500000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-78750000 { 132 opp-hz = /bits/ 64 <78750000>; 133 opp-microvolt = <800000>; 134 }; 135 136 opp-19687500 { 137 opp-hz = /bits/ 64 <19687500>; 138 opp-microvolt = <800000>; 139 }; 140 }; 141 142 pmu { 143 compatible = "arm,cortex-a55-pmu"; 144 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 145 }; 146 147 psci { 148 compatible = "arm,psci-1.0", "arm,psci-0.2"; 149 method = "smc"; 150 }; 151 152 qextal_clk: qextal-clk { 153 compatible = "fixed-clock"; 154 #clock-cells = <0>; 155 /* This value must be overridden by the board */ 156 clock-frequency = <0>; 157 }; 158 159 rtxin_clk: rtxin-clk { 160 compatible = "fixed-clock"; 161 #clock-cells = <0>; 162 /* This value must be overridden by the board */ 163 clock-frequency = <0>; 164 }; 165 166 soc: soc { 167 compatible = "simple-bus"; 168 #address-cells = <2>; 169 #size-cells = <2>; 170 ranges; 171 172 icu: interrupt-controller@10400000 { 173 compatible = "renesas,r9a09g057-icu"; 174 reg = <0 0x10400000 0 0x10000>; 175 #interrupt-cells = <2>; 176 #address-cells = <0>; 177 interrupt-controller; 178 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 226 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 228 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 229 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 230 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 231 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 232 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 233 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 234 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 236 interrupt-names = "nmi", 237 "port_irq0", "port_irq1", "port_irq2", 238 "port_irq3", "port_irq4", "port_irq5", 239 "port_irq6", "port_irq7", "port_irq8", 240 "port_irq9", "port_irq10", "port_irq11", 241 "port_irq12", "port_irq13", "port_irq14", 242 "port_irq15", 243 "tint0", "tint1", "tint2", "tint3", 244 "tint4", "tint5", "tint6", "tint7", 245 "tint8", "tint9", "tint10", "tint11", 246 "tint12", "tint13", "tint14", "tint15", 247 "tint16", "tint17", "tint18", "tint19", 248 "tint20", "tint21", "tint22", "tint23", 249 "tint24", "tint25", "tint26", "tint27", 250 "tint28", "tint29", "tint30", "tint31", 251 "int-ca55-0", "int-ca55-1", 252 "int-ca55-2", "int-ca55-3", 253 "icu-error-ca55", 254 "gpt-u0-gtciada", "gpt-u0-gtciadb", 255 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 256 clocks = <&cpg CPG_MOD 0x5>; 257 power-domains = <&cpg>; 258 resets = <&cpg 0x36>; 259 }; 260 261 pinctrl: pinctrl@10410000 { 262 compatible = "renesas,r9a09g057-pinctrl"; 263 reg = <0 0x10410000 0 0x10000>; 264 clocks = <&cpg CPG_CORE R9A09G057_IOTOP_0_SHCLK>; 265 gpio-controller; 266 #gpio-cells = <2>; 267 gpio-ranges = <&pinctrl 0 0 96>; 268 #interrupt-cells = <2>; 269 interrupt-controller; 270 interrupt-parent = <&icu>; 271 power-domains = <&cpg>; 272 resets = <&cpg 0xa5>, <&cpg 0xa6>; 273 }; 274 275 cpg: clock-controller@10420000 { 276 compatible = "renesas,r9a09g057-cpg"; 277 reg = <0 0x10420000 0 0x10000>; 278 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 279 clock-names = "audio_extal", "rtxin", "qextal"; 280 #clock-cells = <2>; 281 #reset-cells = <1>; 282 #power-domain-cells = <0>; 283 }; 284 285 sys: system-controller@10430000 { 286 compatible = "renesas,r9a09g057-sys"; 287 reg = <0 0x10430000 0 0x10000>; 288 clocks = <&cpg CPG_CORE R9A09G057_SYS_0_PCLK>; 289 resets = <&cpg 0x30>; 290 }; 291 292 tsu0: thermal@11000000 { 293 compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; 294 reg = <0 0x11000000 0 0x1000>; 295 interrupts = <GIC_SPI 248 IRQ_TYPE_EDGE_RISING>, 296 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 297 interrupt-names = "adi", "adcmpi"; 298 clocks = <&cpg CPG_MOD 0x109>; 299 resets = <&cpg 0xf7>; 300 power-domains = <&cpg>; 301 #thermal-sensor-cells = <0>; 302 renesas,tsu-trim = <&sys 0x320>; 303 }; 304 305 tsu1: thermal@14002000 { 306 compatible = "renesas,r9a09g057-tsu", "renesas,r9a09g047-tsu"; 307 reg = <0 0x14002000 0 0x1000>; 308 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 309 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 310 interrupt-names = "adi", "adcmpi"; 311 clocks = <&cpg CPG_MOD 0x10a>; 312 resets = <&cpg 0xf8>; 313 power-domains = <&cpg>; 314 #thermal-sensor-cells = <0>; 315 renesas,tsu-trim = <&sys 0x330>; 316 }; 317 318 xspi: spi@11030000 { 319 compatible = "renesas,r9a09g057-xspi", "renesas,r9a09g047-xspi"; 320 reg = <0 0x11030000 0 0x10000>, 321 <0 0x20000000 0 0x10000000>; 322 reg-names = "regs", "dirmap"; 323 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 325 interrupt-names = "pulse", "err_pulse"; 326 clocks = <&cpg CPG_MOD 0x9f>, 327 <&cpg CPG_MOD 0xa0>, 328 <&cpg CPG_CORE R9A09G057_SPI_CLK_SPI>, 329 <&cpg CPG_MOD 0xa1>; 330 clock-names = "ahb", "axi", "spi", "spix2"; 331 resets = <&cpg 0xa3>, <&cpg 0xa4>; 332 reset-names = "hresetn", "aresetn"; 333 power-domains = <&cpg>; 334 #address-cells = <1>; 335 #size-cells = <0>; 336 status = "disabled"; 337 }; 338 339 dmac0: dma-controller@11400000 { 340 compatible = "renesas,r9a09g057-dmac"; 341 reg = <0 0x11400000 0 0x10000>; 342 interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 343 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 344 <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 345 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 346 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 347 <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 348 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 349 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 352 <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 354 <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 355 <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 357 <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 358 <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 359 interrupt-names = "error", 360 "ch0", "ch1", "ch2", "ch3", 361 "ch4", "ch5", "ch6", "ch7", 362 "ch8", "ch9", "ch10", "ch11", 363 "ch12", "ch13", "ch14", "ch15"; 364 clocks = <&cpg CPG_MOD 0x0>; 365 power-domains = <&cpg>; 366 resets = <&cpg 0x31>; 367 #dma-cells = <1>; 368 dma-channels = <16>; 369 renesas,icu = <&icu 4>; 370 }; 371 372 dmac1: dma-controller@14830000 { 373 compatible = "renesas,r9a09g057-dmac"; 374 reg = <0 0x14830000 0 0x10000>; 375 interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 376 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 377 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 378 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 379 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 380 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 384 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 385 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 387 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 390 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 391 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 392 interrupt-names = "error", 393 "ch0", "ch1", "ch2", "ch3", 394 "ch4", "ch5", "ch6", "ch7", 395 "ch8", "ch9", "ch10", "ch11", 396 "ch12", "ch13", "ch14", "ch15"; 397 clocks = <&cpg CPG_MOD 0x1>; 398 power-domains = <&cpg>; 399 resets = <&cpg 0x32>; 400 #dma-cells = <1>; 401 dma-channels = <16>; 402 renesas,icu = <&icu 0>; 403 }; 404 405 dmac2: dma-controller@14840000 { 406 compatible = "renesas,r9a09g057-dmac"; 407 reg = <0 0x14840000 0 0x10000>; 408 interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 409 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 410 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 411 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 412 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 413 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 414 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 415 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 416 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 417 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 418 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 423 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 424 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 425 interrupt-names = "error", 426 "ch0", "ch1", "ch2", "ch3", 427 "ch4", "ch5", "ch6", "ch7", 428 "ch8", "ch9", "ch10", "ch11", 429 "ch12", "ch13", "ch14", "ch15"; 430 clocks = <&cpg CPG_MOD 0x2>; 431 power-domains = <&cpg>; 432 resets = <&cpg 0x33>; 433 #dma-cells = <1>; 434 dma-channels = <16>; 435 renesas,icu = <&icu 1>; 436 }; 437 438 dmac3: dma-controller@12000000 { 439 compatible = "renesas,r9a09g057-dmac"; 440 reg = <0 0x12000000 0 0x10000>; 441 interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 442 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 443 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 444 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 445 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 446 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 447 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 456 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 457 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 458 interrupt-names = "error", 459 "ch0", "ch1", "ch2", "ch3", 460 "ch4", "ch5", "ch6", "ch7", 461 "ch8", "ch9", "ch10", "ch11", 462 "ch12", "ch13", "ch14", "ch15"; 463 clocks = <&cpg CPG_MOD 0x3>; 464 power-domains = <&cpg>; 465 resets = <&cpg 0x34>; 466 #dma-cells = <1>; 467 dma-channels = <16>; 468 renesas,icu = <&icu 2>; 469 }; 470 471 dmac4: dma-controller@12010000 { 472 compatible = "renesas,r9a09g057-dmac"; 473 reg = <0 0x12010000 0 0x10000>; 474 interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 475 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 476 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 477 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 478 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 479 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 480 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 481 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 482 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 483 <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 484 <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 485 <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 486 <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 487 <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 488 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 489 <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 490 <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 491 interrupt-names = "error", 492 "ch0", "ch1", "ch2", "ch3", 493 "ch4", "ch5", "ch6", "ch7", 494 "ch8", "ch9", "ch10", "ch11", 495 "ch12", "ch13", "ch14", "ch15"; 496 clocks = <&cpg CPG_MOD 0x4>; 497 power-domains = <&cpg>; 498 resets = <&cpg 0x35>; 499 #dma-cells = <1>; 500 dma-channels = <16>; 501 renesas,icu = <&icu 3>; 502 }; 503 504 ostm0: timer@11800000 { 505 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 506 reg = <0x0 0x11800000 0x0 0x1000>; 507 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 508 clocks = <&cpg CPG_MOD 0x43>; 509 resets = <&cpg 0x6d>; 510 power-domains = <&cpg>; 511 status = "disabled"; 512 }; 513 514 ostm1: timer@11801000 { 515 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 516 reg = <0x0 0x11801000 0x0 0x1000>; 517 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 518 clocks = <&cpg CPG_MOD 0x44>; 519 resets = <&cpg 0x6e>; 520 power-domains = <&cpg>; 521 status = "disabled"; 522 }; 523 524 ostm2: timer@14000000 { 525 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 526 reg = <0x0 0x14000000 0x0 0x1000>; 527 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 528 clocks = <&cpg CPG_MOD 0x45>; 529 resets = <&cpg 0x6f>; 530 power-domains = <&cpg>; 531 status = "disabled"; 532 }; 533 534 ostm3: timer@14001000 { 535 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 536 reg = <0x0 0x14001000 0x0 0x1000>; 537 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 538 clocks = <&cpg CPG_MOD 0x46>; 539 resets = <&cpg 0x70>; 540 power-domains = <&cpg>; 541 status = "disabled"; 542 }; 543 544 ostm4: timer@12c00000 { 545 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 546 reg = <0x0 0x12c00000 0x0 0x1000>; 547 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 548 clocks = <&cpg CPG_MOD 0x47>; 549 resets = <&cpg 0x71>; 550 power-domains = <&cpg>; 551 status = "disabled"; 552 }; 553 554 ostm5: timer@12c01000 { 555 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 556 reg = <0x0 0x12c01000 0x0 0x1000>; 557 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 558 clocks = <&cpg CPG_MOD 0x48>; 559 resets = <&cpg 0x72>; 560 power-domains = <&cpg>; 561 status = "disabled"; 562 }; 563 564 ostm6: timer@12c02000 { 565 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 566 reg = <0x0 0x12c02000 0x0 0x1000>; 567 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 568 clocks = <&cpg CPG_MOD 0x49>; 569 resets = <&cpg 0x73>; 570 power-domains = <&cpg>; 571 status = "disabled"; 572 }; 573 574 ostm7: timer@12c03000 { 575 compatible = "renesas,r9a09g057-ostm", "renesas,ostm"; 576 reg = <0x0 0x12c03000 0x0 0x1000>; 577 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 578 clocks = <&cpg CPG_MOD 0x4a>; 579 resets = <&cpg 0x74>; 580 power-domains = <&cpg>; 581 status = "disabled"; 582 }; 583 584 wdt1: watchdog@14400000 { 585 compatible = "renesas,r9a09g057-wdt"; 586 reg = <0 0x14400000 0 0x400>; 587 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 588 clock-names = "pclk", "oscclk"; 589 resets = <&cpg 0x76>; 590 power-domains = <&cpg>; 591 status = "disabled"; 592 }; 593 594 rtc: rtc@11c00800 { 595 compatible = "renesas,r9a09g057-rtca3", "renesas,rz-rtca3"; 596 reg = <0 0x11c00800 0 0x400>; 597 interrupts = <GIC_SPI 524 IRQ_TYPE_EDGE_RISING>, 598 <GIC_SPI 525 IRQ_TYPE_EDGE_RISING>, 599 <GIC_SPI 526 IRQ_TYPE_EDGE_RISING>; 600 interrupt-names = "alarm", "period", "carry"; 601 clocks = <&cpg CPG_MOD 0x53>, <&rtxin_clk>; 602 clock-names = "bus", "counter"; 603 power-domains = <&cpg>; 604 resets = <&cpg 0x79>, <&cpg 0x7a>; 605 reset-names = "rtc", "rtest"; 606 status = "disabled"; 607 }; 608 609 scif: serial@11c01400 { 610 compatible = "renesas,scif-r9a09g057"; 611 reg = <0 0x11c01400 0 0x400>; 612 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 620 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 621 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 622 "tei", "tei-dri", "rxi-edge", "txi-edge"; 623 clocks = <&cpg CPG_MOD 0x8f>; 624 clock-names = "fck"; 625 power-domains = <&cpg>; 626 resets = <&cpg 0x95>; 627 status = "disabled"; 628 }; 629 630 i3c: i3c@12400000 { 631 compatible = "renesas,r9a09g057-i3c", "renesas,r9a09g047-i3c"; 632 reg = <0 0x12400000 0 0x10000>; 633 clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; 634 clock-names = "pclk", "tclk", "pclkrw"; 635 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 639 <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 640 <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 641 <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 642 <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 643 <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 644 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-names = "ierr", "terr", "abort", "resp", 652 "cmd", "ibi", "rx", "tx", "rcv", 653 "st", "sp", "tend", "nack", 654 "al", "tmo", "wu"; 655 resets = <&cpg 0x96>, <&cpg 0x97>; 656 reset-names = "presetn", "tresetn"; 657 power-domains = <&cpg>; 658 #address-cells = <3>; 659 #size-cells = <0>; 660 status = "disabled"; 661 }; 662 663 rspi0: spi@12800000 { 664 compatible = "renesas,r9a09g057-rspi"; 665 reg = <0x0 0x12800000 0x0 0x400>; 666 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 107 IRQ_TYPE_EDGE_RISING>, 669 <GIC_SPI 500 IRQ_TYPE_EDGE_RISING>, 670 <GIC_SPI 501 IRQ_TYPE_EDGE_RISING>; 671 interrupt-names = "idle", "error", "end", "rx", "tx"; 672 clocks = <&cpg CPG_MOD 0x54>, 673 <&cpg CPG_MOD 0x55>, 674 <&cpg CPG_MOD 0x56>; 675 clock-names = "pclk", "pclk_sfr", "tclk"; 676 resets = <&cpg 0x7b>, <&cpg 0x7c>; 677 reset-names = "presetn", "tresetn"; 678 power-domains = <&cpg>; 679 #address-cells = <1>; 680 #size-cells = <0>; 681 status = "disabled"; 682 }; 683 684 rspi1: spi@12800400 { 685 compatible = "renesas,r9a09g057-rspi"; 686 reg = <0x0 0x12800400 0x0 0x400>; 687 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 110 IRQ_TYPE_EDGE_RISING>, 690 <GIC_SPI 502 IRQ_TYPE_EDGE_RISING>, 691 <GIC_SPI 503 IRQ_TYPE_EDGE_RISING>; 692 interrupt-names = "idle", "error", "end", "rx", "tx"; 693 clocks = <&cpg CPG_MOD 0x57>, 694 <&cpg CPG_MOD 0x58>, 695 <&cpg CPG_MOD 0x59>; 696 clock-names = "pclk", "pclk_sfr", "tclk"; 697 resets = <&cpg 0x7d>, <&cpg 0x7e>; 698 reset-names = "presetn", "tresetn"; 699 power-domains = <&cpg>; 700 #address-cells = <1>; 701 #size-cells = <0>; 702 status = "disabled"; 703 }; 704 705 rspi2: spi@12800800 { 706 compatible = "renesas,r9a09g057-rspi"; 707 reg = <0x0 0x12800800 0x0 0x400>; 708 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 113 IRQ_TYPE_EDGE_RISING>, 711 <GIC_SPI 504 IRQ_TYPE_EDGE_RISING>, 712 <GIC_SPI 505 IRQ_TYPE_EDGE_RISING>; 713 interrupt-names = "idle", "error", "end", "rx", "tx"; 714 clocks = <&cpg CPG_MOD 0x5a>, 715 <&cpg CPG_MOD 0x5b>, 716 <&cpg CPG_MOD 0x5c>; 717 clock-names = "pclk", "pclk_sfr", "tclk"; 718 resets = <&cpg 0x7f>, <&cpg 0x80>; 719 reset-names = "presetn", "tresetn"; 720 power-domains = <&cpg>; 721 #address-cells = <1>; 722 #size-cells = <0>; 723 status = "disabled"; 724 }; 725 726 i2c0: i2c@14400400 { 727 compatible = "renesas,riic-r9a09g057"; 728 reg = <0 0x14400400 0 0x400>; 729 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 731 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 732 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 737 interrupt-names = "tei", "ri", "ti", "spi", "sti", 738 "naki", "ali", "tmoi"; 739 clocks = <&cpg CPG_MOD 0x94>; 740 resets = <&cpg 0x98>; 741 power-domains = <&cpg>; 742 #address-cells = <1>; 743 #size-cells = <0>; 744 status = "disabled"; 745 }; 746 747 i2c1: i2c@14400800 { 748 compatible = "renesas,riic-r9a09g057"; 749 reg = <0 0x14400800 0 0x400>; 750 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 752 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 753 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 758 interrupt-names = "tei", "ri", "ti", "spi", "sti", 759 "naki", "ali", "tmoi"; 760 clocks = <&cpg CPG_MOD 0x95>; 761 resets = <&cpg 0x99>; 762 power-domains = <&cpg>; 763 #address-cells = <1>; 764 #size-cells = <0>; 765 status = "disabled"; 766 }; 767 768 i2c2: i2c@14400c00 { 769 compatible = "renesas,riic-r9a09g057"; 770 reg = <0 0x14400c00 0 0x400>; 771 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 773 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 774 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 779 interrupt-names = "tei", "ri", "ti", "spi", "sti", 780 "naki", "ali", "tmoi"; 781 clocks = <&cpg CPG_MOD 0x96>; 782 resets = <&cpg 0x9a>; 783 power-domains = <&cpg>; 784 #address-cells = <1>; 785 #size-cells = <0>; 786 status = "disabled"; 787 }; 788 789 i2c3: i2c@14401000 { 790 compatible = "renesas,riic-r9a09g057"; 791 reg = <0 0x14401000 0 0x400>; 792 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 794 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 795 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 800 interrupt-names = "tei", "ri", "ti", "spi", "sti", 801 "naki", "ali", "tmoi"; 802 clocks = <&cpg CPG_MOD 0x97>; 803 resets = <&cpg 0x9b>; 804 power-domains = <&cpg>; 805 #address-cells = <1>; 806 #size-cells = <0>; 807 status = "disabled"; 808 }; 809 810 i2c4: i2c@14401400 { 811 compatible = "renesas,riic-r9a09g057"; 812 reg = <0 0x14401400 0 0x400>; 813 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 815 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 816 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 817 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 821 interrupt-names = "tei", "ri", "ti", "spi", "sti", 822 "naki", "ali", "tmoi"; 823 clocks = <&cpg CPG_MOD 0x98>; 824 resets = <&cpg 0x9c>; 825 power-domains = <&cpg>; 826 #address-cells = <1>; 827 #size-cells = <0>; 828 status = "disabled"; 829 }; 830 831 i2c5: i2c@14401800 { 832 compatible = "renesas,riic-r9a09g057"; 833 reg = <0 0x14401800 0 0x400>; 834 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 836 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 837 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 842 interrupt-names = "tei", "ri", "ti", "spi", "sti", 843 "naki", "ali", "tmoi"; 844 clocks = <&cpg CPG_MOD 0x99>; 845 resets = <&cpg 0x9d>; 846 power-domains = <&cpg>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 status = "disabled"; 850 }; 851 852 i2c6: i2c@14401c00 { 853 compatible = "renesas,riic-r9a09g057"; 854 reg = <0 0x14401c00 0 0x400>; 855 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 856 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 857 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 858 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 859 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 863 interrupt-names = "tei", "ri", "ti", "spi", "sti", 864 "naki", "ali", "tmoi"; 865 clocks = <&cpg CPG_MOD 0x9a>; 866 resets = <&cpg 0x9e>; 867 power-domains = <&cpg>; 868 #address-cells = <1>; 869 #size-cells = <0>; 870 status = "disabled"; 871 }; 872 873 i2c7: i2c@14402000 { 874 compatible = "renesas,riic-r9a09g057"; 875 reg = <0 0x14402000 0 0x400>; 876 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 878 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 879 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 884 interrupt-names = "tei", "ri", "ti", "spi", "sti", 885 "naki", "ali", "tmoi"; 886 clocks = <&cpg CPG_MOD 0x9b>; 887 resets = <&cpg 0x9f>; 888 power-domains = <&cpg>; 889 #address-cells = <1>; 890 #size-cells = <0>; 891 status = "disabled"; 892 }; 893 894 i2c8: i2c@11c01000 { 895 compatible = "renesas,riic-r9a09g057"; 896 reg = <0 0x11c01000 0 0x400>; 897 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 899 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 900 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 905 interrupt-names = "tei", "ri", "ti", "spi", "sti", 906 "naki", "ali", "tmoi"; 907 clocks = <&cpg CPG_MOD 0x93>; 908 resets = <&cpg 0xa0>; 909 power-domains = <&cpg>; 910 #address-cells = <1>; 911 #size-cells = <0>; 912 status = "disabled"; 913 }; 914 915 gpu: gpu@14850000 { 916 compatible = "renesas,r9a09g057-mali", 917 "arm,mali-bifrost"; 918 reg = <0x0 0x14850000 0x0 0x10000>; 919 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 923 interrupt-names = "job", "mmu", "gpu", "event"; 924 clocks = <&cpg CPG_MOD 0xf0>, 925 <&cpg CPG_MOD 0xf1>, 926 <&cpg CPG_MOD 0xf2>; 927 clock-names = "gpu", "bus", "bus_ace"; 928 power-domains = <&cpg>; 929 resets = <&cpg 0xdd>, 930 <&cpg 0xde>, 931 <&cpg 0xdf>; 932 reset-names = "rst", "axi_rst", "ace_rst"; 933 operating-points-v2 = <&gpu_opp_table>; 934 status = "disabled"; 935 }; 936 937 gic: interrupt-controller@14900000 { 938 compatible = "arm,gic-v3"; 939 reg = <0x0 0x14900000 0 0x20000>, 940 <0x0 0x14940000 0 0x80000>; 941 #interrupt-cells = <3>; 942 #address-cells = <0>; 943 interrupt-controller; 944 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 945 }; 946 947 ohci0: usb@15800000 { 948 compatible = "generic-ohci"; 949 reg = <0 0x15800000 0 0x100>; 950 interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 951 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 952 resets = <&usb20phyrst>, <&cpg 0xac>; 953 phys = <&usb2_phy0 1>; 954 phy-names = "usb"; 955 power-domains = <&cpg>; 956 status = "disabled"; 957 }; 958 959 ohci1: usb@15810000 { 960 compatible = "generic-ohci"; 961 reg = <0 0x15810000 0 0x100>; 962 interrupts = <GIC_SPI 747 IRQ_TYPE_LEVEL_HIGH>; 963 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 964 resets = <&usb21phyrst>, <&cpg 0xad>; 965 phys = <&usb2_phy1 1>; 966 phy-names = "usb"; 967 power-domains = <&cpg>; 968 status = "disabled"; 969 }; 970 971 ehci0: usb@15800100 { 972 compatible = "generic-ehci"; 973 reg = <0 0x15800100 0 0x100>; 974 interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 975 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 976 resets = <&usb20phyrst>, <&cpg 0xac>; 977 phys = <&usb2_phy0 2>; 978 phy-names = "usb"; 979 companion = <&ohci0>; 980 power-domains = <&cpg>; 981 status = "disabled"; 982 }; 983 984 ehci1: usb@15810100 { 985 compatible = "generic-ehci"; 986 reg = <0 0x15810100 0 0x100>; 987 interrupts = <GIC_SPI 748 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&cpg CPG_MOD 0xb4>, <&cpg CPG_MOD 0xb7>; 989 resets = <&usb21phyrst>, <&cpg 0xad>; 990 phys = <&usb2_phy1 2>; 991 phy-names = "usb"; 992 companion = <&ohci1>; 993 power-domains = <&cpg>; 994 status = "disabled"; 995 }; 996 997 usb2_phy0: usb-phy@15800200 { 998 compatible = "renesas,usb2-phy-r9a09g057"; 999 reg = <0 0x15800200 0 0x700>; 1000 interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 1001 clocks = <&cpg CPG_MOD 0xb3>, 1002 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE0>; 1003 clock-names = "fck", "usb_x1"; 1004 resets = <&usb20phyrst>; 1005 #phy-cells = <1>; 1006 power-domains = <&cpg>; 1007 status = "disabled"; 1008 }; 1009 1010 usb2_phy1: usb-phy@15810200 { 1011 compatible = "renesas,usb2-phy-r9a09g057"; 1012 reg = <0 0x15810200 0 0x700>; 1013 interrupts = <GIC_SPI 750 IRQ_TYPE_LEVEL_HIGH>; 1014 clocks = <&cpg CPG_MOD 0xb4>, 1015 <&cpg CPG_CORE R9A09G057_USB2_0_CLK_CORE1>; 1016 clock-names = "fck", "usb_x1"; 1017 resets = <&usb21phyrst>; 1018 #phy-cells = <1>; 1019 power-domains = <&cpg>; 1020 status = "disabled"; 1021 }; 1022 1023 hsusb: usb@15820000 { 1024 compatible = "renesas,usbhs-r9a09g057", 1025 "renesas,rzg2l-usbhs"; 1026 reg = <0 0x15820000 0 0x10000>; 1027 interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 1028 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 1031 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 1032 resets = <&usb20phyrst>, 1033 <&cpg 0xae>; 1034 phys = <&usb2_phy0 3>; 1035 phy-names = "usb"; 1036 power-domains = <&cpg>; 1037 status = "disabled"; 1038 }; 1039 1040 usb20phyrst: usb20phy-reset@15830000 { 1041 compatible = "renesas,r9a09g057-usb2phy-reset"; 1042 reg = <0 0x15830000 0 0x10000>; 1043 clocks = <&cpg CPG_MOD 0xb6>; 1044 resets = <&cpg 0xaf>; 1045 power-domains = <&cpg>; 1046 #reset-cells = <0>; 1047 status = "disabled"; 1048 }; 1049 1050 usb21phyrst: usb21phy-reset@15840000 { 1051 compatible = "renesas,r9a09g057-usb2phy-reset"; 1052 reg = <0 0x15840000 0 0x10000>; 1053 clocks = <&cpg CPG_MOD 0xb7>; 1054 resets = <&cpg 0xaf>; 1055 power-domains = <&cpg>; 1056 #reset-cells = <0>; 1057 status = "disabled"; 1058 }; 1059 1060 sdhi0: mmc@15c00000 { 1061 compatible = "renesas,sdhi-r9a09g057"; 1062 reg = <0x0 0x15c00000 0 0x10000>; 1063 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 1066 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 1067 clock-names = "core", "clkh", "cd", "aclk"; 1068 resets = <&cpg 0xa7>; 1069 power-domains = <&cpg>; 1070 status = "disabled"; 1071 1072 sdhi0_vqmmc: vqmmc-regulator { 1073 regulator-name = "SDHI0-VQMMC"; 1074 regulator-min-microvolt = <1800000>; 1075 regulator-max-microvolt = <3300000>; 1076 status = "disabled"; 1077 }; 1078 }; 1079 1080 sdhi1: mmc@15c10000 { 1081 compatible = "renesas,sdhi-r9a09g057"; 1082 reg = <0x0 0x15c10000 0 0x10000>; 1083 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 1086 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 1087 clock-names = "core", "clkh", "cd", "aclk"; 1088 resets = <&cpg 0xa8>; 1089 power-domains = <&cpg>; 1090 status = "disabled"; 1091 1092 sdhi1_vqmmc: vqmmc-regulator { 1093 regulator-name = "SDHI1-VQMMC"; 1094 regulator-min-microvolt = <1800000>; 1095 regulator-max-microvolt = <3300000>; 1096 status = "disabled"; 1097 }; 1098 }; 1099 1100 sdhi2: mmc@15c20000 { 1101 compatible = "renesas,sdhi-r9a09g057"; 1102 reg = <0x0 0x15c20000 0 0x10000>; 1103 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 1105 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 1106 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 1107 clock-names = "core", "clkh", "cd", "aclk"; 1108 resets = <&cpg 0xa9>; 1109 power-domains = <&cpg>; 1110 status = "disabled"; 1111 1112 sdhi2_vqmmc: vqmmc-regulator { 1113 regulator-name = "SDHI2-VQMMC"; 1114 regulator-min-microvolt = <1800000>; 1115 regulator-max-microvolt = <3300000>; 1116 status = "disabled"; 1117 }; 1118 }; 1119 1120 eth0: ethernet@15c30000 { 1121 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1122 "snps,dwmac-5.20"; 1123 reg = <0 0x15c30000 0 0x10000>; 1124 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 1131 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 1132 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 1133 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 1134 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 1135 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1136 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1137 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1138 "tx-queue-2", "tx-queue-3"; 1139 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 1140 <&cpg CPG_CORE R9A09G057_GBETH_0_CLK_PTP_REF_I>, 1141 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 1142 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 1143 clock-names = "stmmaceth", "pclk", "ptp_ref", 1144 "tx", "rx", "tx-180", "rx-180"; 1145 resets = <&cpg 0xb0>; 1146 power-domains = <&cpg>; 1147 snps,multicast-filter-bins = <256>; 1148 snps,perfect-filter-entries = <128>; 1149 rx-fifo-depth = <8192>; 1150 tx-fifo-depth = <8192>; 1151 snps,fixed-burst; 1152 snps,no-pbl-x8; 1153 snps,force_thresh_dma_mode; 1154 snps,axi-config = <&stmmac_axi_setup>; 1155 snps,mtl-rx-config = <&mtl_rx_setup0>; 1156 snps,mtl-tx-config = <&mtl_tx_setup0>; 1157 snps,txpbl = <32>; 1158 snps,rxpbl = <32>; 1159 status = "disabled"; 1160 1161 mdio0: mdio { 1162 compatible = "snps,dwmac-mdio"; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 }; 1166 1167 mtl_rx_setup0: rx-queues-config { 1168 snps,rx-queues-to-use = <4>; 1169 snps,rx-sched-sp; 1170 1171 queue0 { 1172 snps,dcb-algorithm; 1173 snps,priority = <0x1>; 1174 snps,map-to-dma-channel = <0>; 1175 }; 1176 1177 queue1 { 1178 snps,dcb-algorithm; 1179 snps,priority = <0x2>; 1180 snps,map-to-dma-channel = <1>; 1181 }; 1182 1183 queue2 { 1184 snps,dcb-algorithm; 1185 snps,priority = <0x4>; 1186 snps,map-to-dma-channel = <2>; 1187 }; 1188 1189 queue3 { 1190 snps,dcb-algorithm; 1191 snps,priority = <0x8>; 1192 snps,map-to-dma-channel = <3>; 1193 }; 1194 }; 1195 1196 mtl_tx_setup0: tx-queues-config { 1197 snps,tx-queues-to-use = <4>; 1198 1199 queue0 { 1200 snps,dcb-algorithm; 1201 snps,priority = <0x1>; 1202 }; 1203 1204 queue1 { 1205 snps,dcb-algorithm; 1206 snps,priority = <0x2>; 1207 }; 1208 1209 queue2 { 1210 snps,dcb-algorithm; 1211 snps,priority = <0x4>; 1212 }; 1213 1214 queue3 { 1215 snps,dcb-algorithm; 1216 snps,priority = <0x8>; 1217 }; 1218 }; 1219 }; 1220 1221 eth1: ethernet@15c40000 { 1222 compatible = "renesas,r9a09g057-gbeth", "renesas,rzv2h-gbeth", 1223 "snps,dwmac-5.20"; 1224 reg = <0 0x15c40000 0 0x10000>; 1225 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1228 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1229 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 1230 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 1236 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1237 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1238 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1239 "tx-queue-2", "tx-queue-3"; 1240 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1241 <&cpg CPG_CORE R9A09G057_GBETH_1_CLK_PTP_REF_I>, 1242 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1243 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1244 clock-names = "stmmaceth", "pclk", "ptp_ref", 1245 "tx", "rx", "tx-180", "rx-180"; 1246 resets = <&cpg 0xb1>; 1247 power-domains = <&cpg>; 1248 snps,multicast-filter-bins = <256>; 1249 snps,perfect-filter-entries = <128>; 1250 rx-fifo-depth = <8192>; 1251 tx-fifo-depth = <8192>; 1252 snps,fixed-burst; 1253 snps,no-pbl-x8; 1254 snps,force_thresh_dma_mode; 1255 snps,axi-config = <&stmmac_axi_setup>; 1256 snps,mtl-rx-config = <&mtl_rx_setup1>; 1257 snps,mtl-tx-config = <&mtl_tx_setup1>; 1258 snps,txpbl = <32>; 1259 snps,rxpbl = <32>; 1260 status = "disabled"; 1261 1262 mdio1: mdio { 1263 compatible = "snps,dwmac-mdio"; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 }; 1267 1268 mtl_rx_setup1: rx-queues-config { 1269 snps,rx-queues-to-use = <4>; 1270 snps,rx-sched-sp; 1271 1272 queue0 { 1273 snps,dcb-algorithm; 1274 snps,priority = <0x1>; 1275 snps,map-to-dma-channel = <0>; 1276 }; 1277 1278 queue1 { 1279 snps,dcb-algorithm; 1280 snps,priority = <0x2>; 1281 snps,map-to-dma-channel = <1>; 1282 }; 1283 1284 queue2 { 1285 snps,dcb-algorithm; 1286 snps,priority = <0x4>; 1287 snps,map-to-dma-channel = <2>; 1288 }; 1289 1290 queue3 { 1291 snps,dcb-algorithm; 1292 snps,priority = <0x8>; 1293 snps,map-to-dma-channel = <3>; 1294 }; 1295 }; 1296 1297 mtl_tx_setup1: tx-queues-config { 1298 snps,tx-queues-to-use = <4>; 1299 1300 queue0 { 1301 snps,dcb-algorithm; 1302 snps,priority = <0x1>; 1303 }; 1304 1305 queue1 { 1306 snps,dcb-algorithm; 1307 snps,priority = <0x2>; 1308 }; 1309 1310 queue2 { 1311 snps,dcb-algorithm; 1312 snps,priority = <0x4>; 1313 }; 1314 1315 queue3 { 1316 snps,dcb-algorithm; 1317 snps,priority = <0x8>; 1318 }; 1319 }; 1320 }; 1321 }; 1322 1323 stmmac_axi_setup: stmmac-axi-config { 1324 snps,lpi_en; 1325 snps,wr_osr_lmt = <0xf>; 1326 snps,rd_osr_lmt = <0xf>; 1327 snps,blen = <16 8 4 0 0 0 0>; 1328 }; 1329 1330 thermal-zones { 1331 sensor1_thermal: sensor1-thermal { 1332 polling-delay = <1000>; 1333 polling-delay-passive = <250>; 1334 thermal-sensors = <&tsu0>; 1335 1336 trips { 1337 sensor1_crit: sensor1-crit { 1338 temperature = <120000>; 1339 hysteresis = <1000>; 1340 type = "critical"; 1341 }; 1342 }; 1343 }; 1344 1345 sensor2_thermal: sensor2-thermal { 1346 polling-delay = <1000>; 1347 polling-delay-passive = <250>; 1348 thermal-sensors = <&tsu1>; 1349 1350 cooling-maps { 1351 map0 { 1352 trip = <&sensor2_target>; 1353 cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, 1354 <&cpu2 0 3>, <&cpu3 0 3>; 1355 contribution = <1024>; 1356 }; 1357 }; 1358 1359 trips { 1360 sensor2_target: trip-point { 1361 temperature = <95000>; 1362 hysteresis = <1000>; 1363 type = "passive"; 1364 }; 1365 1366 sensor2_crit: sensor2-crit { 1367 temperature = <120000>; 1368 hysteresis = <1000>; 1369 type = "critical"; 1370 }; 1371 }; 1372 }; 1373 }; 1374 1375 timer { 1376 compatible = "arm,armv8-timer"; 1377 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1378 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1379 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1380 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1381 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1382 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1383 }; 1384};
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