FILE
r9a09g056.dtsi
File preview with syntax highlighting.
linux-6.19.14/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/V2N SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g056-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/pinctrl/rzg2l-pinctrl.h> 11 12/* RZV2N_Px = Offset address of PFC_P_mn - 0x20 */ 13#define RZV2N_P0 0 14#define RZV2N_P1 1 15#define RZV2N_P2 2 16#define RZV2N_P3 3 17#define RZV2N_P4 4 18#define RZV2N_P5 5 19#define RZV2N_P6 6 20#define RZV2N_P7 7 21#define RZV2N_P8 8 22#define RZV2N_P9 9 23#define RZV2N_PA 10 24#define RZV2N_PB 11 25 26#define RZV2N_PORT_PINMUX(b, p, f) RZG2L_PORT_PINMUX(RZV2N_P##b, p, f) 27#define RZV2N_GPIO(port, pin) RZG2L_GPIO(RZV2N_P##port, pin) 28 29/ { 30 compatible = "renesas,r9a09g056"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 interrupt-parent = <&gic>; 34 35 audio_extal_clk: audio-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 /* This value must be overridden by the board */ 39 clock-frequency = <0>; 40 }; 41 42 /* 43 * The default cluster table is based on the assumption that the PLLCA55 clock 44 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 45 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 46 * clocked to 1.8GHz as well). The table below should be overridden in the board 47 * DTS based on the PLLCA55 clock frequency. 48 */ 49 cluster0_opp: opp-table-0 { 50 compatible = "operating-points-v2"; 51 52 opp-1700000000 { 53 opp-hz = /bits/ 64 <1700000000>; 54 opp-microvolt = <900000>; 55 clock-latency-ns = <300000>; 56 }; 57 opp-850000000 { 58 opp-hz = /bits/ 64 <850000000>; 59 opp-microvolt = <800000>; 60 clock-latency-ns = <300000>; 61 }; 62 opp-425000000 { 63 opp-hz = /bits/ 64 <425000000>; 64 opp-microvolt = <800000>; 65 clock-latency-ns = <300000>; 66 }; 67 opp-212500000 { 68 opp-hz = /bits/ 64 <212500000>; 69 opp-microvolt = <800000>; 70 clock-latency-ns = <300000>; 71 opp-suspend; 72 }; 73 }; 74 75 cpus { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 79 cpu0: cpu@0 { 80 compatible = "arm,cortex-a55"; 81 reg = <0>; 82 device_type = "cpu"; 83 next-level-cache = <&L3_CA55>; 84 enable-method = "psci"; 85 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK0>; 86 operating-points-v2 = <&cluster0_opp>; 87 }; 88 89 cpu1: cpu@100 { 90 compatible = "arm,cortex-a55"; 91 reg = <0x100>; 92 device_type = "cpu"; 93 next-level-cache = <&L3_CA55>; 94 enable-method = "psci"; 95 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK1>; 96 operating-points-v2 = <&cluster0_opp>; 97 }; 98 99 cpu2: cpu@200 { 100 compatible = "arm,cortex-a55"; 101 reg = <0x200>; 102 device_type = "cpu"; 103 next-level-cache = <&L3_CA55>; 104 enable-method = "psci"; 105 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK2>; 106 operating-points-v2 = <&cluster0_opp>; 107 }; 108 109 cpu3: cpu@300 { 110 compatible = "arm,cortex-a55"; 111 reg = <0x300>; 112 device_type = "cpu"; 113 next-level-cache = <&L3_CA55>; 114 enable-method = "psci"; 115 clocks = <&cpg CPG_CORE R9A09G056_CA55_0_CORE_CLK3>; 116 operating-points-v2 = <&cluster0_opp>; 117 }; 118 119 L3_CA55: cache-controller-0 { 120 compatible = "cache"; 121 cache-unified; 122 cache-size = <0x100000>; 123 cache-level = <3>; 124 }; 125 }; 126 127 gpu_opp_table: opp-table-1 { 128 compatible = "operating-points-v2"; 129 130 opp-630000000 { 131 opp-hz = /bits/ 64 <630000000>; 132 opp-microvolt = <800000>; 133 }; 134 135 opp-315000000 { 136 opp-hz = /bits/ 64 <315000000>; 137 opp-microvolt = <800000>; 138 }; 139 140 opp-157500000 { 141 opp-hz = /bits/ 64 <157500000>; 142 opp-microvolt = <800000>; 143 }; 144 145 opp-78750000 { 146 opp-hz = /bits/ 64 <78750000>; 147 opp-microvolt = <800000>; 148 }; 149 150 opp-19687500 { 151 opp-hz = /bits/ 64 <19687500>; 152 opp-microvolt = <800000>; 153 }; 154 }; 155 156 pmu { 157 compatible = "arm,cortex-a55-pmu"; 158 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 159 }; 160 161 psci { 162 compatible = "arm,psci-1.0", "arm,psci-0.2"; 163 method = "smc"; 164 }; 165 166 qextal_clk: qextal-clk { 167 compatible = "fixed-clock"; 168 #clock-cells = <0>; 169 /* This value must be overridden by the board */ 170 clock-frequency = <0>; 171 }; 172 173 rtxin_clk: rtxin-clk { 174 compatible = "fixed-clock"; 175 #clock-cells = <0>; 176 /* This value must be overridden by the board */ 177 clock-frequency = <0>; 178 }; 179 180 soc: soc { 181 compatible = "simple-bus"; 182 #address-cells = <2>; 183 #size-cells = <2>; 184 ranges; 185 186 pinctrl: pinctrl@10410000 { 187 compatible = "renesas,r9a09g056-pinctrl"; 188 reg = <0 0x10410000 0 0x10000>; 189 clocks = <&cpg CPG_CORE R9A09G056_IOTOP_0_SHCLK>; 190 gpio-controller; 191 #gpio-cells = <2>; 192 gpio-ranges = <&pinctrl 0 0 96>; 193 power-domains = <&cpg>; 194 resets = <&cpg 0xa5>, <&cpg 0xa6>; 195 }; 196 197 cpg: clock-controller@10420000 { 198 compatible = "renesas,r9a09g056-cpg"; 199 reg = <0 0x10420000 0 0x10000>; 200 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 201 clock-names = "audio_extal", "rtxin", "qextal"; 202 #clock-cells = <2>; 203 #reset-cells = <1>; 204 #power-domain-cells = <0>; 205 }; 206 207 sys: system-controller@10430000 { 208 compatible = "renesas,r9a09g056-sys"; 209 reg = <0 0x10430000 0 0x10000>; 210 clocks = <&cpg CPG_CORE R9A09G056_SYS_0_PCLK>; 211 resets = <&cpg 0x30>; 212 }; 213 214 xspi: spi@11030000 { 215 compatible = "renesas,r9a09g056-xspi", "renesas,r9a09g047-xspi"; 216 reg = <0 0x11030000 0 0x10000>, 217 <0 0x20000000 0 0x10000000>; 218 reg-names = "regs", "dirmap"; 219 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 220 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 221 interrupt-names = "pulse", "err_pulse"; 222 clocks = <&cpg CPG_MOD 0x9f>, 223 <&cpg CPG_MOD 0xa0>, 224 <&cpg CPG_CORE R9A09G056_SPI_CLK_SPI>, 225 <&cpg CPG_MOD 0xa1>; 226 clock-names = "ahb", "axi", "spi", "spix2"; 227 resets = <&cpg 0xa3>, <&cpg 0xa4>; 228 reset-names = "hresetn", "aresetn"; 229 power-domains = <&cpg>; 230 #address-cells = <1>; 231 #size-cells = <0>; 232 status = "disabled"; 233 }; 234 235 ostm0: timer@11800000 { 236 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 237 reg = <0x0 0x11800000 0x0 0x1000>; 238 interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>; 239 clocks = <&cpg CPG_MOD 0x43>; 240 resets = <&cpg 0x6d>; 241 power-domains = <&cpg>; 242 status = "disabled"; 243 }; 244 245 ostm1: timer@11801000 { 246 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 247 reg = <0x0 0x11801000 0x0 0x1000>; 248 interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>; 249 clocks = <&cpg CPG_MOD 0x44>; 250 resets = <&cpg 0x6e>; 251 power-domains = <&cpg>; 252 status = "disabled"; 253 }; 254 255 ostm2: timer@14000000 { 256 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 257 reg = <0x0 0x14000000 0x0 0x1000>; 258 interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>; 259 clocks = <&cpg CPG_MOD 0x45>; 260 resets = <&cpg 0x6f>; 261 power-domains = <&cpg>; 262 status = "disabled"; 263 }; 264 265 ostm3: timer@14001000 { 266 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 267 reg = <0x0 0x14001000 0x0 0x1000>; 268 interrupts = <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>; 269 clocks = <&cpg CPG_MOD 0x46>; 270 resets = <&cpg 0x70>; 271 power-domains = <&cpg>; 272 status = "disabled"; 273 }; 274 275 ostm4: timer@12c00000 { 276 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 277 reg = <0x0 0x12c00000 0x0 0x1000>; 278 interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; 279 clocks = <&cpg CPG_MOD 0x47>; 280 resets = <&cpg 0x71>; 281 power-domains = <&cpg>; 282 status = "disabled"; 283 }; 284 285 ostm5: timer@12c01000 { 286 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 287 reg = <0x0 0x12c01000 0x0 0x1000>; 288 interrupts = <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; 289 clocks = <&cpg CPG_MOD 0x48>; 290 resets = <&cpg 0x72>; 291 power-domains = <&cpg>; 292 status = "disabled"; 293 }; 294 295 ostm6: timer@12c02000 { 296 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 297 reg = <0x0 0x12c02000 0x0 0x1000>; 298 interrupts = <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>; 299 clocks = <&cpg CPG_MOD 0x49>; 300 resets = <&cpg 0x73>; 301 power-domains = <&cpg>; 302 status = "disabled"; 303 }; 304 305 ostm7: timer@12c03000 { 306 compatible = "renesas,r9a09g056-ostm", "renesas,ostm"; 307 reg = <0x0 0x12c03000 0x0 0x1000>; 308 interrupts = <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>; 309 clocks = <&cpg CPG_MOD 0x4a>; 310 resets = <&cpg 0x74>; 311 power-domains = <&cpg>; 312 status = "disabled"; 313 }; 314 315 wdt0: watchdog@11c00400 { 316 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 317 reg = <0 0x11c00400 0 0x400>; 318 clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; 319 clock-names = "pclk", "oscclk"; 320 resets = <&cpg 0x75>; 321 power-domains = <&cpg>; 322 status = "disabled"; 323 }; 324 325 wdt1: watchdog@14400000 { 326 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 327 reg = <0 0x14400000 0 0x400>; 328 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 329 clock-names = "pclk", "oscclk"; 330 resets = <&cpg 0x76>; 331 power-domains = <&cpg>; 332 status = "disabled"; 333 }; 334 335 wdt2: watchdog@13000000 { 336 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 337 reg = <0 0x13000000 0 0x400>; 338 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 339 clock-names = "pclk", "oscclk"; 340 resets = <&cpg 0x77>; 341 power-domains = <&cpg>; 342 status = "disabled"; 343 }; 344 345 wdt3: watchdog@13000400 { 346 compatible = "renesas,r9a09g056-wdt", "renesas,r9a09g057-wdt"; 347 reg = <0 0x13000400 0 0x400>; 348 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 349 clock-names = "pclk", "oscclk"; 350 resets = <&cpg 0x78>; 351 power-domains = <&cpg>; 352 status = "disabled"; 353 }; 354 355 scif: serial@11c01400 { 356 compatible = "renesas,scif-r9a09g056", 357 "renesas,scif-r9a09g057"; 358 reg = <0 0x11c01400 0 0x400>; 359 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 366 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 367 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 368 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 369 "tei", "tei-dri", "rxi-edge", "txi-edge"; 370 clocks = <&cpg CPG_MOD 0x8f>; 371 clock-names = "fck"; 372 power-domains = <&cpg>; 373 resets = <&cpg 0x95>; 374 status = "disabled"; 375 }; 376 377 i3c: i3c@12400000 { 378 compatible = "renesas,r9a09g056-i3c", "renesas,r9a09g047-i3c"; 379 reg = <0 0x12400000 0 0x10000>; 380 clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>; 381 clock-names = "pclk", "tclk", "pclkrw"; 382 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 387 <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 390 <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 391 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 396 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 398 interrupt-names = "ierr", "terr", "abort", "resp", 399 "cmd", "ibi", "rx", "tx", "rcv", 400 "st", "sp", "tend", "nack", 401 "al", "tmo", "wu"; 402 resets = <&cpg 0x96>, <&cpg 0x97>; 403 reset-names = "presetn", "tresetn"; 404 power-domains = <&cpg>; 405 #address-cells = <3>; 406 #size-cells = <0>; 407 status = "disabled"; 408 }; 409 410 i2c0: i2c@14400400 { 411 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 412 reg = <0 0x14400400 0 0x400>; 413 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 414 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 415 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 416 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 417 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 419 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 420 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 421 interrupt-names = "tei", "ri", "ti", "spi", "sti", 422 "naki", "ali", "tmoi"; 423 clocks = <&cpg CPG_MOD 0x94>; 424 resets = <&cpg 0x98>; 425 power-domains = <&cpg>; 426 #address-cells = <1>; 427 #size-cells = <0>; 428 status = "disabled"; 429 }; 430 431 i2c1: i2c@14400800 { 432 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 433 reg = <0 0x14400800 0 0x400>; 434 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 436 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 437 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 438 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 439 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 442 interrupt-names = "tei", "ri", "ti", "spi", "sti", 443 "naki", "ali", "tmoi"; 444 clocks = <&cpg CPG_MOD 0x95>; 445 resets = <&cpg 0x99>; 446 power-domains = <&cpg>; 447 #address-cells = <1>; 448 #size-cells = <0>; 449 status = "disabled"; 450 }; 451 452 i2c2: i2c@14400c00 { 453 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 454 reg = <0 0x14400c00 0 0x400>; 455 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 457 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 458 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 463 interrupt-names = "tei", "ri", "ti", "spi", "sti", 464 "naki", "ali", "tmoi"; 465 clocks = <&cpg CPG_MOD 0x96>; 466 resets = <&cpg 0x9a>; 467 power-domains = <&cpg>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 status = "disabled"; 471 }; 472 473 i2c3: i2c@14401000 { 474 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 475 reg = <0 0x14401000 0 0x400>; 476 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 478 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 479 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 484 interrupt-names = "tei", "ri", "ti", "spi", "sti", 485 "naki", "ali", "tmoi"; 486 clocks = <&cpg CPG_MOD 0x97>; 487 resets = <&cpg 0x9b>; 488 power-domains = <&cpg>; 489 #address-cells = <1>; 490 #size-cells = <0>; 491 status = "disabled"; 492 }; 493 494 i2c4: i2c@14401400 { 495 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 496 reg = <0 0x14401400 0 0x400>; 497 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 499 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 500 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 505 interrupt-names = "tei", "ri", "ti", "spi", "sti", 506 "naki", "ali", "tmoi"; 507 clocks = <&cpg CPG_MOD 0x98>; 508 resets = <&cpg 0x9c>; 509 power-domains = <&cpg>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 status = "disabled"; 513 }; 514 515 i2c5: i2c@14401800 { 516 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 517 reg = <0 0x14401800 0 0x400>; 518 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 520 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 521 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 523 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 524 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 525 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 526 interrupt-names = "tei", "ri", "ti", "spi", "sti", 527 "naki", "ali", "tmoi"; 528 clocks = <&cpg CPG_MOD 0x99>; 529 resets = <&cpg 0x9d>; 530 power-domains = <&cpg>; 531 #address-cells = <1>; 532 #size-cells = <0>; 533 status = "disabled"; 534 }; 535 536 i2c6: i2c@14401c00 { 537 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 538 reg = <0 0x14401c00 0 0x400>; 539 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 541 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 542 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 547 interrupt-names = "tei", "ri", "ti", "spi", "sti", 548 "naki", "ali", "tmoi"; 549 clocks = <&cpg CPG_MOD 0x9a>; 550 resets = <&cpg 0x9e>; 551 power-domains = <&cpg>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 status = "disabled"; 555 }; 556 557 i2c7: i2c@14402000 { 558 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 559 reg = <0 0x14402000 0 0x400>; 560 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 562 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 563 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 568 interrupt-names = "tei", "ri", "ti", "spi", "sti", 569 "naki", "ali", "tmoi"; 570 clocks = <&cpg CPG_MOD 0x9b>; 571 resets = <&cpg 0x9f>; 572 power-domains = <&cpg>; 573 #address-cells = <1>; 574 #size-cells = <0>; 575 status = "disabled"; 576 }; 577 578 i2c8: i2c@11c01000 { 579 compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057"; 580 reg = <0 0x11c01000 0 0x400>; 581 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 582 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 583 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 584 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 585 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 589 interrupt-names = "tei", "ri", "ti", "spi", "sti", 590 "naki", "ali", "tmoi"; 591 clocks = <&cpg CPG_MOD 0x93>; 592 resets = <&cpg 0xa0>; 593 power-domains = <&cpg>; 594 #address-cells = <1>; 595 #size-cells = <0>; 596 status = "disabled"; 597 }; 598 599 gpu: gpu@14850000 { 600 compatible = "renesas,r9a09g056-mali", 601 "arm,mali-bifrost"; 602 reg = <0x0 0x14850000 0x0 0x10000>; 603 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 607 interrupt-names = "job", "mmu", "gpu", "event"; 608 clocks = <&cpg CPG_MOD 0xf0>, 609 <&cpg CPG_MOD 0xf1>, 610 <&cpg CPG_MOD 0xf2>; 611 clock-names = "gpu", "bus", "bus_ace"; 612 resets = <&cpg 0xdd>, 613 <&cpg 0xde>, 614 <&cpg 0xdf>; 615 reset-names = "rst", "axi_rst", "ace_rst"; 616 power-domains = <&cpg>; 617 operating-points-v2 = <&gpu_opp_table>; 618 status = "disabled"; 619 }; 620 621 gic: interrupt-controller@14900000 { 622 compatible = "arm,gic-v3"; 623 reg = <0x0 0x14900000 0 0x20000>, 624 <0x0 0x14940000 0 0x80000>; 625 #interrupt-cells = <3>; 626 #address-cells = <0>; 627 interrupt-controller; 628 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 629 }; 630 631 ohci0: usb@15800000 { 632 compatible = "generic-ohci"; 633 reg = <0 0x15800000 0 0x100>; 634 interrupts = <GIC_SPI 742 IRQ_TYPE_LEVEL_HIGH>; 635 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 636 resets = <&usb20phyrst>, <&cpg 0xac>; 637 phys = <&usb2_phy0 1>; 638 phy-names = "usb"; 639 power-domains = <&cpg>; 640 status = "disabled"; 641 }; 642 643 ehci0: usb@15800100 { 644 compatible = "generic-ehci"; 645 reg = <0 0x15800100 0 0x100>; 646 interrupts = <GIC_SPI 743 IRQ_TYPE_LEVEL_HIGH>; 647 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb6>; 648 resets = <&usb20phyrst>, <&cpg 0xac>; 649 phys = <&usb2_phy0 2>; 650 phy-names = "usb"; 651 companion = <&ohci0>; 652 power-domains = <&cpg>; 653 status = "disabled"; 654 }; 655 656 usb2_phy0: usb-phy@15800200 { 657 compatible = "renesas,usb2-phy-r9a09g056", "renesas,usb2-phy-r9a09g057"; 658 reg = <0 0x15800200 0 0x700>; 659 interrupts = <GIC_SPI 745 IRQ_TYPE_LEVEL_HIGH>; 660 clocks = <&cpg CPG_MOD 0xb3>, 661 <&cpg CPG_CORE R9A09G056_USB2_0_CLK_CORE0>; 662 clock-names = "fck", "usb_x1"; 663 resets = <&usb20phyrst>; 664 #phy-cells = <1>; 665 power-domains = <&cpg>; 666 status = "disabled"; 667 }; 668 669 hsusb: usb@15820000 { 670 compatible = "renesas,usbhs-r9a09g056", 671 "renesas,rzg2l-usbhs"; 672 reg = <0 0x15820000 0 0x10000>; 673 interrupts = <GIC_SPI 751 IRQ_TYPE_EDGE_RISING>, 674 <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 753 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 754 IRQ_TYPE_LEVEL_HIGH>; 677 clocks = <&cpg CPG_MOD 0xb3>, <&cpg CPG_MOD 0xb5>; 678 resets = <&usb20phyrst>, 679 <&cpg 0xae>; 680 phys = <&usb2_phy0 3>; 681 phy-names = "usb"; 682 power-domains = <&cpg>; 683 status = "disabled"; 684 }; 685 686 usb20phyrst: usb20phy-reset@15830000 { 687 compatible = "renesas,r9a09g056-usb2phy-reset", 688 "renesas,r9a09g057-usb2phy-reset"; 689 reg = <0 0x15830000 0 0x10000>; 690 clocks = <&cpg CPG_MOD 0xb6>; 691 resets = <&cpg 0xaf>; 692 power-domains = <&cpg>; 693 #reset-cells = <0>; 694 status = "disabled"; 695 }; 696 697 sdhi0: mmc@15c00000 { 698 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 699 reg = <0x0 0x15c00000 0 0x10000>; 700 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 703 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 704 clock-names = "core", "clkh", "cd", "aclk"; 705 resets = <&cpg 0xa7>; 706 power-domains = <&cpg>; 707 status = "disabled"; 708 709 sdhi0_vqmmc: vqmmc-regulator { 710 regulator-name = "SDHI0-VQMMC"; 711 regulator-min-microvolt = <1800000>; 712 regulator-max-microvolt = <3300000>; 713 status = "disabled"; 714 }; 715 }; 716 717 sdhi1: mmc@15c10000 { 718 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 719 reg = <0x0 0x15c10000 0 0x10000>; 720 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 723 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 724 clock-names = "core", "clkh", "cd", "aclk"; 725 resets = <&cpg 0xa8>; 726 power-domains = <&cpg>; 727 status = "disabled"; 728 729 sdhi1_vqmmc: vqmmc-regulator { 730 regulator-name = "SDHI1-VQMMC"; 731 regulator-min-microvolt = <1800000>; 732 regulator-max-microvolt = <3300000>; 733 status = "disabled"; 734 }; 735 }; 736 737 sdhi2: mmc@15c20000 { 738 compatible = "renesas,sdhi-r9a09g056", "renesas,sdhi-r9a09g057"; 739 reg = <0x0 0x15c20000 0 0x10000>; 740 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 742 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 743 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 744 clock-names = "core", "clkh", "cd", "aclk"; 745 resets = <&cpg 0xa9>; 746 power-domains = <&cpg>; 747 status = "disabled"; 748 749 sdhi2_vqmmc: vqmmc-regulator { 750 regulator-name = "SDHI2-VQMMC"; 751 regulator-min-microvolt = <1800000>; 752 regulator-max-microvolt = <3300000>; 753 status = "disabled"; 754 }; 755 }; 756 757 eth0: ethernet@15c30000 { 758 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 759 "snps,dwmac-5.20"; 760 reg = <0 0x15c30000 0 0x10000>; 761 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 772 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 773 "rx-queue-0", "rx-queue-1", "rx-queue-2", 774 "rx-queue-3", "tx-queue-0", "tx-queue-1", 775 "tx-queue-2", "tx-queue-3"; 776 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 777 <&cpg CPG_CORE R9A09G056_GBETH_0_CLK_PTP_REF_I>, 778 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 779 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 780 clock-names = "stmmaceth", "pclk", "ptp_ref", 781 "tx", "rx", "tx-180", "rx-180"; 782 resets = <&cpg 0xb0>; 783 power-domains = <&cpg>; 784 snps,multicast-filter-bins = <256>; 785 snps,perfect-filter-entries = <128>; 786 rx-fifo-depth = <8192>; 787 tx-fifo-depth = <8192>; 788 snps,fixed-burst; 789 snps,no-pbl-x8; 790 snps,force_thresh_dma_mode; 791 snps,axi-config = <&stmmac_axi_setup>; 792 snps,mtl-rx-config = <&mtl_rx_setup0>; 793 snps,mtl-tx-config = <&mtl_tx_setup0>; 794 snps,txpbl = <32>; 795 snps,rxpbl = <32>; 796 status = "disabled"; 797 798 mdio0: mdio { 799 compatible = "snps,dwmac-mdio"; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 }; 803 804 mtl_rx_setup0: rx-queues-config { 805 snps,rx-queues-to-use = <4>; 806 snps,rx-sched-sp; 807 808 queue0 { 809 snps,dcb-algorithm; 810 snps,priority = <0x1>; 811 snps,map-to-dma-channel = <0>; 812 }; 813 814 queue1 { 815 snps,dcb-algorithm; 816 snps,priority = <0x2>; 817 snps,map-to-dma-channel = <1>; 818 }; 819 820 queue2 { 821 snps,dcb-algorithm; 822 snps,priority = <0x4>; 823 snps,map-to-dma-channel = <2>; 824 }; 825 826 queue3 { 827 snps,dcb-algorithm; 828 snps,priority = <0x8>; 829 snps,map-to-dma-channel = <3>; 830 }; 831 }; 832 833 mtl_tx_setup0: tx-queues-config { 834 snps,tx-queues-to-use = <4>; 835 836 queue0 { 837 snps,dcb-algorithm; 838 snps,priority = <0x1>; 839 }; 840 841 queue1 { 842 snps,dcb-algorithm; 843 snps,priority = <0x2>; 844 }; 845 846 queue2 { 847 snps,dcb-algorithm; 848 snps,priority = <0x4>; 849 }; 850 851 queue3 { 852 snps,dcb-algorithm; 853 snps,priority = <0x8>; 854 }; 855 }; 856 }; 857 858 eth1: ethernet@15c40000 { 859 compatible = "renesas,r9a09g056-gbeth", "renesas,rzv2h-gbeth", 860 "snps,dwmac-5.20"; 861 reg = <0 0x15c40000 0 0x10000>; 862 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 863 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 864 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 865 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 866 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 867 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 874 "rx-queue-0", "rx-queue-1", "rx-queue-2", 875 "rx-queue-3", "tx-queue-0", "tx-queue-1", 876 "tx-queue-2", "tx-queue-3"; 877 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 878 <&cpg CPG_CORE R9A09G056_GBETH_1_CLK_PTP_REF_I>, 879 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 880 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 881 clock-names = "stmmaceth", "pclk", "ptp_ref", 882 "tx", "rx", "tx-180", "rx-180"; 883 resets = <&cpg 0xb1>; 884 power-domains = <&cpg>; 885 snps,multicast-filter-bins = <256>; 886 snps,perfect-filter-entries = <128>; 887 rx-fifo-depth = <8192>; 888 tx-fifo-depth = <8192>; 889 snps,fixed-burst; 890 snps,no-pbl-x8; 891 snps,force_thresh_dma_mode; 892 snps,axi-config = <&stmmac_axi_setup>; 893 snps,mtl-rx-config = <&mtl_rx_setup1>; 894 snps,mtl-tx-config = <&mtl_tx_setup1>; 895 snps,txpbl = <32>; 896 snps,rxpbl = <32>; 897 status = "disabled"; 898 899 mdio1: mdio { 900 compatible = "snps,dwmac-mdio"; 901 #address-cells = <1>; 902 #size-cells = <0>; 903 }; 904 905 mtl_rx_setup1: rx-queues-config { 906 snps,rx-queues-to-use = <4>; 907 snps,rx-sched-sp; 908 909 queue0 { 910 snps,dcb-algorithm; 911 snps,priority = <0x1>; 912 snps,map-to-dma-channel = <0>; 913 }; 914 915 queue1 { 916 snps,dcb-algorithm; 917 snps,priority = <0x2>; 918 snps,map-to-dma-channel = <1>; 919 }; 920 921 queue2 { 922 snps,dcb-algorithm; 923 snps,priority = <0x4>; 924 snps,map-to-dma-channel = <2>; 925 }; 926 927 queue3 { 928 snps,dcb-algorithm; 929 snps,priority = <0x8>; 930 snps,map-to-dma-channel = <3>; 931 }; 932 }; 933 934 mtl_tx_setup1: tx-queues-config { 935 snps,tx-queues-to-use = <4>; 936 937 queue0 { 938 snps,dcb-algorithm; 939 snps,priority = <0x1>; 940 }; 941 942 queue1 { 943 snps,dcb-algorithm; 944 snps,priority = <0x2>; 945 }; 946 947 queue2 { 948 snps,dcb-algorithm; 949 snps,priority = <0x4>; 950 }; 951 952 queue3 { 953 snps,dcb-algorithm; 954 snps,priority = <0x8>; 955 }; 956 }; 957 }; 958 }; 959 960 stmmac_axi_setup: stmmac-axi-config { 961 snps,lpi_en; 962 snps,wr_osr_lmt = <0xf>; 963 snps,rd_osr_lmt = <0xf>; 964 snps,blen = <16 8 4 0 0 0 0>; 965 }; 966 967 timer { 968 compatible = "arm,armv8-timer"; 969 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 970 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 971 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 972 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 973 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 974 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 975 }; 976};
~/
Read-only file preview.