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r9a09g047.dtsi
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linux-6.19.14/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/G3E SoC 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g047-cpg.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/ { 12 compatible = "renesas,r9a09g047"; 13 #address-cells = <2>; 14 #size-cells = <2>; 15 interrupt-parent = <&gic>; 16 17 audio_extal_clk: audio-clk { 18 compatible = "fixed-clock"; 19 #clock-cells = <0>; 20 /* This value must be overridden by the board */ 21 clock-frequency = <0>; 22 }; 23 24 /* 25 * The default cluster table is based on the assumption that the PLLCA55 clock 26 * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to 27 * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be 28 * clocked to 1.8GHz as well). The table below should be overridden in the board 29 * DTS based on the PLLCA55 clock frequency. 30 */ 31 cluster0_opp: opp-table-0 { 32 compatible = "operating-points-v2"; 33 34 opp-1700000000 { 35 opp-hz = /bits/ 64 <1700000000>; 36 opp-microvolt = <900000>; 37 clock-latency-ns = <300000>; 38 }; 39 opp-850000000 { 40 opp-hz = /bits/ 64 <850000000>; 41 opp-microvolt = <800000>; 42 clock-latency-ns = <300000>; 43 }; 44 opp-425000000 { 45 opp-hz = /bits/ 64 <425000000>; 46 opp-microvolt = <800000>; 47 clock-latency-ns = <300000>; 48 }; 49 opp-212500000 { 50 opp-hz = /bits/ 64 <212500000>; 51 opp-microvolt = <800000>; 52 clock-latency-ns = <300000>; 53 opp-suspend; 54 }; 55 }; 56 57 cpus { 58 #address-cells = <1>; 59 #size-cells = <0>; 60 61 cpu0: cpu@0 { 62 compatible = "arm,cortex-a55"; 63 reg = <0>; 64 device_type = "cpu"; 65 next-level-cache = <&L3_CA55>; 66 enable-method = "psci"; 67 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK0>; 68 #cooling-cells = <2>; 69 operating-points-v2 = <&cluster0_opp>; 70 }; 71 72 cpu1: cpu@100 { 73 compatible = "arm,cortex-a55"; 74 reg = <0x100>; 75 device_type = "cpu"; 76 next-level-cache = <&L3_CA55>; 77 enable-method = "psci"; 78 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK1>; 79 #cooling-cells = <2>; 80 operating-points-v2 = <&cluster0_opp>; 81 }; 82 83 cpu2: cpu@200 { 84 compatible = "arm,cortex-a55"; 85 reg = <0x200>; 86 device_type = "cpu"; 87 next-level-cache = <&L3_CA55>; 88 enable-method = "psci"; 89 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK2>; 90 #cooling-cells = <2>; 91 operating-points-v2 = <&cluster0_opp>; 92 }; 93 94 cpu3: cpu@300 { 95 compatible = "arm,cortex-a55"; 96 reg = <0x300>; 97 device_type = "cpu"; 98 next-level-cache = <&L3_CA55>; 99 enable-method = "psci"; 100 clocks = <&cpg CPG_CORE R9A09G047_CA55_0_CORECLK3>; 101 #cooling-cells = <2>; 102 operating-points-v2 = <&cluster0_opp>; 103 }; 104 105 L3_CA55: cache-controller-0 { 106 compatible = "cache"; 107 cache-unified; 108 cache-size = <0x100000>; 109 cache-level = <3>; 110 }; 111 }; 112 113 gpu_opp_table: opp-table-1 { 114 compatible = "operating-points-v2"; 115 116 opp-630000000 { 117 opp-hz = /bits/ 64 <630000000>; 118 opp-microvolt = <800000>; 119 }; 120 121 opp-315000000 { 122 opp-hz = /bits/ 64 <315000000>; 123 opp-microvolt = <800000>; 124 }; 125 126 opp-157500000 { 127 opp-hz = /bits/ 64 <157500000>; 128 opp-microvolt = <800000>; 129 }; 130 131 opp-78750000 { 132 opp-hz = /bits/ 64 <78750000>; 133 opp-microvolt = <800000>; 134 }; 135 136 opp-19687500 { 137 opp-hz = /bits/ 64 <19687500>; 138 opp-microvolt = <800000>; 139 }; 140 }; 141 142 psci { 143 compatible = "arm,psci-1.0", "arm,psci-0.2"; 144 method = "smc"; 145 }; 146 147 qextal_clk: qextal-clk { 148 compatible = "fixed-clock"; 149 #clock-cells = <0>; 150 /* This value must be overridden by the board */ 151 clock-frequency = <0>; 152 }; 153 154 rtxin_clk: rtxin-clk { 155 compatible = "fixed-clock"; 156 #clock-cells = <0>; 157 /* This value must be overridden by the board */ 158 clock-frequency = <0>; 159 }; 160 161 soc: soc { 162 compatible = "simple-bus"; 163 #address-cells = <2>; 164 #size-cells = <2>; 165 ranges; 166 167 icu: interrupt-controller@10400000 { 168 compatible = "renesas,r9a09g047-icu"; 169 reg = <0 0x10400000 0 0x10000>; 170 #interrupt-cells = <2>; 171 #address-cells = <0>; 172 interrupt-controller; 173 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 174 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 175 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 176 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 177 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>, 203 <GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 204 <GIC_SPI 433 IRQ_TYPE_LEVEL_HIGH>, 205 <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 206 <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 207 <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, 208 <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, 209 <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 210 <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, 211 <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, 212 <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 215 <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 216 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>, 217 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 218 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 219 <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 220 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 262 IRQ_TYPE_EDGE_RISING>, 223 <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>, 224 <GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 225 <GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, 226 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 227 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 228 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 229 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 230 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>; 231 interrupt-names = "nmi", 232 "port_irq0", "port_irq1", "port_irq2", 233 "port_irq3", "port_irq4", "port_irq5", 234 "port_irq6", "port_irq7", "port_irq8", 235 "port_irq9", "port_irq10", "port_irq11", 236 "port_irq12", "port_irq13", "port_irq14", 237 "port_irq15", 238 "tint0", "tint1", "tint2", "tint3", 239 "tint4", "tint5", "tint6", "tint7", 240 "tint8", "tint9", "tint10", "tint11", 241 "tint12", "tint13", "tint14", "tint15", 242 "tint16", "tint17", "tint18", "tint19", 243 "tint20", "tint21", "tint22", "tint23", 244 "tint24", "tint25", "tint26", "tint27", 245 "tint28", "tint29", "tint30", "tint31", 246 "int-ca55-0", "int-ca55-1", 247 "int-ca55-2", "int-ca55-3", 248 "icu-error-ca55", 249 "gpt-u0-gtciada", "gpt-u0-gtciadb", 250 "gpt-u1-gtciada", "gpt-u1-gtciadb"; 251 clocks = <&cpg CPG_MOD 0x5>; 252 power-domains = <&cpg>; 253 resets = <&cpg 0x36>; 254 }; 255 256 pinctrl: pinctrl@10410000 { 257 compatible = "renesas,r9a09g047-pinctrl"; 258 reg = <0 0x10410000 0 0x10000>; 259 clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>; 260 gpio-controller; 261 #gpio-cells = <2>; 262 gpio-ranges = <&pinctrl 0 0 232>; 263 #interrupt-cells = <2>; 264 interrupt-controller; 265 interrupt-parent = <&icu>; 266 power-domains = <&cpg>; 267 resets = <&cpg 0xa5>, <&cpg 0xa6>; 268 }; 269 270 cpg: clock-controller@10420000 { 271 compatible = "renesas,r9a09g047-cpg"; 272 reg = <0 0x10420000 0 0x10000>; 273 clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>; 274 clock-names = "audio_extal", "rtxin", "qextal"; 275 #clock-cells = <2>; 276 #reset-cells = <1>; 277 #power-domain-cells = <0>; 278 }; 279 280 sys: system-controller@10430000 { 281 compatible = "renesas,r9a09g047-sys"; 282 reg = <0 0x10430000 0 0x10000>; 283 clocks = <&cpg CPG_CORE R9A09G047_SYS_0_PCLK>; 284 resets = <&cpg 0x30>; 285 }; 286 287 xspi: spi@11030000 { 288 compatible = "renesas,r9a09g047-xspi"; 289 reg = <0 0x11030000 0 0x10000>, 290 <0 0x20000000 0 0x10000000>; 291 reg-names = "regs", "dirmap"; 292 interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>, 293 <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>; 294 interrupt-names = "pulse", "err_pulse"; 295 clocks = <&cpg CPG_MOD 0x9f>, 296 <&cpg CPG_MOD 0xa0>, 297 <&cpg CPG_CORE R9A09G047_SPI_CLK_SPI>, 298 <&cpg CPG_MOD 0xa1>; 299 clock-names = "ahb", "axi", "spi", "spix2"; 300 resets = <&cpg 0xa3>, <&cpg 0xa4>; 301 reset-names = "hresetn", "aresetn"; 302 power-domains = <&cpg>; 303 #address-cells = <1>; 304 #size-cells = <0>; 305 status = "disabled"; 306 }; 307 308 dmac0: dma-controller@11400000 { 309 compatible = "renesas,r9a09g047-dmac", 310 "renesas,r9a09g057-dmac"; 311 reg = <0 0x11400000 0 0x10000>; 312 interrupts = <GIC_SPI 499 IRQ_TYPE_EDGE_RISING>, 313 <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>, 314 <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>, 315 <GIC_SPI 91 IRQ_TYPE_EDGE_RISING>, 316 <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>, 317 <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>, 318 <GIC_SPI 94 IRQ_TYPE_EDGE_RISING>, 319 <GIC_SPI 95 IRQ_TYPE_EDGE_RISING>, 320 <GIC_SPI 96 IRQ_TYPE_EDGE_RISING>, 321 <GIC_SPI 97 IRQ_TYPE_EDGE_RISING>, 322 <GIC_SPI 98 IRQ_TYPE_EDGE_RISING>, 323 <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>, 324 <GIC_SPI 100 IRQ_TYPE_EDGE_RISING>, 325 <GIC_SPI 101 IRQ_TYPE_EDGE_RISING>, 326 <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>, 327 <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>, 328 <GIC_SPI 104 IRQ_TYPE_EDGE_RISING>; 329 interrupt-names = "error", 330 "ch0", "ch1", "ch2", "ch3", 331 "ch4", "ch5", "ch6", "ch7", 332 "ch8", "ch9", "ch10", "ch11", 333 "ch12", "ch13", "ch14", "ch15"; 334 clocks = <&cpg CPG_MOD 0x0>; 335 power-domains = <&cpg>; 336 resets = <&cpg 0x31>; 337 #dma-cells = <1>; 338 dma-channels = <16>; 339 renesas,icu = <&icu 4>; 340 }; 341 342 dmac1: dma-controller@14830000 { 343 compatible = "renesas,r9a09g047-dmac", 344 "renesas,r9a09g057-dmac"; 345 reg = <0 0x14830000 0 0x10000>; 346 interrupts = <GIC_SPI 495 IRQ_TYPE_EDGE_RISING>, 347 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 348 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 349 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 350 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 351 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 352 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 353 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 354 <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 355 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 356 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 357 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 358 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 359 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 360 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 361 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 362 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>; 363 interrupt-names = "error", 364 "ch0", "ch1", "ch2", "ch3", 365 "ch4", "ch5", "ch6", "ch7", 366 "ch8", "ch9", "ch10", "ch11", 367 "ch12", "ch13", "ch14", "ch15"; 368 clocks = <&cpg CPG_MOD 0x1>; 369 power-domains = <&cpg>; 370 resets = <&cpg 0x32>; 371 #dma-cells = <1>; 372 dma-channels = <16>; 373 renesas,icu = <&icu 0>; 374 }; 375 376 dmac2: dma-controller@14840000 { 377 compatible = "renesas,r9a09g047-dmac", 378 "renesas,r9a09g057-dmac"; 379 reg = <0 0x14840000 0 0x10000>; 380 interrupts = <GIC_SPI 496 IRQ_TYPE_EDGE_RISING>, 381 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 382 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 383 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 384 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 385 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 386 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 387 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>, 388 <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 389 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 390 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 391 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 392 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 393 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 394 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 395 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 396 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>; 397 interrupt-names = "error", 398 "ch0", "ch1", "ch2", "ch3", 399 "ch4", "ch5", "ch6", "ch7", 400 "ch8", "ch9", "ch10", "ch11", 401 "ch12", "ch13", "ch14", "ch15"; 402 clocks = <&cpg CPG_MOD 0x2>; 403 power-domains = <&cpg>; 404 resets = <&cpg 0x33>; 405 #dma-cells = <1>; 406 dma-channels = <16>; 407 renesas,icu = <&icu 1>; 408 }; 409 410 dmac3: dma-controller@12000000 { 411 compatible = "renesas,r9a09g047-dmac", 412 "renesas,r9a09g057-dmac"; 413 reg = <0 0x12000000 0 0x10000>; 414 interrupts = <GIC_SPI 497 IRQ_TYPE_EDGE_RISING>, 415 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 416 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 417 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 418 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 421 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>, 422 <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 423 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 424 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 425 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 426 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 427 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 428 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 429 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 430 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>; 431 interrupt-names = "error", 432 "ch0", "ch1", "ch2", "ch3", 433 "ch4", "ch5", "ch6", "ch7", 434 "ch8", "ch9", "ch10", "ch11", 435 "ch12", "ch13", "ch14", "ch15"; 436 clocks = <&cpg CPG_MOD 0x3>; 437 power-domains = <&cpg>; 438 resets = <&cpg 0x34>; 439 #dma-cells = <1>; 440 dma-channels = <16>; 441 renesas,icu = <&icu 2>; 442 }; 443 444 dmac4: dma-controller@12010000 { 445 compatible = "renesas,r9a09g047-dmac", 446 "renesas,r9a09g057-dmac"; 447 reg = <0 0x12010000 0 0x10000>; 448 interrupts = <GIC_SPI 498 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>, 456 <GIC_SPI 80 IRQ_TYPE_EDGE_RISING>, 457 <GIC_SPI 81 IRQ_TYPE_EDGE_RISING>, 458 <GIC_SPI 82 IRQ_TYPE_EDGE_RISING>, 459 <GIC_SPI 83 IRQ_TYPE_EDGE_RISING>, 460 <GIC_SPI 84 IRQ_TYPE_EDGE_RISING>, 461 <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>, 462 <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>, 463 <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>, 464 <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>; 465 interrupt-names = "error", 466 "ch0", "ch1", "ch2", "ch3", 467 "ch4", "ch5", "ch6", "ch7", 468 "ch8", "ch9", "ch10", "ch11", 469 "ch12", "ch13", "ch14", "ch15"; 470 clocks = <&cpg CPG_MOD 0x4>; 471 power-domains = <&cpg>; 472 resets = <&cpg 0x35>; 473 #dma-cells = <1>; 474 dma-channels = <16>; 475 renesas,icu = <&icu 3>; 476 }; 477 478 scif0: serial@11c01400 { 479 compatible = "renesas,scif-r9a09g047", "renesas,scif-r9a09g057"; 480 reg = <0 0x11c01400 0 0x400>; 481 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 536 IRQ_TYPE_EDGE_RISING>, 489 <GIC_SPI 537 IRQ_TYPE_EDGE_RISING>; 490 interrupt-names = "eri", "rxi", "txi", "bri", "dri", 491 "tei", "tei-dri", "rxi-edge", "txi-edge"; 492 clocks = <&cpg CPG_MOD 0x8f>; 493 clock-names = "fck"; 494 power-domains = <&cpg>; 495 resets = <&cpg 0x95>; 496 status = "disabled"; 497 }; 498 499 i3c: i3c@12400000 { 500 compatible = "renesas,r9a09g047-i3c"; 501 reg = <0 0x12400000 0 0x10000>; 502 clocks = <&cpg CPG_MOD 0x91>, 503 <&cpg CPG_MOD 0x92>, 504 <&cpg CPG_MOD 0x90>; 505 clock-names = "pclk", "tclk", "pclkrw"; 506 interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>, 510 <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>, 511 <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>, 512 <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>, 513 <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>, 514 <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>, 515 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; 522 interrupt-names = "ierr", "terr", "abort", "resp", 523 "cmd", "ibi", "rx", "tx", "rcv", 524 "st", "sp", "tend", "nack", "al", 525 "tmo", "wu"; 526 resets = <&cpg 0x96>, <&cpg 0x97>; 527 reset-names = "presetn", "tresetn"; 528 power-domains = <&cpg>; 529 #address-cells = <3>; 530 #size-cells = <0>; 531 status = "disabled"; 532 }; 533 534 canfd: can@12440000 { 535 compatible = "renesas,r9a09g047-canfd"; 536 reg = <0 0x12440000 0 0x40000>; 537 interrupts = <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 698 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 704 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 699 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 705 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH>; 557 interrupt-names = "g_err", "g_recc", 558 "ch0_err", "ch0_rec", "ch0_trx", 559 "ch1_err", "ch1_rec", "ch1_trx", 560 "ch2_err", "ch2_rec", "ch2_trx", 561 "ch3_err", "ch3_rec", "ch3_trx", 562 "ch4_err", "ch4_rec", "ch4_trx", 563 "ch5_err", "ch5_rec", "ch5_trx"; 564 clocks = <&cpg CPG_MOD 0x9c>, <&cpg CPG_MOD 0x9d>, 565 <&cpg CPG_MOD 0x9e>; 566 clock-names = "fck", "ram_clk", "can_clk"; 567 assigned-clocks = <&cpg CPG_MOD 0x9e>; 568 assigned-clock-rates = <80000000>; 569 resets = <&cpg 0xa1>, <&cpg 0xa2>; 570 reset-names = "rstp_n", "rstc_n"; 571 power-domains = <&cpg>; 572 status = "disabled"; 573 574 channel0 { 575 status = "disabled"; 576 }; 577 channel1 { 578 status = "disabled"; 579 }; 580 channel2 { 581 status = "disabled"; 582 }; 583 channel3 { 584 status = "disabled"; 585 }; 586 channel4 { 587 status = "disabled"; 588 }; 589 channel5 { 590 status = "disabled"; 591 }; 592 }; 593 594 wdt1: watchdog@14400000 { 595 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 596 reg = <0 0x14400000 0 0x400>; 597 clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; 598 clock-names = "pclk", "oscclk"; 599 resets = <&cpg 0x76>; 600 power-domains = <&cpg>; 601 status = "disabled"; 602 }; 603 604 wdt2: watchdog@13000000 { 605 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 606 reg = <0 0x13000000 0 0x400>; 607 clocks = <&cpg CPG_MOD 0x4f>, <&cpg CPG_MOD 0x50>; 608 clock-names = "pclk", "oscclk"; 609 resets = <&cpg 0x77>; 610 power-domains = <&cpg>; 611 status = "disabled"; 612 }; 613 614 wdt3: watchdog@13000400 { 615 compatible = "renesas,r9a09g047-wdt", "renesas,r9a09g057-wdt"; 616 reg = <0 0x13000400 0 0x400>; 617 clocks = <&cpg CPG_MOD 0x51>, <&cpg CPG_MOD 0x52>; 618 clock-names = "pclk", "oscclk"; 619 resets = <&cpg 0x78>; 620 power-domains = <&cpg>; 621 status = "disabled"; 622 }; 623 624 tsu: thermal@14002000 { 625 compatible = "renesas,r9a09g047-tsu"; 626 reg = <0 0x14002000 0 0x1000>; 627 interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, 628 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 629 interrupt-names = "adi", "adcmpi"; 630 clocks = <&cpg CPG_MOD 0x10a>; 631 resets = <&cpg 0xf8>; 632 power-domains = <&cpg>; 633 #thermal-sensor-cells = <0>; 634 renesas,tsu-trim = <&sys 0x330>; 635 }; 636 637 i2c0: i2c@14400400 { 638 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 639 reg = <0 0x14400400 0 0x400>; 640 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 507 IRQ_TYPE_EDGE_RISING>, 642 <GIC_SPI 506 IRQ_TYPE_EDGE_RISING>, 643 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 648 interrupt-names = "tei", "ri", "ti", "spi", "sti", 649 "naki", "ali", "tmoi"; 650 clocks = <&cpg CPG_MOD 0x94>; 651 resets = <&cpg 0x98>; 652 power-domains = <&cpg>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 status = "disabled"; 656 }; 657 658 i2c1: i2c@14400800 { 659 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 660 reg = <0 0x14400800 0 0x400>; 661 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 509 IRQ_TYPE_EDGE_RISING>, 663 <GIC_SPI 508 IRQ_TYPE_EDGE_RISING>, 664 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 669 interrupt-names = "tei", "ri", "ti", "spi", "sti", 670 "naki", "ali", "tmoi"; 671 clocks = <&cpg CPG_MOD 0x95>; 672 resets = <&cpg 0x99>; 673 power-domains = <&cpg>; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 status = "disabled"; 677 }; 678 679 i2c2: i2c@14400c00 { 680 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 681 reg = <0 0x14400c00 0 0x400>; 682 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 511 IRQ_TYPE_EDGE_RISING>, 684 <GIC_SPI 510 IRQ_TYPE_EDGE_RISING>, 685 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 690 interrupt-names = "tei", "ri", "ti", "spi", "sti", 691 "naki", "ali", "tmoi"; 692 clocks = <&cpg CPG_MOD 0x96>; 693 resets = <&cpg 0x9a>; 694 power-domains = <&cpg>; 695 #address-cells = <1>; 696 #size-cells = <0>; 697 status = "disabled"; 698 }; 699 700 i2c3: i2c@14401000 { 701 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 702 reg = <0 0x14401000 0 0x400>; 703 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 513 IRQ_TYPE_EDGE_RISING>, 705 <GIC_SPI 512 IRQ_TYPE_EDGE_RISING>, 706 <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, 707 <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 711 interrupt-names = "tei", "ri", "ti", "spi", "sti", 712 "naki", "ali", "tmoi"; 713 clocks = <&cpg CPG_MOD 0x97>; 714 resets = <&cpg 0x9b>; 715 power-domains = <&cpg>; 716 #address-cells = <1>; 717 #size-cells = <0>; 718 status = "disabled"; 719 }; 720 721 i2c4: i2c@14401400 { 722 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 723 reg = <0 0x14401400 0 0x400>; 724 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 515 IRQ_TYPE_EDGE_RISING>, 726 <GIC_SPI 514 IRQ_TYPE_EDGE_RISING>, 727 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>; 732 interrupt-names = "tei", "ri", "ti", "spi", "sti", 733 "naki", "ali", "tmoi"; 734 clocks = <&cpg CPG_MOD 0x98>; 735 resets = <&cpg 0x9c>; 736 power-domains = <&cpg>; 737 #address-cells = <1>; 738 #size-cells = <0>; 739 status = "disabled"; 740 }; 741 742 i2c5: i2c@14401800 { 743 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 744 reg = <0 0x14401800 0 0x400>; 745 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 517 IRQ_TYPE_EDGE_RISING>, 747 <GIC_SPI 516 IRQ_TYPE_EDGE_RISING>, 748 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 753 interrupt-names = "tei", "ri", "ti", "spi", "sti", 754 "naki", "ali", "tmoi"; 755 clocks = <&cpg CPG_MOD 0x99>; 756 resets = <&cpg 0x9d>; 757 power-domains = <&cpg>; 758 #address-cells = <1>; 759 #size-cells = <0>; 760 status = "disabled"; 761 }; 762 763 i2c6: i2c@14401c00 { 764 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 765 reg = <0 0x14401c00 0 0x400>; 766 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 519 IRQ_TYPE_EDGE_RISING>, 768 <GIC_SPI 518 IRQ_TYPE_EDGE_RISING>, 769 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>; 774 interrupt-names = "tei", "ri", "ti", "spi", "sti", 775 "naki", "ali", "tmoi"; 776 clocks = <&cpg CPG_MOD 0x9a>; 777 resets = <&cpg 0x9e>; 778 power-domains = <&cpg>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 status = "disabled"; 782 }; 783 784 i2c7: i2c@14402000 { 785 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 786 reg = <0 0x14402000 0 0x400>; 787 interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 521 IRQ_TYPE_EDGE_RISING>, 789 <GIC_SPI 520 IRQ_TYPE_EDGE_RISING>, 790 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 795 interrupt-names = "tei", "ri", "ti", "spi", "sti", 796 "naki", "ali", "tmoi"; 797 clocks = <&cpg CPG_MOD 0x9b>; 798 resets = <&cpg 0x9f>; 799 power-domains = <&cpg>; 800 #address-cells = <1>; 801 #size-cells = <0>; 802 status = "disabled"; 803 }; 804 805 i2c8: i2c@11c01000 { 806 compatible = "renesas,riic-r9a09g047", "renesas,riic-r9a09g057"; 807 reg = <0 0x11c01000 0 0x400>; 808 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 523 IRQ_TYPE_EDGE_RISING>, 810 <GIC_SPI 522 IRQ_TYPE_EDGE_RISING>, 811 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 812 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 813 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, 814 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 815 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 816 interrupt-names = "tei", "ri", "ti", "spi", "sti", 817 "naki", "ali", "tmoi"; 818 clocks = <&cpg CPG_MOD 0x93>; 819 resets = <&cpg 0xa0>; 820 power-domains = <&cpg>; 821 #address-cells = <1>; 822 #size-cells = <0>; 823 status = "disabled"; 824 }; 825 826 gpu: gpu@14850000 { 827 compatible = "renesas,r9a09g047-mali", 828 "arm,mali-bifrost"; 829 reg = <0x0 0x14850000 0x0 0x10000>; 830 interrupts = <GIC_SPI 884 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 883 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>; 834 interrupt-names = "job", "mmu", "gpu", "event"; 835 clocks = <&cpg CPG_MOD 0xf0>, 836 <&cpg CPG_MOD 0xf1>, 837 <&cpg CPG_MOD 0xf2>; 838 clock-names = "gpu", "bus", "bus_ace"; 839 power-domains = <&cpg>; 840 resets = <&cpg 0xdd>, <&cpg 0xde>, <&cpg 0xdf>; 841 reset-names = "rst", "axi_rst", "ace_rst"; 842 operating-points-v2 = <&gpu_opp_table>; 843 status = "disabled"; 844 }; 845 846 gic: interrupt-controller@14900000 { 847 compatible = "arm,gic-v3"; 848 reg = <0x0 0x14900000 0 0x20000>, 849 <0x0 0x14940000 0 0x80000>; 850 #interrupt-cells = <3>; 851 #address-cells = <0>; 852 interrupt-controller; 853 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 854 }; 855 856 sdhi0: mmc@15c00000 { 857 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 858 reg = <0x0 0x15c00000 0 0x10000>; 859 interrupts = <GIC_SPI 735 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 736 IRQ_TYPE_LEVEL_HIGH>; 861 clocks = <&cpg CPG_MOD 0xa3>, <&cpg CPG_MOD 0xa5>, 862 <&cpg CPG_MOD 0xa4>, <&cpg CPG_MOD 0xa6>; 863 clock-names = "core", "clkh", "cd", "aclk"; 864 resets = <&cpg 0xa7>; 865 power-domains = <&cpg>; 866 status = "disabled"; 867 868 sdhi0_vqmmc: vqmmc-regulator { 869 regulator-name = "SDHI0-VQMMC"; 870 regulator-min-microvolt = <1800000>; 871 regulator-max-microvolt = <3300000>; 872 status = "disabled"; 873 }; 874 }; 875 876 sdhi1: mmc@15c10000 { 877 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 878 reg = <0x0 0x15c10000 0 0x10000>; 879 interrupts = <GIC_SPI 737 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&cpg CPG_MOD 0xa7>, <&cpg CPG_MOD 0xa9>, 882 <&cpg CPG_MOD 0xa8>, <&cpg CPG_MOD 0xaa>; 883 clock-names = "core", "clkh", "cd", "aclk"; 884 resets = <&cpg 0xa8>; 885 power-domains = <&cpg>; 886 status = "disabled"; 887 888 sdhi1_vqmmc: vqmmc-regulator { 889 regulator-name = "SDHI1-VQMMC"; 890 regulator-min-microvolt = <1800000>; 891 regulator-max-microvolt = <3300000>; 892 status = "disabled"; 893 }; 894 }; 895 896 sdhi2: mmc@15c20000 { 897 compatible = "renesas,sdhi-r9a09g047", "renesas,sdhi-r9a09g057"; 898 reg = <0x0 0x15c20000 0 0x10000>; 899 interrupts = <GIC_SPI 739 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 740 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&cpg CPG_MOD 0xab>, <&cpg CPG_MOD 0xad>, 902 <&cpg CPG_MOD 0xac>, <&cpg CPG_MOD 0xae>; 903 clock-names = "core", "clkh", "cd", "aclk"; 904 resets = <&cpg 0xa9>; 905 power-domains = <&cpg>; 906 status = "disabled"; 907 908 sdhi2_vqmmc: vqmmc-regulator { 909 regulator-name = "SDHI2-VQMMC"; 910 regulator-min-microvolt = <1800000>; 911 regulator-max-microvolt = <3300000>; 912 status = "disabled"; 913 }; 914 }; 915 916 eth0: ethernet@15c30000 { 917 compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", 918 "snps,dwmac-5.20"; 919 reg = <0 0x15c30000 0 0x10000>; 920 clocks = <&cpg CPG_MOD 0xbd>, <&cpg CPG_MOD 0xbc>, 921 <&cpg CPG_CORE R9A09G047_GBETH_0_CLK_PTP_REF_I>, 922 <&cpg CPG_MOD 0xb8>, <&cpg CPG_MOD 0xb9>, 923 <&cpg CPG_MOD 0xba>, <&cpg CPG_MOD 0xbb>; 924 clock-names = "stmmaceth", "pclk", "ptp_ref", 925 "tx", "rx", "tx-180", "rx-180"; 926 interrupts = <GIC_SPI 765 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 767 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 766 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 775 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 768 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>; 937 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 938 "rx-queue-0", "rx-queue-1", "rx-queue-2", 939 "rx-queue-3", "tx-queue-0", "tx-queue-1", 940 "tx-queue-2", "tx-queue-3"; 941 resets = <&cpg 0xb0>; 942 power-domains = <&cpg>; 943 snps,multicast-filter-bins = <256>; 944 snps,perfect-filter-entries = <128>; 945 rx-fifo-depth = <8192>; 946 tx-fifo-depth = <8192>; 947 snps,mixed-burst; 948 snps,force_sf_dma_mode; 949 snps,axi-config = <&stmmac_axi_setup>; 950 snps,mtl-rx-config = <&mtl_rx_setup0>; 951 snps,mtl-tx-config = <&mtl_tx_setup0>; 952 snps,txpbl = <32>; 953 snps,rxpbl = <32>; 954 status = "disabled"; 955 956 mdio0: mdio { 957 compatible = "snps,dwmac-mdio"; 958 #address-cells = <1>; 959 #size-cells = <0>; 960 }; 961 962 mtl_rx_setup0: rx-queues-config { 963 snps,rx-queues-to-use = <4>; 964 snps,rx-sched-sp; 965 966 queue0 { 967 snps,dcb-algorithm; 968 snps,priority = <0x1>; 969 snps,map-to-dma-channel = <0>; 970 }; 971 972 queue1 { 973 snps,dcb-algorithm; 974 snps,priority = <0x2>; 975 snps,map-to-dma-channel = <1>; 976 }; 977 978 queue2 { 979 snps,dcb-algorithm; 980 snps,priority = <0x4>; 981 snps,map-to-dma-channel = <2>; 982 }; 983 984 queue3 { 985 snps,dcb-algorithm; 986 snps,priority = <0x8>; 987 snps,map-to-dma-channel = <3>; 988 }; 989 }; 990 991 mtl_tx_setup0: tx-queues-config { 992 snps,tx-queues-to-use = <4>; 993 994 queue0 { 995 snps,dcb-algorithm; 996 snps,priority = <0x1>; 997 }; 998 999 queue1 { 1000 snps,dcb-algorithm; 1001 snps,priority = <0x2>; 1002 }; 1003 1004 queue2 { 1005 snps,dcb-algorithm; 1006 snps,priority = <0x4>; 1007 }; 1008 1009 queue3 { 1010 snps,dcb-algorithm; 1011 snps,priority = <0x8>; 1012 }; 1013 }; 1014 }; 1015 1016 eth1: ethernet@15c40000 { 1017 compatible = "renesas,r9a09g047-gbeth", "renesas,rzv2h-gbeth", 1018 "snps,dwmac-5.20"; 1019 reg = <0 0x15c40000 0 0x10000>; 1020 clocks = <&cpg CPG_MOD 0xc3>, <&cpg CPG_MOD 0xc2>, 1021 <&cpg CPG_CORE R9A09G047_GBETH_1_CLK_PTP_REF_I>, 1022 <&cpg CPG_MOD 0xbe>, <&cpg CPG_MOD 0xbf>, 1023 <&cpg CPG_MOD 0xc0>, <&cpg CPG_MOD 0xc1>; 1024 clock-names = "stmmaceth", "pclk", "ptp_ref", 1025 "tx", "rx", "tx-180", "rx-180"; 1026 interrupts = <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>; 1037 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 1038 "rx-queue-0", "rx-queue-1", "rx-queue-2", 1039 "rx-queue-3", "tx-queue-0", "tx-queue-1", 1040 "tx-queue-2", "tx-queue-3"; 1041 resets = <&cpg 0xb1>; 1042 power-domains = <&cpg>; 1043 snps,multicast-filter-bins = <256>; 1044 snps,perfect-filter-entries = <128>; 1045 rx-fifo-depth = <8192>; 1046 tx-fifo-depth = <8192>; 1047 snps,mixed-burst; 1048 snps,force_sf_dma_mode; 1049 snps,axi-config = <&stmmac_axi_setup>; 1050 snps,mtl-rx-config = <&mtl_rx_setup1>; 1051 snps,mtl-tx-config = <&mtl_tx_setup1>; 1052 snps,txpbl = <32>; 1053 snps,rxpbl = <32>; 1054 status = "disabled"; 1055 1056 mdio1: mdio { 1057 compatible = "snps,dwmac-mdio"; 1058 #address-cells = <1>; 1059 #size-cells = <0>; 1060 }; 1061 1062 mtl_rx_setup1: rx-queues-config { 1063 snps,rx-queues-to-use = <4>; 1064 snps,rx-sched-sp; 1065 1066 queue0 { 1067 snps,dcb-algorithm; 1068 snps,priority = <0x1>; 1069 snps,map-to-dma-channel = <0>; 1070 }; 1071 1072 queue1 { 1073 snps,dcb-algorithm; 1074 snps,priority = <0x2>; 1075 snps,map-to-dma-channel = <1>; 1076 }; 1077 1078 queue2 { 1079 snps,dcb-algorithm; 1080 snps,priority = <0x4>; 1081 snps,map-to-dma-channel = <2>; 1082 }; 1083 1084 queue3 { 1085 snps,dcb-algorithm; 1086 snps,priority = <0x8>; 1087 snps,map-to-dma-channel = <3>; 1088 }; 1089 }; 1090 1091 mtl_tx_setup1: tx-queues-config { 1092 snps,tx-queues-to-use = <4>; 1093 1094 queue0 { 1095 snps,dcb-algorithm; 1096 snps,priority = <0x1>; 1097 }; 1098 1099 queue1 { 1100 snps,dcb-algorithm; 1101 snps,priority = <0x2>; 1102 }; 1103 1104 queue2 { 1105 snps,dcb-algorithm; 1106 snps,priority = <0x4>; 1107 }; 1108 1109 queue3 { 1110 snps,dcb-algorithm; 1111 snps,priority = <0x8>; 1112 }; 1113 }; 1114 }; 1115 1116 cru: video@16000000 { 1117 compatible = "renesas,r9a09g047-cru"; 1118 reg = <0 0x16000000 0 0x400>; 1119 clocks = <&cpg CPG_MOD 0xd3>, 1120 <&cpg CPG_MOD 0xd4>, 1121 <&cpg CPG_MOD 0xd2>; 1122 clock-names = "video", "apb", "axi"; 1123 interrupts = <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 840 IRQ_TYPE_EDGE_RISING>, 1126 <GIC_SPI 841 IRQ_TYPE_EDGE_RISING>, 1127 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>; 1128 interrupt-names = "image_conv", "axi_mst_err", 1129 "vd_addr_wend", "sd_addr_wend", 1130 "vsd_addr_wend"; 1131 resets = <&cpg 0xc5>, <&cpg 0xc6>; 1132 reset-names = "presetn", "aresetn"; 1133 power-domains = <&cpg>; 1134 status = "disabled"; 1135 1136 ports { 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 1140 port@1 { 1141 #address-cells = <1>; 1142 #size-cells = <0>; 1143 1144 reg = <1>; 1145 crucsi2: endpoint@0 { 1146 reg = <0>; 1147 remote-endpoint = <&csi2cru>; 1148 }; 1149 }; 1150 }; 1151 }; 1152 1153 csi2: csi2@16000400 { 1154 compatible = "renesas,r9a09g047-csi2", "renesas,r9a09g057-csi2"; 1155 reg = <0 0x16000400 0 0xc00>; 1156 interrupts = <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&cpg CPG_MOD 0xd3>, <&cpg CPG_MOD 0xd4>; 1158 clock-names = "video", "apb"; 1159 resets = <&cpg 0xc5>, <&cpg 0xc7>; 1160 reset-names = "presetn", "cmn-rstb"; 1161 power-domains = <&cpg>; 1162 status = "disabled"; 1163 1164 ports { 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 1168 port@0 { 1169 reg = <0>; 1170 }; 1171 1172 port@1 { 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 reg = <1>; 1176 1177 csi2cru: endpoint@0 { 1178 reg = <0>; 1179 remote-endpoint = <&crucsi2>; 1180 }; 1181 }; 1182 }; 1183 }; 1184 }; 1185 1186 stmmac_axi_setup: stmmac-axi-config { 1187 snps,lpi_en; 1188 snps,wr_osr_lmt = <0xf>; 1189 snps,rd_osr_lmt = <0xf>; 1190 snps,blen = <16 8 4 0 0 0 0>; 1191 }; 1192 1193 thermal-zones { 1194 cpu-thermal { 1195 polling-delay = <1000>; 1196 polling-delay-passive = <250>; 1197 thermal-sensors = <&tsu>; 1198 1199 cooling-maps { 1200 map0 { 1201 trip = <&target>; 1202 cooling-device = <&cpu0 0 3>, <&cpu1 0 3>, 1203 <&cpu2 0 3>, <&cpu3 0 3>; 1204 contribution = <1024>; 1205 }; 1206 }; 1207 1208 trips { 1209 target: trip-point { 1210 temperature = <95000>; 1211 hysteresis = <1000>; 1212 type = "passive"; 1213 }; 1214 1215 sensor_crit: sensor-crit { 1216 temperature = <120000>; 1217 hysteresis = <1000>; 1218 type = "critical"; 1219 }; 1220 }; 1221 }; 1222 }; 1223 1224 timer { 1225 compatible = "arm,armv8-timer"; 1226 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1227 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1228 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1229 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1230 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1231 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1232 }; 1233};
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