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r8a779h0.dtsi
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linux-6.19.14/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the R-Car V4M (R8A779H0) SoC 4 * 5 * Copyright (C) 2023 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r8a779h0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/renesas,r8a779h0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779h0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 /* External Audio clock - to be overridden by boards that provide it */ 19 audio_clkin: audio_clkin { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <0>; 23 }; 24 25 /* External CAN clock - to be overridden by boards that provide it */ 26 can_clk: can-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <0>; 30 }; 31 32 cluster0_opp: opp-table-0 { 33 compatible = "operating-points-v2"; 34 35 opp-500000000 { 36 opp-hz = /bits/ 64 <500000000>; 37 opp-microvolt = <825000>; 38 clock-latency-ns = <500000>; 39 }; 40 opp-1000000000 { 41 opp-hz = /bits/ 64 <1000000000>; 42 opp-microvolt = <825000>; 43 clock-latency-ns = <500000>; 44 }; 45 }; 46 47 cpus { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 cpu-map { 52 cluster0 { 53 core0 { 54 cpu = <&a76_0>; 55 }; 56 core1 { 57 cpu = <&a76_1>; 58 }; 59 core2 { 60 cpu = <&a76_2>; 61 }; 62 core3 { 63 cpu = <&a76_3>; 64 }; 65 }; 66 }; 67 68 a76_0: cpu@0 { 69 compatible = "arm,cortex-a76"; 70 reg = <0>; 71 device_type = "cpu"; 72 power-domains = <&sysc R8A779H0_PD_A1E0D0C0>; 73 next-level-cache = <&L3_CA76>; 74 enable-method = "psci"; 75 cpu-idle-states = <&CPU_SLEEP_0>; 76 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC0>; 77 operating-points-v2 = <&cluster0_opp>; 78 }; 79 80 a76_1: cpu@100 { 81 compatible = "arm,cortex-a76"; 82 reg = <0x100>; 83 device_type = "cpu"; 84 power-domains = <&sysc R8A779H0_PD_A1E0D0C1>; 85 next-level-cache = <&L3_CA76>; 86 enable-method = "psci"; 87 cpu-idle-states = <&CPU_SLEEP_0>; 88 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC1>; 89 operating-points-v2 = <&cluster0_opp>; 90 }; 91 92 a76_2: cpu@200 { 93 compatible = "arm,cortex-a76"; 94 reg = <0x200>; 95 device_type = "cpu"; 96 power-domains = <&sysc R8A779H0_PD_A1E0D0C2>; 97 next-level-cache = <&L3_CA76>; 98 enable-method = "psci"; 99 cpu-idle-states = <&CPU_SLEEP_0>; 100 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC2>; 101 operating-points-v2 = <&cluster0_opp>; 102 }; 103 104 a76_3: cpu@300 { 105 compatible = "arm,cortex-a76"; 106 reg = <0x300>; 107 device_type = "cpu"; 108 power-domains = <&sysc R8A779H0_PD_A1E0D0C3>; 109 next-level-cache = <&L3_CA76>; 110 enable-method = "psci"; 111 cpu-idle-states = <&CPU_SLEEP_0>; 112 clocks = <&cpg CPG_CORE R8A779H0_CLK_ZC3>; 113 operating-points-v2 = <&cluster0_opp>; 114 }; 115 116 idle-states { 117 entry-method = "psci"; 118 119 CPU_SLEEP_0: cpu-sleep-0 { 120 compatible = "arm,idle-state"; 121 arm,psci-suspend-param = <0x0010000>; 122 local-timer-stop; 123 entry-latency-us = <400>; 124 exit-latency-us = <500>; 125 min-residency-us = <4000>; 126 }; 127 }; 128 129 L3_CA76: cache-controller { 130 compatible = "cache"; 131 power-domains = <&sysc R8A779H0_PD_A2E0D0>; 132 cache-unified; 133 cache-level = <3>; 134 }; 135 }; 136 137 extal_clk: extal-clk { 138 compatible = "fixed-clock"; 139 #clock-cells = <0>; 140 /* This value must be overridden by the board */ 141 clock-frequency = <0>; 142 bootph-all; 143 }; 144 145 extalr_clk: extalr-clk { 146 compatible = "fixed-clock"; 147 #clock-cells = <0>; 148 /* This value must be overridden by the board */ 149 clock-frequency = <0>; 150 bootph-all; 151 }; 152 153 pcie0_clkref: pcie0-clkref { 154 compatible = "fixed-clock"; 155 #clock-cells = <0>; 156 /* This value must be overridden by the board */ 157 clock-frequency = <0>; 158 }; 159 160 pmu-a76 { 161 compatible = "arm,cortex-a76-pmu"; 162 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 163 }; 164 165 psci { 166 compatible = "arm,psci-1.0", "arm,psci-0.2"; 167 method = "smc"; 168 }; 169 170 /* External SCIF clocks - to be overridden by boards that provide them */ 171 scif_clk: scif-clk { 172 compatible = "fixed-clock"; 173 #clock-cells = <0>; 174 clock-frequency = <0>; 175 }; 176 177 scif_clk2: scif-clk2 { 178 compatible = "fixed-clock"; 179 #clock-cells = <0>; 180 clock-frequency = <0>; 181 }; 182 183 soc: soc { 184 compatible = "simple-bus"; 185 bootph-all; 186 187 #address-cells = <2>; 188 #size-cells = <2>; 189 ranges; 190 191 rwdt: watchdog@e6020000 { 192 compatible = "renesas,r8a779h0-wdt", 193 "renesas,rcar-gen4-wdt"; 194 reg = <0 0xe6020000 0 0x0c>; 195 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&cpg CPG_MOD 907>; 197 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 198 resets = <&cpg 907>; 199 status = "disabled"; 200 }; 201 202 swdt: watchdog@e6030000 { 203 compatible = "renesas,r8a779h0-wdt", "renesas,rcar-gen4-wdt"; 204 reg = <0 0xe6030000 0 0x0c>; 205 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 206 clocks = <&cpg CPG_CORE R8A779H0_CLK_OSC>; 207 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 208 resets = <&cpg 1128>; 209 status = "disabled"; 210 }; 211 212 pfc: pinctrl@e6050000 { 213 compatible = "renesas,pfc-r8a779h0"; 214 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 215 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, 216 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, 217 <0 0xe6061000 0 0x16c>, <0 0xe6061800 0 0x16c>; 218 bootph-all; 219 }; 220 221 gpio0: gpio@e6050180 { 222 compatible = "renesas,gpio-r8a779h0", 223 "renesas,rcar-gen4-gpio"; 224 reg = <0 0xe6050180 0 0x54>; 225 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>; 226 #gpio-cells = <2>; 227 gpio-controller; 228 gpio-ranges = <&pfc 0 0 19>; 229 #interrupt-cells = <2>; 230 interrupt-controller; 231 clocks = <&cpg CPG_MOD 915>; 232 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 233 resets = <&cpg 915>; 234 }; 235 236 gpio1: gpio@e6050980 { 237 compatible = "renesas,gpio-r8a779h0", 238 "renesas,rcar-gen4-gpio"; 239 reg = <0 0xe6050980 0 0x54>; 240 interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL_HIGH>; 241 #gpio-cells = <2>; 242 gpio-controller; 243 gpio-ranges = <&pfc 0 32 30>; 244 #interrupt-cells = <2>; 245 interrupt-controller; 246 clocks = <&cpg CPG_MOD 915>; 247 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 248 resets = <&cpg 915>; 249 }; 250 251 gpio2: gpio@e6058180 { 252 compatible = "renesas,gpio-r8a779h0", 253 "renesas,rcar-gen4-gpio"; 254 reg = <0 0xe6058180 0 0x54>; 255 interrupts = <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>; 256 #gpio-cells = <2>; 257 gpio-controller; 258 gpio-ranges = <&pfc 0 64 20>; 259 #interrupt-cells = <2>; 260 interrupt-controller; 261 clocks = <&cpg CPG_MOD 916>; 262 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 263 resets = <&cpg 916>; 264 }; 265 266 gpio3: gpio@e6058980 { 267 compatible = "renesas,gpio-r8a779h0", 268 "renesas,rcar-gen4-gpio"; 269 reg = <0 0xe6058980 0 0x54>; 270 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>; 271 #gpio-cells = <2>; 272 gpio-controller; 273 gpio-ranges = <&pfc 0 96 32>; 274 #interrupt-cells = <2>; 275 interrupt-controller; 276 clocks = <&cpg CPG_MOD 916>; 277 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 278 resets = <&cpg 916>; 279 }; 280 281 gpio4: gpio@e6060180 { 282 compatible = "renesas,gpio-r8a779h0", 283 "renesas,rcar-gen4-gpio"; 284 reg = <0 0xe6060180 0 0x54>; 285 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH>; 286 #gpio-cells = <2>; 287 gpio-controller; 288 gpio-ranges = <&pfc 0 128 25>; 289 #interrupt-cells = <2>; 290 interrupt-controller; 291 clocks = <&cpg CPG_MOD 917>; 292 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 293 resets = <&cpg 917>; 294 }; 295 296 gpio5: gpio@e6060980 { 297 compatible = "renesas,gpio-r8a779h0", 298 "renesas,rcar-gen4-gpio"; 299 reg = <0 0xe6060980 0 0x54>; 300 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>; 301 #gpio-cells = <2>; 302 gpio-controller; 303 gpio-ranges = <&pfc 0 160 21>; 304 #interrupt-cells = <2>; 305 interrupt-controller; 306 clocks = <&cpg CPG_MOD 917>; 307 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 308 resets = <&cpg 917>; 309 }; 310 311 gpio6: gpio@e6061180 { 312 compatible = "renesas,gpio-r8a779h0", 313 "renesas,rcar-gen4-gpio"; 314 reg = <0 0xe6061180 0 0x54>; 315 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>; 316 #gpio-cells = <2>; 317 gpio-controller; 318 gpio-ranges = <&pfc 0 192 21>; 319 #interrupt-cells = <2>; 320 interrupt-controller; 321 clocks = <&cpg CPG_MOD 917>; 322 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 323 resets = <&cpg 917>; 324 }; 325 326 gpio7: gpio@e6061980 { 327 compatible = "renesas,gpio-r8a779h0", 328 "renesas,rcar-gen4-gpio"; 329 reg = <0 0xe6061980 0 0x54>; 330 interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>; 331 #gpio-cells = <2>; 332 gpio-controller; 333 gpio-ranges = <&pfc 0 224 21>; 334 #interrupt-cells = <2>; 335 interrupt-controller; 336 clocks = <&cpg CPG_MOD 917>; 337 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 338 resets = <&cpg 917>; 339 }; 340 341 cmt0: timer@e60f0000 { 342 compatible = "renesas,r8a779h0-cmt0", 343 "renesas,rcar-gen4-cmt0"; 344 reg = <0 0xe60f0000 0 0x1004>; 345 interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&cpg CPG_MOD 910>; 348 clock-names = "fck"; 349 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 350 resets = <&cpg 910>; 351 status = "disabled"; 352 }; 353 354 cmt1: timer@e6130000 { 355 compatible = "renesas,r8a779h0-cmt1", 356 "renesas,rcar-gen4-cmt1"; 357 reg = <0 0xe6130000 0 0x1004>; 358 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 362 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 363 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&cpg CPG_MOD 911>; 367 clock-names = "fck"; 368 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 369 resets = <&cpg 911>; 370 status = "disabled"; 371 }; 372 373 cmt2: timer@e6140000 { 374 compatible = "renesas,r8a779h0-cmt1", 375 "renesas,rcar-gen4-cmt1"; 376 reg = <0 0xe6140000 0 0x1004>; 377 interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 383 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 384 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&cpg CPG_MOD 912>; 386 clock-names = "fck"; 387 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 388 resets = <&cpg 912>; 389 status = "disabled"; 390 }; 391 392 cmt3: timer@e6148000 { 393 compatible = "renesas,r8a779h0-cmt1", 394 "renesas,rcar-gen4-cmt1"; 395 reg = <0 0xe6148000 0 0x1004>; 396 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 397 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 398 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 399 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 400 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 401 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 402 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>; 404 clocks = <&cpg CPG_MOD 913>; 405 clock-names = "fck"; 406 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 407 resets = <&cpg 913>; 408 status = "disabled"; 409 }; 410 411 cpg: clock-controller@e6150000 { 412 compatible = "renesas,r8a779h0-cpg-mssr"; 413 reg = <0 0xe6150000 0 0x4000>; 414 clocks = <&extal_clk>, <&extalr_clk>; 415 clock-names = "extal", "extalr"; 416 #clock-cells = <2>; 417 #power-domain-cells = <0>; 418 #reset-cells = <1>; 419 bootph-all; 420 }; 421 422 rst: reset-controller@e6160000 { 423 compatible = "renesas,r8a779h0-rst"; 424 reg = <0 0xe6160000 0 0x4000>; 425 bootph-all; 426 }; 427 428 sysc: system-controller@e6180000 { 429 compatible = "renesas,r8a779h0-sysc"; 430 reg = <0 0xe6180000 0 0x4000>; 431 #power-domain-cells = <1>; 432 }; 433 434 tsc: thermal@e6198000 { 435 compatible = "renesas,r8a779h0-thermal"; 436 reg = <0 0xe6198000 0 0x200>, 437 <0 0xe61a0000 0 0x200>; 438 clocks = <&cpg CPG_MOD 919>; 439 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 440 resets = <&cpg 919>; 441 #thermal-sensor-cells = <1>; 442 }; 443 444 otp: otp@e61be000 { 445 compatible = "renesas,r8a779h0-otp"; 446 reg = <0 0xe61be000 0 0x1000>, <0 0xe61bf000 0 0x1000>; 447 }; 448 449 intc_ex: interrupt-controller@e61c0000 { 450 compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc"; 451 #interrupt-cells = <2>; 452 interrupt-controller; 453 reg = <0 0xe61c0000 0 0x200>; 454 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&cpg CPG_MOD 611>; 461 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 462 resets = <&cpg 611>; 463 }; 464 465 tmu0: timer@e61e0000 { 466 compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; 467 reg = <0 0xe61e0000 0 0x30>; 468 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>; 471 interrupt-names = "tuni0", "tuni1", "tuni2"; 472 clocks = <&cpg CPG_MOD 713>; 473 clock-names = "fck"; 474 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 475 resets = <&cpg 713>; 476 status = "disabled"; 477 }; 478 479 tmu1: timer@e6fc0000 { 480 compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; 481 reg = <0 0xe6fc0000 0 0x30>; 482 interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>; 486 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 487 clocks = <&cpg CPG_MOD 714>; 488 clock-names = "fck"; 489 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 490 resets = <&cpg 714>; 491 status = "disabled"; 492 }; 493 494 tmu2: timer@e6fd0000 { 495 compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; 496 reg = <0 0xe6fd0000 0 0x30>; 497 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 501 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 502 clocks = <&cpg CPG_MOD 715>; 503 clock-names = "fck"; 504 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 505 resets = <&cpg 715>; 506 status = "disabled"; 507 }; 508 509 tmu3: timer@e6fe0000 { 510 compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; 511 reg = <0 0xe6fe0000 0 0x30>; 512 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 513 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>; 516 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 517 clocks = <&cpg CPG_MOD 716>; 518 clock-names = "fck"; 519 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 520 resets = <&cpg 716>; 521 status = "disabled"; 522 }; 523 524 tmu4: timer@ffc00000 { 525 compatible = "renesas,tmu-r8a779h0", "renesas,tmu"; 526 reg = <0 0xffc00000 0 0x30>; 527 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 531 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 532 clocks = <&cpg CPG_MOD 717>; 533 clock-names = "fck"; 534 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 535 resets = <&cpg 717>; 536 status = "disabled"; 537 }; 538 539 i2c0: i2c@e6500000 { 540 compatible = "renesas,i2c-r8a779h0", 541 "renesas,rcar-gen4-i2c"; 542 reg = <0 0xe6500000 0 0x40>; 543 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>; 544 clocks = <&cpg CPG_MOD 518>; 545 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 546 resets = <&cpg 518>; 547 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 548 <&dmac2 0x91>, <&dmac2 0x90>; 549 dma-names = "tx", "rx", "tx", "rx"; 550 i2c-scl-internal-delay-ns = <110>; 551 #address-cells = <1>; 552 #size-cells = <0>; 553 status = "disabled"; 554 }; 555 556 i2c1: i2c@e6508000 { 557 compatible = "renesas,i2c-r8a779h0", 558 "renesas,rcar-gen4-i2c"; 559 reg = <0 0xe6508000 0 0x40>; 560 interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&cpg CPG_MOD 519>; 562 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 563 resets = <&cpg 519>; 564 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 565 <&dmac2 0x93>, <&dmac2 0x92>; 566 dma-names = "tx", "rx", "tx", "rx"; 567 i2c-scl-internal-delay-ns = <110>; 568 #address-cells = <1>; 569 #size-cells = <0>; 570 status = "disabled"; 571 }; 572 573 i2c2: i2c@e6510000 { 574 compatible = "renesas,i2c-r8a779h0", 575 "renesas,rcar-gen4-i2c"; 576 reg = <0 0xe6510000 0 0x40>; 577 interrupts = <GIC_SPI 612 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&cpg CPG_MOD 520>; 579 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 580 resets = <&cpg 520>; 581 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 582 <&dmac2 0x95>, <&dmac2 0x94>; 583 dma-names = "tx", "rx", "tx", "rx"; 584 i2c-scl-internal-delay-ns = <110>; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 i2c3: i2c@e66d0000 { 591 compatible = "renesas,i2c-r8a779h0", 592 "renesas,rcar-gen4-i2c"; 593 reg = <0 0xe66d0000 0 0x40>; 594 interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 595 clocks = <&cpg CPG_MOD 521>; 596 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 597 resets = <&cpg 521>; 598 dmas = <&dmac1 0x97>, <&dmac1 0x96>, 599 <&dmac2 0x97>, <&dmac2 0x96>; 600 dma-names = "tx", "rx", "tx", "rx"; 601 i2c-scl-internal-delay-ns = <110>; 602 #address-cells = <1>; 603 #size-cells = <0>; 604 status = "disabled"; 605 }; 606 607 hscif0: serial@e6540000 { 608 compatible = "renesas,hscif-r8a779h0", 609 "renesas,rcar-gen4-hscif", "renesas,hscif"; 610 reg = <0 0xe6540000 0 0x60>; 611 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cpg CPG_MOD 514>, 613 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, 614 <&scif_clk>; 615 clock-names = "fck", "brg_int", "scif_clk"; 616 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 617 resets = <&cpg 514>; 618 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 619 <&dmac2 0x31>, <&dmac2 0x30>; 620 dma-names = "tx", "rx", "tx", "rx"; 621 status = "disabled"; 622 }; 623 624 hscif1: serial@e6550000 { 625 compatible = "renesas,hscif-r8a779h0", 626 "renesas,rcar-gen4-hscif", "renesas,hscif"; 627 reg = <0 0xe6550000 0 0x60>; 628 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&cpg CPG_MOD 515>, 630 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, 631 <&scif_clk>; 632 clock-names = "fck", "brg_int", "scif_clk"; 633 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 634 resets = <&cpg 515>; 635 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 636 <&dmac2 0x33>, <&dmac2 0x32>; 637 dma-names = "tx", "rx", "tx", "rx"; 638 status = "disabled"; 639 }; 640 641 hscif2: serial@e6560000 { 642 compatible = "renesas,hscif-r8a779h0", 643 "renesas,rcar-gen4-hscif", "renesas,hscif"; 644 reg = <0 0xe6560000 0 0x60>; 645 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&cpg CPG_MOD 516>, 647 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, 648 <&scif_clk2>; 649 clock-names = "fck", "brg_int", "scif_clk"; 650 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 651 resets = <&cpg 516>; 652 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 653 <&dmac2 0x35>, <&dmac2 0x34>; 654 dma-names = "tx", "rx", "tx", "rx"; 655 status = "disabled"; 656 }; 657 658 hscif3: serial@e66a0000 { 659 compatible = "renesas,hscif-r8a779h0", 660 "renesas,rcar-gen4-hscif", "renesas,hscif"; 661 reg = <0 0xe66a0000 0 0x60>; 662 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cpg CPG_MOD 517>, 664 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, 665 <&scif_clk>; 666 clock-names = "fck", "brg_int", "scif_clk"; 667 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 668 resets = <&cpg 517>; 669 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 670 <&dmac2 0x37>, <&dmac2 0x36>; 671 dma-names = "tx", "rx", "tx", "rx"; 672 status = "disabled"; 673 }; 674 675 pciec0: pcie@e65d0000 { 676 compatible = "renesas,r8a779h0-pcie", 677 "renesas,rcar-gen4-pcie"; 678 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>, 679 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, 680 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, 681 <0 0xfe000000 0 0x400000>; 682 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; 683 interrupts = <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>; 687 interrupt-names = "msi", "dma", "sft_ce", "app"; 688 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; 689 clock-names = "core", "ref"; 690 power-domains = <&sysc R8A779H0_PD_A2PCIPHY>; 691 resets = <&cpg 624>; 692 reset-names = "pwr"; 693 max-link-speed = <4>; 694 num-lanes = <2>; 695 #address-cells = <3>; 696 #size-cells = <2>; 697 bus-range = <0x00 0xff>; 698 device_type = "pci"; 699 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>, 700 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>; 701 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 702 #interrupt-cells = <1>; 703 interrupt-map-mask = <0 0 0 7>; 704 interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 705 <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 706 <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 707 <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; 708 snps,enable-cdm-check; 709 status = "disabled"; 710 }; 711 712 pciec0_ep: pcie-ep@e65d0000 { 713 compatible = "renesas,r8a779h0-pcie-ep", 714 "renesas,rcar-gen4-pcie-ep"; 715 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>, 716 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, 717 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, 718 <0 0xfe000000 0 0x400000>; 719 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; 720 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>; 723 interrupt-names = "dma", "sft_ce", "app"; 724 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; 725 clock-names = "core", "ref"; 726 power-domains = <&sysc R8A779H0_PD_A2PCIPHY>; 727 resets = <&cpg 624>; 728 reset-names = "pwr"; 729 max-link-speed = <4>; 730 num-lanes = <2>; 731 max-functions = /bits/ 8 <2>; 732 status = "disabled"; 733 }; 734 735 canfd: can@e6660000 { 736 compatible = "renesas,r8a779h0-canfd", 737 "renesas,rcar-gen4-canfd"; 738 reg = <0 0xe6660000 0 0x8500>; 739 interrupts = <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>; 741 interrupt-names = "ch_int", "g_int"; 742 clocks = <&cpg CPG_MOD 328>, 743 <&cpg CPG_CORE R8A779H0_CLK_CANFD>, 744 <&can_clk>; 745 clock-names = "fck", "canfd", "can_clk"; 746 assigned-clocks = <&cpg CPG_CORE R8A779H0_CLK_CANFD>; 747 assigned-clock-rates = <80000000>; 748 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 749 resets = <&cpg 328>; 750 status = "disabled"; 751 752 channel0 { 753 status = "disabled"; 754 }; 755 756 channel1 { 757 status = "disabled"; 758 }; 759 760 channel2 { 761 status = "disabled"; 762 }; 763 764 channel3 { 765 status = "disabled"; 766 }; 767 }; 768 769 avb0: ethernet@e6800000 { 770 compatible = "renesas,etheravb-r8a779h0", 771 "renesas,etheravb-rcar-gen4"; 772 reg = <0 0xe6800000 0 0x1000>; 773 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 775 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 798 interrupt-names = "ch0", "ch1", "ch2", "ch3", 799 "ch4", "ch5", "ch6", "ch7", 800 "ch8", "ch9", "ch10", "ch11", 801 "ch12", "ch13", "ch14", "ch15", 802 "ch16", "ch17", "ch18", "ch19", 803 "ch20", "ch21", "ch22", "ch23", 804 "ch24"; 805 clocks = <&cpg CPG_MOD 211>; 806 clock-names = "fck"; 807 power-domains = <&sysc R8A779H0_PD_C4>; 808 resets = <&cpg 211>; 809 phy-mode = "rgmii"; 810 rx-internal-delay-ps = <0>; 811 tx-internal-delay-ps = <0>; 812 iommus = <&ipmmu_hc 0>; 813 status = "disabled"; 814 }; 815 816 avb1: ethernet@e6810000 { 817 compatible = "renesas,etheravb-r8a779h0", 818 "renesas,etheravb-rcar-gen4"; 819 reg = <0 0xe6810000 0 0x1000>; 820 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 821 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 845 interrupt-names = "ch0", "ch1", "ch2", "ch3", 846 "ch4", "ch5", "ch6", "ch7", 847 "ch8", "ch9", "ch10", "ch11", 848 "ch12", "ch13", "ch14", "ch15", 849 "ch16", "ch17", "ch18", "ch19", 850 "ch20", "ch21", "ch22", "ch23", 851 "ch24"; 852 clocks = <&cpg CPG_MOD 212>; 853 clock-names = "fck"; 854 power-domains = <&sysc R8A779H0_PD_C4>; 855 resets = <&cpg 212>; 856 phy-mode = "rgmii"; 857 rx-internal-delay-ps = <0>; 858 tx-internal-delay-ps = <0>; 859 iommus = <&ipmmu_hc 1>; 860 status = "disabled"; 861 }; 862 863 avb2: ethernet@e6820000 { 864 compatible = "renesas,etheravb-r8a779h0", 865 "renesas,etheravb-rcar-gen4"; 866 reg = <0 0xe6820000 0 0x1000>; 867 interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 869 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 870 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 871 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 873 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 877 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 878 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 880 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>; 892 interrupt-names = "ch0", "ch1", "ch2", "ch3", 893 "ch4", "ch5", "ch6", "ch7", 894 "ch8", "ch9", "ch10", "ch11", 895 "ch12", "ch13", "ch14", "ch15", 896 "ch16", "ch17", "ch18", "ch19", 897 "ch20", "ch21", "ch22", "ch23", 898 "ch24"; 899 clocks = <&cpg CPG_MOD 213>; 900 clock-names = "fck"; 901 power-domains = <&sysc R8A779H0_PD_C4>; 902 resets = <&cpg 213>; 903 phy-mode = "rgmii"; 904 rx-internal-delay-ps = <0>; 905 tx-internal-delay-ps = <0>; 906 iommus = <&ipmmu_hc 2>; 907 status = "disabled"; 908 }; 909 910 pwm0: pwm@e6e30000 { 911 compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar"; 912 reg = <0 0xe6e30000 0 0x10>; 913 #pwm-cells = <2>; 914 clocks = <&cpg CPG_MOD 628>; 915 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 916 resets = <&cpg 628>; 917 status = "disabled"; 918 }; 919 920 pwm1: pwm@e6e31000 { 921 compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar"; 922 reg = <0 0xe6e31000 0 0x10>; 923 #pwm-cells = <2>; 924 clocks = <&cpg CPG_MOD 628>; 925 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 926 resets = <&cpg 628>; 927 status = "disabled"; 928 }; 929 930 pwm2: pwm@e6e32000 { 931 compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar"; 932 reg = <0 0xe6e32000 0 0x10>; 933 #pwm-cells = <2>; 934 clocks = <&cpg CPG_MOD 628>; 935 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 936 resets = <&cpg 628>; 937 status = "disabled"; 938 }; 939 940 pwm3: pwm@e6e33000 { 941 compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar"; 942 reg = <0 0xe6e33000 0 0x10>; 943 #pwm-cells = <2>; 944 clocks = <&cpg CPG_MOD 628>; 945 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 946 resets = <&cpg 628>; 947 status = "disabled"; 948 }; 949 950 pwm4: pwm@e6e34000 { 951 compatible = "renesas,pwm-r8a779h0", "renesas,pwm-rcar"; 952 reg = <0 0xe6e34000 0 0x10>; 953 #pwm-cells = <2>; 954 clocks = <&cpg CPG_MOD 628>; 955 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 956 resets = <&cpg 628>; 957 status = "disabled"; 958 }; 959 960 scif0: serial@e6e60000 { 961 compatible = "renesas,scif-r8a779h0", 962 "renesas,rcar-gen4-scif", "renesas,scif"; 963 reg = <0 0xe6e60000 0 64>; 964 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&cpg CPG_MOD 702>, 966 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, 967 <&scif_clk>; 968 clock-names = "fck", "brg_int", "scif_clk"; 969 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 970 resets = <&cpg 702>; 971 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 972 <&dmac2 0x51>, <&dmac2 0x50>; 973 dma-names = "tx", "rx", "tx", "rx"; 974 status = "disabled"; 975 }; 976 977 scif1: serial@e6e68000 { 978 compatible = "renesas,scif-r8a779h0", 979 "renesas,rcar-gen4-scif", "renesas,scif"; 980 reg = <0 0xe6e68000 0 64>; 981 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 982 clocks = <&cpg CPG_MOD 703>, 983 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, 984 <&scif_clk>; 985 clock-names = "fck", "brg_int", "scif_clk"; 986 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 987 resets = <&cpg 703>; 988 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 989 <&dmac2 0x53>, <&dmac2 0x52>; 990 dma-names = "tx", "rx", "tx", "rx"; 991 status = "disabled"; 992 }; 993 994 scif3: serial@e6c50000 { 995 compatible = "renesas,scif-r8a779h0", 996 "renesas,rcar-gen4-scif", "renesas,scif"; 997 reg = <0 0xe6c50000 0 64>; 998 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 999 clocks = <&cpg CPG_MOD 704>, 1000 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, 1001 <&scif_clk>; 1002 clock-names = "fck", "brg_int", "scif_clk"; 1003 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1004 resets = <&cpg 704>; 1005 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 1006 <&dmac2 0x57>, <&dmac2 0x56>; 1007 dma-names = "tx", "rx", "tx", "rx"; 1008 status = "disabled"; 1009 }; 1010 1011 scif4: serial@e6c40000 { 1012 compatible = "renesas,scif-r8a779h0", 1013 "renesas,rcar-gen4-scif", "renesas,scif"; 1014 reg = <0 0xe6c40000 0 64>; 1015 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&cpg CPG_MOD 705>, 1017 <&cpg CPG_CORE R8A779H0_CLK_SASYNCPERD1>, 1018 <&scif_clk2>; 1019 clock-names = "fck", "brg_int", "scif_clk"; 1020 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1021 resets = <&cpg 705>; 1022 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 1023 <&dmac2 0x59>, <&dmac2 0x58>; 1024 dma-names = "tx", "rx", "tx", "rx"; 1025 status = "disabled"; 1026 }; 1027 1028 msiof0: spi@e6e90000 { 1029 compatible = "renesas,msiof-r8a779h0", 1030 "renesas,rcar-gen4-msiof"; 1031 reg = <0 0xe6e90000 0 0x0064>; 1032 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&cpg CPG_MOD 618>; 1034 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 1035 <&dmac2 0x41>, <&dmac2 0x40>; 1036 dma-names = "tx", "rx", "tx", "rx"; 1037 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1038 resets = <&cpg 618>; 1039 #address-cells = <1>; 1040 #size-cells = <0>; 1041 status = "disabled"; 1042 }; 1043 1044 msiof1: spi@e6ea0000 { 1045 compatible = "renesas,msiof-r8a779h0", 1046 "renesas,rcar-gen4-msiof"; 1047 reg = <0 0xe6ea0000 0 0x0064>; 1048 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1049 clocks = <&cpg CPG_MOD 619>; 1050 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 1051 <&dmac2 0x43>, <&dmac2 0x42>; 1052 dma-names = "tx", "rx", "tx", "rx"; 1053 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1054 resets = <&cpg 619>; 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 status = "disabled"; 1058 }; 1059 1060 msiof2: spi@e6c00000 { 1061 compatible = "renesas,msiof-r8a779h0", 1062 "renesas,rcar-gen4-msiof"; 1063 reg = <0 0xe6c00000 0 0x0064>; 1064 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1065 clocks = <&cpg CPG_MOD 620>; 1066 dmas = <&dmac1 0x45>, <&dmac1 0x44>, 1067 <&dmac2 0x45>, <&dmac2 0x44>; 1068 dma-names = "tx", "rx", "tx", "rx"; 1069 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1070 resets = <&cpg 620>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 status = "disabled"; 1074 }; 1075 1076 msiof3: spi@e6c10000 { 1077 compatible = "renesas,msiof-r8a779h0", 1078 "renesas,rcar-gen4-msiof"; 1079 reg = <0 0xe6c10000 0 0x0064>; 1080 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&cpg CPG_MOD 621>; 1082 dmas = <&dmac1 0x47>, <&dmac1 0x46>, 1083 <&dmac2 0x47>, <&dmac2 0x46>; 1084 dma-names = "tx", "rx", "tx", "rx"; 1085 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1086 resets = <&cpg 621>; 1087 #address-cells = <1>; 1088 #size-cells = <0>; 1089 status = "disabled"; 1090 }; 1091 1092 msiof4: spi@e6c20000 { 1093 compatible = "renesas,msiof-r8a779h0", 1094 "renesas,rcar-gen4-msiof"; 1095 reg = <0 0xe6c20000 0 0x0064>; 1096 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 1097 clocks = <&cpg CPG_MOD 622>; 1098 dmas = <&dmac1 0x49>, <&dmac1 0x48>, 1099 <&dmac2 0x49>, <&dmac2 0x48>; 1100 dma-names = "tx", "rx", "tx", "rx"; 1101 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1102 resets = <&cpg 622>; 1103 #address-cells = <1>; 1104 #size-cells = <0>; 1105 status = "disabled"; 1106 }; 1107 1108 msiof5: spi@e6c28000 { 1109 compatible = "renesas,msiof-r8a779h0", 1110 "renesas,rcar-gen4-msiof"; 1111 reg = <0 0xe6c28000 0 0x0064>; 1112 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&cpg CPG_MOD 623>; 1114 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>, 1115 <&dmac2 0x4b>, <&dmac2 0x4a>; 1116 dma-names = "tx", "rx", "tx", "rx"; 1117 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1118 resets = <&cpg 623>; 1119 #address-cells = <1>; 1120 #size-cells = <0>; 1121 status = "disabled"; 1122 }; 1123 1124 vin00: video@e6ef0000 { 1125 compatible = "renesas,vin-r8a779h0", 1126 "renesas,rcar-gen4-vin"; 1127 reg = <0 0xe6ef0000 0 0x1000>; 1128 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&cpg CPG_MOD 730>; 1130 power-domains = <&sysc R8A779H0_PD_C4>; 1131 resets = <&cpg 730>; 1132 renesas,id = <0>; 1133 status = "disabled"; 1134 1135 ports { 1136 #address-cells = <1>; 1137 #size-cells = <0>; 1138 1139 port@2 { 1140 #address-cells = <1>; 1141 #size-cells = <0>; 1142 1143 reg = <2>; 1144 1145 vin00isp0: endpoint@0 { 1146 reg = <0>; 1147 remote-endpoint = <&isp0vin00>; 1148 }; 1149 }; 1150 }; 1151 }; 1152 1153 vin01: video@e6ef1000 { 1154 compatible = "renesas,vin-r8a779h0", 1155 "renesas,rcar-gen4-vin"; 1156 reg = <0 0xe6ef1000 0 0x1000>; 1157 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1158 clocks = <&cpg CPG_MOD 731>; 1159 power-domains = <&sysc R8A779H0_PD_C4>; 1160 resets = <&cpg 731>; 1161 renesas,id = <1>; 1162 status = "disabled"; 1163 1164 ports { 1165 #address-cells = <1>; 1166 #size-cells = <0>; 1167 1168 port@2 { 1169 #address-cells = <1>; 1170 #size-cells = <0>; 1171 1172 reg = <2>; 1173 1174 vin01isp0: endpoint@0 { 1175 reg = <0>; 1176 remote-endpoint = <&isp0vin01>; 1177 }; 1178 }; 1179 }; 1180 }; 1181 1182 vin02: video@e6ef2000 { 1183 compatible = "renesas,vin-r8a779h0", 1184 "renesas,rcar-gen4-vin"; 1185 reg = <0 0xe6ef2000 0 0x1000>; 1186 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&cpg CPG_MOD 800>; 1188 power-domains = <&sysc R8A779H0_PD_C4>; 1189 resets = <&cpg 800>; 1190 renesas,id = <2>; 1191 status = "disabled"; 1192 1193 ports { 1194 #address-cells = <1>; 1195 #size-cells = <0>; 1196 1197 port@2 { 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 1201 reg = <2>; 1202 1203 vin02isp0: endpoint@0 { 1204 reg = <0>; 1205 remote-endpoint = <&isp0vin02>; 1206 }; 1207 }; 1208 }; 1209 }; 1210 1211 vin03: video@e6ef3000 { 1212 compatible = "renesas,vin-r8a779h0", 1213 "renesas,rcar-gen4-vin"; 1214 reg = <0 0xe6ef3000 0 0x1000>; 1215 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>; 1216 clocks = <&cpg CPG_MOD 801>; 1217 power-domains = <&sysc R8A779H0_PD_C4>; 1218 resets = <&cpg 801>; 1219 renesas,id = <3>; 1220 status = "disabled"; 1221 1222 ports { 1223 #address-cells = <1>; 1224 #size-cells = <0>; 1225 1226 port@2 { 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 1230 reg = <2>; 1231 1232 vin03isp0: endpoint@0 { 1233 reg = <0>; 1234 remote-endpoint = <&isp0vin03>; 1235 }; 1236 }; 1237 }; 1238 }; 1239 1240 vin04: video@e6ef4000 { 1241 compatible = "renesas,vin-r8a779h0", 1242 "renesas,rcar-gen4-vin"; 1243 reg = <0 0xe6ef4000 0 0x1000>; 1244 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&cpg CPG_MOD 802>; 1246 power-domains = <&sysc R8A779H0_PD_C4>; 1247 resets = <&cpg 802>; 1248 renesas,id = <4>; 1249 status = "disabled"; 1250 1251 ports { 1252 #address-cells = <1>; 1253 #size-cells = <0>; 1254 1255 port@2 { 1256 #address-cells = <1>; 1257 #size-cells = <0>; 1258 1259 reg = <2>; 1260 1261 vin04isp0: endpoint@0 { 1262 reg = <0>; 1263 remote-endpoint = <&isp0vin04>; 1264 }; 1265 }; 1266 }; 1267 }; 1268 1269 vin05: video@e6ef5000 { 1270 compatible = "renesas,vin-r8a779h0", 1271 "renesas,rcar-gen4-vin"; 1272 reg = <0 0xe6ef5000 0 0x1000>; 1273 interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>; 1274 clocks = <&cpg CPG_MOD 803>; 1275 power-domains = <&sysc R8A779H0_PD_C4>; 1276 resets = <&cpg 803>; 1277 renesas,id = <5>; 1278 status = "disabled"; 1279 1280 ports { 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 1284 port@2 { 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 1288 reg = <2>; 1289 1290 vin05isp0: endpoint@0 { 1291 reg = <0>; 1292 remote-endpoint = <&isp0vin05>; 1293 }; 1294 }; 1295 }; 1296 }; 1297 1298 vin06: video@e6ef6000 { 1299 compatible = "renesas,vin-r8a779h0", 1300 "renesas,rcar-gen4-vin"; 1301 reg = <0 0xe6ef6000 0 0x1000>; 1302 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1303 clocks = <&cpg CPG_MOD 804>; 1304 power-domains = <&sysc R8A779H0_PD_C4>; 1305 resets = <&cpg 804>; 1306 renesas,id = <6>; 1307 status = "disabled"; 1308 1309 ports { 1310 #address-cells = <1>; 1311 #size-cells = <0>; 1312 1313 port@2 { 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 1317 reg = <2>; 1318 1319 vin06isp0: endpoint@0 { 1320 reg = <0>; 1321 remote-endpoint = <&isp0vin06>; 1322 }; 1323 }; 1324 }; 1325 }; 1326 1327 vin07: video@e6ef7000 { 1328 compatible = "renesas,vin-r8a779h0", 1329 "renesas,rcar-gen4-vin"; 1330 reg = <0 0xe6ef7000 0 0x1000>; 1331 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1332 clocks = <&cpg CPG_MOD 805>; 1333 power-domains = <&sysc R8A779H0_PD_C4>; 1334 resets = <&cpg 805>; 1335 renesas,id = <7>; 1336 status = "disabled"; 1337 1338 ports { 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 1342 port@2 { 1343 #address-cells = <1>; 1344 #size-cells = <0>; 1345 1346 reg = <2>; 1347 1348 vin07isp0: endpoint@0 { 1349 reg = <0>; 1350 remote-endpoint = <&isp0vin07>; 1351 }; 1352 }; 1353 }; 1354 }; 1355 1356 vin08: video@e6ef8000 { 1357 compatible = "renesas,vin-r8a779h0", 1358 "renesas,rcar-gen4-vin"; 1359 reg = <0 0xe6ef8000 0 0x1000>; 1360 interrupts = <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>; 1361 clocks = <&cpg CPG_MOD 806>; 1362 power-domains = <&sysc R8A779H0_PD_C4>; 1363 resets = <&cpg 806>; 1364 renesas,id = <8>; 1365 status = "disabled"; 1366 1367 ports { 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 1371 port@2 { 1372 #address-cells = <1>; 1373 #size-cells = <0>; 1374 1375 reg = <2>; 1376 1377 vin08isp1: endpoint@1 { 1378 reg = <1>; 1379 remote-endpoint = <&isp1vin08>; 1380 }; 1381 }; 1382 }; 1383 }; 1384 1385 vin09: video@e6ef9000 { 1386 compatible = "renesas,vin-r8a779h0", 1387 "renesas,rcar-gen4-vin"; 1388 reg = <0 0xe6ef9000 0 0x1000>; 1389 interrupts = <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>; 1390 clocks = <&cpg CPG_MOD 807>; 1391 power-domains = <&sysc R8A779H0_PD_C4>; 1392 resets = <&cpg 807>; 1393 renesas,id = <9>; 1394 status = "disabled"; 1395 1396 ports { 1397 #address-cells = <1>; 1398 #size-cells = <0>; 1399 1400 port@2 { 1401 #address-cells = <1>; 1402 #size-cells = <0>; 1403 1404 reg = <2>; 1405 1406 vin09isp1: endpoint@1 { 1407 reg = <1>; 1408 remote-endpoint = <&isp1vin09>; 1409 }; 1410 }; 1411 }; 1412 }; 1413 1414 vin10: video@e6efa000 { 1415 compatible = "renesas,vin-r8a779h0", 1416 "renesas,rcar-gen4-vin"; 1417 reg = <0 0xe6efa000 0 0x1000>; 1418 interrupts = <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>; 1419 clocks = <&cpg CPG_MOD 808>; 1420 power-domains = <&sysc R8A779H0_PD_C4>; 1421 resets = <&cpg 808>; 1422 renesas,id = <10>; 1423 status = "disabled"; 1424 1425 ports { 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 1429 port@2 { 1430 #address-cells = <1>; 1431 #size-cells = <0>; 1432 1433 reg = <2>; 1434 1435 vin10isp1: endpoint@1 { 1436 reg = <1>; 1437 remote-endpoint = <&isp1vin10>; 1438 }; 1439 }; 1440 }; 1441 }; 1442 1443 vin11: video@e6efb000 { 1444 compatible = "renesas,vin-r8a779h0", 1445 "renesas,rcar-gen4-vin"; 1446 reg = <0 0xe6efb000 0 0x1000>; 1447 interrupts = <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>; 1448 clocks = <&cpg CPG_MOD 809>; 1449 power-domains = <&sysc R8A779H0_PD_C4>; 1450 resets = <&cpg 809>; 1451 renesas,id = <11>; 1452 status = "disabled"; 1453 1454 ports { 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 1458 port@2 { 1459 #address-cells = <1>; 1460 #size-cells = <0>; 1461 1462 reg = <2>; 1463 1464 vin11isp1: endpoint@1 { 1465 reg = <1>; 1466 remote-endpoint = <&isp1vin11>; 1467 }; 1468 }; 1469 }; 1470 }; 1471 1472 vin12: video@e6efc000 { 1473 compatible = "renesas,vin-r8a779h0", 1474 "renesas,rcar-gen4-vin"; 1475 reg = <0 0xe6efc000 0 0x1000>; 1476 interrupts = <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>; 1477 clocks = <&cpg CPG_MOD 810>; 1478 power-domains = <&sysc R8A779H0_PD_C4>; 1479 resets = <&cpg 810>; 1480 renesas,id = <12>; 1481 status = "disabled"; 1482 1483 ports { 1484 #address-cells = <1>; 1485 #size-cells = <0>; 1486 1487 port@2 { 1488 #address-cells = <1>; 1489 #size-cells = <0>; 1490 1491 reg = <2>; 1492 1493 vin12isp1: endpoint@1 { 1494 reg = <1>; 1495 remote-endpoint = <&isp1vin12>; 1496 }; 1497 }; 1498 }; 1499 }; 1500 1501 vin13: video@e6efd000 { 1502 compatible = "renesas,vin-r8a779h0", 1503 "renesas,rcar-gen4-vin"; 1504 reg = <0 0xe6efd000 0 0x1000>; 1505 interrupts = <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>; 1506 clocks = <&cpg CPG_MOD 811>; 1507 power-domains = <&sysc R8A779H0_PD_C4>; 1508 resets = <&cpg 811>; 1509 renesas,id = <13>; 1510 status = "disabled"; 1511 1512 ports { 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 1516 port@2 { 1517 #address-cells = <1>; 1518 #size-cells = <0>; 1519 1520 reg = <2>; 1521 1522 vin13isp1: endpoint@1 { 1523 reg = <1>; 1524 remote-endpoint = <&isp1vin13>; 1525 }; 1526 }; 1527 }; 1528 }; 1529 1530 vin14: video@e6efe000 { 1531 compatible = "renesas,vin-r8a779h0", 1532 "renesas,rcar-gen4-vin"; 1533 reg = <0 0xe6efe000 0 0x1000>; 1534 interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>; 1535 clocks = <&cpg CPG_MOD 812>; 1536 power-domains = <&sysc R8A779H0_PD_C4>; 1537 resets = <&cpg 812>; 1538 renesas,id = <14>; 1539 status = "disabled"; 1540 1541 ports { 1542 #address-cells = <1>; 1543 #size-cells = <0>; 1544 1545 port@2 { 1546 #address-cells = <1>; 1547 #size-cells = <0>; 1548 1549 reg = <2>; 1550 1551 vin14isp1: endpoint@1 { 1552 reg = <1>; 1553 remote-endpoint = <&isp1vin14>; 1554 }; 1555 }; 1556 }; 1557 }; 1558 1559 vin15: video@e6eff000 { 1560 compatible = "renesas,vin-r8a779h0", 1561 "renesas,rcar-gen4-vin"; 1562 reg = <0 0xe6eff000 0 0x1000>; 1563 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; 1564 clocks = <&cpg CPG_MOD 813>; 1565 power-domains = <&sysc R8A779H0_PD_C4>; 1566 resets = <&cpg 813>; 1567 renesas,id = <15>; 1568 status = "disabled"; 1569 1570 ports { 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 1574 port@2 { 1575 #address-cells = <1>; 1576 #size-cells = <0>; 1577 1578 reg = <2>; 1579 1580 vin15isp1: endpoint@1 { 1581 reg = <1>; 1582 remote-endpoint = <&isp1vin15>; 1583 }; 1584 }; 1585 }; 1586 }; 1587 1588 dmac1: dma-controller@e7350000 { 1589 compatible = "renesas,dmac-r8a779h0", 1590 "renesas,rcar-gen4-dmac"; 1591 reg = <0 0xe7350000 0 0x1000>, 1592 <0 0xe7300000 0 0x10000>; 1593 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 1595 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 1596 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1610 interrupt-names = "error", 1611 "ch0", "ch1", "ch2", "ch3", "ch4", 1612 "ch5", "ch6", "ch7", "ch8", "ch9", 1613 "ch10", "ch11", "ch12", "ch13", 1614 "ch14", "ch15"; 1615 clocks = <&cpg CPG_MOD 709>; 1616 clock-names = "fck"; 1617 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1618 resets = <&cpg 709>; 1619 #dma-cells = <1>; 1620 dma-channels = <16>; 1621 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 1622 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 1623 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 1624 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 1625 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 1626 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 1627 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 1628 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 1629 }; 1630 1631 dmac2: dma-controller@e7351000 { 1632 compatible = "renesas,dmac-r8a779h0", 1633 "renesas,rcar-gen4-dmac"; 1634 reg = <0 0xe7351000 0 0x1000>, 1635 <0 0xe7310000 0 0x10000>; 1636 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1637 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1638 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1639 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1640 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1641 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1642 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1643 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1645 interrupt-names = "error", 1646 "ch0", "ch1", "ch2", "ch3", "ch4", 1647 "ch5", "ch6", "ch7"; 1648 clocks = <&cpg CPG_MOD 710>; 1649 clock-names = "fck"; 1650 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1651 resets = <&cpg 710>; 1652 #dma-cells = <1>; 1653 dma-channels = <8>; 1654 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, 1655 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, 1656 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, 1657 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>; 1658 }; 1659 1660 rcar_sound: sound@ec400000 { 1661 compatible = "renesas,rcar_sound-r8a779h0", "renesas,rcar_sound-gen4"; 1662 reg = <0 0xec400000 0 0x40000>, 1663 <0 0xec540000 0 0x1000>, 1664 <0 0xec541000 0 0x050>, 1665 <0 0xec5a0000 0 0x020>; 1666 reg-names = "sdmc", "ssiu", "ssi", "adg"; 1667 clocks = <&cpg CPG_MOD 2926>, <&cpg CPG_MOD 2927>, <&audio_clkin>; 1668 clock-names = "ssiu.0", "ssi.0", "clkin"; 1669 /* #clock-cells is fixed */ 1670 #clock-cells = <0>; 1671 /* #sound-dai-cells is fixed */ 1672 #sound-dai-cells = <0>; 1673 1674 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1675 resets = <&cpg 2926>, <&cpg 2927>; 1676 reset-names = "ssiu.0", "ssi.0"; 1677 status = "disabled"; 1678 1679 rcar_sound,ssiu { 1680 ssiu00: ssiu-0 { 1681 dmas = <&dmac1 0x6e>, <&dmac1 0x6f>; 1682 dma-names = "tx", "rx"; 1683 }; 1684 ssiu01: ssiu-1 { 1685 dmas = <&dmac1 0x6c>, <&dmac1 0x6d>; 1686 dma-names = "tx", "rx"; 1687 }; 1688 ssiu02: ssiu-2 { 1689 dmas = <&dmac1 0x6a>, <&dmac1 0x6b>; 1690 dma-names = "tx", "rx"; 1691 }; 1692 ssiu03: ssiu-3 { 1693 dmas = <&dmac1 0x68>, <&dmac1 0x69>; 1694 dma-names = "tx", "rx"; 1695 }; 1696 ssiu04: ssiu-4 { 1697 dmas = <&dmac1 0x66>, <&dmac1 0x67>; 1698 dma-names = "tx", "rx"; 1699 }; 1700 ssiu05: ssiu-5 { 1701 dmas = <&dmac1 0x64>, <&dmac1 0x65>; 1702 dma-names = "tx", "rx"; 1703 }; 1704 ssiu06: ssiu-6 { 1705 dmas = <&dmac1 0x62>, <&dmac1 0x63>; 1706 dma-names = "tx", "rx"; 1707 }; 1708 ssiu07: ssiu-7 { 1709 dmas = <&dmac1 0x60>, <&dmac1 0x61>; 1710 dma-names = "tx", "rx"; 1711 }; 1712 }; 1713 1714 rcar_sound,ssi { 1715 ssi0: ssi-0 { 1716 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>; 1717 }; 1718 }; 1719 }; 1720 1721 mmc0: mmc@ee140000 { 1722 compatible = "renesas,sdhi-r8a779h0", 1723 "renesas,rcar-gen4-sdhi"; 1724 reg = <0 0xee140000 0 0x2000>; 1725 interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>; 1726 clocks = <&cpg CPG_MOD 706>, 1727 <&cpg CPG_CORE R8A779H0_CLK_SD0H>; 1728 clock-names = "core", "clkh"; 1729 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1730 resets = <&cpg 706>; 1731 max-frequency = <200000000>; 1732 iommus = <&ipmmu_ds0 32>; 1733 status = "disabled"; 1734 }; 1735 1736 rpc: spi@ee200000 { 1737 compatible = "renesas,r8a779h0-rpc-if", 1738 "renesas,rcar-gen4-rpc-if"; 1739 reg = <0 0xee200000 0 0x200>, 1740 <0 0x08000000 0 0x04000000>, 1741 <0 0xee208000 0 0x100>; 1742 reg-names = "regs", "dirmap", "wbuf"; 1743 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1744 clocks = <&cpg CPG_MOD 629>; 1745 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1746 resets = <&cpg 629>; 1747 #address-cells = <1>; 1748 #size-cells = <0>; 1749 status = "disabled"; 1750 }; 1751 1752 ipmmu_rt0: iommu@ee480000 { 1753 compatible = "renesas,ipmmu-r8a779h0", 1754 "renesas,rcar-gen4-ipmmu-vmsa"; 1755 reg = <0 0xee480000 0 0x20000>; 1756 renesas,ipmmu-main = <&ipmmu_mm>; 1757 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1758 #iommu-cells = <1>; 1759 }; 1760 1761 ipmmu_rt1: iommu@ee4c0000 { 1762 compatible = "renesas,ipmmu-r8a779h0", 1763 "renesas,rcar-gen4-ipmmu-vmsa"; 1764 reg = <0 0xee4c0000 0 0x20000>; 1765 renesas,ipmmu-main = <&ipmmu_mm>; 1766 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1767 #iommu-cells = <1>; 1768 }; 1769 1770 ipmmu_ds0: iommu@eed00000 { 1771 compatible = "renesas,ipmmu-r8a779h0", 1772 "renesas,rcar-gen4-ipmmu-vmsa"; 1773 reg = <0 0xeed00000 0 0x20000>; 1774 renesas,ipmmu-main = <&ipmmu_mm>; 1775 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1776 #iommu-cells = <1>; 1777 }; 1778 1779 ipmmu_hc: iommu@eed40000 { 1780 compatible = "renesas,ipmmu-r8a779h0", 1781 "renesas,rcar-gen4-ipmmu-vmsa"; 1782 reg = <0 0xeed40000 0 0x20000>; 1783 renesas,ipmmu-main = <&ipmmu_mm>; 1784 power-domains = <&sysc R8A779H0_PD_C4>; 1785 #iommu-cells = <1>; 1786 }; 1787 1788 ipmmu_ir: iommu@eed80000 { 1789 compatible = "renesas,ipmmu-r8a779h0", 1790 "renesas,rcar-gen4-ipmmu-vmsa"; 1791 reg = <0 0xeed80000 0 0x20000>; 1792 renesas,ipmmu-main = <&ipmmu_mm>; 1793 power-domains = <&sysc R8A779H0_PD_C4>; 1794 #iommu-cells = <1>; 1795 }; 1796 1797 ipmmu_vc: iommu@eedc0000 { 1798 compatible = "renesas,ipmmu-r8a779h0", 1799 "renesas,rcar-gen4-ipmmu-vmsa"; 1800 reg = <0 0xeedc0000 0 0x20000>; 1801 renesas,ipmmu-main = <&ipmmu_mm>; 1802 power-domains = <&sysc R8A779H0_PD_C4>; 1803 #iommu-cells = <1>; 1804 }; 1805 1806 ipmmu_3dg: iommu@eee00000 { 1807 compatible = "renesas,ipmmu-r8a779h0", 1808 "renesas,rcar-gen4-ipmmu-vmsa"; 1809 reg = <0 0xeee00000 0 0x20000>; 1810 renesas,ipmmu-main = <&ipmmu_mm>; 1811 power-domains = <&sysc R8A779H0_PD_C4>; 1812 #iommu-cells = <1>; 1813 }; 1814 1815 ipmmu_vi0: iommu@eee80000 { 1816 compatible = "renesas,ipmmu-r8a779h0", 1817 "renesas,rcar-gen4-ipmmu-vmsa"; 1818 reg = <0 0xeee80000 0 0x20000>; 1819 renesas,ipmmu-main = <&ipmmu_mm>; 1820 power-domains = <&sysc R8A779H0_PD_C4>; 1821 #iommu-cells = <1>; 1822 }; 1823 1824 ipmmu_vi1: iommu@eeec0000 { 1825 compatible = "renesas,ipmmu-r8a779h0", 1826 "renesas,rcar-gen4-ipmmu-vmsa"; 1827 reg = <0 0xeeec0000 0 0x20000>; 1828 renesas,ipmmu-main = <&ipmmu_mm>; 1829 power-domains = <&sysc R8A779H0_PD_C4>; 1830 #iommu-cells = <1>; 1831 }; 1832 1833 ipmmu_vip0: iommu@eef00000 { 1834 compatible = "renesas,ipmmu-r8a779h0", 1835 "renesas,rcar-gen4-ipmmu-vmsa"; 1836 reg = <0 0xeef00000 0 0x20000>; 1837 renesas,ipmmu-main = <&ipmmu_mm>; 1838 power-domains = <&sysc R8A779H0_PD_C4>; 1839 #iommu-cells = <1>; 1840 }; 1841 1842 ipmmu_mm: iommu@eefc0000 { 1843 compatible = "renesas,ipmmu-r8a779h0", 1844 "renesas,rcar-gen4-ipmmu-vmsa"; 1845 reg = <0 0xeefc0000 0 0x20000>; 1846 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>, 1847 <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 1848 power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>; 1849 #iommu-cells = <1>; 1850 }; 1851 1852 gic: interrupt-controller@f1000000 { 1853 compatible = "arm,gic-v3"; 1854 #interrupt-cells = <3>; 1855 #address-cells = <0>; 1856 interrupt-controller; 1857 reg = <0x0 0xf1000000 0 0x20000>, 1858 <0x0 0xf1060000 0 0x110000>; 1859 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1860 }; 1861 1862 csi40: csi2@fe500000 { 1863 compatible = "renesas,r8a779h0-csi2"; 1864 reg = <0 0xfe500000 0 0x40000>; 1865 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; 1866 clocks = <&cpg CPG_MOD 331>; 1867 power-domains = <&sysc R8A779H0_PD_C4>; 1868 resets = <&cpg 331>; 1869 status = "disabled"; 1870 1871 ports { 1872 #address-cells = <1>; 1873 #size-cells = <0>; 1874 1875 port@0 { 1876 reg = <0>; 1877 }; 1878 1879 port@1 { 1880 reg = <1>; 1881 csi40isp0: endpoint { 1882 remote-endpoint = <&isp0csi40>; 1883 }; 1884 }; 1885 }; 1886 }; 1887 1888 csi41: csi2@fe540000 { 1889 compatible = "renesas,r8a779h0-csi2"; 1890 reg = <0 0xfe540000 0 0x40000>; 1891 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>; 1892 clocks = <&cpg CPG_MOD 400>; 1893 power-domains = <&sysc R8A779H0_PD_C4>; 1894 resets = <&cpg 400>; 1895 status = "disabled"; 1896 1897 ports { 1898 #address-cells = <1>; 1899 #size-cells = <0>; 1900 1901 port@0 { 1902 reg = <0>; 1903 }; 1904 1905 port@1 { 1906 reg = <1>; 1907 csi41isp1: endpoint { 1908 remote-endpoint = <&isp1csi41>; 1909 }; 1910 }; 1911 }; 1912 }; 1913 1914 fcpvd0: fcp@fea10000 { 1915 compatible = "renesas,fcpv"; 1916 reg = <0 0xfea10000 0 0x200>; 1917 clocks = <&cpg CPG_MOD 508>; 1918 power-domains = <&sysc R8A779H0_PD_C4>; 1919 resets = <&cpg 508>; 1920 }; 1921 1922 fcpvx0: fcp@fedb0000 { 1923 compatible = "renesas,fcpv"; 1924 reg = <0 0xfedb0000 0 0x200>; 1925 clocks = <&cpg CPG_MOD 1100>; 1926 power-domains = <&sysc R8A779H0_PD_A3ISP0>; 1927 resets = <&cpg 1100>; 1928 iommus = <&ipmmu_vi1 24>; 1929 }; 1930 1931 vspd0: vsp@fea20000 { 1932 compatible = "renesas,vsp2"; 1933 reg = <0 0xfea20000 0 0x8000>; 1934 interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; 1935 clocks = <&cpg CPG_MOD 830>; 1936 power-domains = <&sysc R8A779H0_PD_C4>; 1937 resets = <&cpg 830>; 1938 renesas,fcp = <&fcpvd0>; 1939 }; 1940 1941 vspx0: vsp@fedd0000 { 1942 compatible = "renesas,vsp2"; 1943 reg = <0 0xfedd0000 0 0x8000>; 1944 interrupts = <GIC_SPI 556 IRQ_TYPE_LEVEL_HIGH>; 1945 clocks = <&cpg CPG_MOD 1028>; 1946 power-domains = <&sysc R8A779H0_PD_A3ISP0>; 1947 resets = <&cpg 1028>; 1948 1949 renesas,fcp = <&fcpvx0>; 1950 }; 1951 1952 du: display@feb00000 { 1953 compatible = "renesas,du-r8a779h0"; 1954 reg = <0 0xfeb00000 0 0x40000>; 1955 interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>; 1956 clocks = <&cpg CPG_MOD 411>; 1957 clock-names = "du.0"; 1958 power-domains = <&sysc R8A779H0_PD_C4>; 1959 resets = <&cpg 411>; 1960 reset-names = "du.0"; 1961 renesas,vsps = <&vspd0 0>; 1962 1963 status = "disabled"; 1964 1965 ports { 1966 #address-cells = <1>; 1967 #size-cells = <0>; 1968 1969 port@0 { 1970 reg = <0>; 1971 du_out_dsi0: endpoint { 1972 remote-endpoint = <&dsi0_in>; 1973 }; 1974 }; 1975 }; 1976 }; 1977 1978 isp0: isp@fed00000 { 1979 compatible = "renesas,r8a779h0-isp", 1980 "renesas,rcar-gen4-isp"; 1981 reg = <0 0xfed00000 0 0x10000>, <0 0xfec00000 0 0x100000>; 1982 reg-names = "cs", "core"; 1983 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 1984 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>; 1985 interrupt-names = "cs", "core"; 1986 clocks = <&cpg CPG_MOD 612>, <&cpg CPG_MOD 16>; 1987 clock-names = "cs", "core"; 1988 power-domains = <&sysc R8A779H0_PD_A3ISP0>; 1989 resets = <&cpg 612>, <&cpg 16>; 1990 reset-names = "cs", "core"; 1991 status = "disabled"; 1992 1993 renesas,vspx = <&vspx0>; 1994 1995 ports { 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 1999 port@0 { 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 2003 reg = <0>; 2004 2005 isp0csi40: endpoint@0 { 2006 reg = <0>; 2007 remote-endpoint = <&csi40isp0>; 2008 }; 2009 }; 2010 2011 port@1 { 2012 reg = <1>; 2013 isp0vin00: endpoint { 2014 remote-endpoint = <&vin00isp0>; 2015 }; 2016 }; 2017 2018 port@2 { 2019 reg = <2>; 2020 isp0vin01: endpoint { 2021 remote-endpoint = <&vin01isp0>; 2022 }; 2023 }; 2024 2025 port@3 { 2026 reg = <3>; 2027 isp0vin02: endpoint { 2028 remote-endpoint = <&vin02isp0>; 2029 }; 2030 }; 2031 2032 port@4 { 2033 reg = <4>; 2034 isp0vin03: endpoint { 2035 remote-endpoint = <&vin03isp0>; 2036 }; 2037 }; 2038 2039 port@5 { 2040 reg = <5>; 2041 isp0vin04: endpoint { 2042 remote-endpoint = <&vin04isp0>; 2043 }; 2044 }; 2045 2046 port@6 { 2047 reg = <6>; 2048 isp0vin05: endpoint { 2049 remote-endpoint = <&vin05isp0>; 2050 }; 2051 }; 2052 2053 port@7 { 2054 reg = <7>; 2055 isp0vin06: endpoint { 2056 remote-endpoint = <&vin06isp0>; 2057 }; 2058 }; 2059 2060 port@8 { 2061 reg = <8>; 2062 isp0vin07: endpoint { 2063 remote-endpoint = <&vin07isp0>; 2064 }; 2065 }; 2066 }; 2067 }; 2068 2069 isp1: isp@fed20000 { 2070 compatible = "renesas,r8a779h0-isp", 2071 "renesas,rcar-gen4-isp"; 2072 reg = <0 0xfed20000 0 0x10000>; 2073 reg-names = "cs"; 2074 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 2075 interrupt-names = "cs"; 2076 clocks = <&cpg CPG_MOD 613>; 2077 clock-names = "cs"; 2078 power-domains = <&sysc R8A779H0_PD_A3ISP0>; 2079 resets = <&cpg 613>; 2080 reset-names = "cs"; 2081 status = "disabled"; 2082 2083 ports { 2084 #address-cells = <1>; 2085 #size-cells = <0>; 2086 2087 port@0 { 2088 #address-cells = <1>; 2089 #size-cells = <0>; 2090 2091 reg = <0>; 2092 2093 isp1csi41: endpoint@1 { 2094 reg = <1>; 2095 remote-endpoint = <&csi41isp1>; 2096 }; 2097 }; 2098 2099 port@1 { 2100 reg = <1>; 2101 isp1vin08: endpoint { 2102 remote-endpoint = <&vin08isp1>; 2103 }; 2104 }; 2105 2106 port@2 { 2107 reg = <2>; 2108 isp1vin09: endpoint { 2109 remote-endpoint = <&vin09isp1>; 2110 }; 2111 }; 2112 2113 port@3 { 2114 reg = <3>; 2115 isp1vin10: endpoint { 2116 remote-endpoint = <&vin10isp1>; 2117 }; 2118 }; 2119 2120 port@4 { 2121 reg = <4>; 2122 isp1vin11: endpoint { 2123 remote-endpoint = <&vin11isp1>; 2124 }; 2125 }; 2126 2127 port@5 { 2128 reg = <5>; 2129 isp1vin12: endpoint { 2130 remote-endpoint = <&vin12isp1>; 2131 }; 2132 }; 2133 2134 port@6 { 2135 reg = <6>; 2136 isp1vin13: endpoint { 2137 remote-endpoint = <&vin13isp1>; 2138 }; 2139 }; 2140 2141 port@7 { 2142 reg = <7>; 2143 isp1vin14: endpoint { 2144 remote-endpoint = <&vin14isp1>; 2145 }; 2146 }; 2147 2148 port@8 { 2149 reg = <8>; 2150 isp1vin15: endpoint { 2151 remote-endpoint = <&vin15isp1>; 2152 }; 2153 }; 2154 }; 2155 }; 2156 2157 dsi0: dsi@fed80000 { 2158 compatible = "renesas,r8a779h0-dsi-csi2-tx"; 2159 reg = <0 0xfed80000 0 0x10000>; 2160 clocks = <&cpg CPG_MOD 415>, 2161 <&cpg CPG_CORE R8A779H0_CLK_DSIEXT>, 2162 <&cpg CPG_CORE R8A779H0_CLK_DSIREF>; 2163 clock-names = "fck", "dsi", "pll"; 2164 power-domains = <&sysc R8A779H0_PD_C4>; 2165 resets = <&cpg 415>; 2166 2167 status = "disabled"; 2168 2169 ports { 2170 #address-cells = <1>; 2171 #size-cells = <0>; 2172 2173 port@0 { 2174 reg = <0>; 2175 dsi0_in: endpoint { 2176 remote-endpoint = <&du_out_dsi0>; 2177 }; 2178 }; 2179 2180 port@1 { 2181 reg = <1>; 2182 }; 2183 }; 2184 }; 2185 2186 prr: chipid@fff00044 { 2187 compatible = "renesas,prr"; 2188 reg = <0 0xfff00044 0 4>; 2189 bootph-all; 2190 }; 2191 }; 2192 2193 thermal-zones { 2194 sensor_thermal_cr52: sensor1-thermal { 2195 polling-delay-passive = <250>; 2196 polling-delay = <1000>; 2197 thermal-sensors = <&tsc 0>; 2198 2199 trips { 2200 sensor1_crit: sensor1-crit { 2201 temperature = <120000>; 2202 hysteresis = <1000>; 2203 type = "critical"; 2204 }; 2205 }; 2206 }; 2207 2208 sensor_thermal_ca76: sensor2-thermal { 2209 polling-delay-passive = <250>; 2210 polling-delay = <1000>; 2211 thermal-sensors = <&tsc 1>; 2212 2213 trips { 2214 sensor2_crit: sensor2-crit { 2215 temperature = <120000>; 2216 hysteresis = <1000>; 2217 type = "critical"; 2218 }; 2219 }; 2220 }; 2221 }; 2222 2223 timer { 2224 compatible = "arm,armv8-timer"; 2225 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 2226 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 2227 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 2228 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 2229 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 2230 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 2231 "hyp-virt"; 2232 }; 2233};
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