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r8a779f0.dtsi
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linux-6.19.14/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Device Tree Source for the R-Car S4-8 (R8A779F0) SoC 4 * 5 * Copyright (C) 2021 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779f0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779f0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779f0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 interrupt-parent = <&gic>; 17 18 cluster01_opp: opp-table-0 { 19 compatible = "operating-points-v2"; 20 opp-shared; 21 22 opp-500000000 { 23 opp-hz = /bits/ 64 <500000000>; 24 opp-microvolt = <880000>; 25 clock-latency-ns = <500000>; 26 }; 27 opp-800000000 { 28 opp-hz = /bits/ 64 <800000000>; 29 opp-microvolt = <880000>; 30 clock-latency-ns = <500000>; 31 }; 32 opp-1000000000 { 33 opp-hz = /bits/ 64 <1000000000>; 34 opp-microvolt = <880000>; 35 clock-latency-ns = <500000>; 36 }; 37 opp-1200000000 { 38 opp-hz = /bits/ 64 <1200000000>; 39 opp-microvolt = <880000>; 40 clock-latency-ns = <500000>; 41 opp-suspend; 42 }; 43 }; 44 45 cluster23_opp: opp-table-1 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 49 opp-500000000 { 50 opp-hz = /bits/ 64 <500000000>; 51 opp-microvolt = <880000>; 52 clock-latency-ns = <500000>; 53 }; 54 opp-800000000 { 55 opp-hz = /bits/ 64 <800000000>; 56 opp-microvolt = <880000>; 57 clock-latency-ns = <500000>; 58 }; 59 opp-1000000000 { 60 opp-hz = /bits/ 64 <1000000000>; 61 opp-microvolt = <880000>; 62 clock-latency-ns = <500000>; 63 }; 64 opp-1200000000 { 65 opp-hz = /bits/ 64 <1200000000>; 66 opp-microvolt = <880000>; 67 clock-latency-ns = <500000>; 68 opp-suspend; 69 }; 70 }; 71 72 cpus { 73 #address-cells = <1>; 74 #size-cells = <0>; 75 76 cpu-map { 77 cluster0 { 78 core0 { 79 cpu = <&a55_0>; 80 }; 81 core1 { 82 cpu = <&a55_1>; 83 }; 84 }; 85 86 cluster1 { 87 core0 { 88 cpu = <&a55_2>; 89 }; 90 core1 { 91 cpu = <&a55_3>; 92 }; 93 }; 94 95 cluster2 { 96 core0 { 97 cpu = <&a55_4>; 98 }; 99 core1 { 100 cpu = <&a55_5>; 101 }; 102 }; 103 104 cluster3 { 105 core0 { 106 cpu = <&a55_6>; 107 }; 108 core1 { 109 cpu = <&a55_7>; 110 }; 111 }; 112 }; 113 114 a55_0: cpu@0 { 115 compatible = "arm,cortex-a55"; 116 reg = <0>; 117 device_type = "cpu"; 118 power-domains = <&sysc R8A779F0_PD_A1E0D0C0>; 119 next-level-cache = <&L3_CA55_0>; 120 enable-method = "psci"; 121 cpu-idle-states = <&CPU_SLEEP_0>; 122 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 123 operating-points-v2 = <&cluster01_opp>; 124 }; 125 126 a55_1: cpu@100 { 127 compatible = "arm,cortex-a55"; 128 reg = <0x100>; 129 device_type = "cpu"; 130 power-domains = <&sysc R8A779F0_PD_A1E0D0C1>; 131 next-level-cache = <&L3_CA55_0>; 132 enable-method = "psci"; 133 cpu-idle-states = <&CPU_SLEEP_0>; 134 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 135 operating-points-v2 = <&cluster01_opp>; 136 }; 137 138 a55_2: cpu@10000 { 139 compatible = "arm,cortex-a55"; 140 reg = <0x10000>; 141 device_type = "cpu"; 142 power-domains = <&sysc R8A779F0_PD_A1E0D1C0>; 143 next-level-cache = <&L3_CA55_1>; 144 enable-method = "psci"; 145 cpu-idle-states = <&CPU_SLEEP_0>; 146 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 147 operating-points-v2 = <&cluster01_opp>; 148 }; 149 150 a55_3: cpu@10100 { 151 compatible = "arm,cortex-a55"; 152 reg = <0x10100>; 153 device_type = "cpu"; 154 power-domains = <&sysc R8A779F0_PD_A1E0D1C1>; 155 next-level-cache = <&L3_CA55_1>; 156 enable-method = "psci"; 157 cpu-idle-states = <&CPU_SLEEP_0>; 158 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z0>; 159 operating-points-v2 = <&cluster01_opp>; 160 }; 161 162 a55_4: cpu@20000 { 163 compatible = "arm,cortex-a55"; 164 reg = <0x20000>; 165 device_type = "cpu"; 166 power-domains = <&sysc R8A779F0_PD_A1E1D0C0>; 167 next-level-cache = <&L3_CA55_2>; 168 enable-method = "psci"; 169 cpu-idle-states = <&CPU_SLEEP_0>; 170 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 171 operating-points-v2 = <&cluster23_opp>; 172 }; 173 174 a55_5: cpu@20100 { 175 compatible = "arm,cortex-a55"; 176 reg = <0x20100>; 177 device_type = "cpu"; 178 power-domains = <&sysc R8A779F0_PD_A1E1D0C1>; 179 next-level-cache = <&L3_CA55_2>; 180 enable-method = "psci"; 181 cpu-idle-states = <&CPU_SLEEP_0>; 182 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 183 operating-points-v2 = <&cluster23_opp>; 184 }; 185 186 a55_6: cpu@30000 { 187 compatible = "arm,cortex-a55"; 188 reg = <0x30000>; 189 device_type = "cpu"; 190 power-domains = <&sysc R8A779F0_PD_A1E1D1C0>; 191 next-level-cache = <&L3_CA55_3>; 192 enable-method = "psci"; 193 cpu-idle-states = <&CPU_SLEEP_0>; 194 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 195 operating-points-v2 = <&cluster23_opp>; 196 }; 197 198 a55_7: cpu@30100 { 199 compatible = "arm,cortex-a55"; 200 reg = <0x30100>; 201 device_type = "cpu"; 202 power-domains = <&sysc R8A779F0_PD_A1E1D1C1>; 203 next-level-cache = <&L3_CA55_3>; 204 enable-method = "psci"; 205 cpu-idle-states = <&CPU_SLEEP_0>; 206 clocks = <&cpg CPG_CORE R8A779F0_CLK_Z1>; 207 operating-points-v2 = <&cluster23_opp>; 208 }; 209 210 L3_CA55_0: cache-controller-0 { 211 compatible = "cache"; 212 power-domains = <&sysc R8A779F0_PD_A2E0D0>; 213 cache-unified; 214 cache-level = <3>; 215 }; 216 217 L3_CA55_1: cache-controller-1 { 218 compatible = "cache"; 219 power-domains = <&sysc R8A779F0_PD_A2E0D1>; 220 cache-unified; 221 cache-level = <3>; 222 }; 223 224 L3_CA55_2: cache-controller-2 { 225 compatible = "cache"; 226 power-domains = <&sysc R8A779F0_PD_A2E1D0>; 227 cache-unified; 228 cache-level = <3>; 229 }; 230 231 L3_CA55_3: cache-controller-3 { 232 compatible = "cache"; 233 power-domains = <&sysc R8A779F0_PD_A2E1D1>; 234 cache-unified; 235 cache-level = <3>; 236 }; 237 238 idle-states { 239 entry-method = "psci"; 240 241 CPU_SLEEP_0: cpu-sleep-0 { 242 compatible = "arm,idle-state"; 243 arm,psci-suspend-param = <0x0010000>; 244 local-timer-stop; 245 entry-latency-us = <400>; 246 exit-latency-us = <500>; 247 min-residency-us = <4000>; 248 }; 249 }; 250 }; 251 252 extal_clk: extal { 253 compatible = "fixed-clock"; 254 #clock-cells = <0>; 255 /* This value must be overridden by the board */ 256 clock-frequency = <0>; 257 bootph-all; 258 }; 259 260 extalr_clk: extalr { 261 compatible = "fixed-clock"; 262 #clock-cells = <0>; 263 /* This value must be overridden by the board */ 264 clock-frequency = <0>; 265 bootph-all; 266 }; 267 268 pcie0_clkref: pcie0-clkref { 269 compatible = "fixed-clock"; 270 #clock-cells = <0>; 271 /* This value must be overridden by the board */ 272 clock-frequency = <0>; 273 }; 274 275 pcie1_clkref: pcie1-clkref { 276 compatible = "fixed-clock"; 277 #clock-cells = <0>; 278 /* This value must be overridden by the board */ 279 clock-frequency = <0>; 280 }; 281 282 pmu_a55 { 283 compatible = "arm,cortex-a55-pmu"; 284 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 285 }; 286 287 psci { 288 compatible = "arm,psci-1.0", "arm,psci-0.2"; 289 method = "smc"; 290 }; 291 292 /* External SCIF clock - to be overridden by boards that provide it */ 293 scif_clk: scif { 294 compatible = "fixed-clock"; 295 #clock-cells = <0>; 296 clock-frequency = <0>; 297 }; 298 299 soc: soc { 300 compatible = "simple-bus"; 301 bootph-all; 302 303 #address-cells = <2>; 304 #size-cells = <2>; 305 ranges; 306 307 rwdt: watchdog@e6020000 { 308 compatible = "renesas,r8a779f0-wdt", 309 "renesas,rcar-gen4-wdt"; 310 reg = <0 0xe6020000 0 0x0c>; 311 interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 312 clocks = <&cpg CPG_MOD 907>; 313 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 314 resets = <&cpg 907>; 315 status = "disabled"; 316 }; 317 318 swdt: watchdog@e6030000 { 319 compatible = "renesas,r8a779f0-wdt", "renesas,rcar-gen4-wdt"; 320 reg = <0 0xe6030000 0 0x0c>; 321 interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&cpg CPG_CORE R8A779F0_CLK_OSC>; 323 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 324 resets = <&cpg 1128>; 325 status = "disabled"; 326 }; 327 328 pfc: pinctrl@e6050000 { 329 compatible = "renesas,pfc-r8a779f0"; 330 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 331 <0 0xe6051000 0 0x16c>, <0 0xe6051800 0 0x16c>; 332 bootph-all; 333 }; 334 335 gpio0: gpio@e6050180 { 336 compatible = "renesas,gpio-r8a779f0", 337 "renesas,rcar-gen4-gpio"; 338 reg = <0 0xe6050180 0 0x54>; 339 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&cpg CPG_MOD 915>; 341 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 342 resets = <&cpg 915>; 343 gpio-controller; 344 #gpio-cells = <2>; 345 gpio-ranges = <&pfc 0 0 21>; 346 interrupt-controller; 347 #interrupt-cells = <2>; 348 }; 349 350 gpio1: gpio@e6050980 { 351 compatible = "renesas,gpio-r8a779f0", 352 "renesas,rcar-gen4-gpio"; 353 reg = <0 0xe6050980 0 0x54>; 354 interrupts = <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&cpg CPG_MOD 915>; 356 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 357 resets = <&cpg 915>; 358 gpio-controller; 359 #gpio-cells = <2>; 360 gpio-ranges = <&pfc 0 32 25>; 361 interrupt-controller; 362 #interrupt-cells = <2>; 363 }; 364 365 gpio2: gpio@e6051180 { 366 compatible = "renesas,gpio-r8a779f0", 367 "renesas,rcar-gen4-gpio"; 368 reg = <0 0xe6051180 0 0x54>; 369 interrupts = <GIC_SPI 824 IRQ_TYPE_LEVEL_HIGH>; 370 clocks = <&cpg CPG_MOD 915>; 371 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 372 resets = <&cpg 915>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 gpio-ranges = <&pfc 0 64 17>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 }; 379 380 gpio3: gpio@e6051980 { 381 compatible = "renesas,gpio-r8a779f0", 382 "renesas,rcar-gen4-gpio"; 383 reg = <0 0xe6051980 0 0x54>; 384 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH>; 385 clocks = <&cpg CPG_MOD 915>; 386 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 387 resets = <&cpg 915>; 388 gpio-controller; 389 #gpio-cells = <2>; 390 gpio-ranges = <&pfc 0 96 19>; 391 interrupt-controller; 392 #interrupt-cells = <2>; 393 }; 394 395 fuse: fuse@e6078800 { 396 compatible = "renesas,r8a779f0-efuse"; 397 reg = <0 0xe6078800 0 0x200>; 398 clocks = <&cpg CPG_MOD 915>; 399 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 400 resets = <&cpg 915>; 401 }; 402 403 cmt0: timer@e60f0000 { 404 compatible = "renesas,r8a779f0-cmt0", 405 "renesas,rcar-gen4-cmt0"; 406 reg = <0 0xe60f0000 0 0x1004>; 407 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&cpg CPG_MOD 910>; 410 clock-names = "fck"; 411 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 412 resets = <&cpg 910>; 413 status = "disabled"; 414 }; 415 416 cmt1: timer@e6130000 { 417 compatible = "renesas,r8a779f0-cmt1", 418 "renesas,rcar-gen4-cmt1"; 419 reg = <0 0xe6130000 0 0x1004>; 420 interrupts = <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 421 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 422 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&cpg CPG_MOD 911>; 429 clock-names = "fck"; 430 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 431 resets = <&cpg 911>; 432 status = "disabled"; 433 }; 434 435 cmt2: timer@e6140000 { 436 compatible = "renesas,r8a779f0-cmt1", 437 "renesas,rcar-gen4-cmt1"; 438 reg = <0 0xe6140000 0 0x1004>; 439 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 440 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 444 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>, 445 <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 446 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&cpg CPG_MOD 912>; 448 clock-names = "fck"; 449 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 450 resets = <&cpg 912>; 451 status = "disabled"; 452 }; 453 454 cmt3: timer@e6148000 { 455 compatible = "renesas,r8a779f0-cmt1", 456 "renesas,rcar-gen4-cmt1"; 457 reg = <0 0xe6148000 0 0x1004>; 458 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 466 clocks = <&cpg CPG_MOD 913>; 467 clock-names = "fck"; 468 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 469 resets = <&cpg 913>; 470 status = "disabled"; 471 }; 472 473 cpg: clock-controller@e6150000 { 474 compatible = "renesas,r8a779f0-cpg-mssr"; 475 reg = <0 0xe6150000 0 0x4000>; 476 clocks = <&extal_clk>, <&extalr_clk>; 477 clock-names = "extal", "extalr"; 478 #clock-cells = <2>; 479 #power-domain-cells = <0>; 480 #reset-cells = <1>; 481 bootph-all; 482 }; 483 484 rst: reset-controller@e6160000 { 485 compatible = "renesas,r8a779f0-rst"; 486 reg = <0 0xe6160000 0 0x4000>; 487 bootph-all; 488 }; 489 490 sysc: system-controller@e6180000 { 491 compatible = "renesas,r8a779f0-sysc"; 492 reg = <0 0xe6180000 0 0x4000>; 493 #power-domain-cells = <1>; 494 }; 495 496 tsc: thermal@e6198000 { 497 compatible = "renesas,r8a779f0-thermal"; 498 /* The 4th sensor is in control domain and not for Linux */ 499 reg = <0 0xe6198000 0 0x200>, 500 <0 0xe61a0000 0 0x200>, 501 <0 0xe61a8000 0 0x200>; 502 clocks = <&cpg CPG_MOD 919>; 503 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 504 resets = <&cpg 919>; 505 #thermal-sensor-cells = <1>; 506 }; 507 508 intc_ex: interrupt-controller@e61c0000 { 509 compatible = "renesas,intc-ex-r8a779f0", "renesas,irqc"; 510 #interrupt-cells = <2>; 511 interrupt-controller; 512 reg = <0 0xe61c0000 0 0x200>; 513 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 514 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 515 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 516 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 517 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 518 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 519 clocks = <&cpg CPG_CORE R8A779F0_CLK_CL16M>; 520 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 521 }; 522 523 tmu0: timer@e61e0000 { 524 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 525 reg = <0 0xe61e0000 0 0x30>; 526 interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>; 529 interrupt-names = "tuni0", "tuni1", "tuni2"; 530 clocks = <&cpg CPG_MOD 713>; 531 clock-names = "fck"; 532 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 533 resets = <&cpg 713>; 534 status = "disabled"; 535 }; 536 537 tmu1: timer@e6fc0000 { 538 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 539 reg = <0 0xe6fc0000 0 0x30>; 540 interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 479 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 480 IRQ_TYPE_LEVEL_HIGH>; 544 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 545 clocks = <&cpg CPG_MOD 714>; 546 clock-names = "fck"; 547 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 548 resets = <&cpg 714>; 549 status = "disabled"; 550 }; 551 552 tmu2: timer@e6fd0000 { 553 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 554 reg = <0 0xe6fd0000 0 0x30>; 555 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 482 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 483 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>; 559 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 560 clocks = <&cpg CPG_MOD 715>; 561 clock-names = "fck"; 562 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 563 resets = <&cpg 715>; 564 status = "disabled"; 565 }; 566 567 tmu3: timer@e6fe0000 { 568 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 569 reg = <0 0xe6fe0000 0 0x30>; 570 interrupts = <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>; 574 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 575 clocks = <&cpg CPG_MOD 716>; 576 clock-names = "fck"; 577 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 578 resets = <&cpg 716>; 579 status = "disabled"; 580 }; 581 582 tmu4: timer@ffc00000 { 583 compatible = "renesas,tmu-r8a779f0", "renesas,tmu"; 584 reg = <0 0xffc00000 0 0x30>; 585 interrupts = <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 586 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>; 589 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 590 clocks = <&cpg CPG_MOD 717>; 591 clock-names = "fck"; 592 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 593 resets = <&cpg 717>; 594 status = "disabled"; 595 }; 596 597 eth_serdes: phy@e6444000 { 598 compatible = "renesas,r8a779f0-ether-serdes"; 599 reg = <0 0xe6444000 0 0x2800>; 600 clocks = <&cpg CPG_MOD 1506>; 601 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 602 resets = <&cpg 1506>; 603 #phy-cells = <1>; 604 status = "disabled"; 605 }; 606 607 i2c0: i2c@e6500000 { 608 compatible = "renesas,i2c-r8a779f0", 609 "renesas,rcar-gen4-i2c"; 610 reg = <0 0xe6500000 0 0x40>; 611 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 612 clocks = <&cpg CPG_MOD 518>; 613 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 614 resets = <&cpg 518>; 615 dmas = <&dmac0 0x91>, <&dmac0 0x90>, 616 <&dmac1 0x91>, <&dmac1 0x90>; 617 dma-names = "tx", "rx", "tx", "rx"; 618 i2c-scl-internal-delay-ns = <110>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 status = "disabled"; 622 }; 623 624 i2c1: i2c@e6508000 { 625 compatible = "renesas,i2c-r8a779f0", 626 "renesas,rcar-gen4-i2c"; 627 reg = <0 0xe6508000 0 0x40>; 628 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 629 clocks = <&cpg CPG_MOD 519>; 630 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 631 resets = <&cpg 519>; 632 dmas = <&dmac0 0x93>, <&dmac0 0x92>, 633 <&dmac1 0x93>, <&dmac1 0x92>; 634 dma-names = "tx", "rx", "tx", "rx"; 635 i2c-scl-internal-delay-ns = <110>; 636 #address-cells = <1>; 637 #size-cells = <0>; 638 status = "disabled"; 639 }; 640 641 i2c2: i2c@e6510000 { 642 compatible = "renesas,i2c-r8a779f0", 643 "renesas,rcar-gen4-i2c"; 644 reg = <0 0xe6510000 0 0x40>; 645 interrupts = <0 240 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&cpg CPG_MOD 520>; 647 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 648 resets = <&cpg 520>; 649 dmas = <&dmac0 0x95>, <&dmac0 0x94>, 650 <&dmac1 0x95>, <&dmac1 0x94>; 651 dma-names = "tx", "rx", "tx", "rx"; 652 i2c-scl-internal-delay-ns = <110>; 653 #address-cells = <1>; 654 #size-cells = <0>; 655 status = "disabled"; 656 }; 657 658 i2c3: i2c@e66d0000 { 659 compatible = "renesas,i2c-r8a779f0", 660 "renesas,rcar-gen4-i2c"; 661 reg = <0 0xe66d0000 0 0x40>; 662 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 663 clocks = <&cpg CPG_MOD 521>; 664 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 665 resets = <&cpg 521>; 666 dmas = <&dmac0 0x97>, <&dmac0 0x96>, 667 <&dmac1 0x97>, <&dmac1 0x96>; 668 dma-names = "tx", "rx", "tx", "rx"; 669 i2c-scl-internal-delay-ns = <110>; 670 #address-cells = <1>; 671 #size-cells = <0>; 672 status = "disabled"; 673 }; 674 675 i2c4: i2c@e66d8000 { 676 compatible = "renesas,i2c-r8a779f0", 677 "renesas,rcar-gen4-i2c"; 678 reg = <0 0xe66d8000 0 0x40>; 679 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&cpg CPG_MOD 522>; 681 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 682 resets = <&cpg 522>; 683 dmas = <&dmac0 0x99>, <&dmac0 0x98>, 684 <&dmac1 0x99>, <&dmac1 0x98>; 685 dma-names = "tx", "rx", "tx", "rx"; 686 i2c-scl-internal-delay-ns = <110>; 687 #address-cells = <1>; 688 #size-cells = <0>; 689 status = "disabled"; 690 }; 691 692 i2c5: i2c@e66e0000 { 693 compatible = "renesas,i2c-r8a779f0", 694 "renesas,rcar-gen4-i2c"; 695 reg = <0 0xe66e0000 0 0x40>; 696 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&cpg CPG_MOD 523>; 698 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 699 resets = <&cpg 523>; 700 dmas = <&dmac0 0x9b>, <&dmac0 0x9a>, 701 <&dmac1 0x9b>, <&dmac1 0x9a>; 702 dma-names = "tx", "rx", "tx", "rx"; 703 i2c-scl-internal-delay-ns = <110>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 status = "disabled"; 707 }; 708 709 hscif0: serial@e6540000 { 710 compatible = "renesas,hscif-r8a779f0", 711 "renesas,rcar-gen4-hscif", "renesas,hscif"; 712 reg = <0 0xe6540000 0 0x60>; 713 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&cpg CPG_MOD 514>, 715 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 716 <&scif_clk>; 717 clock-names = "fck", "brg_int", "scif_clk"; 718 dmas = <&dmac0 0x31>, <&dmac0 0x30>, 719 <&dmac1 0x31>, <&dmac1 0x30>; 720 dma-names = "tx", "rx", "tx", "rx"; 721 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 722 resets = <&cpg 514>; 723 status = "disabled"; 724 }; 725 726 hscif1: serial@e6550000 { 727 compatible = "renesas,hscif-r8a779f0", 728 "renesas,rcar-gen4-hscif", "renesas,hscif"; 729 reg = <0 0xe6550000 0 0x60>; 730 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 731 clocks = <&cpg CPG_MOD 515>, 732 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 733 <&scif_clk>; 734 clock-names = "fck", "brg_int", "scif_clk"; 735 dmas = <&dmac0 0x33>, <&dmac0 0x32>, 736 <&dmac1 0x33>, <&dmac1 0x32>; 737 dma-names = "tx", "rx", "tx", "rx"; 738 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 739 resets = <&cpg 515>; 740 status = "disabled"; 741 }; 742 743 hscif2: serial@e6560000 { 744 compatible = "renesas,hscif-r8a779f0", 745 "renesas,rcar-gen4-hscif", "renesas,hscif"; 746 reg = <0 0xe6560000 0 0x60>; 747 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&cpg CPG_MOD 516>, 749 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 750 <&scif_clk>; 751 clock-names = "fck", "brg_int", "scif_clk"; 752 dmas = <&dmac0 0x35>, <&dmac0 0x34>, 753 <&dmac1 0x35>, <&dmac1 0x34>; 754 dma-names = "tx", "rx", "tx", "rx"; 755 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 756 resets = <&cpg 516>; 757 status = "disabled"; 758 }; 759 760 hscif3: serial@e66a0000 { 761 compatible = "renesas,hscif-r8a779f0", 762 "renesas,rcar-gen4-hscif", "renesas,hscif"; 763 reg = <0 0xe66a0000 0 0x60>; 764 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&cpg CPG_MOD 517>, 766 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 767 <&scif_clk>; 768 clock-names = "fck", "brg_int", "scif_clk"; 769 dmas = <&dmac0 0x37>, <&dmac0 0x36>, 770 <&dmac1 0x37>, <&dmac1 0x36>; 771 dma-names = "tx", "rx", "tx", "rx"; 772 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 773 resets = <&cpg 517>; 774 status = "disabled"; 775 }; 776 777 pciec0: pcie@e65d0000 { 778 compatible = "renesas,r8a779f0-pcie", 779 "renesas,rcar-gen4-pcie"; 780 reg = <0 0xe65d0000 0 0x1000>, <0 0xe65d2000 0 0x0800>, 781 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, 782 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, 783 <0 0xfe000000 0 0x400000>; 784 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; 785 interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 789 interrupt-names = "msi", "dma", "sft_ce", "app"; 790 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; 791 clock-names = "core", "ref"; 792 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 793 resets = <&cpg 624>; 794 reset-names = "pwr"; 795 max-link-speed = <4>; 796 num-lanes = <2>; 797 #address-cells = <3>; 798 #size-cells = <2>; 799 bus-range = <0x00 0xff>; 800 device_type = "pci"; 801 ranges = <0x01000000 0 0x00000000 0 0xfe000000 0 0x00400000>, 802 <0x02000000 0 0x30000000 0 0x30000000 0 0x10000000>; 803 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 804 #interrupt-cells = <1>; 805 interrupt-map-mask = <0 0 0 7>; 806 interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 807 <0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 808 <0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 809 <0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; 810 snps,enable-cdm-check; 811 status = "disabled"; 812 }; 813 814 pciec1: pcie@e65d8000 { 815 compatible = "renesas,r8a779f0-pcie", 816 "renesas,rcar-gen4-pcie"; 817 reg = <0 0xe65d8000 0 0x1000>, <0 0xe65da000 0 0x0800>, 818 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, 819 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, 820 <0 0xee900000 0 0x400000>; 821 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "config"; 822 interrupts = <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 823 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 826 interrupt-names = "msi", "dma", "sft_ce", "app"; 827 clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; 828 clock-names = "core", "ref"; 829 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 830 resets = <&cpg 625>; 831 reset-names = "pwr"; 832 max-link-speed = <4>; 833 num-lanes = <2>; 834 #address-cells = <3>; 835 #size-cells = <2>; 836 bus-range = <0x00 0xff>; 837 device_type = "pci"; 838 ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00400000>, 839 <0x02000000 0 0xc0000000 0 0xc0000000 0 0x10000000>; 840 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 841 #interrupt-cells = <1>; 842 interrupt-map-mask = <0 0 0 7>; 843 interrupt-map = <0 0 0 1 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 844 <0 0 0 2 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 845 <0 0 0 3 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 846 <0 0 0 4 &gic GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>; 847 snps,enable-cdm-check; 848 status = "disabled"; 849 }; 850 851 pciec0_ep: pcie-ep@e65d0000 { 852 compatible = "renesas,r8a779f0-pcie-ep", 853 "renesas,rcar-gen4-pcie-ep"; 854 reg = <0 0xe65d0000 0 0x2000>, <0 0xe65d2000 0 0x1000>, 855 <0 0xe65d3000 0 0x2000>, <0 0xe65d5000 0 0x1200>, 856 <0 0xe65d6200 0 0x0e00>, <0 0xe65d7000 0 0x0400>, 857 <0 0xfe000000 0 0x400000>; 858 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; 859 interrupts = <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 862 interrupt-names = "dma", "sft_ce", "app"; 863 clocks = <&cpg CPG_MOD 624>, <&pcie0_clkref>; 864 clock-names = "core", "ref"; 865 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 866 resets = <&cpg 624>; 867 reset-names = "pwr"; 868 max-link-speed = <4>; 869 num-lanes = <2>; 870 max-functions = /bits/ 8 <2>; 871 status = "disabled"; 872 }; 873 874 pciec1_ep: pcie-ep@e65d8000 { 875 compatible = "renesas,r8a779f0-pcie-ep", 876 "renesas,rcar-gen4-pcie-ep"; 877 reg = <0 0xe65d8000 0 0x2000>, <0 0xe65da000 0 0x1000>, 878 <0 0xe65db000 0 0x2000>, <0 0xe65dd000 0 0x1200>, 879 <0 0xe65de200 0 0x0e00>, <0 0xe65df000 0 0x0400>, 880 <0 0xee900000 0 0x400000>; 881 reg-names = "dbi", "dbi2", "atu", "dma", "app", "phy", "addr_space"; 882 interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>; 885 interrupt-names = "dma", "sft_ce", "app"; 886 clocks = <&cpg CPG_MOD 625>, <&pcie1_clkref>; 887 clock-names = "core", "ref"; 888 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 889 resets = <&cpg 625>; 890 reset-names = "pwr"; 891 max-link-speed = <4>; 892 num-lanes = <2>; 893 max-functions = /bits/ 8 <2>; 894 status = "disabled"; 895 }; 896 897 ufs: ufs@e6860000 { 898 compatible = "renesas,r8a779f0-ufs"; 899 reg = <0 0xe6860000 0 0x100>; 900 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 901 clocks = <&cpg CPG_MOD 1514>, <&ufs30_clk>; 902 clock-names = "fck", "ref_clk"; 903 freq-table-hz = <200000000 200000000>, <38400000 38400000>; 904 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 905 resets = <&cpg 1514>; 906 status = "disabled"; 907 }; 908 909 rswitch: ethernet@e6880000 { 910 compatible = "renesas,r8a779f0-ether-switch"; 911 reg = <0 0xe6880000 0 0x20000>, <0 0xe68c0000 0 0x20000>; 912 reg-names = "base", "secure_base"; 913 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 915 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 916 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 917 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 918 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 919 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 920 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 921 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 922 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 923 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 924 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 938 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 960 interrupt-names = "mfwd_error", "race_error", 961 "coma_error", "gwca0_error", 962 "gwca1_error", "etha0_error", 963 "etha1_error", "etha2_error", 964 "gptp0_status", "gptp1_status", 965 "mfwd_status", "race_status", 966 "coma_status", "gwca0_status", 967 "gwca1_status", "etha0_status", 968 "etha1_status", "etha2_status", 969 "rmac0_status", "rmac1_status", 970 "rmac2_status", 971 "gwca0_rxtx0", "gwca0_rxtx1", 972 "gwca0_rxtx2", "gwca0_rxtx3", 973 "gwca0_rxtx4", "gwca0_rxtx5", 974 "gwca0_rxtx6", "gwca0_rxtx7", 975 "gwca1_rxtx0", "gwca1_rxtx1", 976 "gwca1_rxtx2", "gwca1_rxtx3", 977 "gwca1_rxtx4", "gwca1_rxtx5", 978 "gwca1_rxtx6", "gwca1_rxtx7", 979 "gwca0_rxts0", "gwca0_rxts1", 980 "gwca1_rxts0", "gwca1_rxts1", 981 "rmac0_mdio", "rmac1_mdio", 982 "rmac2_mdio", 983 "rmac0_phy", "rmac1_phy", 984 "rmac2_phy"; 985 clocks = <&cpg CPG_MOD 1505>; 986 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 987 resets = <&cpg 1505>; 988 status = "disabled"; 989 990 ethernet-ports { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 994 rswitch_port0: port@0 { 995 reg = <0>; 996 phys = <ð_serdes 0>; 997 status = "disabled"; 998 }; 999 rswitch_port1: port@1 { 1000 reg = <1>; 1001 phys = <ð_serdes 1>; 1002 status = "disabled"; 1003 }; 1004 rswitch_port2: port@2 { 1005 reg = <2>; 1006 phys = <ð_serdes 2>; 1007 status = "disabled"; 1008 }; 1009 }; 1010 }; 1011 1012 scif0: serial@e6e60000 { 1013 compatible = "renesas,scif-r8a779f0", 1014 "renesas,rcar-gen4-scif", "renesas,scif"; 1015 reg = <0 0xe6e60000 0 64>; 1016 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 1017 clocks = <&cpg CPG_MOD 702>, 1018 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1019 <&scif_clk>; 1020 clock-names = "fck", "brg_int", "scif_clk"; 1021 dmas = <&dmac0 0x51>, <&dmac0 0x50>, 1022 <&dmac1 0x51>, <&dmac1 0x50>; 1023 dma-names = "tx", "rx", "tx", "rx"; 1024 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1025 resets = <&cpg 702>; 1026 status = "disabled"; 1027 }; 1028 1029 scif1: serial@e6e68000 { 1030 compatible = "renesas,scif-r8a779f0", 1031 "renesas,rcar-gen4-scif", "renesas,scif"; 1032 reg = <0 0xe6e68000 0 64>; 1033 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; 1034 clocks = <&cpg CPG_MOD 703>, 1035 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1036 <&scif_clk>; 1037 clock-names = "fck", "brg_int", "scif_clk"; 1038 dmas = <&dmac0 0x53>, <&dmac0 0x52>, 1039 <&dmac1 0x53>, <&dmac1 0x52>; 1040 dma-names = "tx", "rx", "tx", "rx"; 1041 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1042 resets = <&cpg 703>; 1043 status = "disabled"; 1044 }; 1045 1046 scif3: serial@e6c50000 { 1047 compatible = "renesas,scif-r8a779f0", 1048 "renesas,rcar-gen4-scif", "renesas,scif"; 1049 reg = <0 0xe6c50000 0 64>; 1050 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&cpg CPG_MOD 704>, 1052 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1053 <&scif_clk>; 1054 clock-names = "fck", "brg_int", "scif_clk"; 1055 dmas = <&dmac0 0x57>, <&dmac0 0x56>, 1056 <&dmac1 0x57>, <&dmac1 0x56>; 1057 dma-names = "tx", "rx", "tx", "rx"; 1058 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1059 resets = <&cpg 704>; 1060 status = "disabled"; 1061 }; 1062 1063 scif4: serial@e6c40000 { 1064 compatible = "renesas,scif-r8a779f0", 1065 "renesas,rcar-gen4-scif", "renesas,scif"; 1066 reg = <0 0xe6c40000 0 64>; 1067 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 1068 clocks = <&cpg CPG_MOD 705>, 1069 <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>, 1070 <&scif_clk>; 1071 clock-names = "fck", "brg_int", "scif_clk"; 1072 dmas = <&dmac0 0x59>, <&dmac0 0x58>, 1073 <&dmac1 0x59>, <&dmac1 0x58>; 1074 dma-names = "tx", "rx", "tx", "rx"; 1075 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1076 resets = <&cpg 705>; 1077 status = "disabled"; 1078 }; 1079 1080 msiof0: spi@e6e90000 { 1081 compatible = "renesas,msiof-r8a779f0", 1082 "renesas,rcar-gen4-msiof"; 1083 reg = <0 0xe6e90000 0 0x0064>; 1084 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&cpg CPG_MOD 618>; 1086 dmas = <&dmac0 0x41>, <&dmac0 0x40>, 1087 <&dmac1 0x41>, <&dmac1 0x40>; 1088 dma-names = "tx", "rx", "tx", "rx"; 1089 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1090 resets = <&cpg 618>; 1091 #address-cells = <1>; 1092 #size-cells = <0>; 1093 status = "disabled"; 1094 }; 1095 1096 msiof1: spi@e6ea0000 { 1097 compatible = "renesas,msiof-r8a779f0", 1098 "renesas,rcar-gen4-msiof"; 1099 reg = <0 0xe6ea0000 0 0x0064>; 1100 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>; 1101 clocks = <&cpg CPG_MOD 619>; 1102 dmas = <&dmac0 0x43>, <&dmac0 0x42>, 1103 <&dmac1 0x43>, <&dmac1 0x42>; 1104 dma-names = "tx", "rx", "tx", "rx"; 1105 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1106 resets = <&cpg 619>; 1107 #address-cells = <1>; 1108 #size-cells = <0>; 1109 status = "disabled"; 1110 }; 1111 1112 msiof2: spi@e6c00000 { 1113 compatible = "renesas,msiof-r8a779f0", 1114 "renesas,rcar-gen4-msiof"; 1115 reg = <0 0xe6c00000 0 0x0064>; 1116 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&cpg CPG_MOD 620>; 1118 dmas = <&dmac0 0x45>, <&dmac0 0x44>, 1119 <&dmac1 0x45>, <&dmac1 0x44>; 1120 dma-names = "tx", "rx", "tx", "rx"; 1121 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1122 resets = <&cpg 620>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 msiof3: spi@e6c10000 { 1129 compatible = "renesas,msiof-r8a779f0", 1130 "renesas,rcar-gen4-msiof"; 1131 reg = <0 0xe6c10000 0 0x0064>; 1132 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&cpg CPG_MOD 621>; 1134 dmas = <&dmac0 0x47>, <&dmac0 0x46>, 1135 <&dmac1 0x47>, <&dmac1 0x46>; 1136 dma-names = "tx", "rx", "tx", "rx"; 1137 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1138 resets = <&cpg 621>; 1139 #address-cells = <1>; 1140 #size-cells = <0>; 1141 status = "disabled"; 1142 }; 1143 1144 dmac0: dma-controller@e7350000 { 1145 compatible = "renesas,dmac-r8a779f0", 1146 "renesas,rcar-gen4-dmac"; 1147 reg = <0 0xe7350000 0 0x1000>, 1148 <0 0xe7300000 0 0x10000>; 1149 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1150 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1153 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1154 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1155 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1156 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1157 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1158 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1159 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1160 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1161 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1162 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1163 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 1166 interrupt-names = "error", 1167 "ch0", "ch1", "ch2", "ch3", "ch4", 1168 "ch5", "ch6", "ch7", "ch8", "ch9", 1169 "ch10", "ch11", "ch12", "ch13", 1170 "ch14", "ch15"; 1171 clocks = <&cpg CPG_MOD 709>; 1172 clock-names = "fck"; 1173 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1174 resets = <&cpg 709>; 1175 #dma-cells = <1>; 1176 dma-channels = <16>; 1177 iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>, 1178 <&ipmmu_ds0 2>, <&ipmmu_ds0 3>, 1179 <&ipmmu_ds0 4>, <&ipmmu_ds0 5>, 1180 <&ipmmu_ds0 6>, <&ipmmu_ds0 7>, 1181 <&ipmmu_ds0 8>, <&ipmmu_ds0 9>, 1182 <&ipmmu_ds0 10>, <&ipmmu_ds0 11>, 1183 <&ipmmu_ds0 12>, <&ipmmu_ds0 13>, 1184 <&ipmmu_ds0 14>, <&ipmmu_ds0 15>; 1185 }; 1186 1187 dmac1: dma-controller@e7351000 { 1188 compatible = "renesas,dmac-r8a779f0", 1189 "renesas,rcar-gen4-dmac"; 1190 reg = <0 0xe7351000 0 0x1000>, 1191 <0 0xe7310000 0 0x10000>; 1192 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1205 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1206 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 1207 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1208 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1209 interrupt-names = "error", 1210 "ch0", "ch1", "ch2", "ch3", "ch4", 1211 "ch5", "ch6", "ch7", "ch8", "ch9", 1212 "ch10", "ch11", "ch12", "ch13", 1213 "ch14", "ch15"; 1214 clocks = <&cpg CPG_MOD 710>; 1215 clock-names = "fck"; 1216 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1217 resets = <&cpg 710>; 1218 #dma-cells = <1>; 1219 dma-channels = <16>; 1220 iommus = <&ipmmu_ds0 16>, <&ipmmu_ds0 17>, 1221 <&ipmmu_ds0 18>, <&ipmmu_ds0 19>, 1222 <&ipmmu_ds0 20>, <&ipmmu_ds0 21>, 1223 <&ipmmu_ds0 22>, <&ipmmu_ds0 23>, 1224 <&ipmmu_ds0 24>, <&ipmmu_ds0 25>, 1225 <&ipmmu_ds0 26>, <&ipmmu_ds0 27>, 1226 <&ipmmu_ds0 28>, <&ipmmu_ds0 29>, 1227 <&ipmmu_ds0 30>, <&ipmmu_ds0 31>; 1228 }; 1229 1230 mmc0: mmc@ee140000 { 1231 compatible = "renesas,sdhi-r8a779f0", 1232 "renesas,rcar-gen4-sdhi"; 1233 reg = <0 0xee140000 0 0x2000>; 1234 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&cpg CPG_MOD 706>, <&cpg CPG_CORE R8A779F0_CLK_SD0H>; 1236 clock-names = "core", "clkh"; 1237 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1238 resets = <&cpg 706>; 1239 max-frequency = <200000000>; 1240 iommus = <&ipmmu_ds0 32>; 1241 status = "disabled"; 1242 }; 1243 1244 ipmmu_rt0: iommu@ee480000 { 1245 compatible = "renesas,ipmmu-r8a779f0", 1246 "renesas,rcar-gen4-ipmmu-vmsa"; 1247 reg = <0 0xee480000 0 0x20000>; 1248 renesas,ipmmu-main = <&ipmmu_mm>; 1249 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1250 #iommu-cells = <1>; 1251 }; 1252 1253 ipmmu_rt1: iommu@ee4c0000 { 1254 compatible = "renesas,ipmmu-r8a779f0", 1255 "renesas,rcar-gen4-ipmmu-vmsa"; 1256 reg = <0 0xee4c0000 0 0x20000>; 1257 renesas,ipmmu-main = <&ipmmu_mm>; 1258 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1259 #iommu-cells = <1>; 1260 }; 1261 1262 ipmmu_ds0: iommu@eed00000 { 1263 compatible = "renesas,ipmmu-r8a779f0", 1264 "renesas,rcar-gen4-ipmmu-vmsa"; 1265 reg = <0 0xeed00000 0 0x20000>; 1266 renesas,ipmmu-main = <&ipmmu_mm>; 1267 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1268 #iommu-cells = <1>; 1269 }; 1270 1271 ipmmu_hc: iommu@eed40000 { 1272 compatible = "renesas,ipmmu-r8a779f0", 1273 "renesas,rcar-gen4-ipmmu-vmsa"; 1274 reg = <0 0xeed40000 0 0x20000>; 1275 renesas,ipmmu-main = <&ipmmu_mm>; 1276 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1277 #iommu-cells = <1>; 1278 }; 1279 1280 ipmmu_mm: iommu@eefc0000 { 1281 compatible = "renesas,ipmmu-r8a779f0", 1282 "renesas,rcar-gen4-ipmmu-vmsa"; 1283 reg = <0 0xeefc0000 0 0x20000>; 1284 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 1285 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1286 power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; 1287 #iommu-cells = <1>; 1288 }; 1289 1290 gic: interrupt-controller@f1000000 { 1291 compatible = "arm,gic-v3"; 1292 #interrupt-cells = <3>; 1293 #address-cells = <0>; 1294 interrupt-controller; 1295 reg = <0x0 0xf1000000 0 0x20000>, 1296 <0x0 0xf1060000 0 0x110000>; 1297 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1298 }; 1299 1300 prr: chipid@fff00044 { 1301 compatible = "renesas,prr"; 1302 reg = <0 0xfff00044 0 4>; 1303 bootph-all; 1304 }; 1305 }; 1306 1307 thermal-zones { 1308 sensor_thermal_rtcore: sensor1-thermal { 1309 polling-delay-passive = <250>; 1310 polling-delay = <1000>; 1311 thermal-sensors = <&tsc 0>; 1312 1313 trips { 1314 sensor1_crit: sensor1-crit { 1315 temperature = <120000>; 1316 hysteresis = <1000>; 1317 type = "critical"; 1318 }; 1319 }; 1320 }; 1321 1322 sensor_thermal_apcore0: sensor2-thermal { 1323 polling-delay-passive = <250>; 1324 polling-delay = <1000>; 1325 thermal-sensors = <&tsc 1>; 1326 1327 trips { 1328 sensor2_crit: sensor2-crit { 1329 temperature = <120000>; 1330 hysteresis = <1000>; 1331 type = "critical"; 1332 }; 1333 }; 1334 }; 1335 1336 sensor_thermal_apcore4: sensor3-thermal { 1337 polling-delay-passive = <250>; 1338 polling-delay = <1000>; 1339 thermal-sensors = <&tsc 2>; 1340 1341 trips { 1342 sensor3_crit: sensor3-crit { 1343 temperature = <120000>; 1344 hysteresis = <1000>; 1345 type = "critical"; 1346 }; 1347 }; 1348 }; 1349 }; 1350 1351 timer { 1352 compatible = "arm,armv8-timer"; 1353 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1354 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1355 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1356 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1357 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1358 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", 1359 "hyp-virt"; 1360 }; 1361 1362 ufs30_clk: ufs30-clk { 1363 compatible = "fixed-clock"; 1364 #clock-cells = <0>; 1365 /* This value must be overridden by the board */ 1366 clock-frequency = <0>; 1367 }; 1368};
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