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r8a77980.dtsi
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linux-6.19.14/arch/arm64/boot/dts/renesas/r8a77980.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3H (R8A77980) SoC 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77980-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/r8a77980-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77980"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&gic>; 19 20 /* External CAN clock - to be overridden by boards that provide it */ 21 can_clk: can { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <0>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 a53_0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 reg = <0>; 35 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 36 power-domains = <&sysc R8A77980_PD_CA53_CPU0>; 37 next-level-cache = <&L2_CA53>; 38 enable-method = "psci"; 39 }; 40 41 a53_1: cpu@1 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <1>; 45 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 46 power-domains = <&sysc R8A77980_PD_CA53_CPU1>; 47 next-level-cache = <&L2_CA53>; 48 enable-method = "psci"; 49 }; 50 51 a53_2: cpu@2 { 52 device_type = "cpu"; 53 compatible = "arm,cortex-a53"; 54 reg = <2>; 55 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 56 power-domains = <&sysc R8A77980_PD_CA53_CPU2>; 57 next-level-cache = <&L2_CA53>; 58 enable-method = "psci"; 59 }; 60 61 a53_3: cpu@3 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 reg = <3>; 65 clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>; 66 power-domains = <&sysc R8A77980_PD_CA53_CPU3>; 67 next-level-cache = <&L2_CA53>; 68 enable-method = "psci"; 69 }; 70 71 L2_CA53: cache-controller { 72 compatible = "cache"; 73 power-domains = <&sysc R8A77980_PD_CA53_SCU>; 74 cache-unified; 75 cache-level = <2>; 76 }; 77 }; 78 79 extal_clk: extal { 80 compatible = "fixed-clock"; 81 #clock-cells = <0>; 82 /* This value must be overridden by the board */ 83 clock-frequency = <0>; 84 bootph-all; 85 }; 86 87 extalr_clk: extalr { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 /* This value must be overridden by the board */ 91 clock-frequency = <0>; 92 bootph-all; 93 }; 94 95 /* External PCIe clock - can be overridden by the board */ 96 pcie_bus_clk: pcie_bus { 97 compatible = "fixed-clock"; 98 #clock-cells = <0>; 99 clock-frequency = <0>; 100 }; 101 102 pmu_a53 { 103 compatible = "arm,cortex-a53-pmu"; 104 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 105 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 106 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, 107 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 108 interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>; 109 }; 110 111 psci { 112 compatible = "arm,psci-1.0", "arm,psci-0.2"; 113 method = "smc"; 114 }; 115 116 /* External SCIF clock - to be overridden by boards that provide it */ 117 scif_clk: scif { 118 compatible = "fixed-clock"; 119 #clock-cells = <0>; 120 clock-frequency = <0>; 121 }; 122 123 soc { 124 compatible = "simple-bus"; 125 bootph-all; 126 127 #address-cells = <2>; 128 #size-cells = <2>; 129 ranges; 130 131 rwdt: watchdog@e6020000 { 132 compatible = "renesas,r8a77980-wdt", 133 "renesas,rcar-gen3-wdt"; 134 reg = <0 0xe6020000 0 0x0c>; 135 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 136 clocks = <&cpg CPG_MOD 402>; 137 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 138 resets = <&cpg 402>; 139 status = "disabled"; 140 }; 141 142 gpio0: gpio@e6050000 { 143 compatible = "renesas,gpio-r8a77980", 144 "renesas,rcar-gen3-gpio"; 145 reg = <0 0xe6050000 0 0x50>; 146 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 147 #gpio-cells = <2>; 148 gpio-controller; 149 gpio-ranges = <&pfc 0 0 22>; 150 #interrupt-cells = <2>; 151 interrupt-controller; 152 clocks = <&cpg CPG_MOD 912>; 153 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 154 resets = <&cpg 912>; 155 }; 156 157 gpio1: gpio@e6051000 { 158 compatible = "renesas,gpio-r8a77980", 159 "renesas,rcar-gen3-gpio"; 160 reg = <0 0xe6051000 0 0x50>; 161 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 162 #gpio-cells = <2>; 163 gpio-controller; 164 gpio-ranges = <&pfc 0 32 28>; 165 #interrupt-cells = <2>; 166 interrupt-controller; 167 clocks = <&cpg CPG_MOD 911>; 168 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 169 resets = <&cpg 911>; 170 }; 171 172 gpio2: gpio@e6052000 { 173 compatible = "renesas,gpio-r8a77980", 174 "renesas,rcar-gen3-gpio"; 175 reg = <0 0xe6052000 0 0x50>; 176 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 177 #gpio-cells = <2>; 178 gpio-controller; 179 gpio-ranges = <&pfc 0 64 30>; 180 #interrupt-cells = <2>; 181 interrupt-controller; 182 clocks = <&cpg CPG_MOD 910>; 183 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 184 resets = <&cpg 910>; 185 }; 186 187 gpio3: gpio@e6053000 { 188 compatible = "renesas,gpio-r8a77980", 189 "renesas,rcar-gen3-gpio"; 190 reg = <0 0xe6053000 0 0x50>; 191 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 192 #gpio-cells = <2>; 193 gpio-controller; 194 gpio-ranges = <&pfc 0 96 17>; 195 #interrupt-cells = <2>; 196 interrupt-controller; 197 clocks = <&cpg CPG_MOD 909>; 198 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 199 resets = <&cpg 909>; 200 }; 201 202 gpio4: gpio@e6054000 { 203 compatible = "renesas,gpio-r8a77980", 204 "renesas,rcar-gen3-gpio"; 205 reg = <0 0xe6054000 0 0x50>; 206 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 207 #gpio-cells = <2>; 208 gpio-controller; 209 gpio-ranges = <&pfc 0 128 25>; 210 #interrupt-cells = <2>; 211 interrupt-controller; 212 clocks = <&cpg CPG_MOD 908>; 213 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 214 resets = <&cpg 908>; 215 }; 216 217 gpio5: gpio@e6055000 { 218 compatible = "renesas,gpio-r8a77980", 219 "renesas,rcar-gen3-gpio"; 220 reg = <0 0xe6055000 0 0x50>; 221 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 222 #gpio-cells = <2>; 223 gpio-controller; 224 gpio-ranges = <&pfc 0 160 15>; 225 #interrupt-cells = <2>; 226 interrupt-controller; 227 clocks = <&cpg CPG_MOD 907>; 228 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 229 resets = <&cpg 907>; 230 }; 231 232 pfc: pinctrl@e6060000 { 233 compatible = "renesas,pfc-r8a77980"; 234 reg = <0 0xe6060000 0 0x50c>; 235 bootph-all; 236 }; 237 238 cmt0: timer@e60f0000 { 239 compatible = "renesas,r8a77980-cmt0", 240 "renesas,rcar-gen3-cmt0"; 241 reg = <0 0xe60f0000 0 0x1004>; 242 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&cpg CPG_MOD 303>; 245 clock-names = "fck"; 246 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 247 resets = <&cpg 303>; 248 status = "disabled"; 249 }; 250 251 cmt1: timer@e6130000 { 252 compatible = "renesas,r8a77980-cmt1", 253 "renesas,rcar-gen3-cmt1"; 254 reg = <0 0xe6130000 0 0x1004>; 255 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&cpg CPG_MOD 302>; 264 clock-names = "fck"; 265 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 266 resets = <&cpg 302>; 267 status = "disabled"; 268 }; 269 270 cmt2: timer@e6140000 { 271 compatible = "renesas,r8a77980-cmt1", 272 "renesas,rcar-gen3-cmt1"; 273 reg = <0 0xe6140000 0 0x1004>; 274 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&cpg CPG_MOD 301>; 283 clock-names = "fck"; 284 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 285 resets = <&cpg 301>; 286 status = "disabled"; 287 }; 288 289 cmt3: timer@e6148000 { 290 compatible = "renesas,r8a77980-cmt1", 291 "renesas,rcar-gen3-cmt1"; 292 reg = <0 0xe6148000 0 0x1004>; 293 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 301 clocks = <&cpg CPG_MOD 300>; 302 clock-names = "fck"; 303 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 304 resets = <&cpg 300>; 305 status = "disabled"; 306 }; 307 308 cpg: clock-controller@e6150000 { 309 compatible = "renesas,r8a77980-cpg-mssr"; 310 reg = <0 0xe6150000 0 0x1000>; 311 clocks = <&extal_clk>, <&extalr_clk>; 312 clock-names = "extal", "extalr"; 313 #clock-cells = <2>; 314 #power-domain-cells = <0>; 315 #reset-cells = <1>; 316 bootph-all; 317 }; 318 319 rst: reset-controller@e6160000 { 320 compatible = "renesas,r8a77980-rst"; 321 reg = <0 0xe6160000 0 0x200>; 322 bootph-all; 323 }; 324 325 sysc: system-controller@e6180000 { 326 compatible = "renesas,r8a77980-sysc"; 327 reg = <0 0xe6180000 0 0x440>; 328 #power-domain-cells = <1>; 329 }; 330 331 tsc: thermal@e6198000 { 332 compatible = "renesas,r8a77980-thermal"; 333 reg = <0 0xe6198000 0 0x100>, 334 <0 0xe61a0000 0 0x100>; 335 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 336 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 337 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&cpg CPG_MOD 522>; 339 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 340 resets = <&cpg 522>; 341 #thermal-sensor-cells = <1>; 342 }; 343 344 intc_ex: interrupt-controller@e61c0000 { 345 compatible = "renesas,intc-ex-r8a77980", "renesas,irqc"; 346 #interrupt-cells = <2>; 347 interrupt-controller; 348 reg = <0 0xe61c0000 0 0x200>; 349 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 350 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 351 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 352 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 353 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 354 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&cpg CPG_MOD 407>; 356 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 357 resets = <&cpg 407>; 358 }; 359 360 tmu0: timer@e61e0000 { 361 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 362 reg = <0 0xe61e0000 0 0x30>; 363 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 364 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 365 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 366 interrupt-names = "tuni0", "tuni1", "tuni2"; 367 clocks = <&cpg CPG_MOD 125>; 368 clock-names = "fck"; 369 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 370 resets = <&cpg 125>; 371 status = "disabled"; 372 }; 373 374 tmu1: timer@e6fc0000 { 375 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 376 reg = <0 0xe6fc0000 0 0x30>; 377 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 378 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 381 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 382 clocks = <&cpg CPG_MOD 124>; 383 clock-names = "fck"; 384 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 385 resets = <&cpg 124>; 386 status = "disabled"; 387 }; 388 389 tmu2: timer@e6fd0000 { 390 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 391 reg = <0 0xe6fd0000 0 0x30>; 392 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 393 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 394 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 395 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 396 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 397 clocks = <&cpg CPG_MOD 123>; 398 clock-names = "fck"; 399 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 400 resets = <&cpg 123>; 401 status = "disabled"; 402 }; 403 404 tmu3: timer@e6fe0000 { 405 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 406 reg = <0 0xe6fe0000 0 0x30>; 407 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 408 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 411 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 412 clocks = <&cpg CPG_MOD 122>; 413 clock-names = "fck"; 414 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 415 resets = <&cpg 122>; 416 status = "disabled"; 417 }; 418 419 tmu4: timer@ffc00000 { 420 compatible = "renesas,tmu-r8a77980", "renesas,tmu"; 421 reg = <0 0xffc00000 0 0x30>; 422 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 423 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 424 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 425 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 426 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 427 clocks = <&cpg CPG_MOD 121>; 428 clock-names = "fck"; 429 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 430 resets = <&cpg 121>; 431 status = "disabled"; 432 }; 433 434 i2c0: i2c@e6500000 { 435 compatible = "renesas,i2c-r8a77980", 436 "renesas,rcar-gen3-i2c"; 437 reg = <0 0xe6500000 0 0x40>; 438 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&cpg CPG_MOD 931>; 440 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 441 resets = <&cpg 931>; 442 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 443 <&dmac2 0x91>, <&dmac2 0x90>; 444 dma-names = "tx", "rx", "tx", "rx"; 445 i2c-scl-internal-delay-ns = <6>; 446 #address-cells = <1>; 447 #size-cells = <0>; 448 status = "disabled"; 449 }; 450 451 i2c1: i2c@e6508000 { 452 compatible = "renesas,i2c-r8a77980", 453 "renesas,rcar-gen3-i2c"; 454 reg = <0 0xe6508000 0 0x40>; 455 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 456 clocks = <&cpg CPG_MOD 930>; 457 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 458 resets = <&cpg 930>; 459 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 460 <&dmac2 0x93>, <&dmac2 0x92>; 461 dma-names = "tx", "rx", "tx", "rx"; 462 i2c-scl-internal-delay-ns = <6>; 463 #address-cells = <1>; 464 #size-cells = <0>; 465 status = "disabled"; 466 }; 467 468 i2c2: i2c@e6510000 { 469 compatible = "renesas,i2c-r8a77980", 470 "renesas,rcar-gen3-i2c"; 471 reg = <0 0xe6510000 0 0x40>; 472 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 473 clocks = <&cpg CPG_MOD 929>; 474 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 475 resets = <&cpg 929>; 476 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 477 <&dmac2 0x95>, <&dmac2 0x94>; 478 dma-names = "tx", "rx", "tx", "rx"; 479 i2c-scl-internal-delay-ns = <6>; 480 #address-cells = <1>; 481 #size-cells = <0>; 482 status = "disabled"; 483 }; 484 485 i2c3: i2c@e66d0000 { 486 compatible = "renesas,i2c-r8a77980", 487 "renesas,rcar-gen3-i2c"; 488 reg = <0 0xe66d0000 0 0x40>; 489 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&cpg CPG_MOD 928>; 491 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 492 resets = <&cpg 928>; 493 i2c-scl-internal-delay-ns = <6>; 494 #address-cells = <1>; 495 #size-cells = <0>; 496 status = "disabled"; 497 }; 498 499 i2c4: i2c@e66d8000 { 500 compatible = "renesas,i2c-r8a77980", 501 "renesas,rcar-gen3-i2c"; 502 reg = <0 0xe66d8000 0 0x40>; 503 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cpg CPG_MOD 927>; 505 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 506 resets = <&cpg 927>; 507 i2c-scl-internal-delay-ns = <6>; 508 #address-cells = <1>; 509 #size-cells = <0>; 510 status = "disabled"; 511 }; 512 513 i2c5: i2c@e66e0000 { 514 compatible = "renesas,i2c-r8a77980", 515 "renesas,rcar-gen3-i2c"; 516 reg = <0 0xe66e0000 0 0x40>; 517 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 518 clocks = <&cpg CPG_MOD 919>; 519 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 520 resets = <&cpg 919>; 521 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>, 522 <&dmac2 0x9b>, <&dmac2 0x9a>; 523 dma-names = "tx", "rx", "tx", "rx"; 524 i2c-scl-internal-delay-ns = <6>; 525 #address-cells = <1>; 526 #size-cells = <0>; 527 status = "disabled"; 528 }; 529 530 hscif0: serial@e6540000 { 531 compatible = "renesas,hscif-r8a77980", 532 "renesas,rcar-gen3-hscif", 533 "renesas,hscif"; 534 reg = <0 0xe6540000 0 0x60>; 535 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&cpg CPG_MOD 520>, 537 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 538 <&scif_clk>; 539 clock-names = "fck", "brg_int", "scif_clk"; 540 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 541 <&dmac2 0x31>, <&dmac2 0x30>; 542 dma-names = "tx", "rx", "tx", "rx"; 543 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 544 resets = <&cpg 520>; 545 status = "disabled"; 546 }; 547 548 hscif1: serial@e6550000 { 549 compatible = "renesas,hscif-r8a77980", 550 "renesas,rcar-gen3-hscif", 551 "renesas,hscif"; 552 reg = <0 0xe6550000 0 0x60>; 553 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 554 clocks = <&cpg CPG_MOD 519>, 555 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 556 <&scif_clk>; 557 clock-names = "fck", "brg_int", "scif_clk"; 558 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 559 <&dmac2 0x33>, <&dmac2 0x32>; 560 dma-names = "tx", "rx", "tx", "rx"; 561 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 562 resets = <&cpg 519>; 563 status = "disabled"; 564 }; 565 566 hscif2: serial@e6560000 { 567 compatible = "renesas,hscif-r8a77980", 568 "renesas,rcar-gen3-hscif", 569 "renesas,hscif"; 570 reg = <0 0xe6560000 0 0x60>; 571 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 572 clocks = <&cpg CPG_MOD 518>, 573 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 574 <&scif_clk>; 575 clock-names = "fck", "brg_int", "scif_clk"; 576 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 577 <&dmac2 0x35>, <&dmac2 0x34>; 578 dma-names = "tx", "rx", "tx", "rx"; 579 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 580 resets = <&cpg 518>; 581 status = "disabled"; 582 }; 583 584 hscif3: serial@e66a0000 { 585 compatible = "renesas,hscif-r8a77980", 586 "renesas,rcar-gen3-hscif", 587 "renesas,hscif"; 588 reg = <0 0xe66a0000 0 0x60>; 589 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 590 clocks = <&cpg CPG_MOD 517>, 591 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 592 <&scif_clk>; 593 clock-names = "fck", "brg_int", "scif_clk"; 594 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 595 <&dmac2 0x37>, <&dmac2 0x36>; 596 dma-names = "tx", "rx", "tx", "rx"; 597 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 598 resets = <&cpg 517>; 599 status = "disabled"; 600 }; 601 602 pcie_phy: pcie-phy@e65d0000 { 603 compatible = "renesas,r8a77980-pcie-phy"; 604 reg = <0 0xe65d0000 0 0x8000>; 605 #phy-cells = <0>; 606 clocks = <&cpg CPG_MOD 319>; 607 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 608 resets = <&cpg 319>; 609 status = "disabled"; 610 }; 611 612 canfd: can@e66c0000 { 613 compatible = "renesas,r8a77980-canfd", 614 "renesas,rcar-gen3-canfd"; 615 reg = <0 0xe66c0000 0 0x8000>; 616 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 618 interrupt-names = "ch_int", "g_int"; 619 clocks = <&cpg CPG_MOD 914>, 620 <&cpg CPG_CORE R8A77980_CLK_CANFD>, 621 <&can_clk>; 622 clock-names = "fck", "canfd", "can_clk"; 623 assigned-clocks = <&cpg CPG_CORE R8A77980_CLK_CANFD>; 624 assigned-clock-rates = <80000000>; 625 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 626 resets = <&cpg 914>; 627 status = "disabled"; 628 629 channel0 { 630 status = "disabled"; 631 }; 632 633 channel1 { 634 status = "disabled"; 635 }; 636 }; 637 638 avb: ethernet@e6800000 { 639 compatible = "renesas,etheravb-r8a77980", 640 "renesas,etheravb-rcar-gen3"; 641 reg = <0 0xe6800000 0 0x800>; 642 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "ch0", "ch1", "ch2", "ch3", 668 "ch4", "ch5", "ch6", "ch7", 669 "ch8", "ch9", "ch10", "ch11", 670 "ch12", "ch13", "ch14", "ch15", 671 "ch16", "ch17", "ch18", "ch19", 672 "ch20", "ch21", "ch22", "ch23", 673 "ch24"; 674 clocks = <&cpg CPG_MOD 812>; 675 clock-names = "fck"; 676 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 677 resets = <&cpg 812>; 678 phy-mode = "rgmii"; 679 rx-internal-delay-ps = <0>; 680 tx-internal-delay-ps = <2000>; 681 iommus = <&ipmmu_ds1 33>; 682 #address-cells = <1>; 683 #size-cells = <0>; 684 status = "disabled"; 685 }; 686 687 pwm0: pwm@e6e30000 { 688 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 689 reg = <0 0xe6e30000 0 0x10>; 690 #pwm-cells = <2>; 691 clocks = <&cpg CPG_MOD 523>; 692 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 693 resets = <&cpg 523>; 694 status = "disabled"; 695 }; 696 697 pwm1: pwm@e6e31000 { 698 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 699 reg = <0 0xe6e31000 0 0x10>; 700 #pwm-cells = <2>; 701 clocks = <&cpg CPG_MOD 523>; 702 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 703 resets = <&cpg 523>; 704 status = "disabled"; 705 }; 706 707 pwm2: pwm@e6e32000 { 708 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 709 reg = <0 0xe6e32000 0 0x10>; 710 #pwm-cells = <2>; 711 clocks = <&cpg CPG_MOD 523>; 712 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 713 resets = <&cpg 523>; 714 status = "disabled"; 715 }; 716 717 pwm3: pwm@e6e33000 { 718 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 719 reg = <0 0xe6e33000 0 0x10>; 720 #pwm-cells = <2>; 721 clocks = <&cpg CPG_MOD 523>; 722 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 723 resets = <&cpg 523>; 724 status = "disabled"; 725 }; 726 727 pwm4: pwm@e6e34000 { 728 compatible = "renesas,pwm-r8a77980", "renesas,pwm-rcar"; 729 reg = <0 0xe6e34000 0 0x10>; 730 #pwm-cells = <2>; 731 clocks = <&cpg CPG_MOD 523>; 732 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 733 resets = <&cpg 523>; 734 status = "disabled"; 735 }; 736 737 scif0: serial@e6e60000 { 738 compatible = "renesas,scif-r8a77980", 739 "renesas,rcar-gen3-scif", 740 "renesas,scif"; 741 reg = <0 0xe6e60000 0 0x40>; 742 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 743 clocks = <&cpg CPG_MOD 207>, 744 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 745 <&scif_clk>; 746 clock-names = "fck", "brg_int", "scif_clk"; 747 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 748 <&dmac2 0x51>, <&dmac2 0x50>; 749 dma-names = "tx", "rx", "tx", "rx"; 750 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 751 resets = <&cpg 207>; 752 status = "disabled"; 753 }; 754 755 scif1: serial@e6e68000 { 756 compatible = "renesas,scif-r8a77980", 757 "renesas,rcar-gen3-scif", 758 "renesas,scif"; 759 reg = <0 0xe6e68000 0 0x40>; 760 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&cpg CPG_MOD 206>, 762 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 763 <&scif_clk>; 764 clock-names = "fck", "brg_int", "scif_clk"; 765 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 766 <&dmac2 0x53>, <&dmac2 0x52>; 767 dma-names = "tx", "rx", "tx", "rx"; 768 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 769 resets = <&cpg 206>; 770 status = "disabled"; 771 }; 772 773 scif3: serial@e6c50000 { 774 compatible = "renesas,scif-r8a77980", 775 "renesas,rcar-gen3-scif", 776 "renesas,scif"; 777 reg = <0 0xe6c50000 0 0x40>; 778 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&cpg CPG_MOD 204>, 780 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 781 <&scif_clk>; 782 clock-names = "fck", "brg_int", "scif_clk"; 783 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 784 <&dmac2 0x57>, <&dmac2 0x56>; 785 dma-names = "tx", "rx", "tx", "rx"; 786 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 787 resets = <&cpg 204>; 788 status = "disabled"; 789 }; 790 791 scif4: serial@e6c40000 { 792 compatible = "renesas,scif-r8a77980", 793 "renesas,rcar-gen3-scif", 794 "renesas,scif"; 795 reg = <0 0xe6c40000 0 0x40>; 796 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cpg CPG_MOD 203>, 798 <&cpg CPG_CORE R8A77980_CLK_S3D1>, 799 <&scif_clk>; 800 clock-names = "fck", "brg_int", "scif_clk"; 801 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 802 <&dmac2 0x59>, <&dmac2 0x58>; 803 dma-names = "tx", "rx", "tx", "rx"; 804 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 805 resets = <&cpg 203>; 806 status = "disabled"; 807 }; 808 809 tpu: pwm@e6e80000 { 810 compatible = "renesas,tpu-r8a77980", "renesas,tpu"; 811 reg = <0 0xe6e80000 0 0x148>; 812 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&cpg CPG_MOD 304>; 814 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 815 resets = <&cpg 304>; 816 #pwm-cells = <3>; 817 status = "disabled"; 818 }; 819 820 msiof0: spi@e6e90000 { 821 compatible = "renesas,msiof-r8a77980", 822 "renesas,rcar-gen3-msiof"; 823 reg = <0 0xe6e90000 0 0x64>; 824 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 825 clocks = <&cpg CPG_MOD 211>; 826 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 827 resets = <&cpg 211>; 828 #address-cells = <1>; 829 #size-cells = <0>; 830 status = "disabled"; 831 }; 832 833 msiof1: spi@e6ea0000 { 834 compatible = "renesas,msiof-r8a77980", 835 "renesas,rcar-gen3-msiof"; 836 reg = <0 0xe6ea0000 0 0x0064>; 837 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&cpg CPG_MOD 210>; 839 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 840 resets = <&cpg 210>; 841 #address-cells = <1>; 842 #size-cells = <0>; 843 status = "disabled"; 844 }; 845 846 msiof2: spi@e6c00000 { 847 compatible = "renesas,msiof-r8a77980", 848 "renesas,rcar-gen3-msiof"; 849 reg = <0 0xe6c00000 0 0x0064>; 850 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 851 clocks = <&cpg CPG_MOD 209>; 852 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 853 resets = <&cpg 209>; 854 #address-cells = <1>; 855 #size-cells = <0>; 856 status = "disabled"; 857 }; 858 859 msiof3: spi@e6c10000 { 860 compatible = "renesas,msiof-r8a77980", 861 "renesas,rcar-gen3-msiof"; 862 reg = <0 0xe6c10000 0 0x0064>; 863 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&cpg CPG_MOD 208>; 865 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 866 resets = <&cpg 208>; 867 #address-cells = <1>; 868 #size-cells = <0>; 869 status = "disabled"; 870 }; 871 872 vin0: video@e6ef0000 { 873 compatible = "renesas,vin-r8a77980"; 874 reg = <0 0xe6ef0000 0 0x1000>; 875 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 876 clocks = <&cpg CPG_MOD 811>; 877 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 878 resets = <&cpg 811>; 879 renesas,id = <0>; 880 status = "disabled"; 881 882 ports { 883 #address-cells = <1>; 884 #size-cells = <0>; 885 886 port@1 { 887 #address-cells = <1>; 888 #size-cells = <0>; 889 890 reg = <1>; 891 892 vin0csi40: endpoint@2 { 893 reg = <2>; 894 remote-endpoint = <&csi40vin0>; 895 }; 896 }; 897 }; 898 }; 899 900 vin1: video@e6ef1000 { 901 compatible = "renesas,vin-r8a77980"; 902 reg = <0 0xe6ef1000 0 0x1000>; 903 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 904 clocks = <&cpg CPG_MOD 810>; 905 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 906 status = "disabled"; 907 renesas,id = <1>; 908 resets = <&cpg 810>; 909 910 ports { 911 #address-cells = <1>; 912 #size-cells = <0>; 913 914 port@1 { 915 #address-cells = <1>; 916 #size-cells = <0>; 917 918 reg = <1>; 919 920 vin1csi40: endpoint@2 { 921 reg = <2>; 922 remote-endpoint = <&csi40vin1>; 923 }; 924 }; 925 }; 926 }; 927 928 vin2: video@e6ef2000 { 929 compatible = "renesas,vin-r8a77980"; 930 reg = <0 0xe6ef2000 0 0x1000>; 931 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&cpg CPG_MOD 809>; 933 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 934 resets = <&cpg 809>; 935 renesas,id = <2>; 936 status = "disabled"; 937 938 ports { 939 #address-cells = <1>; 940 #size-cells = <0>; 941 942 port@1 { 943 #address-cells = <1>; 944 #size-cells = <0>; 945 946 reg = <1>; 947 948 vin2csi40: endpoint@2 { 949 reg = <2>; 950 remote-endpoint = <&csi40vin2>; 951 }; 952 }; 953 }; 954 }; 955 956 vin3: video@e6ef3000 { 957 compatible = "renesas,vin-r8a77980"; 958 reg = <0 0xe6ef3000 0 0x1000>; 959 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 960 clocks = <&cpg CPG_MOD 808>; 961 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 962 resets = <&cpg 808>; 963 renesas,id = <3>; 964 status = "disabled"; 965 966 ports { 967 #address-cells = <1>; 968 #size-cells = <0>; 969 970 port@1 { 971 #address-cells = <1>; 972 #size-cells = <0>; 973 974 reg = <1>; 975 976 vin3csi40: endpoint@2 { 977 reg = <2>; 978 remote-endpoint = <&csi40vin3>; 979 }; 980 }; 981 }; 982 }; 983 984 vin4: video@e6ef4000 { 985 compatible = "renesas,vin-r8a77980"; 986 reg = <0 0xe6ef4000 0 0x1000>; 987 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 988 clocks = <&cpg CPG_MOD 807>; 989 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 990 resets = <&cpg 807>; 991 renesas,id = <4>; 992 status = "disabled"; 993 994 ports { 995 #address-cells = <1>; 996 #size-cells = <0>; 997 998 port@1 { 999 #address-cells = <1>; 1000 #size-cells = <0>; 1001 1002 reg = <1>; 1003 1004 vin4csi41: endpoint@3 { 1005 reg = <3>; 1006 remote-endpoint = <&csi41vin4>; 1007 }; 1008 }; 1009 }; 1010 }; 1011 1012 vin5: video@e6ef5000 { 1013 compatible = "renesas,vin-r8a77980"; 1014 reg = <0 0xe6ef5000 0 0x1000>; 1015 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&cpg CPG_MOD 806>; 1017 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1018 resets = <&cpg 806>; 1019 renesas,id = <5>; 1020 status = "disabled"; 1021 1022 ports { 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 1026 port@1 { 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 1030 reg = <1>; 1031 1032 vin5csi41: endpoint@3 { 1033 reg = <3>; 1034 remote-endpoint = <&csi41vin5>; 1035 }; 1036 }; 1037 }; 1038 }; 1039 1040 vin6: video@e6ef6000 { 1041 compatible = "renesas,vin-r8a77980"; 1042 reg = <0 0xe6ef6000 0 0x1000>; 1043 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 1044 clocks = <&cpg CPG_MOD 805>; 1045 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1046 resets = <&cpg 805>; 1047 renesas,id = <6>; 1048 status = "disabled"; 1049 1050 ports { 1051 #address-cells = <1>; 1052 #size-cells = <0>; 1053 1054 port@1 { 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 1058 reg = <1>; 1059 1060 vin6csi41: endpoint@3 { 1061 reg = <3>; 1062 remote-endpoint = <&csi41vin6>; 1063 }; 1064 }; 1065 }; 1066 }; 1067 1068 vin7: video@e6ef7000 { 1069 compatible = "renesas,vin-r8a77980"; 1070 reg = <0 0xe6ef7000 0 0x1000>; 1071 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1072 clocks = <&cpg CPG_MOD 804>; 1073 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1074 resets = <&cpg 804>; 1075 renesas,id = <7>; 1076 status = "disabled"; 1077 1078 ports { 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 1082 port@1 { 1083 #address-cells = <1>; 1084 #size-cells = <0>; 1085 1086 reg = <1>; 1087 1088 vin7csi41: endpoint@3 { 1089 reg = <3>; 1090 remote-endpoint = <&csi41vin7>; 1091 }; 1092 }; 1093 }; 1094 }; 1095 1096 vin8: video@e6ef8000 { 1097 compatible = "renesas,vin-r8a77980"; 1098 reg = <0 0xe6ef8000 0 0x1000>; 1099 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&cpg CPG_MOD 628>; 1101 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1102 resets = <&cpg 628>; 1103 renesas,id = <8>; 1104 status = "disabled"; 1105 }; 1106 1107 vin9: video@e6ef9000 { 1108 compatible = "renesas,vin-r8a77980"; 1109 reg = <0 0xe6ef9000 0 0x1000>; 1110 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>; 1111 clocks = <&cpg CPG_MOD 627>; 1112 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1113 resets = <&cpg 627>; 1114 renesas,id = <9>; 1115 status = "disabled"; 1116 }; 1117 1118 vin10: video@e6efa000 { 1119 compatible = "renesas,vin-r8a77980"; 1120 reg = <0 0xe6efa000 0 0x1000>; 1121 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&cpg CPG_MOD 625>; 1123 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1124 resets = <&cpg 625>; 1125 renesas,id = <10>; 1126 status = "disabled"; 1127 }; 1128 1129 vin11: video@e6efb000 { 1130 compatible = "renesas,vin-r8a77980"; 1131 reg = <0 0xe6efb000 0 0x1000>; 1132 interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&cpg CPG_MOD 618>; 1134 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1135 resets = <&cpg 618>; 1136 renesas,id = <11>; 1137 status = "disabled"; 1138 }; 1139 1140 vin12: video@e6efc000 { 1141 compatible = "renesas,vin-r8a77980"; 1142 reg = <0 0xe6efc000 0 0x1000>; 1143 interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1144 clocks = <&cpg CPG_MOD 612>; 1145 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1146 resets = <&cpg 612>; 1147 renesas,id = <12>; 1148 status = "disabled"; 1149 }; 1150 1151 vin13: video@e6efd000 { 1152 compatible = "renesas,vin-r8a77980"; 1153 reg = <0 0xe6efd000 0 0x1000>; 1154 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&cpg CPG_MOD 608>; 1156 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1157 resets = <&cpg 608>; 1158 renesas,id = <13>; 1159 status = "disabled"; 1160 }; 1161 1162 vin14: video@e6efe000 { 1163 compatible = "renesas,vin-r8a77980"; 1164 reg = <0 0xe6efe000 0 0x1000>; 1165 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1166 clocks = <&cpg CPG_MOD 605>; 1167 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1168 resets = <&cpg 605>; 1169 renesas,id = <14>; 1170 status = "disabled"; 1171 }; 1172 1173 vin15: video@e6eff000 { 1174 compatible = "renesas,vin-r8a77980"; 1175 reg = <0 0xe6eff000 0 0x1000>; 1176 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1177 clocks = <&cpg CPG_MOD 604>; 1178 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1179 resets = <&cpg 604>; 1180 renesas,id = <15>; 1181 status = "disabled"; 1182 }; 1183 1184 dmac1: dma-controller@e7300000 { 1185 compatible = "renesas,dmac-r8a77980", 1186 "renesas,rcar-dmac"; 1187 reg = <0 0xe7300000 0 0x10000>; 1188 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 1189 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 1190 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1191 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 1195 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 1196 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 1197 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 1198 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 1199 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, 1200 <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 1201 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 1202 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 1203 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 1204 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1205 interrupt-names = "error", 1206 "ch0", "ch1", "ch2", "ch3", 1207 "ch4", "ch5", "ch6", "ch7", 1208 "ch8", "ch9", "ch10", "ch11", 1209 "ch12", "ch13", "ch14", "ch15"; 1210 clocks = <&cpg CPG_MOD 218>; 1211 clock-names = "fck"; 1212 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1213 resets = <&cpg 218>; 1214 #dma-cells = <1>; 1215 dma-channels = <16>; 1216 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 1217 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 1218 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 1219 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>, 1220 <&ipmmu_ds1 8>, <&ipmmu_ds1 9>, 1221 <&ipmmu_ds1 10>, <&ipmmu_ds1 11>, 1222 <&ipmmu_ds1 12>, <&ipmmu_ds1 13>, 1223 <&ipmmu_ds1 14>, <&ipmmu_ds1 15>; 1224 }; 1225 1226 dmac2: dma-controller@e7310000 { 1227 compatible = "renesas,dmac-r8a77980", 1228 "renesas,rcar-dmac"; 1229 reg = <0 0xe7310000 0 0x10000>; 1230 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1231 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1232 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1233 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1234 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1235 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1236 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 1241 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 1242 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 1243 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 1244 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 1245 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 1246 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1247 interrupt-names = "error", 1248 "ch0", "ch1", "ch2", "ch3", 1249 "ch4", "ch5", "ch6", "ch7", 1250 "ch8", "ch9", "ch10", "ch11", 1251 "ch12", "ch13", "ch14", "ch15"; 1252 clocks = <&cpg CPG_MOD 217>; 1253 clock-names = "fck"; 1254 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1255 resets = <&cpg 217>; 1256 #dma-cells = <1>; 1257 dma-channels = <16>; 1258 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1259 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1260 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1261 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>, 1262 <&ipmmu_ds1 24>, <&ipmmu_ds1 25>, 1263 <&ipmmu_ds1 26>, <&ipmmu_ds1 27>, 1264 <&ipmmu_ds1 28>, <&ipmmu_ds1 29>, 1265 <&ipmmu_ds1 30>, <&ipmmu_ds1 31>; 1266 }; 1267 1268 gether: ethernet@e7400000 { 1269 compatible = "renesas,gether-r8a77980"; 1270 reg = <0 0xe7400000 0 0x1000>; 1271 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1272 clocks = <&cpg CPG_MOD 813>; 1273 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1274 resets = <&cpg 813>; 1275 iommus = <&ipmmu_ds1 34>; 1276 #address-cells = <1>; 1277 #size-cells = <0>; 1278 status = "disabled"; 1279 }; 1280 1281 ipmmu_ds1: iommu@e7740000 { 1282 compatible = "renesas,ipmmu-r8a77980"; 1283 reg = <0 0xe7740000 0 0x1000>; 1284 renesas,ipmmu-main = <&ipmmu_mm 0>; 1285 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1286 #iommu-cells = <1>; 1287 }; 1288 1289 ipmmu_ir: iommu@ff8b0000 { 1290 compatible = "renesas,ipmmu-r8a77980"; 1291 reg = <0 0xff8b0000 0 0x1000>; 1292 renesas,ipmmu-main = <&ipmmu_mm 3>; 1293 power-domains = <&sysc R8A77980_PD_A3IR>; 1294 #iommu-cells = <1>; 1295 }; 1296 1297 ipmmu_mm: iommu@e67b0000 { 1298 compatible = "renesas,ipmmu-r8a77980"; 1299 reg = <0 0xe67b0000 0 0x1000>; 1300 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1301 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1302 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1303 #iommu-cells = <1>; 1304 }; 1305 1306 ipmmu_rt: iommu@ffc80000 { 1307 compatible = "renesas,ipmmu-r8a77980"; 1308 reg = <0 0xffc80000 0 0x1000>; 1309 renesas,ipmmu-main = <&ipmmu_mm 10>; 1310 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1311 #iommu-cells = <1>; 1312 }; 1313 1314 ipmmu_vc0: iommu@fe990000 { 1315 compatible = "renesas,ipmmu-r8a77980"; 1316 reg = <0 0xfe990000 0 0x1000>; 1317 renesas,ipmmu-main = <&ipmmu_mm 12>; 1318 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1319 #iommu-cells = <1>; 1320 }; 1321 1322 ipmmu_vi0: iommu@febd0000 { 1323 compatible = "renesas,ipmmu-r8a77980"; 1324 reg = <0 0xfebd0000 0 0x1000>; 1325 renesas,ipmmu-main = <&ipmmu_mm 14>; 1326 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1327 #iommu-cells = <1>; 1328 }; 1329 1330 ipmmu_vip0: iommu@e7b00000 { 1331 compatible = "renesas,ipmmu-r8a77980"; 1332 reg = <0 0xe7b00000 0 0x1000>; 1333 renesas,ipmmu-main = <&ipmmu_mm 4>; 1334 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1335 #iommu-cells = <1>; 1336 }; 1337 1338 ipmmu_vip1: iommu@e7960000 { 1339 compatible = "renesas,ipmmu-r8a77980"; 1340 reg = <0 0xe7960000 0 0x1000>; 1341 renesas,ipmmu-main = <&ipmmu_mm 11>; 1342 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1343 #iommu-cells = <1>; 1344 }; 1345 1346 mmc0: mmc@ee140000 { 1347 compatible = "renesas,sdhi-r8a77980", 1348 "renesas,rcar-gen3-sdhi"; 1349 reg = <0 0xee140000 0 0x2000>; 1350 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1351 clocks = <&cpg CPG_MOD 314>, <&cpg CPG_CORE R8A77980_CLK_SD0H>; 1352 clock-names = "core", "clkh"; 1353 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1354 resets = <&cpg 314>; 1355 max-frequency = <200000000>; 1356 iommus = <&ipmmu_ds1 32>; 1357 status = "disabled"; 1358 }; 1359 1360 rpc: spi@ee200000 { 1361 compatible = "renesas,r8a77980-rpc-if", 1362 "renesas,rcar-gen3-rpc-if"; 1363 reg = <0 0xee200000 0 0x200>, 1364 <0 0x08000000 0 0x4000000>, 1365 <0 0xee208000 0 0x100>; 1366 reg-names = "regs", "dirmap", "wbuf"; 1367 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1368 clocks = <&cpg CPG_MOD 917>; 1369 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1370 resets = <&cpg 917>; 1371 #address-cells = <1>; 1372 #size-cells = <0>; 1373 status = "disabled"; 1374 }; 1375 1376 gic: interrupt-controller@f1010000 { 1377 compatible = "arm,gic-400"; 1378 #interrupt-cells = <3>; 1379 #address-cells = <0>; 1380 interrupt-controller; 1381 reg = <0x0 0xf1010000 0 0x1000>, 1382 <0x0 0xf1020000 0 0x20000>, 1383 <0x0 0xf1040000 0 0x20000>, 1384 <0x0 0xf1060000 0 0x20000>; 1385 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | 1386 IRQ_TYPE_LEVEL_HIGH)>; 1387 clocks = <&cpg CPG_MOD 408>; 1388 clock-names = "clk"; 1389 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1390 resets = <&cpg 408>; 1391 }; 1392 1393 pciec: pcie@fe000000 { 1394 compatible = "renesas,pcie-r8a77980", 1395 "renesas,pcie-rcar-gen3"; 1396 reg = <0 0xfe000000 0 0x80000>; 1397 #address-cells = <3>; 1398 #size-cells = <2>; 1399 bus-range = <0x00 0xff>; 1400 device_type = "pci"; 1401 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x0100000>, 1402 <0x02000000 0 0xfe200000 0 0xfe200000 0 0x0200000>, 1403 <0x02000000 0 0x30000000 0 0x30000000 0 0x8000000>, 1404 <0x42000000 0 0x38000000 0 0x38000000 0 0x8000000>; 1405 /* Map all possible DDR/IOMMU as inbound ranges */ 1406 dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; 1407 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1408 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1409 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1410 #interrupt-cells = <1>; 1411 interrupt-map-mask = <0 0 0 0>; 1412 interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1413 clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; 1414 clock-names = "pcie", "pcie_bus"; 1415 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1416 resets = <&cpg 319>; 1417 phys = <&pcie_phy>; 1418 phy-names = "pcie"; 1419 iommu-map = <0 &ipmmu_vi0 5 1>; 1420 iommu-map-mask = <0>; 1421 status = "disabled"; 1422 }; 1423 1424 vspd0: vsp@fea20000 { 1425 compatible = "renesas,vsp2"; 1426 reg = <0 0xfea20000 0 0x5000>; 1427 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1428 clocks = <&cpg CPG_MOD 623>; 1429 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1430 resets = <&cpg 623>; 1431 renesas,fcp = <&fcpvd0>; 1432 }; 1433 1434 fcpvd0: fcp@fea27000 { 1435 compatible = "renesas,fcpv"; 1436 reg = <0 0xfea27000 0 0x200>; 1437 clocks = <&cpg CPG_MOD 603>; 1438 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1439 resets = <&cpg 603>; 1440 iommus = <&ipmmu_vi0 8>; 1441 }; 1442 1443 csi40: csi2@feaa0000 { 1444 compatible = "renesas,r8a77980-csi2"; 1445 reg = <0 0xfeaa0000 0 0x10000>; 1446 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1447 clocks = <&cpg CPG_MOD 716>; 1448 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1449 resets = <&cpg 716>; 1450 status = "disabled"; 1451 1452 ports { 1453 #address-cells = <1>; 1454 #size-cells = <0>; 1455 1456 port@0 { 1457 reg = <0>; 1458 }; 1459 1460 port@1 { 1461 #address-cells = <1>; 1462 #size-cells = <0>; 1463 1464 reg = <1>; 1465 1466 csi40vin0: endpoint@0 { 1467 reg = <0>; 1468 remote-endpoint = <&vin0csi40>; 1469 }; 1470 csi40vin1: endpoint@1 { 1471 reg = <1>; 1472 remote-endpoint = <&vin1csi40>; 1473 }; 1474 csi40vin2: endpoint@2 { 1475 reg = <2>; 1476 remote-endpoint = <&vin2csi40>; 1477 }; 1478 csi40vin3: endpoint@3 { 1479 reg = <3>; 1480 remote-endpoint = <&vin3csi40>; 1481 }; 1482 }; 1483 }; 1484 }; 1485 1486 csi41: csi2@feab0000 { 1487 compatible = "renesas,r8a77980-csi2"; 1488 reg = <0 0xfeab0000 0 0x10000>; 1489 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1490 clocks = <&cpg CPG_MOD 715>; 1491 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1492 resets = <&cpg 715>; 1493 status = "disabled"; 1494 1495 ports { 1496 #address-cells = <1>; 1497 #size-cells = <0>; 1498 1499 port@0 { 1500 reg = <0>; 1501 }; 1502 1503 port@1 { 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 1507 reg = <1>; 1508 1509 csi41vin4: endpoint@0 { 1510 reg = <0>; 1511 remote-endpoint = <&vin4csi41>; 1512 }; 1513 csi41vin5: endpoint@1 { 1514 reg = <1>; 1515 remote-endpoint = <&vin5csi41>; 1516 }; 1517 csi41vin6: endpoint@2 { 1518 reg = <2>; 1519 remote-endpoint = <&vin6csi41>; 1520 }; 1521 csi41vin7: endpoint@3 { 1522 reg = <3>; 1523 remote-endpoint = <&vin7csi41>; 1524 }; 1525 }; 1526 }; 1527 }; 1528 1529 du: display@feb00000 { 1530 compatible = "renesas,du-r8a77980"; 1531 reg = <0 0xfeb00000 0 0x80000>; 1532 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1533 clocks = <&cpg CPG_MOD 724>; 1534 clock-names = "du.0"; 1535 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1536 resets = <&cpg 724>; 1537 reset-names = "du.0"; 1538 renesas,vsps = <&vspd0 0>; 1539 1540 status = "disabled"; 1541 1542 ports { 1543 #address-cells = <1>; 1544 #size-cells = <0>; 1545 1546 port@0 { 1547 reg = <0>; 1548 }; 1549 1550 port@1 { 1551 reg = <1>; 1552 du_out_lvds0: endpoint { 1553 remote-endpoint = <&lvds0_in>; 1554 }; 1555 }; 1556 }; 1557 }; 1558 1559 lvds0: lvds-encoder@feb90000 { 1560 compatible = "renesas,r8a77980-lvds"; 1561 reg = <0 0xfeb90000 0 0x14>; 1562 clocks = <&cpg CPG_MOD 727>; 1563 power-domains = <&sysc R8A77980_PD_ALWAYS_ON>; 1564 resets = <&cpg 727>; 1565 status = "disabled"; 1566 1567 ports { 1568 #address-cells = <1>; 1569 #size-cells = <0>; 1570 1571 port@0 { 1572 reg = <0>; 1573 lvds0_in: endpoint { 1574 remote-endpoint = 1575 <&du_out_lvds0>; 1576 }; 1577 }; 1578 1579 port@1 { 1580 reg = <1>; 1581 }; 1582 }; 1583 }; 1584 1585 prr: chipid@fff00044 { 1586 compatible = "renesas,prr"; 1587 reg = <0 0xfff00044 0 4>; 1588 bootph-all; 1589 }; 1590 }; 1591 1592 thermal-zones { 1593 sensor1_thermal: sensor1-thermal { 1594 polling-delay-passive = <250>; 1595 polling-delay = <1000>; 1596 thermal-sensors = <&tsc 0>; 1597 1598 trips { 1599 sensor1-passive { 1600 temperature = <95000>; 1601 hysteresis = <1000>; 1602 type = "passive"; 1603 }; 1604 sensor1-critical { 1605 temperature = <120000>; 1606 hysteresis = <1000>; 1607 type = "critical"; 1608 }; 1609 }; 1610 }; 1611 1612 sensor2_thermal: sensor2-thermal { 1613 polling-delay-passive = <250>; 1614 polling-delay = <1000>; 1615 thermal-sensors = <&tsc 1>; 1616 1617 trips { 1618 sensor2-passive { 1619 temperature = <95000>; 1620 hysteresis = <1000>; 1621 type = "passive"; 1622 }; 1623 sensor2-critical { 1624 temperature = <120000>; 1625 hysteresis = <1000>; 1626 type = "critical"; 1627 }; 1628 }; 1629 }; 1630 }; 1631 1632 timer { 1633 compatible = "arm,armv8-timer"; 1634 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1635 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1636 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1637 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1638 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 1639 }; 1640};
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