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r8a77970.dtsi
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linux-6.19.14/arch/arm64/boot/dts/renesas/r8a77970.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3M (R8A77970) SoC 4 * 5 * Copyright (C) 2016-2017 Renesas Electronics Corp. 6 * Copyright (C) 2017 Cogent Embedded, Inc. 7 */ 8 9#include <dt-bindings/clock/r8a77970-cpg-mssr.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/power/r8a77970-sysc.h> 13 14/ { 15 compatible = "renesas,r8a77970"; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&gic>; 19 20 /* External CAN clock - to be overridden by boards that provide it */ 21 can_clk: can { 22 compatible = "fixed-clock"; 23 #clock-cells = <0>; 24 clock-frequency = <0>; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 a53_0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a53"; 34 reg = <0>; 35 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 36 power-domains = <&sysc R8A77970_PD_CA53_CPU0>; 37 next-level-cache = <&L2_CA53>; 38 enable-method = "psci"; 39 }; 40 41 a53_1: cpu@1 { 42 device_type = "cpu"; 43 compatible = "arm,cortex-a53"; 44 reg = <1>; 45 clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>; 46 power-domains = <&sysc R8A77970_PD_CA53_CPU1>; 47 next-level-cache = <&L2_CA53>; 48 enable-method = "psci"; 49 }; 50 51 L2_CA53: cache-controller { 52 compatible = "cache"; 53 power-domains = <&sysc R8A77970_PD_CA53_SCU>; 54 cache-unified; 55 cache-level = <2>; 56 }; 57 }; 58 59 extal_clk: extal { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 /* This value must be overridden by the board */ 63 clock-frequency = <0>; 64 bootph-all; 65 }; 66 67 extalr_clk: extalr { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 /* This value must be overridden by the board */ 71 clock-frequency = <0>; 72 bootph-all; 73 }; 74 75 pmu_a53 { 76 compatible = "arm,cortex-a53-pmu"; 77 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 78 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 79 interrupt-affinity = <&a53_0>, <&a53_1>; 80 }; 81 82 psci { 83 compatible = "arm,psci-1.0", "arm,psci-0.2"; 84 method = "smc"; 85 }; 86 87 /* External SCIF clock - to be overridden by boards that provide it */ 88 scif_clk: scif { 89 compatible = "fixed-clock"; 90 #clock-cells = <0>; 91 clock-frequency = <0>; 92 }; 93 94 soc { 95 compatible = "simple-bus"; 96 bootph-all; 97 98 #address-cells = <2>; 99 #size-cells = <2>; 100 ranges; 101 102 rwdt: watchdog@e6020000 { 103 compatible = "renesas,r8a77970-wdt", 104 "renesas,rcar-gen3-wdt"; 105 reg = <0 0xe6020000 0 0x0c>; 106 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&cpg CPG_MOD 402>; 108 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 109 resets = <&cpg 402>; 110 status = "disabled"; 111 }; 112 113 swdt: watchdog@e6030000 { 114 compatible = "renesas,r8a77970-wdt", "renesas,rcar-gen3-wdt"; 115 reg = <0 0xe6030000 0 0x0c>; 116 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&cpg CPG_CORE R8A77970_CLK_OSC>; 118 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 119 resets = <&cpg 401>; 120 status = "disabled"; 121 }; 122 123 gpio0: gpio@e6050000 { 124 compatible = "renesas,gpio-r8a77970", 125 "renesas,rcar-gen3-gpio"; 126 reg = <0 0xe6050000 0 0x50>; 127 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 128 #gpio-cells = <2>; 129 gpio-controller; 130 gpio-ranges = <&pfc 0 0 22>; 131 #interrupt-cells = <2>; 132 interrupt-controller; 133 clocks = <&cpg CPG_MOD 912>; 134 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 135 resets = <&cpg 912>; 136 }; 137 138 gpio1: gpio@e6051000 { 139 compatible = "renesas,gpio-r8a77970", 140 "renesas,rcar-gen3-gpio"; 141 reg = <0 0xe6051000 0 0x50>; 142 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 143 #gpio-cells = <2>; 144 gpio-controller; 145 gpio-ranges = <&pfc 0 32 28>; 146 #interrupt-cells = <2>; 147 interrupt-controller; 148 clocks = <&cpg CPG_MOD 911>; 149 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 150 resets = <&cpg 911>; 151 }; 152 153 gpio2: gpio@e6052000 { 154 compatible = "renesas,gpio-r8a77970", 155 "renesas,rcar-gen3-gpio"; 156 reg = <0 0xe6052000 0 0x50>; 157 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 158 #gpio-cells = <2>; 159 gpio-controller; 160 gpio-ranges = <&pfc 0 64 17>; 161 #interrupt-cells = <2>; 162 interrupt-controller; 163 clocks = <&cpg CPG_MOD 910>; 164 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 165 resets = <&cpg 910>; 166 }; 167 168 gpio3: gpio@e6053000 { 169 compatible = "renesas,gpio-r8a77970", 170 "renesas,rcar-gen3-gpio"; 171 reg = <0 0xe6053000 0 0x50>; 172 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 173 #gpio-cells = <2>; 174 gpio-controller; 175 gpio-ranges = <&pfc 0 96 17>; 176 #interrupt-cells = <2>; 177 interrupt-controller; 178 clocks = <&cpg CPG_MOD 909>; 179 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 180 resets = <&cpg 909>; 181 }; 182 183 gpio4: gpio@e6054000 { 184 compatible = "renesas,gpio-r8a77970", 185 "renesas,rcar-gen3-gpio"; 186 reg = <0 0xe6054000 0 0x50>; 187 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 188 #gpio-cells = <2>; 189 gpio-controller; 190 gpio-ranges = <&pfc 0 128 6>; 191 #interrupt-cells = <2>; 192 interrupt-controller; 193 clocks = <&cpg CPG_MOD 908>; 194 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 195 resets = <&cpg 908>; 196 }; 197 198 gpio5: gpio@e6055000 { 199 compatible = "renesas,gpio-r8a77970", 200 "renesas,rcar-gen3-gpio"; 201 reg = <0 0xe6055000 0 0x50>; 202 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 203 #gpio-cells = <2>; 204 gpio-controller; 205 gpio-ranges = <&pfc 0 160 15>; 206 #interrupt-cells = <2>; 207 interrupt-controller; 208 clocks = <&cpg CPG_MOD 907>; 209 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 210 resets = <&cpg 907>; 211 }; 212 213 pfc: pinctrl@e6060000 { 214 compatible = "renesas,pfc-r8a77970"; 215 reg = <0 0xe6060000 0 0x504>; 216 bootph-all; 217 }; 218 219 cmt0: timer@e60f0000 { 220 compatible = "renesas,r8a77970-cmt0", 221 "renesas,rcar-gen3-cmt0"; 222 reg = <0 0xe60f0000 0 0x1004>; 223 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 225 clocks = <&cpg CPG_MOD 303>; 226 clock-names = "fck"; 227 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 228 resets = <&cpg 303>; 229 status = "disabled"; 230 }; 231 232 cmt1: timer@e6130000 { 233 compatible = "renesas,r8a77970-cmt1", 234 "renesas,rcar-gen3-cmt1"; 235 reg = <0 0xe6130000 0 0x1004>; 236 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 237 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 239 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 240 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 241 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 242 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 243 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&cpg CPG_MOD 302>; 245 clock-names = "fck"; 246 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 247 resets = <&cpg 302>; 248 status = "disabled"; 249 }; 250 251 cmt2: timer@e6140000 { 252 compatible = "renesas,r8a77970-cmt1", 253 "renesas,rcar-gen3-cmt1"; 254 reg = <0 0xe6140000 0 0x1004>; 255 interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 256 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&cpg CPG_MOD 301>; 264 clock-names = "fck"; 265 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 266 resets = <&cpg 301>; 267 status = "disabled"; 268 }; 269 270 cmt3: timer@e6148000 { 271 compatible = "renesas,r8a77970-cmt1", 272 "renesas,rcar-gen3-cmt1"; 273 reg = <0 0xe6148000 0 0x1004>; 274 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 275 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 282 clocks = <&cpg CPG_MOD 300>; 283 clock-names = "fck"; 284 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 285 resets = <&cpg 300>; 286 status = "disabled"; 287 }; 288 289 cpg: clock-controller@e6150000 { 290 compatible = "renesas,r8a77970-cpg-mssr"; 291 reg = <0 0xe6150000 0 0x1000>; 292 clocks = <&extal_clk>, <&extalr_clk>; 293 clock-names = "extal", "extalr"; 294 #clock-cells = <2>; 295 #power-domain-cells = <0>; 296 #reset-cells = <1>; 297 bootph-all; 298 }; 299 300 rst: reset-controller@e6160000 { 301 compatible = "renesas,r8a77970-rst"; 302 reg = <0 0xe6160000 0 0x200>; 303 bootph-all; 304 }; 305 306 sysc: system-controller@e6180000 { 307 compatible = "renesas,r8a77970-sysc"; 308 reg = <0 0xe6180000 0 0x440>; 309 #power-domain-cells = <1>; 310 }; 311 312 thermal: thermal@e6190000 { 313 compatible = "renesas,thermal-r8a77970"; 314 reg = <0 0xe6190000 0 0x10>, 315 <0 0xe6190100 0 0x120>; 316 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>, 317 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 318 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&cpg CPG_MOD 522>; 320 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 321 resets = <&cpg 522>; 322 #thermal-sensor-cells = <0>; 323 }; 324 325 intc_ex: interrupt-controller@e61c0000 { 326 compatible = "renesas,intc-ex-r8a77970", "renesas,irqc"; 327 #interrupt-cells = <2>; 328 interrupt-controller; 329 reg = <0 0xe61c0000 0 0x200>; 330 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 331 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 332 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 333 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&cpg CPG_MOD 407>; 337 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 338 resets = <&cpg 407>; 339 }; 340 341 tmu0: timer@e61e0000 { 342 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 343 reg = <0 0xe61e0000 0 0x30>; 344 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 345 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 346 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 347 interrupt-names = "tuni0", "tuni1", "tuni2"; 348 clocks = <&cpg CPG_MOD 125>; 349 clock-names = "fck"; 350 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 351 resets = <&cpg 125>; 352 status = "disabled"; 353 }; 354 355 tmu1: timer@e6fc0000 { 356 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 357 reg = <0 0xe6fc0000 0 0x30>; 358 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 359 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 362 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 363 clocks = <&cpg CPG_MOD 124>; 364 clock-names = "fck"; 365 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 366 resets = <&cpg 124>; 367 status = "disabled"; 368 }; 369 370 tmu2: timer@e6fd0000 { 371 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 372 reg = <0 0xe6fd0000 0 0x30>; 373 interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 375 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, 376 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 377 interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2"; 378 clocks = <&cpg CPG_MOD 123>; 379 clock-names = "fck"; 380 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 381 resets = <&cpg 123>; 382 status = "disabled"; 383 }; 384 385 tmu3: timer@e6fe0000 { 386 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 387 reg = <0 0xe6fe0000 0 0x30>; 388 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 389 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 390 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 391 interrupt-names = "tuni0", "tuni1", "tuni2"; 392 clocks = <&cpg CPG_MOD 122>; 393 clock-names = "fck"; 394 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 395 resets = <&cpg 122>; 396 status = "disabled"; 397 }; 398 399 tmu4: timer@ffc00000 { 400 compatible = "renesas,tmu-r8a77970", "renesas,tmu"; 401 reg = <0 0xffc00000 0 0x30>; 402 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 404 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 405 interrupt-names = "tuni0", "tuni1", "tuni2"; 406 clocks = <&cpg CPG_MOD 121>; 407 clock-names = "fck"; 408 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 409 resets = <&cpg 121>; 410 status = "disabled"; 411 }; 412 413 i2c0: i2c@e6500000 { 414 compatible = "renesas,i2c-r8a77970", 415 "renesas,rcar-gen3-i2c"; 416 reg = <0 0xe6500000 0 0x40>; 417 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&cpg CPG_MOD 931>; 419 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 420 resets = <&cpg 931>; 421 dmas = <&dmac1 0x91>, <&dmac1 0x90>, 422 <&dmac2 0x91>, <&dmac2 0x90>; 423 dma-names = "tx", "rx", "tx", "rx"; 424 i2c-scl-internal-delay-ns = <6>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 status = "disabled"; 428 }; 429 430 i2c1: i2c@e6508000 { 431 compatible = "renesas,i2c-r8a77970", 432 "renesas,rcar-gen3-i2c"; 433 reg = <0 0xe6508000 0 0x40>; 434 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 435 clocks = <&cpg CPG_MOD 930>; 436 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 437 resets = <&cpg 930>; 438 dmas = <&dmac1 0x93>, <&dmac1 0x92>, 439 <&dmac2 0x93>, <&dmac2 0x92>; 440 dma-names = "tx", "rx", "tx", "rx"; 441 i2c-scl-internal-delay-ns = <6>; 442 #address-cells = <1>; 443 #size-cells = <0>; 444 status = "disabled"; 445 }; 446 447 i2c2: i2c@e6510000 { 448 compatible = "renesas,i2c-r8a77970", 449 "renesas,rcar-gen3-i2c"; 450 reg = <0 0xe6510000 0 0x40>; 451 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 452 clocks = <&cpg CPG_MOD 929>; 453 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 454 resets = <&cpg 929>; 455 dmas = <&dmac1 0x95>, <&dmac1 0x94>, 456 <&dmac2 0x95>, <&dmac2 0x94>; 457 dma-names = "tx", "rx", "tx", "rx"; 458 i2c-scl-internal-delay-ns = <6>; 459 #address-cells = <1>; 460 #size-cells = <0>; 461 status = "disabled"; 462 }; 463 464 i2c3: i2c@e66d0000 { 465 compatible = "renesas,i2c-r8a77970", 466 "renesas,rcar-gen3-i2c"; 467 reg = <0 0xe66d0000 0 0x40>; 468 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; 469 clocks = <&cpg CPG_MOD 928>; 470 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 471 resets = <&cpg 928>; 472 dmas = <&dmac1 0x97>, <&dmac1 0x96>, 473 <&dmac2 0x97>, <&dmac2 0x96>; 474 dma-names = "tx", "rx", "tx", "rx"; 475 i2c-scl-internal-delay-ns = <6>; 476 #address-cells = <1>; 477 #size-cells = <0>; 478 status = "disabled"; 479 }; 480 481 i2c4: i2c@e66d8000 { 482 compatible = "renesas,i2c-r8a77970", 483 "renesas,rcar-gen3-i2c"; 484 reg = <0 0xe66d8000 0 0x40>; 485 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&cpg CPG_MOD 927>; 487 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 488 resets = <&cpg 927>; 489 dmas = <&dmac1 0x99>, <&dmac1 0x98>, 490 <&dmac2 0x99>, <&dmac2 0x98>; 491 dma-names = "tx", "rx", "tx", "rx"; 492 i2c-scl-internal-delay-ns = <6>; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 status = "disabled"; 496 }; 497 498 hscif0: serial@e6540000 { 499 compatible = "renesas,hscif-r8a77970", 500 "renesas,rcar-gen3-hscif", 501 "renesas,hscif"; 502 reg = <0 0xe6540000 0 96>; 503 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 504 clocks = <&cpg CPG_MOD 520>, 505 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 506 <&scif_clk>; 507 clock-names = "fck", "brg_int", "scif_clk"; 508 dmas = <&dmac1 0x31>, <&dmac1 0x30>, 509 <&dmac2 0x31>, <&dmac2 0x30>; 510 dma-names = "tx", "rx", "tx", "rx"; 511 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 512 resets = <&cpg 520>; 513 status = "disabled"; 514 }; 515 516 hscif1: serial@e6550000 { 517 compatible = "renesas,hscif-r8a77970", 518 "renesas,rcar-gen3-hscif", 519 "renesas,hscif"; 520 reg = <0 0xe6550000 0 96>; 521 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 522 clocks = <&cpg CPG_MOD 519>, 523 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 524 <&scif_clk>; 525 clock-names = "fck", "brg_int", "scif_clk"; 526 dmas = <&dmac1 0x33>, <&dmac1 0x32>, 527 <&dmac2 0x33>, <&dmac2 0x32>; 528 dma-names = "tx", "rx", "tx", "rx"; 529 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 530 resets = <&cpg 519>; 531 status = "disabled"; 532 }; 533 534 hscif2: serial@e6560000 { 535 compatible = "renesas,hscif-r8a77970", 536 "renesas,rcar-gen3-hscif", 537 "renesas,hscif"; 538 reg = <0 0xe6560000 0 96>; 539 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&cpg CPG_MOD 518>, 541 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 542 <&scif_clk>; 543 clock-names = "fck", "brg_int", "scif_clk"; 544 dmas = <&dmac1 0x35>, <&dmac1 0x34>, 545 <&dmac2 0x35>, <&dmac2 0x34>; 546 dma-names = "tx", "rx", "tx", "rx"; 547 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 548 resets = <&cpg 518>; 549 status = "disabled"; 550 }; 551 552 hscif3: serial@e66a0000 { 553 compatible = "renesas,hscif-r8a77970", 554 "renesas,rcar-gen3-hscif", "renesas,hscif"; 555 reg = <0 0xe66a0000 0 96>; 556 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&cpg CPG_MOD 517>, 558 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 559 <&scif_clk>; 560 clock-names = "fck", "brg_int", "scif_clk"; 561 dmas = <&dmac1 0x37>, <&dmac1 0x36>, 562 <&dmac2 0x37>, <&dmac2 0x36>; 563 dma-names = "tx", "rx", "tx", "rx"; 564 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 565 resets = <&cpg 517>; 566 status = "disabled"; 567 }; 568 569 canfd: can@e66c0000 { 570 compatible = "renesas,r8a77970-canfd", 571 "renesas,rcar-gen3-canfd"; 572 reg = <0 0xe66c0000 0 0x8000>; 573 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 575 interrupt-names = "ch_int", "g_int"; 576 clocks = <&cpg CPG_MOD 914>, 577 <&cpg CPG_CORE R8A77970_CLK_CANFD>, 578 <&can_clk>; 579 clock-names = "fck", "canfd", "can_clk"; 580 assigned-clocks = <&cpg CPG_CORE R8A77970_CLK_CANFD>; 581 assigned-clock-rates = <80000000>; 582 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 583 resets = <&cpg 914>; 584 status = "disabled"; 585 586 channel0 { 587 status = "disabled"; 588 }; 589 590 channel1 { 591 status = "disabled"; 592 }; 593 }; 594 595 avb: ethernet@e6800000 { 596 compatible = "renesas,etheravb-r8a77970", 597 "renesas,etheravb-rcar-gen3"; 598 reg = <0 0xe6800000 0 0x800>; 599 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 615 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 616 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 617 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 618 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 621 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 622 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 623 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 624 interrupt-names = "ch0", "ch1", "ch2", "ch3", 625 "ch4", "ch5", "ch6", "ch7", 626 "ch8", "ch9", "ch10", "ch11", 627 "ch12", "ch13", "ch14", "ch15", 628 "ch16", "ch17", "ch18", "ch19", 629 "ch20", "ch21", "ch22", "ch23", 630 "ch24"; 631 clocks = <&cpg CPG_MOD 812>; 632 clock-names = "fck"; 633 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 634 resets = <&cpg 812>; 635 phy-mode = "rgmii"; 636 rx-internal-delay-ps = <0>; 637 tx-internal-delay-ps = <0>; 638 iommus = <&ipmmu_rt 3>; 639 #address-cells = <1>; 640 #size-cells = <0>; 641 status = "disabled"; 642 }; 643 644 pwm0: pwm@e6e30000 { 645 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 646 reg = <0 0xe6e30000 0 8>; 647 #pwm-cells = <2>; 648 clocks = <&cpg CPG_MOD 523>; 649 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 650 resets = <&cpg 523>; 651 status = "disabled"; 652 }; 653 654 pwm1: pwm@e6e31000 { 655 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 656 reg = <0 0xe6e31000 0 8>; 657 #pwm-cells = <2>; 658 clocks = <&cpg CPG_MOD 523>; 659 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 660 resets = <&cpg 523>; 661 status = "disabled"; 662 }; 663 664 pwm2: pwm@e6e32000 { 665 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 666 reg = <0 0xe6e32000 0 8>; 667 #pwm-cells = <2>; 668 clocks = <&cpg CPG_MOD 523>; 669 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 670 resets = <&cpg 523>; 671 status = "disabled"; 672 }; 673 674 pwm3: pwm@e6e33000 { 675 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 676 reg = <0 0xe6e33000 0 8>; 677 #pwm-cells = <2>; 678 clocks = <&cpg CPG_MOD 523>; 679 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 680 resets = <&cpg 523>; 681 status = "disabled"; 682 }; 683 684 pwm4: pwm@e6e34000 { 685 compatible = "renesas,pwm-r8a77970", "renesas,pwm-rcar"; 686 reg = <0 0xe6e34000 0 8>; 687 #pwm-cells = <2>; 688 clocks = <&cpg CPG_MOD 523>; 689 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 690 resets = <&cpg 523>; 691 status = "disabled"; 692 }; 693 694 scif0: serial@e6e60000 { 695 compatible = "renesas,scif-r8a77970", 696 "renesas,rcar-gen3-scif", 697 "renesas,scif"; 698 reg = <0 0xe6e60000 0 64>; 699 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 700 clocks = <&cpg CPG_MOD 207>, 701 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 702 <&scif_clk>; 703 clock-names = "fck", "brg_int", "scif_clk"; 704 dmas = <&dmac1 0x51>, <&dmac1 0x50>, 705 <&dmac2 0x51>, <&dmac2 0x50>; 706 dma-names = "tx", "rx", "tx", "rx"; 707 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 708 resets = <&cpg 207>; 709 status = "disabled"; 710 }; 711 712 scif1: serial@e6e68000 { 713 compatible = "renesas,scif-r8a77970", 714 "renesas,rcar-gen3-scif", 715 "renesas,scif"; 716 reg = <0 0xe6e68000 0 64>; 717 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 718 clocks = <&cpg CPG_MOD 206>, 719 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 720 <&scif_clk>; 721 clock-names = "fck", "brg_int", "scif_clk"; 722 dmas = <&dmac1 0x53>, <&dmac1 0x52>, 723 <&dmac2 0x53>, <&dmac2 0x52>; 724 dma-names = "tx", "rx", "tx", "rx"; 725 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 726 resets = <&cpg 206>; 727 status = "disabled"; 728 }; 729 730 scif3: serial@e6c50000 { 731 compatible = "renesas,scif-r8a77970", 732 "renesas,rcar-gen3-scif", 733 "renesas,scif"; 734 reg = <0 0xe6c50000 0 64>; 735 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 736 clocks = <&cpg CPG_MOD 204>, 737 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 738 <&scif_clk>; 739 clock-names = "fck", "brg_int", "scif_clk"; 740 dmas = <&dmac1 0x57>, <&dmac1 0x56>, 741 <&dmac2 0x57>, <&dmac2 0x56>; 742 dma-names = "tx", "rx", "tx", "rx"; 743 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 744 resets = <&cpg 204>; 745 status = "disabled"; 746 }; 747 748 scif4: serial@e6c40000 { 749 compatible = "renesas,scif-r8a77970", 750 "renesas,rcar-gen3-scif", "renesas,scif"; 751 reg = <0 0xe6c40000 0 64>; 752 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 753 clocks = <&cpg CPG_MOD 203>, 754 <&cpg CPG_CORE R8A77970_CLK_S2D1>, 755 <&scif_clk>; 756 clock-names = "fck", "brg_int", "scif_clk"; 757 dmas = <&dmac1 0x59>, <&dmac1 0x58>, 758 <&dmac2 0x59>, <&dmac2 0x58>; 759 dma-names = "tx", "rx", "tx", "rx"; 760 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 761 resets = <&cpg 203>; 762 status = "disabled"; 763 }; 764 765 tpu: pwm@e6e80000 { 766 compatible = "renesas,tpu-r8a77970", "renesas,tpu"; 767 reg = <0 0xe6e80000 0 0x148>; 768 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; 769 clocks = <&cpg CPG_MOD 304>; 770 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 771 resets = <&cpg 304>; 772 #pwm-cells = <3>; 773 status = "disabled"; 774 }; 775 776 msiof0: spi@e6e90000 { 777 compatible = "renesas,msiof-r8a77970", 778 "renesas,rcar-gen3-msiof"; 779 reg = <0 0xe6e90000 0 0x64>; 780 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&cpg CPG_MOD 211>; 782 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 783 resets = <&cpg 211>; 784 dmas = <&dmac1 0x41>, <&dmac1 0x40>, 785 <&dmac2 0x41>, <&dmac2 0x40>; 786 dma-names = "tx", "rx", "tx", "rx"; 787 #address-cells = <1>; 788 #size-cells = <0>; 789 status = "disabled"; 790 }; 791 792 msiof1: spi@e6ea0000 { 793 compatible = "renesas,msiof-r8a77970", 794 "renesas,rcar-gen3-msiof"; 795 reg = <0 0xe6ea0000 0 0x0064>; 796 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; 797 clocks = <&cpg CPG_MOD 210>; 798 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 799 resets = <&cpg 210>; 800 dmas = <&dmac1 0x43>, <&dmac1 0x42>, 801 <&dmac2 0x43>, <&dmac2 0x42>; 802 dma-names = "tx", "rx", "tx", "rx"; 803 #address-cells = <1>; 804 #size-cells = <0>; 805 status = "disabled"; 806 }; 807 808 msiof2: spi@e6c00000 { 809 compatible = "renesas,msiof-r8a77970", 810 "renesas,rcar-gen3-msiof"; 811 reg = <0 0xe6c00000 0 0x0064>; 812 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&cpg CPG_MOD 209>; 814 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 815 resets = <&cpg 209>; 816 dmas = <&dmac1 0x45>, <&dmac1 0x44>, 817 <&dmac2 0x45>, <&dmac2 0x44>; 818 dma-names = "tx", "rx", "tx", "rx"; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 status = "disabled"; 822 }; 823 824 msiof3: spi@e6c10000 { 825 compatible = "renesas,msiof-r8a77970", 826 "renesas,rcar-gen3-msiof"; 827 reg = <0 0xe6c10000 0 0x0064>; 828 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 829 clocks = <&cpg CPG_MOD 208>; 830 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 831 resets = <&cpg 208>; 832 dmas = <&dmac1 0x47>, <&dmac1 0x46>, 833 <&dmac2 0x47>, <&dmac2 0x46>; 834 dma-names = "tx", "rx", "tx", "rx"; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 status = "disabled"; 838 }; 839 840 vin0: video@e6ef0000 { 841 compatible = "renesas,vin-r8a77970"; 842 reg = <0 0xe6ef0000 0 0x1000>; 843 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 844 clocks = <&cpg CPG_MOD 811>; 845 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 846 resets = <&cpg 811>; 847 renesas,id = <0>; 848 status = "disabled"; 849 850 ports { 851 #address-cells = <1>; 852 #size-cells = <0>; 853 854 port@1 { 855 #address-cells = <1>; 856 #size-cells = <0>; 857 858 reg = <1>; 859 860 vin0csi40: endpoint@2 { 861 reg = <2>; 862 remote-endpoint = <&csi40vin0>; 863 }; 864 }; 865 }; 866 }; 867 868 vin1: video@e6ef1000 { 869 compatible = "renesas,vin-r8a77970"; 870 reg = <0 0xe6ef1000 0 0x1000>; 871 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; 872 clocks = <&cpg CPG_MOD 810>; 873 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 874 resets = <&cpg 810>; 875 renesas,id = <1>; 876 status = "disabled"; 877 878 ports { 879 #address-cells = <1>; 880 #size-cells = <0>; 881 882 port@1 { 883 #address-cells = <1>; 884 #size-cells = <0>; 885 886 reg = <1>; 887 888 vin1csi40: endpoint@2 { 889 reg = <2>; 890 remote-endpoint = <&csi40vin1>; 891 }; 892 }; 893 }; 894 }; 895 896 vin2: video@e6ef2000 { 897 compatible = "renesas,vin-r8a77970"; 898 reg = <0 0xe6ef2000 0 0x1000>; 899 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 900 clocks = <&cpg CPG_MOD 809>; 901 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 902 resets = <&cpg 809>; 903 renesas,id = <2>; 904 status = "disabled"; 905 906 ports { 907 #address-cells = <1>; 908 #size-cells = <0>; 909 910 port@1 { 911 #address-cells = <1>; 912 #size-cells = <0>; 913 914 reg = <1>; 915 916 vin2csi40: endpoint@2 { 917 reg = <2>; 918 remote-endpoint = <&csi40vin2>; 919 }; 920 }; 921 }; 922 }; 923 924 vin3: video@e6ef3000 { 925 compatible = "renesas,vin-r8a77970"; 926 reg = <0 0xe6ef3000 0 0x1000>; 927 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&cpg CPG_MOD 808>; 929 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 930 resets = <&cpg 808>; 931 renesas,id = <3>; 932 status = "disabled"; 933 934 ports { 935 #address-cells = <1>; 936 #size-cells = <0>; 937 938 port@1 { 939 #address-cells = <1>; 940 #size-cells = <0>; 941 942 reg = <1>; 943 944 vin3csi40: endpoint@2 { 945 reg = <2>; 946 remote-endpoint = <&csi40vin3>; 947 }; 948 }; 949 }; 950 }; 951 952 dmac1: dma-controller@e7300000 { 953 compatible = "renesas,dmac-r8a77970", 954 "renesas,rcar-dmac"; 955 reg = <0 0xe7300000 0 0x10000>; 956 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 959 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 960 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>, 961 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 962 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 963 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 964 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 965 interrupt-names = "error", 966 "ch0", "ch1", "ch2", "ch3", 967 "ch4", "ch5", "ch6", "ch7"; 968 clocks = <&cpg CPG_MOD 218>; 969 clock-names = "fck"; 970 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 971 resets = <&cpg 218>; 972 #dma-cells = <1>; 973 dma-channels = <8>; 974 iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>, 975 <&ipmmu_ds1 2>, <&ipmmu_ds1 3>, 976 <&ipmmu_ds1 4>, <&ipmmu_ds1 5>, 977 <&ipmmu_ds1 6>, <&ipmmu_ds1 7>; 978 }; 979 980 dmac2: dma-controller@e7310000 { 981 compatible = "renesas,dmac-r8a77970", 982 "renesas,rcar-dmac"; 983 reg = <0 0xe7310000 0 0x10000>; 984 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 985 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 993 interrupt-names = "error", 994 "ch0", "ch1", "ch2", "ch3", 995 "ch4", "ch5", "ch6", "ch7"; 996 clocks = <&cpg CPG_MOD 217>; 997 clock-names = "fck"; 998 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 999 resets = <&cpg 217>; 1000 #dma-cells = <1>; 1001 dma-channels = <8>; 1002 iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>, 1003 <&ipmmu_ds1 18>, <&ipmmu_ds1 19>, 1004 <&ipmmu_ds1 20>, <&ipmmu_ds1 21>, 1005 <&ipmmu_ds1 22>, <&ipmmu_ds1 23>; 1006 }; 1007 1008 ipmmu_ds1: iommu@e7740000 { 1009 compatible = "renesas,ipmmu-r8a77970"; 1010 reg = <0 0xe7740000 0 0x1000>; 1011 renesas,ipmmu-main = <&ipmmu_mm 0>; 1012 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1013 #iommu-cells = <1>; 1014 }; 1015 1016 ipmmu_ir: iommu@ff8b0000 { 1017 compatible = "renesas,ipmmu-r8a77970"; 1018 reg = <0 0xff8b0000 0 0x1000>; 1019 renesas,ipmmu-main = <&ipmmu_mm 3>; 1020 power-domains = <&sysc R8A77970_PD_A3IR>; 1021 #iommu-cells = <1>; 1022 }; 1023 1024 ipmmu_mm: iommu@e67b0000 { 1025 compatible = "renesas,ipmmu-r8a77970"; 1026 reg = <0 0xe67b0000 0 0x1000>; 1027 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 1029 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1030 #iommu-cells = <1>; 1031 }; 1032 1033 ipmmu_rt: iommu@ffc80000 { 1034 compatible = "renesas,ipmmu-r8a77970"; 1035 reg = <0 0xffc80000 0 0x1000>; 1036 renesas,ipmmu-main = <&ipmmu_mm 7>; 1037 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1038 #iommu-cells = <1>; 1039 }; 1040 1041 ipmmu_vi0: iommu@febd0000 { 1042 compatible = "renesas,ipmmu-r8a77970"; 1043 reg = <0 0xfebd0000 0 0x1000>; 1044 renesas,ipmmu-main = <&ipmmu_mm 9>; 1045 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1046 #iommu-cells = <1>; 1047 }; 1048 1049 mmc0: mmc@ee140000 { 1050 compatible = "renesas,sdhi-r8a77970", 1051 "renesas,rcar-gen3-sdhi"; 1052 reg = <0 0xee140000 0 0x2000>; 1053 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 1054 clocks = <&cpg CPG_MOD 314>; 1055 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1056 resets = <&cpg 314>; 1057 max-frequency = <200000000>; 1058 iommus = <&ipmmu_ds1 32>; 1059 status = "disabled"; 1060 }; 1061 1062 rpc: spi@ee200000 { 1063 compatible = "renesas,r8a77970-rpc-if", 1064 "renesas,rcar-gen3-rpc-if"; 1065 reg = <0 0xee200000 0 0x200>, 1066 <0 0x08000000 0 0x4000000>, 1067 <0 0xee208000 0 0x100>; 1068 reg-names = "regs", "dirmap", "wbuf"; 1069 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1070 clocks = <&cpg CPG_MOD 917>; 1071 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1072 resets = <&cpg 917>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 status = "disabled"; 1076 }; 1077 1078 gic: interrupt-controller@f1010000 { 1079 compatible = "arm,gic-400"; 1080 #interrupt-cells = <3>; 1081 #address-cells = <0>; 1082 interrupt-controller; 1083 reg = <0 0xf1010000 0 0x1000>, 1084 <0 0xf1020000 0 0x20000>, 1085 <0 0xf1040000 0 0x20000>, 1086 <0 0xf1060000 0 0x20000>; 1087 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | 1088 IRQ_TYPE_LEVEL_HIGH)>; 1089 clocks = <&cpg CPG_MOD 408>; 1090 clock-names = "clk"; 1091 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1092 resets = <&cpg 408>; 1093 }; 1094 1095 vspd0: vsp@fea20000 { 1096 compatible = "renesas,vsp2"; 1097 reg = <0 0xfea20000 0 0x5000>; 1098 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&cpg CPG_MOD 623>; 1100 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1101 resets = <&cpg 623>; 1102 renesas,fcp = <&fcpvd0>; 1103 }; 1104 1105 fcpvd0: fcp@fea27000 { 1106 compatible = "renesas,fcpv"; 1107 reg = <0 0xfea27000 0 0x200>; 1108 clocks = <&cpg CPG_MOD 603>; 1109 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1110 resets = <&cpg 603>; 1111 iommus = <&ipmmu_vi0 8>; 1112 }; 1113 1114 csi40: csi2@feaa0000 { 1115 compatible = "renesas,r8a77970-csi2"; 1116 reg = <0 0xfeaa0000 0 0x10000>; 1117 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1118 clocks = <&cpg CPG_MOD 716>; 1119 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1120 resets = <&cpg 716>; 1121 status = "disabled"; 1122 1123 ports { 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 1127 port@0 { 1128 reg = <0>; 1129 }; 1130 1131 port@1 { 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 1135 reg = <1>; 1136 1137 csi40vin0: endpoint@0 { 1138 reg = <0>; 1139 remote-endpoint = <&vin0csi40>; 1140 }; 1141 csi40vin1: endpoint@1 { 1142 reg = <1>; 1143 remote-endpoint = <&vin1csi40>; 1144 }; 1145 csi40vin2: endpoint@2 { 1146 reg = <2>; 1147 remote-endpoint = <&vin2csi40>; 1148 }; 1149 csi40vin3: endpoint@3 { 1150 reg = <3>; 1151 remote-endpoint = <&vin3csi40>; 1152 }; 1153 }; 1154 }; 1155 }; 1156 1157 du: display@feb00000 { 1158 compatible = "renesas,du-r8a77970"; 1159 reg = <0 0xfeb00000 0 0x80000>; 1160 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&cpg CPG_MOD 724>; 1162 clock-names = "du.0"; 1163 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1164 resets = <&cpg 724>; 1165 reset-names = "du.0"; 1166 renesas,vsps = <&vspd0 0>; 1167 1168 status = "disabled"; 1169 1170 ports { 1171 #address-cells = <1>; 1172 #size-cells = <0>; 1173 1174 port@0 { 1175 reg = <0>; 1176 }; 1177 1178 port@1 { 1179 reg = <1>; 1180 du_out_lvds0: endpoint { 1181 remote-endpoint = <&lvds0_in>; 1182 }; 1183 }; 1184 }; 1185 }; 1186 1187 lvds0: lvds-encoder@feb90000 { 1188 compatible = "renesas,r8a77970-lvds"; 1189 reg = <0 0xfeb90000 0 0x14>; 1190 clocks = <&cpg CPG_MOD 727>; 1191 power-domains = <&sysc R8A77970_PD_ALWAYS_ON>; 1192 resets = <&cpg 727>; 1193 status = "disabled"; 1194 1195 ports { 1196 #address-cells = <1>; 1197 #size-cells = <0>; 1198 1199 port@0 { 1200 reg = <0>; 1201 lvds0_in: endpoint { 1202 remote-endpoint = 1203 <&du_out_lvds0>; 1204 }; 1205 }; 1206 port@1 { 1207 reg = <1>; 1208 }; 1209 }; 1210 }; 1211 1212 prr: chipid@fff00044 { 1213 compatible = "renesas,prr"; 1214 reg = <0 0xfff00044 0 4>; 1215 bootph-all; 1216 }; 1217 }; 1218 1219 thermal-zones { 1220 cpu-thermal { 1221 polling-delay-passive = <250>; 1222 polling-delay = <1000>; 1223 thermal-sensors = <&thermal>; 1224 1225 cooling-maps { 1226 }; 1227 1228 trips { 1229 cpu-crit { 1230 temperature = <120000>; 1231 hysteresis = <2000>; 1232 type = "critical"; 1233 }; 1234 }; 1235 }; 1236 }; 1237 1238 timer { 1239 compatible = "arm,armv8-timer"; 1240 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1241 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1242 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 1243 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 1244 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 1245 }; 1246};
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