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talos.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/talos.dtsi
1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,qcs615-camcc.h> 8#include <dt-bindings/clock/qcom,qcs615-dispcc.h> 9#include <dt-bindings/clock/qcom,qcs615-gcc.h> 10#include <dt-bindings/clock/qcom,qcs615-gpucc.h> 11#include <dt-bindings/clock/qcom,qcs615-videocc.h> 12#include <dt-bindings/clock/qcom,rpmh.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,qcs615-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/power/qcom-rpmpd.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/soc/qcom,rpmh-rsc.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 #address-cells = <2>; 25 #size-cells = <2>; 26 27 cpus { 28 #address-cells = <2>; 29 #size-cells = <0>; 30 31 cpu0: cpu@0 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a55"; 34 reg = <0x0 0x0>; 35 enable-method = "psci"; 36 power-domains = <&cpu_pd0>; 37 power-domain-names = "psci"; 38 capacity-dmips-mhz = <1024>; 39 dynamic-power-coefficient = <100>; 40 next-level-cache = <&l2_0>; 41 clocks = <&cpufreq_hw 0>; 42 qcom,freq-domain = <&cpufreq_hw 0>; 43 #cooling-cells = <2>; 44 operating-points-v2 = <&cpu0_opp_table>; 45 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 46 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 47 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 48 49 l2_0: l2-cache { 50 compatible = "cache"; 51 cache-level = <2>; 52 cache-unified; 53 next-level-cache = <&l3_0>; 54 }; 55 }; 56 57 cpu1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a55"; 60 reg = <0x0 0x100>; 61 enable-method = "psci"; 62 power-domains = <&cpu_pd1>; 63 power-domain-names = "psci"; 64 capacity-dmips-mhz = <1024>; 65 dynamic-power-coefficient = <100>; 66 next-level-cache = <&l2_100>; 67 clocks = <&cpufreq_hw 0>; 68 qcom,freq-domain = <&cpufreq_hw 0>; 69 operating-points-v2 = <&cpu0_opp_table>; 70 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 71 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 72 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 73 74 l2_100: l2-cache { 75 compatible = "cache"; 76 cache-level = <2>; 77 cache-unified; 78 next-level-cache = <&l3_0>; 79 }; 80 }; 81 82 cpu2: cpu@200 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a55"; 85 reg = <0x0 0x200>; 86 enable-method = "psci"; 87 power-domains = <&cpu_pd2>; 88 power-domain-names = "psci"; 89 capacity-dmips-mhz = <1024>; 90 dynamic-power-coefficient = <100>; 91 next-level-cache = <&l2_200>; 92 clocks = <&cpufreq_hw 0>; 93 qcom,freq-domain = <&cpufreq_hw 0>; 94 operating-points-v2 = <&cpu0_opp_table>; 95 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 96 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 97 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 98 99 l2_200: l2-cache { 100 compatible = "cache"; 101 cache-level = <2>; 102 cache-unified; 103 next-level-cache = <&l3_0>; 104 }; 105 }; 106 107 cpu3: cpu@300 { 108 device_type = "cpu"; 109 compatible = "arm,cortex-a55"; 110 reg = <0x0 0x300>; 111 enable-method = "psci"; 112 power-domains = <&cpu_pd3>; 113 power-domain-names = "psci"; 114 capacity-dmips-mhz = <1024>; 115 dynamic-power-coefficient = <100>; 116 next-level-cache = <&l2_300>; 117 clocks = <&cpufreq_hw 0>; 118 qcom,freq-domain = <&cpufreq_hw 0>; 119 operating-points-v2 = <&cpu0_opp_table>; 120 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 121 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 122 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 123 124 l2_300: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 next-level-cache = <&l3_0>; 129 }; 130 }; 131 132 cpu4: cpu@400 { 133 device_type = "cpu"; 134 compatible = "arm,cortex-a55"; 135 reg = <0x0 0x400>; 136 enable-method = "psci"; 137 power-domains = <&cpu_pd4>; 138 power-domain-names = "psci"; 139 capacity-dmips-mhz = <1024>; 140 dynamic-power-coefficient = <100>; 141 next-level-cache = <&l2_400>; 142 clocks = <&cpufreq_hw 0>; 143 qcom,freq-domain = <&cpufreq_hw 0>; 144 operating-points-v2 = <&cpu0_opp_table>; 145 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 146 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 147 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 148 149 l2_400: l2-cache { 150 compatible = "cache"; 151 cache-level = <2>; 152 cache-unified; 153 next-level-cache = <&l3_0>; 154 }; 155 }; 156 157 cpu5: cpu@500 { 158 device_type = "cpu"; 159 compatible = "arm,cortex-a55"; 160 reg = <0x0 0x500>; 161 enable-method = "psci"; 162 power-domains = <&cpu_pd5>; 163 power-domain-names = "psci"; 164 capacity-dmips-mhz = <1024>; 165 dynamic-power-coefficient = <100>; 166 next-level-cache = <&l2_500>; 167 clocks = <&cpufreq_hw 0>; 168 qcom,freq-domain = <&cpufreq_hw 0>; 169 operating-points-v2 = <&cpu0_opp_table>; 170 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 171 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 172 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 173 174 l2_500: l2-cache { 175 compatible = "cache"; 176 cache-level = <2>; 177 cache-unified; 178 next-level-cache = <&l3_0>; 179 }; 180 }; 181 182 cpu6: cpu@600 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a76"; 185 reg = <0x0 0x600>; 186 enable-method = "psci"; 187 power-domains = <&cpu_pd6>; 188 power-domain-names = "psci"; 189 capacity-dmips-mhz = <1740>; 190 dynamic-power-coefficient = <404>; 191 next-level-cache = <&l2_600>; 192 clocks = <&cpufreq_hw 1>; 193 qcom,freq-domain = <&cpufreq_hw 1>; 194 #cooling-cells = <2>; 195 operating-points-v2 = <&cpu6_opp_table>; 196 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 197 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 198 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 199 200 l2_600: l2-cache { 201 compatible = "cache"; 202 cache-level = <2>; 203 cache-unified; 204 next-level-cache = <&l3_0>; 205 }; 206 }; 207 208 cpu7: cpu@700 { 209 device_type = "cpu"; 210 compatible = "arm,cortex-a76"; 211 reg = <0x0 0x700>; 212 enable-method = "psci"; 213 power-domains = <&cpu_pd7>; 214 power-domain-names = "psci"; 215 capacity-dmips-mhz = <1740>; 216 dynamic-power-coefficient = <404>; 217 next-level-cache = <&l2_700>; 218 clocks = <&cpufreq_hw 1>; 219 qcom,freq-domain = <&cpufreq_hw 1>; 220 operating-points-v2 = <&cpu6_opp_table>; 221 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 222 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 223 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 224 225 l2_700: l2-cache { 226 compatible = "cache"; 227 cache-level = <2>; 228 cache-unified; 229 next-level-cache = <&l3_0>; 230 }; 231 }; 232 233 cpu-map { 234 cluster0 { 235 core0 { 236 cpu = <&cpu0>; 237 }; 238 239 core1 { 240 cpu = <&cpu1>; 241 }; 242 243 core2 { 244 cpu = <&cpu2>; 245 }; 246 247 core3 { 248 cpu = <&cpu3>; 249 }; 250 251 core4 { 252 cpu = <&cpu4>; 253 }; 254 255 core5 { 256 cpu = <&cpu5>; 257 }; 258 259 core6 { 260 cpu = <&cpu6>; 261 }; 262 263 core7 { 264 cpu = <&cpu7>; 265 }; 266 }; 267 }; 268 269 l3_0: l3-cache { 270 compatible = "cache"; 271 cache-level = <3>; 272 cache-unified; 273 }; 274 }; 275 276 cpu0_opp_table: opp-table-cpu0 { 277 compatible = "operating-points-v2"; 278 opp-shared; 279 280 opp-300000000 { 281 opp-hz = /bits/ 64 <300000000>; 282 opp-peak-kBps = <(300000 * 4) (300000 * 16)>; 283 }; 284 285 opp-576000000 { 286 opp-hz = /bits/ 64 <576000000>; 287 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 288 }; 289 290 opp-748800000 { 291 opp-hz = /bits/ 64 <748800000>; 292 opp-peak-kBps = <(300000 * 4) (576000 * 16)>; 293 }; 294 295 opp-998400000 { 296 opp-hz = /bits/ 64 <998400000>; 297 opp-peak-kBps = <(451000 * 4) (806400 * 16)>; 298 }; 299 300 opp-1209600000 { 301 opp-hz = /bits/ 64 <1209600000>; 302 opp-peak-kBps = <(547000 * 4) (1017600 * 16)>; 303 }; 304 305 opp-1363200000 { 306 opp-hz = /bits/ 64 <1363200000>; 307 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 308 }; 309 310 opp-1516800000 { 311 opp-hz = /bits/ 64 <1516800000>; 312 opp-peak-kBps = <(768000 * 4) (1209600 * 16)>; 313 }; 314 315 opp-1593600000 { 316 opp-hz = /bits/ 64 <1593600000>; 317 opp-peak-kBps = <(1017000 * 4) (1363200 * 16)>; 318 }; 319 }; 320 321 cpu6_opp_table: opp-table-cpu6 { 322 compatible = "operating-points-v2"; 323 opp-shared; 324 325 opp-300000000 { 326 opp-hz = /bits/ 64 <300000000>; 327 opp-peak-kBps = <(451000 * 4) (300000 * 16)>; 328 }; 329 330 opp-652800000 { 331 opp-hz = /bits/ 64 <652800000>; 332 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 333 }; 334 335 opp-768000000 { 336 opp-hz = /bits/ 64 <768000000>; 337 opp-peak-kBps = <(451000 * 4) (576000 * 16)>; 338 }; 339 340 opp-979200000 { 341 opp-hz = /bits/ 64 <979200000>; 342 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 343 }; 344 345 opp-1017600000 { 346 opp-hz = /bits/ 64 <1017600000>; 347 opp-peak-kBps = <(547000 * 4) (806400 * 16)>; 348 }; 349 350 opp-1094400000 { 351 opp-hz = /bits/ 64 <109440000>; 352 opp-peak-kBps = <(1017600 * 4) (940800 * 16)>; 353 }; 354 355 opp-1209600000 { 356 opp-hz = /bits/ 64 <1209600000>; 357 opp-peak-kBps = <(1017600 * 4) (1017600 * 16)>; 358 }; 359 360 opp-1363200000 { 361 opp-hz = /bits/ 64 <1363200000>; 362 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 363 }; 364 365 opp-1516800000 { 366 opp-hz = /bits/ 64 <1516800000>; 367 opp-peak-kBps = <(1555000 * 4) (1209600 * 16)>; 368 }; 369 370 opp-1708800000 { 371 opp-hz = /bits/ 64 <1708800000>; 372 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 373 }; 374 375 opp-1900800000 { 376 opp-hz = /bits/ 64 <1900800000>; 377 opp-peak-kBps = <(1555000 * 4) (1363200 * 16)>; 378 }; 379 }; 380 381 dummy_eud: dummy-sink { 382 compatible = "arm,coresight-dummy-sink"; 383 384 in-ports { 385 port { 386 eud_in: endpoint { 387 remote-endpoint = <&replicator_swao_out1>; 388 }; 389 }; 390 }; 391 }; 392 393 idle-states { 394 entry-method = "psci"; 395 396 little_cpu_sleep_0: cpu-sleep-0-0 { 397 compatible = "arm,idle-state"; 398 idle-state-name = "silver-power-collapse"; 399 arm,psci-suspend-param = <0x40000003>; 400 entry-latency-us = <549>; 401 exit-latency-us = <901>; 402 min-residency-us = <1774>; 403 local-timer-stop; 404 }; 405 406 little_cpu_sleep_1: cpu-sleep-0-1 { 407 compatible = "arm,idle-state"; 408 idle-state-name = "silver-rail-power-collapse"; 409 arm,psci-suspend-param = <0x40000004>; 410 entry-latency-us = <702>; 411 exit-latency-us = <915>; 412 min-residency-us = <4001>; 413 local-timer-stop; 414 }; 415 416 big_cpu_sleep_0: cpu-sleep-1-0 { 417 compatible = "arm,idle-state"; 418 idle-state-name = "gold-power-collapse"; 419 arm,psci-suspend-param = <0x40000003>; 420 entry-latency-us = <523>; 421 exit-latency-us = <1244>; 422 min-residency-us = <2207>; 423 local-timer-stop; 424 }; 425 426 big_cpu_sleep_1: cpu-sleep-1-1 { 427 compatible = "arm,idle-state"; 428 idle-state-name = "gold-rail-power-collapse"; 429 arm,psci-suspend-param = <0x40000004>; 430 entry-latency-us = <526>; 431 exit-latency-us = <1854>; 432 min-residency-us = <5555>; 433 local-timer-stop; 434 }; 435 }; 436 437 domain-idle-states { 438 cluster_sleep_0: cluster-sleep-0 { 439 compatible = "domain-idle-state"; 440 arm,psci-suspend-param = <0x41000044>; 441 entry-latency-us = <2752>; 442 exit-latency-us = <3048>; 443 min-residency-us = <6118>; 444 }; 445 446 cluster_sleep_1: cluster-sleep-1 { 447 compatible = "domain-idle-state"; 448 arm,psci-suspend-param = <0x41001344>; 449 entry-latency-us = <3263>; 450 exit-latency-us = <4562>; 451 min-residency-us = <8467>; 452 }; 453 454 cluster_sleep_2: cluster-sleep-2 { 455 compatible = "domain-idle-state"; 456 arm,psci-suspend-param = <0x4100b344>; 457 entry-latency-us = <3638>; 458 exit-latency-us = <6562>; 459 min-residency-us = <9826>; 460 }; 461 }; 462 463 memory@80000000 { 464 device_type = "memory"; 465 /* We expect the bootloader to fill in the size */ 466 reg = <0 0x80000000 0 0>; 467 }; 468 469 firmware { 470 scm { 471 compatible = "qcom,scm-qcs615", "qcom,scm"; 472 qcom,dload-mode = <&tcsr 0x13000>; 473 }; 474 }; 475 476 camnoc_virt: interconnect-0 { 477 compatible = "qcom,qcs615-camnoc-virt"; 478 #interconnect-cells = <2>; 479 qcom,bcm-voters = <&apps_bcm_voter>; 480 }; 481 482 ipa_virt: interconnect-1 { 483 compatible = "qcom,qcs615-ipa-virt"; 484 #interconnect-cells = <2>; 485 qcom,bcm-voters = <&apps_bcm_voter>; 486 }; 487 488 mc_virt: interconnect-2 { 489 compatible = "qcom,qcs615-mc-virt"; 490 #interconnect-cells = <2>; 491 qcom,bcm-voters = <&apps_bcm_voter>; 492 }; 493 494 smp2p-adsp { 495 compatible = "qcom,smp2p"; 496 qcom,smem = <443>, <429>; 497 interrupts = <GIC_SPI 172 IRQ_TYPE_EDGE_RISING>; 498 /* On this platform, bit 26 (normally SLPI) is repurposed for ADSP */ 499 mboxes = <&apss_shared 26>; 500 501 qcom,local-pid = <0>; 502 qcom,remote-pid = <2>; 503 504 adsp_smp2p_out: master-kernel { 505 qcom,entry-name = "master-kernel"; 506 #qcom,smem-state-cells = <1>; 507 }; 508 509 adsp_smp2p_in: slave-kernel { 510 qcom,entry-name = "slave-kernel"; 511 interrupt-controller; 512 #interrupt-cells = <2>; 513 }; 514 }; 515 516 smp2p-cdsp { 517 compatible = "qcom,smp2p"; 518 qcom,smem = <94>, <432>; 519 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>; 520 mboxes = <&apss_shared 6>; 521 522 qcom,local-pid = <0>; 523 qcom,remote-pid = <5>; 524 525 cdsp_smp2p_out: master-kernel { 526 qcom,entry-name = "master-kernel"; 527 #qcom,smem-state-cells = <1>; 528 }; 529 530 cdsp_smp2p_in: slave-kernel { 531 qcom,entry-name = "slave-kernel"; 532 interrupt-controller; 533 #interrupt-cells = <2>; 534 }; 535 536 }; 537 538 qup_opp_table: opp-table-qup { 539 compatible = "operating-points-v2"; 540 541 opp-75000000 { 542 opp-hz = /bits/ 64 <75000000>; 543 required-opps = <&rpmhpd_opp_low_svs>; 544 }; 545 546 opp-100000000 { 547 opp-hz = /bits/ 64 <100000000>; 548 required-opps = <&rpmhpd_opp_svs>; 549 }; 550 551 opp-128000000 { 552 opp-hz = /bits/ 64 <128000000>; 553 required-opps = <&rpmhpd_opp_nom>; 554 }; 555 }; 556 557 psci { 558 compatible = "arm,psci-1.0"; 559 method = "smc"; 560 561 cpu_pd0: power-domain-cpu0 { 562 #power-domain-cells = <0>; 563 power-domains = <&cluster_pd>; 564 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 565 }; 566 567 cpu_pd1: power-domain-cpu1 { 568 #power-domain-cells = <0>; 569 power-domains = <&cluster_pd>; 570 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 571 }; 572 573 cpu_pd2: power-domain-cpu2 { 574 #power-domain-cells = <0>; 575 power-domains = <&cluster_pd>; 576 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 577 }; 578 579 cpu_pd3: power-domain-cpu3 { 580 #power-domain-cells = <0>; 581 power-domains = <&cluster_pd>; 582 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 583 }; 584 585 cpu_pd4: power-domain-cpu4 { 586 #power-domain-cells = <0>; 587 power-domains = <&cluster_pd>; 588 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 589 }; 590 591 cpu_pd5: power-domain-cpu5 { 592 #power-domain-cells = <0>; 593 power-domains = <&cluster_pd>; 594 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 595 }; 596 597 cpu_pd6: power-domain-cpu6 { 598 #power-domain-cells = <0>; 599 power-domains = <&cluster_pd>; 600 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 601 }; 602 603 cpu_pd7: power-domain-cpu7 { 604 #power-domain-cells = <0>; 605 power-domains = <&cluster_pd>; 606 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 607 }; 608 609 cluster_pd: power-domain-cluster { 610 #power-domain-cells = <0>; 611 domain-idle-states = <&cluster_sleep_0 612 &cluster_sleep_1 613 &cluster_sleep_2>; 614 }; 615 }; 616 617 reserved-memory { 618 #address-cells = <2>; 619 #size-cells = <2>; 620 ranges; 621 622 aop_cmd_db_mem: aop-cmd-db@85f20000 { 623 compatible = "qcom,cmd-db"; 624 reg = <0x0 0x85f20000 0x0 0x20000>; 625 no-map; 626 }; 627 628 smem_region: smem@86000000 { 629 compatible = "qcom,smem"; 630 reg = <0x0 0x86000000 0x0 0x200000>; 631 no-map; 632 hwlocks = <&tcsr_mutex 3>; 633 }; 634 635 pil_video_mem: pil-video@93400000 { 636 reg = <0x0 0x93400000 0x0 0x500000>; 637 no-map; 638 }; 639 640 rproc_cdsp_mem: rproc-cdsp@93b00000 { 641 reg = <0x0 0x93b00000 0x0 0x1e00000>; 642 no-map; 643 }; 644 645 rproc_adsp_mem: rproc-adsp@95900000 { 646 reg = <0x0 0x95900000 0x0 0x1e00000>; 647 no-map; 648 }; 649 }; 650 651 soc: soc@0 { 652 compatible = "simple-bus"; 653 ranges = <0 0 0 0 0x10 0>; 654 dma-ranges = <0 0 0 0 0x10 0>; 655 #address-cells = <2>; 656 #size-cells = <2>; 657 658 gcc: clock-controller@100000 { 659 compatible = "qcom,qcs615-gcc"; 660 reg = <0 0x00100000 0 0x1f0000>; 661 clocks = <&rpmhcc RPMH_CXO_CLK>, 662 <&rpmhcc RPMH_CXO_CLK_A>, 663 <&sleep_clk>; 664 665 #clock-cells = <1>; 666 #reset-cells = <1>; 667 #power-domain-cells = <1>; 668 }; 669 670 qfprom: efuse@780000 { 671 compatible = "qcom,qcs615-qfprom", "qcom,qfprom"; 672 reg = <0x0 0x00780000 0x0 0x7000>; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 676 qusb2_hstx_trim: hstx-trim@1f8 { 677 reg = <0x1fb 0x1>; 678 bits = <1 4>; 679 }; 680 }; 681 682 rng@793000 { 683 compatible = "qcom,qcs615-trng", "qcom,trng"; 684 reg = <0x0 0x00793000 0x0 0x1000>; 685 }; 686 687 sdhc_1: mmc@7c4000 { 688 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 689 reg = <0x0 0x007c4000 0x0 0x1000>, 690 <0x0 0x007c5000 0x0 0x1000>, 691 <0x0 0x007c8000 0x0 0x8000>; 692 reg-names = "hc", 693 "cqhci", 694 "ice"; 695 696 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 698 interrupt-names = "hc_irq", 699 "pwr_irq"; 700 701 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 702 <&gcc GCC_SDCC1_APPS_CLK>, 703 <&rpmhcc RPMH_CXO_CLK>, 704 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 705 clock-names = "iface", 706 "core", 707 "xo", 708 "ice"; 709 710 resets = <&gcc GCC_SDCC1_BCR>; 711 712 power-domains = <&rpmhpd RPMHPD_CX>; 713 operating-points-v2 = <&sdhc1_opp_table>; 714 iommus = <&apps_smmu 0x02c0 0x0>; 715 interconnects = <&aggre1_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS 716 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 717 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 718 &config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 719 interconnect-names = "sdhc-ddr", 720 "cpu-sdhc"; 721 722 qcom,dll-config = <0x000f642c>; 723 qcom,ddr-config = <0x80040868>; 724 supports-cqe; 725 dma-coherent; 726 727 status = "disabled"; 728 729 sdhc1_opp_table: opp-table { 730 compatible = "operating-points-v2"; 731 732 opp-50000000 { 733 opp-hz = /bits/ 64 <50000000>; 734 required-opps = <&rpmhpd_opp_low_svs>; 735 }; 736 737 opp-100000000 { 738 opp-hz = /bits/ 64 <100000000>; 739 required-opps = <&rpmhpd_opp_svs>; 740 }; 741 742 opp-200000000 { 743 opp-hz = /bits/ 64 <200000000>; 744 required-opps = <&rpmhpd_opp_svs_l1>; 745 }; 746 747 opp-384000000 { 748 opp-hz = /bits/ 64 <384000000>; 749 required-opps = <&rpmhpd_opp_nom>; 750 }; 751 }; 752 }; 753 754 gpi_dma0: dma-controller@800000 { 755 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 756 reg = <0x0 0x800000 0x0 0x60000>; 757 #dma-cells = <3>; 758 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 766 dma-channels = <8>; 767 dma-channel-mask = <0xf>; 768 iommus = <&apps_smmu 0xd6 0x0>; 769 status = "disabled"; 770 }; 771 772 qupv3_id_0: geniqup@8c0000 { 773 compatible = "qcom,geni-se-qup"; 774 reg = <0x0 0x008c0000 0x0 0x6000>; 775 ranges; 776 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 777 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 778 clock-names = "m-ahb", 779 "s-ahb"; 780 iommus = <&apps_smmu 0xc3 0x0>; 781 #address-cells = <2>; 782 #size-cells = <2>; 783 status = "disabled"; 784 785 uart0: serial@880000 { 786 compatible = "qcom,geni-debug-uart"; 787 reg = <0x0 0x00880000 0x0 0x4000>; 788 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 789 clock-names = "se"; 790 pinctrl-0 = <&qup_uart0_tx>, <&qup_uart0_rx>; 791 pinctrl-names = "default"; 792 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 793 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 794 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 795 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 796 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 797 interconnect-names = "qup-core", 798 "qup-config"; 799 power-domains = <&rpmhpd RPMHPD_CX>; 800 operating-points-v2 = <&qup_opp_table>; 801 status = "disabled"; 802 }; 803 804 i2c1: i2c@884000 { 805 compatible = "qcom,geni-i2c"; 806 reg = <0x0 0x884000 0x0 0x4000>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 810 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 811 clock-names = "se"; 812 pinctrl-0 = <&qup_i2c1_data_clk>; 813 pinctrl-names = "default"; 814 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 815 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 816 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 817 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 818 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 819 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 820 interconnect-names = "qup-core", 821 "qup-config", 822 "qup-memory"; 823 power-domains = <&rpmhpd RPMHPD_CX>; 824 required-opps = <&rpmhpd_opp_low_svs>; 825 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 826 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 827 dma-names = "tx", 828 "rx"; 829 status = "disabled"; 830 }; 831 832 i2c2: i2c@888000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0x0 0x888000 0x0 0x4000>; 835 #address-cells = <1>; 836 #size-cells = <0>; 837 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 838 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 839 clock-names = "se"; 840 pinctrl-0 = <&qup_i2c2_data_clk>; 841 pinctrl-names = "default"; 842 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 843 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 844 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 845 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 846 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 847 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 848 interconnect-names = "qup-core", 849 "qup-config", 850 "qup-memory"; 851 power-domains = <&rpmhpd RPMHPD_CX>; 852 required-opps = <&rpmhpd_opp_low_svs>; 853 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 854 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 855 dma-names = "tx", 856 "rx"; 857 status = "disabled"; 858 }; 859 860 spi2: spi@888000 { 861 compatible = "qcom,geni-spi"; 862 reg = <0x0 0x00888000 0x0 0x4000>; 863 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 865 clock-names = "se"; 866 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 867 pinctrl-names = "default"; 868 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 869 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 870 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 871 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 872 interconnect-names = "qup-core", 873 "qup-config"; 874 power-domains = <&rpmhpd RPMHPD_CX>; 875 operating-points-v2 = <&qup_opp_table>; 876 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 877 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 878 dma-names = "tx", 879 "rx"; 880 #address-cells = <1>; 881 #size-cells = <0>; 882 status = "disabled"; 883 }; 884 885 uart2: serial@888000 { 886 compatible = "qcom,geni-uart"; 887 reg = <0x0 0x00888000 0x0 0x4000>; 888 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 889 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 890 clock-names = "se"; 891 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 892 <&qup_uart2_tx>, <&qup_uart2_rx>; 893 pinctrl-names = "default"; 894 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 895 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 896 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 897 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 898 interconnect-names = "qup-core", 899 "qup-config"; 900 power-domains = <&rpmhpd RPMHPD_CX>; 901 operating-points-v2 = <&qup_opp_table>; 902 status = "disabled"; 903 }; 904 905 i2c3: i2c@88c000 { 906 compatible = "qcom,geni-i2c"; 907 reg = <0x0 0x88c000 0x0 0x4000>; 908 #address-cells = <1>; 909 #size-cells = <0>; 910 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 911 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 912 clock-names = "se"; 913 pinctrl-0 = <&qup_i2c3_data_clk>; 914 pinctrl-names = "default"; 915 interconnects = <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 916 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 917 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 918 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 919 <&aggre1_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 920 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 921 interconnect-names = "qup-core", 922 "qup-config", 923 "qup-memory"; 924 power-domains = <&rpmhpd RPMHPD_CX>; 925 required-opps = <&rpmhpd_opp_low_svs>; 926 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 927 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 928 dma-names = "tx", 929 "rx"; 930 status = "disabled"; 931 }; 932 }; 933 934 gpi_dma1: dma-controller@a00000 { 935 compatible = "qcom,qcs615-gpi-dma", "qcom,sdm845-gpi-dma"; 936 reg = <0x0 0xa00000 0x0 0x60000>; 937 #dma-cells = <3>; 938 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 939 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 946 dma-channels = <8>; 947 dma-channel-mask = <0xf>; 948 iommus = <&apps_smmu 0x376 0x0>; 949 status = "disabled"; 950 }; 951 952 qupv3_id_1: geniqup@ac0000 { 953 compatible = "qcom,geni-se-qup"; 954 reg = <0x0 0xac0000 0x0 0x2000>; 955 ranges; 956 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 957 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 958 clock-names = "m-ahb", 959 "s-ahb"; 960 iommus = <&apps_smmu 0x363 0x0>; 961 #address-cells = <2>; 962 #size-cells = <2>; 963 status = "disabled"; 964 965 i2c4: i2c@a80000 { 966 compatible = "qcom,geni-i2c"; 967 reg = <0x0 0xa80000 0x0 0x4000>; 968 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 969 clock-names = "se"; 970 pinctrl-0 = <&qup_i2c4_data_clk>; 971 pinctrl-names = "default"; 972 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 976 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 977 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 978 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 979 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 980 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 981 interconnect-names = "qup-core", 982 "qup-config", 983 "qup-memory"; 984 power-domains = <&rpmhpd RPMHPD_CX>; 985 required-opps = <&rpmhpd_opp_low_svs>; 986 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 987 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 988 dma-names = "tx", 989 "rx"; 990 status = "disabled"; 991 }; 992 993 spi4: spi@a80000 { 994 compatible = "qcom,geni-spi"; 995 reg = <0x0 0xa80000 0x0 0x4000>; 996 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 997 clock-names = "se"; 998 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 999 pinctrl-names = "default"; 1000 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1001 #address-cells = <1>; 1002 #size-cells = <0>; 1003 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1004 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1005 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1006 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1007 interconnect-names = "qup-core", 1008 "qup-config"; 1009 power-domains = <&rpmhpd RPMHPD_CX>; 1010 operating-points-v2 = <&qup_opp_table>; 1011 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1012 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1013 dma-names = "tx", 1014 "rx"; 1015 status = "disabled"; 1016 }; 1017 1018 uart4: serial@a80000 { 1019 compatible = "qcom,geni-uart"; 1020 reg = <0x0 0xa80000 0x0 0x4000>; 1021 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1022 clock-names = "se"; 1023 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1024 <&qup_uart4_tx>, <&qup_uart4_rx>; 1025 pinctrl-names = "default"; 1026 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1027 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1028 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1029 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1030 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1031 interconnect-names = "qup-core", 1032 "qup-config"; 1033 power-domains = <&rpmhpd RPMHPD_CX>; 1034 operating-points-v2 = <&qup_opp_table>; 1035 status = "disabled"; 1036 }; 1037 1038 i2c5: i2c@a84000 { 1039 compatible = "qcom,geni-i2c"; 1040 reg = <0x0 0xa84000 0x0 0x4000>; 1041 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1042 clock-names = "se"; 1043 pinctrl-0 = <&qup_i2c5_data_clk>; 1044 pinctrl-names = "default"; 1045 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1046 #address-cells = <1>; 1047 #size-cells = <0>; 1048 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1049 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1050 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1051 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1052 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1053 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1054 interconnect-names = "qup-core", 1055 "qup-config", 1056 "qup-memory"; 1057 power-domains = <&rpmhpd RPMHPD_CX>; 1058 required-opps = <&rpmhpd_opp_low_svs>; 1059 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1060 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1061 dma-names = "tx", 1062 "rx"; 1063 status = "disabled"; 1064 }; 1065 1066 i2c6: i2c@a88000 { 1067 compatible = "qcom,geni-i2c"; 1068 reg = <0x0 0xa88000 0x0 0x4000>; 1069 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1070 clock-names = "se"; 1071 pinctrl-0 = <&qup_i2c6_data_clk>; 1072 pinctrl-names = "default"; 1073 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1077 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1078 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1079 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1080 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1081 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1082 interconnect-names = "qup-core", 1083 "qup-config", 1084 "qup-memory"; 1085 power-domains = <&rpmhpd RPMHPD_CX>; 1086 required-opps = <&rpmhpd_opp_low_svs>; 1087 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1088 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1089 dma-names = "tx", 1090 "rx"; 1091 status = "disabled"; 1092 }; 1093 1094 spi6: spi@a88000 { 1095 compatible = "qcom,geni-spi"; 1096 reg = <0x0 0xa88000 0x0 0x4000>; 1097 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1098 clock-names = "se"; 1099 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1100 pinctrl-names = "default"; 1101 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1105 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1106 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1107 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1108 interconnect-names = "qup-core", 1109 "qup-config"; 1110 power-domains = <&rpmhpd RPMHPD_CX>; 1111 operating-points-v2 = <&qup_opp_table>; 1112 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1113 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1114 dma-names = "tx", 1115 "rx"; 1116 status = "disabled"; 1117 }; 1118 1119 uart6: serial@a88000 { 1120 compatible = "qcom,geni-uart"; 1121 reg = <0x0 0xa88000 0x0 0x4000>; 1122 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1123 clock-names = "se"; 1124 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1125 <&qup_uart6_tx>, <&qup_uart6_rx>; 1126 pinctrl-names = "default"; 1127 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1128 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1129 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1130 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1131 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1132 interconnect-names = "qup-core", 1133 "qup-config"; 1134 power-domains = <&rpmhpd RPMHPD_CX>; 1135 operating-points-v2 = <&qup_opp_table>; 1136 status = "disabled"; 1137 }; 1138 1139 i2c7: i2c@a8c000 { 1140 compatible = "qcom,geni-i2c"; 1141 reg = <0x0 0xa8c000 0x0 0x4000>; 1142 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1143 clock-names = "se"; 1144 pinctrl-0 = <&qup_i2c7_data_clk>; 1145 pinctrl-names = "default"; 1146 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1147 #address-cells = <1>; 1148 #size-cells = <0>; 1149 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1150 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1151 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1152 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1153 <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1154 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1155 interconnect-names = "qup-core", 1156 "qup-config", 1157 "qup-memory"; 1158 power-domains = <&rpmhpd RPMHPD_CX>; 1159 required-opps = <&rpmhpd_opp_low_svs>; 1160 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1161 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1162 dma-names = "tx", 1163 "rx"; 1164 status = "disabled"; 1165 }; 1166 1167 spi7: spi@a8c000 { 1168 compatible = "qcom,geni-spi"; 1169 reg = <0x0 0xa8c000 0x0 0x4000>; 1170 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1171 clock-names = "se"; 1172 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1173 pinctrl-names = "default"; 1174 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1175 #address-cells = <1>; 1176 #size-cells = <0>; 1177 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1178 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1179 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1180 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1181 interconnect-names = "qup-core", 1182 "qup-config"; 1183 power-domains = <&rpmhpd RPMHPD_CX>; 1184 operating-points-v2 = <&qup_opp_table>; 1185 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1186 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1187 dma-names = "tx", 1188 "rx"; 1189 status = "disabled"; 1190 }; 1191 1192 uart7: serial@a8c000 { 1193 compatible = "qcom,geni-uart"; 1194 reg = <0x0 0xa8c000 0x0 0x4000>; 1195 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1196 clock-names = "se"; 1197 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, 1198 <&qup_uart7_tx>, <&qup_uart7_rx>; 1199 pinctrl-names = "default"; 1200 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1201 interconnects = <&aggre1_noc MASTER_BLSP_1 QCOM_ICC_TAG_ALWAYS 1202 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1203 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1204 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1205 interconnect-names = "qup-core", 1206 "qup-config"; 1207 power-domains = <&rpmhpd RPMHPD_CX>; 1208 operating-points-v2 = <&qup_opp_table>; 1209 status = "disabled"; 1210 }; 1211 }; 1212 1213 config_noc: interconnect@1500000 { 1214 reg = <0x0 0x01500000 0x0 0x5080>; 1215 compatible = "qcom,qcs615-config-noc"; 1216 #interconnect-cells = <2>; 1217 qcom,bcm-voters = <&apps_bcm_voter>; 1218 }; 1219 1220 system_noc: interconnect@1620000 { 1221 reg = <0x0 0x01620000 0x0 0x1f300>; 1222 compatible = "qcom,qcs615-system-noc"; 1223 #interconnect-cells = <2>; 1224 qcom,bcm-voters = <&apps_bcm_voter>; 1225 }; 1226 1227 aggre1_noc: interconnect@1700000 { 1228 reg = <0x0 0x01700000 0x0 0x3f200>; 1229 compatible = "qcom,qcs615-aggre1-noc"; 1230 #interconnect-cells = <2>; 1231 qcom,bcm-voters = <&apps_bcm_voter>; 1232 }; 1233 1234 mmss_noc: interconnect@1740000 { 1235 reg = <0x0 0x01740000 0x0 0x1c100>; 1236 compatible = "qcom,qcs615-mmss-noc"; 1237 #interconnect-cells = <2>; 1238 qcom,bcm-voters = <&apps_bcm_voter>; 1239 }; 1240 1241 pcie: pcie@1c08000 { 1242 device_type = "pci"; 1243 compatible = "qcom,pcie-qcs615", "qcom,pcie-sm8150"; 1244 reg = <0x0 0x01c08000 0x0 0x3000>, 1245 <0x0 0x40000000 0x0 0xf1d>, 1246 <0x0 0x40000f20 0x0 0xa8>, 1247 <0x0 0x40001000 0x0 0x1000>, 1248 <0x0 0x40100000 0x0 0x100000>, 1249 <0x0 0x01c0b000 0x0 0x1000>; 1250 reg-names = "parf", 1251 "dbi", 1252 "elbi", 1253 "atu", 1254 "config", 1255 "mhi"; 1256 #address-cells = <3>; 1257 #size-cells = <2>; 1258 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 1259 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 1260 bus-range = <0x00 0xff>; 1261 1262 dma-coherent; 1263 1264 linux,pci-domain = <0>; 1265 num-lanes = <1>; 1266 1267 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1268 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1269 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1270 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1271 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1272 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1273 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1274 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1275 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1276 interrupt-names = "msi0", 1277 "msi1", 1278 "msi2", 1279 "msi3", 1280 "msi4", 1281 "msi5", 1282 "msi6", 1283 "msi7", 1284 "global"; 1285 1286 #interrupt-cells = <1>; 1287 interrupt-map-mask = <0 0 0 0x7>; 1288 interrupt-map = <0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1289 <0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1290 <0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1291 <0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1292 1293 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 1294 <&gcc GCC_PCIE_0_AUX_CLK>, 1295 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1296 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1297 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 1298 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; 1299 clock-names = "pipe", 1300 "aux", 1301 "cfg", 1302 "bus_master", 1303 "bus_slave", 1304 "slave_q2a"; 1305 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; 1306 assigned-clock-rates = <19200000>; 1307 1308 interconnects = <&aggre1_noc MASTER_PCIE QCOM_ICC_TAG_ALWAYS 1309 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1310 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1311 &config_noc SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 1312 interconnect-names = "pcie-mem", "cpu-pcie"; 1313 1314 iommu-map = <0x0 &apps_smmu 0x400 0x1>, 1315 <0x100 &apps_smmu 0x401 0x1>; 1316 1317 resets = <&gcc GCC_PCIE_0_BCR>; 1318 reset-names = "pci"; 1319 1320 power-domains = <&gcc PCIE_0_GDSC>; 1321 1322 phys = <&pcie_phy>; 1323 phy-names = "pciephy"; 1324 1325 max-link-speed = <2>; 1326 1327 operating-points-v2 = <&pcie_opp_table>; 1328 1329 status = "disabled"; 1330 1331 pcie_opp_table: opp-table { 1332 compatible = "operating-points-v2"; 1333 1334 /* GEN 1 x1 */ 1335 opp-2500000 { 1336 opp-hz = /bits/ 64 <2500000>; 1337 required-opps = <&rpmhpd_opp_low_svs>; 1338 opp-peak-kBps = <250000 1>; 1339 }; 1340 1341 /* GEN 2 x1 */ 1342 opp-5000000 { 1343 opp-hz = /bits/ 64 <5000000>; 1344 required-opps = <&rpmhpd_opp_low_svs>; 1345 opp-peak-kBps = <500000 1>; 1346 }; 1347 }; 1348 1349 pcie_port0: pcie@0 { 1350 device_type = "pci"; 1351 reg = <0x0 0x0 0x0 0x0 0x0>; 1352 #address-cells = <3>; 1353 #size-cells = <2>; 1354 ranges; 1355 bus-range = <0x01 0xff>; 1356 }; 1357 }; 1358 1359 pcie_phy: phy@1c0e000 { 1360 compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy"; 1361 reg = <0x0 0x01c0e000 0x0 0x1000>; 1362 1363 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 1364 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1365 <&gcc GCC_PCIE_0_CLKREF_CLK>, 1366 <&gcc GCC_PCIE0_PHY_REFGEN_CLK>, 1367 <&gcc GCC_PCIE_0_PIPE_CLK>; 1368 clock-names = "aux", 1369 "cfg_ahb", 1370 "ref", 1371 "refgen", 1372 "pipe"; 1373 1374 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 1375 reset-names = "phy"; 1376 1377 assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>; 1378 assigned-clock-rates = <100000000>; 1379 1380 #clock-cells = <0>; 1381 clock-output-names = "pcie_0_pipe_clk"; 1382 1383 #phy-cells = <0>; 1384 1385 status = "disabled"; 1386 }; 1387 1388 ufs_mem_hc: ufshc@1d84000 { 1389 compatible = "qcom,qcs615-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1390 reg = <0x0 0x01d84000 0x0 0x3000>, 1391 <0x0 0x01d90000 0x0 0x8000>; 1392 reg-names = "std", 1393 "ice"; 1394 1395 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1396 1397 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 1398 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1399 <&gcc GCC_UFS_PHY_AHB_CLK>, 1400 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 1401 <&rpmhcc RPMH_CXO_CLK>, 1402 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 1403 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 1404 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 1405 clock-names = "core_clk", 1406 "bus_aggr_clk", 1407 "iface_clk", 1408 "core_clk_unipro", 1409 "ref_clk", 1410 "tx_lane0_sync_clk", 1411 "rx_lane0_sync_clk", 1412 "ice_core_clk"; 1413 1414 resets = <&gcc GCC_UFS_PHY_BCR>; 1415 reset-names = "rst"; 1416 1417 operating-points-v2 = <&ufs_opp_table>; 1418 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 1419 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 1420 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1421 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 1422 interconnect-names = "ufs-ddr", 1423 "cpu-ufs"; 1424 1425 power-domains = <&gcc UFS_PHY_GDSC>; 1426 1427 iommus = <&apps_smmu 0x300 0x0>; 1428 dma-coherent; 1429 1430 lanes-per-direction = <1>; 1431 1432 phys = <&ufs_mem_phy>; 1433 phy-names = "ufsphy"; 1434 1435 #reset-cells = <1>; 1436 1437 status = "disabled"; 1438 1439 ufs_opp_table: opp-table { 1440 compatible = "operating-points-v2"; 1441 1442 opp-50000000 { 1443 opp-hz = /bits/ 64 <50000000>, 1444 /bits/ 64 <0>, 1445 /bits/ 64 <0>, 1446 /bits/ 64 <37500000>, 1447 /bits/ 64 <0>, 1448 /bits/ 64 <0>, 1449 /bits/ 64 <0>, 1450 /bits/ 64 <75000000>; 1451 required-opps = <&rpmhpd_opp_low_svs>; 1452 }; 1453 1454 opp-100000000 { 1455 opp-hz = /bits/ 64 <100000000>, 1456 /bits/ 64 <0>, 1457 /bits/ 64 <0>, 1458 /bits/ 64 <75000000>, 1459 /bits/ 64 <0>, 1460 /bits/ 64 <0>, 1461 /bits/ 64 <0>, 1462 /bits/ 64 <150000000>; 1463 required-opps = <&rpmhpd_opp_svs>; 1464 }; 1465 1466 opp-200000000 { 1467 opp-hz = /bits/ 64 <200000000>, 1468 /bits/ 64 <0>, 1469 /bits/ 64 <0>, 1470 /bits/ 64 <150000000>, 1471 /bits/ 64 <0>, 1472 /bits/ 64 <0>, 1473 /bits/ 64 <0>, 1474 /bits/ 64 <300000000>; 1475 required-opps = <&rpmhpd_opp_nom>; 1476 }; 1477 }; 1478 }; 1479 1480 ufs_mem_phy: phy@1d87000 { 1481 compatible = "qcom,qcs615-qmp-ufs-phy", "qcom,sm6115-qmp-ufs-phy"; 1482 reg = <0x0 0x01d87000 0x0 0xe00>; 1483 clocks = <&rpmhcc RPMH_CXO_CLK>, 1484 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 1485 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 1486 clock-names = "ref", 1487 "ref_aux", 1488 "qref"; 1489 1490 power-domains = <&gcc UFS_PHY_GDSC>; 1491 1492 resets = <&ufs_mem_hc 0>; 1493 reset-names = "ufsphy"; 1494 1495 #clock-cells = <1>; 1496 #phy-cells = <0>; 1497 1498 status = "disabled"; 1499 }; 1500 1501 cryptobam: dma-controller@1dc4000 { 1502 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 1503 reg = <0x0 0x01dc4000 0x0 0x24000>; 1504 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 1505 #dma-cells = <1>; 1506 qcom,ee = <0>; 1507 qcom,controlled-remotely; 1508 num-channels = <16>; 1509 qcom,num-ees = <4>; 1510 iommus = <&apps_smmu 0x0104 0x0011>; 1511 }; 1512 1513 crypto: crypto@1dfa000 { 1514 compatible = "qcom,qcs615-qce", "qcom,sm8150-qce", "qcom,qce"; 1515 reg = <0x0 0x01dfa000 0x0 0x6000>; 1516 dmas = <&cryptobam 4>, <&cryptobam 5>; 1517 dma-names = "rx", "tx"; 1518 iommus = <&apps_smmu 0x0104 0x0011>; 1519 interconnects = <&aggre1_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 1520 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1521 interconnect-names = "memory"; 1522 }; 1523 1524 tcsr_mutex: hwlock@1f40000 { 1525 compatible = "qcom,tcsr-mutex"; 1526 reg = <0x0 0x01f40000 0x0 0x20000>; 1527 #hwlock-cells = <1>; 1528 }; 1529 1530 tcsr: syscon@1fc0000 { 1531 compatible = "qcom,qcs615-tcsr", "syscon"; 1532 reg = <0x0 0x01fc0000 0x0 0x30000>; 1533 }; 1534 1535 tlmm: pinctrl@3100000 { 1536 compatible = "qcom,qcs615-tlmm"; 1537 reg = <0x0 0x03100000 0x0 0x300000>, 1538 <0x0 0x03500000 0x0 0x300000>, 1539 <0x0 0x03d00000 0x0 0x300000>; 1540 reg-names = "east", 1541 "west", 1542 "south"; 1543 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1544 gpio-ranges = <&tlmm 0 0 124>; 1545 gpio-controller; 1546 #gpio-cells = <2>; 1547 interrupt-controller; 1548 #interrupt-cells = <2>; 1549 wakeup-parent = <&pdc>; 1550 1551 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 1552 pins = "gpio4", "gpio5"; 1553 function = "qup0"; 1554 1555 }; 1556 1557 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 1558 pins = "gpio0", "gpio1"; 1559 function = "qup0"; 1560 }; 1561 1562 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 1563 pins = "gpio18", "gpio19"; 1564 function = "qup0"; 1565 }; 1566 1567 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 1568 pins = "gpio20", "gpio21"; 1569 function = "qup1"; 1570 }; 1571 1572 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 1573 pins = "gpio14", "gpio15"; 1574 function = "qup1"; 1575 }; 1576 1577 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 1578 pins = "gpio6", "gpio7"; 1579 function = "qup1"; 1580 }; 1581 1582 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 1583 pins = "gpio10", "gpio11"; 1584 function = "qup1"; 1585 }; 1586 1587 qup_spi2_data_clk: qup-spi2-data-clk-state { 1588 pins = "gpio0", "gpio1", "gpio2"; 1589 function = "qup0"; 1590 }; 1591 1592 qup_spi2_cs: qup-spi2-cs-state { 1593 pins = "gpio3"; 1594 function = "qup0"; 1595 }; 1596 1597 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 1598 pins = "gpio3"; 1599 function = "gpio"; 1600 }; 1601 1602 qup_spi4_data_clk: qup-spi4-data-clk-state { 1603 pins = "gpio20", "gpio21", "gpio22"; 1604 function = "qup1"; 1605 }; 1606 1607 qup_spi4_cs: qup-spi4-cs-state { 1608 pins = "gpio23"; 1609 function = "qup1"; 1610 }; 1611 1612 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 1613 pins = "gpio23"; 1614 function = "gpio"; 1615 }; 1616 1617 qup_spi6_data_clk: qup-spi6-data-clk-state { 1618 pins = "gpio6", "gpio7", "gpio8"; 1619 function = "qup1"; 1620 }; 1621 1622 qup_spi6_cs: qup-spi6-cs-state { 1623 pins = "gpio9"; 1624 function = "qup1"; 1625 }; 1626 1627 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 1628 pins = "gpio9"; 1629 function = "gpio"; 1630 }; 1631 1632 qup_spi7_data_clk: qup-spi7-data-clk-state { 1633 pins = "gpio10", "gpio11", "gpio12"; 1634 function = "qup1"; 1635 }; 1636 1637 qup_spi7_cs: qup-spi7-cs-state { 1638 pins = "gpio13"; 1639 function = "qup1"; 1640 }; 1641 1642 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 1643 pins = "gpio13"; 1644 function = "gpio"; 1645 }; 1646 1647 qup_uart0_tx: qup-uart0-tx-state { 1648 pins = "gpio16"; 1649 function = "qup0"; 1650 }; 1651 1652 qup_uart0_rx: qup-uart0-rx-state { 1653 pins = "gpio17"; 1654 function = "qup0"; 1655 }; 1656 1657 qup_uart2_cts: qup-uart2-cts-state { 1658 pins = "gpio0"; 1659 function = "qup0"; 1660 }; 1661 1662 qup_uart2_rts: qup-uart2-rts-state { 1663 pins = "gpio1"; 1664 function = "qup0"; 1665 }; 1666 1667 qup_uart2_tx: qup-uart2-tx-state { 1668 pins = "gpio2"; 1669 function = "qup0"; 1670 }; 1671 1672 qup_uart2_rx: qup-uart2-rx-state { 1673 pins = "gpio3"; 1674 function = "qup0"; 1675 }; 1676 1677 qup_uart4_cts: qup-uart4-cts-state { 1678 pins = "gpio20"; 1679 function = "qup1"; 1680 }; 1681 1682 qup_uart4_rts: qup-uart4-rts-state { 1683 pins = "gpio21"; 1684 function = "qup1"; 1685 }; 1686 1687 qup_uart4_tx: qup-uart4-tx-state { 1688 pins = "gpio22"; 1689 function = "qup1"; 1690 }; 1691 1692 qup_uart4_rx: qup-uart4-rx-state { 1693 pins = "gpio23"; 1694 function = "qup1"; 1695 }; 1696 1697 qup_uart6_cts: qup-uart6-cts-state { 1698 pins = "gpio6"; 1699 function = "qup1"; 1700 }; 1701 1702 qup_uart6_rts: qup-uart6-rts-state { 1703 pins = "gpio7"; 1704 function = "qup1"; 1705 }; 1706 1707 qup_uart6_tx: qup-uart6-tx-state { 1708 pins = "gpio8"; 1709 function = "qup1"; 1710 }; 1711 1712 qup_uart6_rx: qup-uart6-rx-state { 1713 pins = "gpio9"; 1714 function = "qup1"; 1715 }; 1716 1717 qup_uart7_cts: qup-uart7-cts-state { 1718 pins = "gpio10"; 1719 function = "qup1"; 1720 }; 1721 1722 qup_uart7_rts: qup-uart7-rts-state { 1723 pins = "gpio11"; 1724 function = "qup1"; 1725 }; 1726 1727 qup_uart7_tx: qup-uart7-tx-state { 1728 pins = "gpio12"; 1729 function = "qup1"; 1730 }; 1731 1732 qup_uart7_rx: qup-uart7-rx-state { 1733 pins = "gpio13"; 1734 function = "qup1"; 1735 }; 1736 1737 sdc1_state_on: sdc1-on-state { 1738 clk-pins { 1739 pins = "sdc1_clk"; 1740 bias-disable; 1741 drive-strength = <16>; 1742 }; 1743 1744 cmd-pins { 1745 pins = "sdc1_cmd"; 1746 bias-pull-up; 1747 drive-strength = <10>; 1748 }; 1749 1750 data-pins { 1751 pins = "sdc1_data"; 1752 bias-pull-up; 1753 drive-strength = <10>; 1754 }; 1755 1756 rclk-pins { 1757 pins = "sdc1_rclk"; 1758 bias-pull-down; 1759 }; 1760 }; 1761 1762 sdc1_state_off: sdc1-off-state { 1763 clk-pins { 1764 pins = "sdc1_clk"; 1765 bias-disable; 1766 drive-strength = <2>; 1767 }; 1768 1769 cmd-pins { 1770 pins = "sdc1_cmd"; 1771 bias-pull-up; 1772 drive-strength = <2>; 1773 }; 1774 1775 data-pins { 1776 pins = "sdc1_data"; 1777 bias-pull-up; 1778 drive-strength = <2>; 1779 }; 1780 1781 rclk-pins { 1782 pins = "sdc1_rclk"; 1783 bias-pull-down; 1784 }; 1785 }; 1786 1787 sdc2_state_on: sdc2-on-state { 1788 clk-pins { 1789 pins = "sdc2_clk"; 1790 bias-disable; 1791 drive-strength = <16>; 1792 }; 1793 1794 cmd-pins { 1795 pins = "sdc2_cmd"; 1796 bias-pull-up; 1797 drive-strength = <10>; 1798 }; 1799 1800 data-pins { 1801 pins = "sdc2_data"; 1802 bias-pull-up; 1803 drive-strength = <10>; 1804 }; 1805 }; 1806 1807 sdc2_state_off: sdc2-off-state { 1808 clk-pins { 1809 pins = "sdc2_clk"; 1810 bias-disable; 1811 drive-strength = <2>; 1812 }; 1813 1814 cmd-pins { 1815 pins = "sdc2_cmd"; 1816 bias-pull-up; 1817 drive-strength = <2>; 1818 }; 1819 1820 data-pins { 1821 pins = "sdc2_data"; 1822 bias-pull-up; 1823 drive-strength = <2>; 1824 }; 1825 }; 1826 }; 1827 1828 gpucc: clock-controller@5090000 { 1829 compatible = "qcom,qcs615-gpucc"; 1830 reg = <0 0x05090000 0 0x9000>; 1831 1832 clocks = <&rpmhcc RPMH_CXO_CLK>, 1833 <&gcc GPLL0>, 1834 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1835 1836 #clock-cells = <1>; 1837 #reset-cells = <1>; 1838 #power-domain-cells = <1>; 1839 }; 1840 1841 stm@6002000 { 1842 compatible = "arm,coresight-stm", "arm,primecell"; 1843 reg = <0x0 0x06002000 0x0 0x1000>, 1844 <0x0 0x16280000 0x0 0x180000>; 1845 reg-names = "stm-base", 1846 "stm-stimulus-base"; 1847 1848 clocks = <&aoss_qmp>; 1849 clock-names = "apb_pclk"; 1850 1851 out-ports { 1852 port { 1853 stm_out: endpoint { 1854 remote-endpoint = <&funnel_in0_in7>; 1855 }; 1856 }; 1857 }; 1858 }; 1859 1860 tpda@6004000 { 1861 compatible = "qcom,coresight-tpda", "arm,primecell"; 1862 reg = <0x0 0x06004000 0x0 0x1000>; 1863 1864 clocks = <&aoss_qmp>; 1865 clock-names = "apb_pclk"; 1866 1867 in-ports { 1868 #address-cells = <1>; 1869 #size-cells = <0>; 1870 1871 port@0 { 1872 reg = <0>; 1873 1874 tpda_qdss_in0: endpoint { 1875 remote-endpoint = <&tpdm_center_out>; 1876 }; 1877 }; 1878 1879 port@4 { 1880 reg = <4>; 1881 1882 tpda_qdss_in4: endpoint { 1883 remote-endpoint = <&funnel_monaq_out>; 1884 }; 1885 }; 1886 1887 port@5 { 1888 reg = <5>; 1889 1890 tpda_qdss_in5: endpoint { 1891 remote-endpoint = <&funnel_ddr_0_out>; 1892 }; 1893 }; 1894 1895 port@6 { 1896 reg = <6>; 1897 1898 tpda_qdss_in6: endpoint { 1899 remote-endpoint = <&funnel_turing_out>; 1900 }; 1901 }; 1902 1903 port@7 { 1904 reg = <7>; 1905 1906 tpda_qdss_in7: endpoint { 1907 remote-endpoint = <&tpdm_vsense_out>; 1908 }; 1909 }; 1910 1911 port@8 { 1912 reg = <8>; 1913 1914 tpda_qdss_in8: endpoint { 1915 remote-endpoint = <&tpdm_dcc_out>; 1916 }; 1917 }; 1918 1919 port@9 { 1920 reg = <9>; 1921 1922 tpda_qdss_in9: endpoint { 1923 remote-endpoint = <&tpdm_prng_out>; 1924 }; 1925 }; 1926 1927 port@b { 1928 reg = <11>; 1929 1930 tpda_qdss_in11: endpoint { 1931 remote-endpoint = <&tpdm_qm_out>; 1932 }; 1933 }; 1934 1935 port@c { 1936 reg = <12>; 1937 1938 tpda_qdss_in12: endpoint { 1939 remote-endpoint = <&tpdm_west_out>; 1940 }; 1941 }; 1942 1943 port@d { 1944 reg = <13>; 1945 1946 tpda_qdss_in13: endpoint { 1947 remote-endpoint = <&tpdm_pimem_out>; 1948 }; 1949 }; 1950 }; 1951 1952 out-ports { 1953 port { 1954 tpda_qdss_out: endpoint { 1955 remote-endpoint = <&funnel_qatb_in>; 1956 }; 1957 }; 1958 }; 1959 }; 1960 1961 funnel@6005000 { 1962 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1963 reg = <0x0 0x06005000 0x0 0x1000>; 1964 1965 clocks = <&aoss_qmp>; 1966 clock-names = "apb_pclk"; 1967 1968 in-ports { 1969 port { 1970 funnel_qatb_in: endpoint { 1971 remote-endpoint = <&tpda_qdss_out>; 1972 }; 1973 }; 1974 }; 1975 1976 out-ports { 1977 port { 1978 funnel_qatb_out: endpoint { 1979 remote-endpoint = <&funnel_in0_in6>; 1980 }; 1981 }; 1982 }; 1983 }; 1984 1985 cti@6010000 { 1986 compatible = "arm,coresight-cti", "arm,primecell"; 1987 reg = <0x0 0x06010000 0x0 0x1000>; 1988 1989 clocks = <&aoss_qmp>; 1990 clock-names = "apb_pclk"; 1991 }; 1992 1993 cti@6011000 { 1994 compatible = "arm,coresight-cti", "arm,primecell"; 1995 reg = <0x0 0x06011000 0x0 0x1000>; 1996 1997 clocks = <&aoss_qmp>; 1998 clock-names = "apb_pclk"; 1999 }; 2000 2001 cti@6012000 { 2002 compatible = "arm,coresight-cti", "arm,primecell"; 2003 reg = <0x0 0x06012000 0x0 0x1000>; 2004 2005 clocks = <&aoss_qmp>; 2006 clock-names = "apb_pclk"; 2007 }; 2008 2009 cti@6013000 { 2010 compatible = "arm,coresight-cti", "arm,primecell"; 2011 reg = <0x0 0x06013000 0x0 0x1000>; 2012 2013 clocks = <&aoss_qmp>; 2014 clock-names = "apb_pclk"; 2015 }; 2016 2017 cti@6014000 { 2018 compatible = "arm,coresight-cti", "arm,primecell"; 2019 reg = <0x0 0x06014000 0x0 0x1000>; 2020 2021 clocks = <&aoss_qmp>; 2022 clock-names = "apb_pclk"; 2023 }; 2024 2025 cti@6015000 { 2026 compatible = "arm,coresight-cti", "arm,primecell"; 2027 reg = <0x0 0x06015000 0x0 0x1000>; 2028 2029 clocks = <&aoss_qmp>; 2030 clock-names = "apb_pclk"; 2031 }; 2032 2033 cti@6016000 { 2034 compatible = "arm,coresight-cti", "arm,primecell"; 2035 reg = <0x0 0x06016000 0x0 0x1000>; 2036 2037 clocks = <&aoss_qmp>; 2038 clock-names = "apb_pclk"; 2039 }; 2040 2041 cti@6017000 { 2042 compatible = "arm,coresight-cti", "arm,primecell"; 2043 reg = <0x0 0x06017000 0x0 0x1000>; 2044 2045 clocks = <&aoss_qmp>; 2046 clock-names = "apb_pclk"; 2047 }; 2048 2049 cti@6018000 { 2050 compatible = "arm,coresight-cti", "arm,primecell"; 2051 reg = <0x0 0x06018000 0x0 0x1000>; 2052 2053 clocks = <&aoss_qmp>; 2054 clock-names = "apb_pclk"; 2055 }; 2056 2057 cti@6019000 { 2058 compatible = "arm,coresight-cti", "arm,primecell"; 2059 reg = <0x0 0x06019000 0x0 0x1000>; 2060 2061 clocks = <&aoss_qmp>; 2062 clock-names = "apb_pclk"; 2063 }; 2064 2065 cti@601a000 { 2066 compatible = "arm,coresight-cti", "arm,primecell"; 2067 reg = <0x0 0x0601a000 0x0 0x1000>; 2068 2069 clocks = <&aoss_qmp>; 2070 clock-names = "apb_pclk"; 2071 }; 2072 2073 cti@601b000 { 2074 compatible = "arm,coresight-cti", "arm,primecell"; 2075 reg = <0x0 0x0601b000 0x0 0x1000>; 2076 2077 clocks = <&aoss_qmp>; 2078 clock-names = "apb_pclk"; 2079 }; 2080 2081 cti@601c000 { 2082 compatible = "arm,coresight-cti", "arm,primecell"; 2083 reg = <0x0 0x0601c000 0x0 0x1000>; 2084 2085 clocks = <&aoss_qmp>; 2086 clock-names = "apb_pclk"; 2087 }; 2088 2089 cti@601d000 { 2090 compatible = "arm,coresight-cti", "arm,primecell"; 2091 reg = <0x0 0x0601d000 0x0 0x1000>; 2092 2093 clocks = <&aoss_qmp>; 2094 clock-names = "apb_pclk"; 2095 }; 2096 2097 cti@601e000 { 2098 compatible = "arm,coresight-cti", "arm,primecell"; 2099 reg = <0x0 0x0601e000 0x0 0x1000>; 2100 2101 clocks = <&aoss_qmp>; 2102 clock-names = "apb_pclk"; 2103 }; 2104 2105 cti@601f000 { 2106 compatible = "arm,coresight-cti", "arm,primecell"; 2107 reg = <0x0 0x0601f000 0x0 0x1000>; 2108 2109 clocks = <&aoss_qmp>; 2110 clock-names = "apb_pclk"; 2111 }; 2112 2113 funnel@6041000 { 2114 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2115 reg = <0x0 0x06041000 0x0 0x1000>; 2116 2117 clocks = <&aoss_qmp>; 2118 clock-names = "apb_pclk"; 2119 2120 in-ports { 2121 #address-cells = <1>; 2122 #size-cells = <0>; 2123 2124 port@6 { 2125 reg = <6>; 2126 2127 funnel_in0_in6: endpoint { 2128 remote-endpoint = <&funnel_qatb_out>; 2129 }; 2130 }; 2131 2132 port@7 { 2133 reg = <7>; 2134 2135 funnel_in0_in7: endpoint { 2136 remote-endpoint = <&stm_out>; 2137 }; 2138 }; 2139 }; 2140 2141 out-ports { 2142 port { 2143 funnel_in0_out: endpoint { 2144 remote-endpoint = <&funnel_merg_in0>; 2145 }; 2146 }; 2147 }; 2148 }; 2149 2150 funnel@6042000 { 2151 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2152 reg = <0x0 0x06042000 0x0 0x1000>; 2153 2154 clocks = <&aoss_qmp>; 2155 clock-names = "apb_pclk"; 2156 2157 in-ports { 2158 #address-cells = <1>; 2159 #size-cells = <0>; 2160 2161 port@3 { 2162 reg = <3>; 2163 2164 funnel_in1_in3: endpoint { 2165 remote-endpoint = <&replicator_swao_out0>; 2166 }; 2167 }; 2168 2169 port@4 { 2170 reg = <4>; 2171 2172 funnel_in1_in4: endpoint { 2173 remote-endpoint = <&tpdm_wcss_out>; 2174 }; 2175 }; 2176 2177 port@7 { 2178 reg = <7>; 2179 2180 funnel_in1_in7: endpoint { 2181 remote-endpoint = <&funnel_apss_merg_out>; 2182 }; 2183 }; 2184 }; 2185 2186 out-ports { 2187 port { 2188 funnel_in1_out: endpoint { 2189 remote-endpoint = <&funnel_merg_in1>; 2190 }; 2191 }; 2192 }; 2193 }; 2194 2195 funnel@6045000 { 2196 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2197 reg = <0x0 0x06045000 0x0 0x1000>; 2198 2199 clocks = <&aoss_qmp>; 2200 clock-names = "apb_pclk"; 2201 2202 in-ports { 2203 #address-cells = <1>; 2204 #size-cells = <0>; 2205 2206 port@0 { 2207 reg = <0>; 2208 2209 funnel_merg_in0: endpoint { 2210 remote-endpoint = <&funnel_in0_out>; 2211 }; 2212 }; 2213 2214 port@1 { 2215 reg = <1>; 2216 2217 funnel_merg_in1: endpoint { 2218 remote-endpoint = <&funnel_in1_out>; 2219 }; 2220 }; 2221 }; 2222 2223 out-ports { 2224 port { 2225 funnel_merg_out: endpoint { 2226 remote-endpoint = <&tmc_etf_in>; 2227 }; 2228 }; 2229 }; 2230 }; 2231 2232 replicator@6046000 { 2233 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2234 reg = <0x0 0x06046000 0x0 0x1000>; 2235 2236 clocks = <&aoss_qmp>; 2237 clock-names = "apb_pclk"; 2238 2239 in-ports { 2240 port { 2241 replicator0_in: endpoint { 2242 remote-endpoint = <&tmc_etf_out>; 2243 }; 2244 }; 2245 }; 2246 2247 out-ports { 2248 #address-cells = <1>; 2249 #size-cells = <0>; 2250 2251 port@1 { 2252 reg = <1>; 2253 2254 replicator0_out1: endpoint { 2255 remote-endpoint = <&replicator1_in>; 2256 }; 2257 }; 2258 }; 2259 }; 2260 2261 tmc@6047000 { 2262 compatible = "arm,coresight-tmc", "arm,primecell"; 2263 reg = <0x0 0x06047000 0x0 0x1000>; 2264 2265 clocks = <&aoss_qmp>; 2266 clock-names = "apb_pclk"; 2267 2268 in-ports { 2269 port { 2270 tmc_etf_in: endpoint { 2271 remote-endpoint = <&funnel_merg_out>; 2272 }; 2273 }; 2274 }; 2275 2276 out-ports { 2277 port { 2278 tmc_etf_out: endpoint { 2279 remote-endpoint = <&replicator0_in>; 2280 }; 2281 }; 2282 }; 2283 }; 2284 2285 replicator@604a000 { 2286 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2287 reg = <0x0 0x0604a000 0x0 0x1000>; 2288 2289 clocks = <&aoss_qmp>; 2290 clock-names = "apb_pclk"; 2291 status = "disabled"; 2292 2293 in-ports { 2294 port { 2295 replicator1_in: endpoint { 2296 remote-endpoint = <&replicator0_out1>; 2297 }; 2298 }; 2299 }; 2300 2301 out-ports { 2302 port { 2303 replicator1_out: endpoint { 2304 remote-endpoint = <&funnel_swao_in6>; 2305 }; 2306 }; 2307 }; 2308 }; 2309 2310 cti@683b000 { 2311 compatible = "arm,coresight-cti", "arm,primecell"; 2312 reg = <0x0 0x0683b000 0x0 0x1000>; 2313 2314 clocks = <&aoss_qmp>; 2315 clock-names = "apb_pclk"; 2316 }; 2317 2318 tpdm@6840000 { 2319 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2320 reg = <0x0 0x06840000 0x0 0x1000>; 2321 2322 clocks = <&aoss_qmp>; 2323 clock-names = "apb_pclk"; 2324 2325 qcom,cmb-element-bits = <64>; 2326 qcom,cmb-msrs-num = <32>; 2327 status = "disabled"; 2328 2329 out-ports { 2330 port { 2331 tpdm_vsense_out: endpoint { 2332 remote-endpoint = <&tpda_qdss_in7>; 2333 }; 2334 }; 2335 }; 2336 }; 2337 2338 tpdm@684c000 { 2339 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2340 reg = <0x0 0x0684c000 0x0 0x1000>; 2341 2342 clocks = <&aoss_qmp>; 2343 clock-names = "apb_pclk"; 2344 2345 qcom,cmb-element-bits = <32>; 2346 qcom,cmb-msrs-num = <32>; 2347 2348 out-ports { 2349 port { 2350 tpdm_prng_out: endpoint { 2351 remote-endpoint = <&tpda_qdss_in9>; 2352 }; 2353 }; 2354 }; 2355 }; 2356 2357 tpdm@6850000 { 2358 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2359 reg = <0x0 0x06850000 0x0 0x1000>; 2360 2361 clocks = <&aoss_qmp>; 2362 clock-names = "apb_pclk"; 2363 2364 qcom,cmb-element-bits = <64>; 2365 qcom,cmb-msrs-num = <32>; 2366 qcom,dsb-element-bits = <32>; 2367 qcom,dsb-msrs-num = <32>; 2368 2369 out-ports { 2370 port { 2371 tpdm_pimem_out: endpoint { 2372 remote-endpoint = <&tpda_qdss_in13>; 2373 }; 2374 }; 2375 }; 2376 }; 2377 2378 tpdm@6860000 { 2379 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2380 reg = <0x0 0x06860000 0x0 0x1000>; 2381 2382 clocks = <&aoss_qmp>; 2383 clock-names = "apb_pclk"; 2384 2385 qcom,dsb-element-bits = <32>; 2386 qcom,dsb-msrs-num = <32>; 2387 2388 out-ports { 2389 port { 2390 tpdm_turing_out: endpoint { 2391 remote-endpoint = <&funnel_turing_in>; 2392 }; 2393 }; 2394 }; 2395 }; 2396 2397 funnel@6861000 { 2398 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2399 reg = <0x0 0x06861000 0x0 0x1000>; 2400 2401 clocks = <&aoss_qmp>; 2402 clock-names = "apb_pclk"; 2403 2404 in-ports { 2405 port { 2406 funnel_turing_in: endpoint { 2407 remote-endpoint = <&tpdm_turing_out>; 2408 }; 2409 }; 2410 }; 2411 2412 out-ports { 2413 port { 2414 funnel_turing_out: endpoint { 2415 remote-endpoint = <&tpda_qdss_in6>; 2416 }; 2417 }; 2418 }; 2419 }; 2420 2421 cti@6867000 { 2422 compatible = "arm,coresight-cti", "arm,primecell"; 2423 reg = <0x0 0x06867000 0x0 0x1000>; 2424 2425 clocks = <&aoss_qmp>; 2426 clock-names = "apb_pclk"; 2427 }; 2428 2429 tpdm@6870000 { 2430 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2431 reg = <0x0 0x06870000 0x0 0x1000>; 2432 2433 clocks = <&aoss_qmp>; 2434 clock-names = "apb_pclk"; 2435 2436 qcom,cmb-element-bits = <32>; 2437 qcom,cmb-msrs-num = <32>; 2438 status = "disabled"; 2439 2440 out-ports { 2441 port { 2442 tpdm_dcc_out: endpoint { 2443 remote-endpoint = <&tpda_qdss_in8>; 2444 }; 2445 }; 2446 }; 2447 }; 2448 2449 tpdm@699c000 { 2450 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2451 reg = <0x0 0x0699c000 0x0 0x1000>; 2452 2453 clocks = <&aoss_qmp>; 2454 clock-names = "apb_pclk"; 2455 2456 qcom,cmb-element-bits = <32>; 2457 qcom,cmb-msrs-num = <32>; 2458 qcom,dsb-element-bits = <32>; 2459 qcom,dsb-msrs-num = <32>; 2460 status = "disabled"; 2461 2462 out-ports { 2463 port { 2464 tpdm_wcss_out: endpoint { 2465 remote-endpoint = <&funnel_in1_in4>; 2466 }; 2467 }; 2468 }; 2469 }; 2470 2471 tpdm@69c0000 { 2472 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2473 reg = <0x0 0x069c0000 0x0 0x1000>; 2474 2475 clocks = <&aoss_qmp>; 2476 clock-names = "apb_pclk"; 2477 2478 qcom,dsb-element-bits = <32>; 2479 qcom,dsb-msrs-num = <32>; 2480 2481 out-ports { 2482 port { 2483 tpdm_monaq_out: endpoint { 2484 remote-endpoint = <&funnel_monaq_in>; 2485 }; 2486 }; 2487 }; 2488 }; 2489 2490 funnel@69c3000 { 2491 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2492 reg = <0x0 0x069c3000 0x0 0x1000>; 2493 2494 clocks = <&aoss_qmp>; 2495 clock-names = "apb_pclk"; 2496 2497 in-ports { 2498 port { 2499 funnel_monaq_in: endpoint { 2500 remote-endpoint = <&tpdm_monaq_out>; 2501 }; 2502 }; 2503 }; 2504 2505 out-ports { 2506 port { 2507 funnel_monaq_out: endpoint { 2508 remote-endpoint = <&tpda_qdss_in4>; 2509 }; 2510 }; 2511 }; 2512 }; 2513 2514 tpdm@69d0000 { 2515 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2516 reg = <0x0 0x069d0000 0x0 0x1000>; 2517 2518 clocks = <&aoss_qmp>; 2519 clock-names = "apb_pclk"; 2520 2521 qcom,dsb-element-bits = <32>; 2522 qcom,dsb-msrs-num = <32>; 2523 status = "disabled"; 2524 2525 out-ports { 2526 port { 2527 tpdm_qm_out: endpoint { 2528 remote-endpoint = <&tpda_qdss_in11>; 2529 }; 2530 }; 2531 }; 2532 }; 2533 2534 tpdm@6a00000 { 2535 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2536 reg = <0x0 0x06a00000 0x0 0x1000>; 2537 2538 clocks = <&aoss_qmp>; 2539 clock-names = "apb_pclk"; 2540 2541 qcom,dsb-element-bits = <32>; 2542 qcom,dsb-msrs-num = <32>; 2543 status = "disabled"; 2544 2545 out-ports { 2546 port { 2547 tpdm_ddr_out: endpoint { 2548 remote-endpoint = <&funnel_ddr_0_in>; 2549 }; 2550 }; 2551 }; 2552 }; 2553 2554 cti@6a02000 { 2555 compatible = "arm,coresight-cti", "arm,primecell"; 2556 reg = <0x0 0x06a02000 0x0 0x1000>; 2557 2558 clocks = <&aoss_qmp>; 2559 clock-names = "apb_pclk"; 2560 }; 2561 2562 cti@6a03000 { 2563 compatible = "arm,coresight-cti", "arm,primecell"; 2564 reg = <0x0 0x06a03000 0x0 0x1000>; 2565 2566 clocks = <&aoss_qmp>; 2567 clock-names = "apb_pclk"; 2568 }; 2569 2570 cti@6a10000 { 2571 compatible = "arm,coresight-cti", "arm,primecell"; 2572 reg = <0x0 0x06a10000 0x0 0x1000>; 2573 2574 clocks = <&aoss_qmp>; 2575 clock-names = "apb_pclk"; 2576 }; 2577 2578 cti@6a11000 { 2579 compatible = "arm,coresight-cti", "arm,primecell"; 2580 reg = <0x0 0x06a11000 0x0 0x1000>; 2581 2582 clocks = <&aoss_qmp>; 2583 clock-names = "apb_pclk"; 2584 }; 2585 2586 funnel@6a05000 { 2587 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2588 reg = <0x0 0x06a05000 0x0 0x1000>; 2589 2590 clocks = <&aoss_qmp>; 2591 clock-names = "apb_pclk"; 2592 2593 in-ports { 2594 port { 2595 funnel_ddr_0_in: endpoint { 2596 remote-endpoint = <&tpdm_ddr_out>; 2597 }; 2598 }; 2599 }; 2600 2601 out-ports { 2602 port { 2603 funnel_ddr_0_out: endpoint { 2604 remote-endpoint = <&tpda_qdss_in5>; 2605 }; 2606 }; 2607 }; 2608 }; 2609 2610 tpda@6b01000 { 2611 compatible = "qcom,coresight-tpda", "arm,primecell"; 2612 reg = <0x0 0x06b01000 0x0 0x1000>; 2613 2614 clocks = <&aoss_qmp>; 2615 clock-names = "apb_pclk"; 2616 2617 in-ports { 2618 #address-cells = <1>; 2619 #size-cells = <0>; 2620 2621 port@0 { 2622 reg = <0>; 2623 2624 tpda_swao_in0: endpoint { 2625 remote-endpoint = <&tpdm_swao0_out>; 2626 }; 2627 }; 2628 2629 port@1 { 2630 reg = <1>; 2631 2632 tpda_swao_in1: endpoint { 2633 remote-endpoint = <&tpdm_swao1_out>; 2634 }; 2635 2636 }; 2637 }; 2638 2639 out-ports { 2640 port { 2641 tpda_swao_out: endpoint { 2642 remote-endpoint = <&funnel_swao_in7>; 2643 }; 2644 }; 2645 }; 2646 }; 2647 2648 tpdm@6b02000 { 2649 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2650 reg = <0x0 0x06b02000 0x0 0x1000>; 2651 2652 clocks = <&aoss_qmp>; 2653 clock-names = "apb_pclk"; 2654 2655 qcom,cmb-element-bits = <64>; 2656 qcom,cmb-msrs-num = <32>; 2657 status = "disabled"; 2658 2659 out-ports { 2660 port { 2661 tpdm_swao0_out: endpoint { 2662 remote-endpoint = <&tpda_swao_in0>; 2663 }; 2664 }; 2665 }; 2666 }; 2667 2668 tpdm@6b03000 { 2669 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2670 reg = <0x0 0x06b03000 0x0 0x1000>; 2671 2672 clocks = <&aoss_qmp>; 2673 clock-names = "apb_pclk"; 2674 2675 qcom,dsb-element-bits = <32>; 2676 qcom,dsb-msrs-num = <32>; 2677 status = "disabled"; 2678 2679 out-ports { 2680 port { 2681 tpdm_swao1_out: endpoint { 2682 remote-endpoint = <&tpda_swao_in1>; 2683 }; 2684 }; 2685 }; 2686 }; 2687 2688 cti@6b04000 { 2689 compatible = "arm,coresight-cti", "arm,primecell"; 2690 reg = <0x0 0x06b04000 0x0 0x1000>; 2691 2692 clocks = <&aoss_qmp>; 2693 clock-names = "apb_pclk"; 2694 }; 2695 2696 cti@6b05000 { 2697 compatible = "arm,coresight-cti", "arm,primecell"; 2698 reg = <0x0 0x06b05000 0x0 0x1000>; 2699 2700 clocks = <&aoss_qmp>; 2701 clock-names = "apb_pclk"; 2702 }; 2703 2704 cti@6b06000 { 2705 compatible = "arm,coresight-cti", "arm,primecell"; 2706 reg = <0x0 0x06b06000 0x0 0x1000>; 2707 2708 clocks = <&aoss_qmp>; 2709 clock-names = "apb_pclk"; 2710 }; 2711 2712 cti@6b07000 { 2713 compatible = "arm,coresight-cti", "arm,primecell"; 2714 reg = <0x0 0x06b07000 0x0 0x1000>; 2715 2716 clocks = <&aoss_qmp>; 2717 clock-names = "apb_pclk"; 2718 }; 2719 2720 funnel@6b08000 { 2721 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2722 reg = <0x0 0x06b08000 0x0 0x1000>; 2723 2724 clocks = <&aoss_qmp>; 2725 clock-names = "apb_pclk"; 2726 2727 in-ports { 2728 #address-cells = <1>; 2729 #size-cells = <0>; 2730 2731 port@6 { 2732 reg = <6>; 2733 2734 funnel_swao_in6: endpoint { 2735 remote-endpoint = <&replicator1_out>; 2736 }; 2737 }; 2738 2739 port@7 { 2740 reg = <7>; 2741 2742 funnel_swao_in7: endpoint { 2743 remote-endpoint = <&tpda_swao_out>; 2744 }; 2745 }; 2746 }; 2747 2748 out-ports { 2749 port { 2750 funnel_swao_out: endpoint { 2751 remote-endpoint = <&tmc_etf_swao_in>; 2752 }; 2753 }; 2754 }; 2755 }; 2756 2757 tmc@6b09000 { 2758 compatible = "arm,coresight-tmc", "arm,primecell"; 2759 reg = <0x0 0x06b09000 0x0 0x1000>; 2760 2761 clocks = <&aoss_qmp>; 2762 clock-names = "apb_pclk"; 2763 2764 in-ports { 2765 port { 2766 tmc_etf_swao_in: endpoint { 2767 remote-endpoint = <&funnel_swao_out>; 2768 }; 2769 }; 2770 }; 2771 2772 out-ports { 2773 port { 2774 tmc_etf_swao_out: endpoint { 2775 remote-endpoint = <&replicator_swao_in>; 2776 }; 2777 }; 2778 }; 2779 }; 2780 2781 replicator@6b0a000 { 2782 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 2783 reg = <0x0 0x06b0a000 0x0 0x1000>; 2784 2785 clocks = <&aoss_qmp>; 2786 clock-names = "apb_pclk"; 2787 2788 in-ports { 2789 port { 2790 replicator_swao_in: endpoint { 2791 remote-endpoint = <&tmc_etf_swao_out>; 2792 }; 2793 }; 2794 }; 2795 2796 out-ports { 2797 #address-cells = <1>; 2798 #size-cells = <0>; 2799 2800 port@0 { 2801 reg = <0>; 2802 2803 replicator_swao_out0: endpoint { 2804 remote-endpoint = <&funnel_in1_in3>; 2805 }; 2806 }; 2807 2808 port@1 { 2809 reg = <1>; 2810 2811 replicator_swao_out1: endpoint { 2812 remote-endpoint = <&eud_in>; 2813 }; 2814 }; 2815 }; 2816 }; 2817 2818 cti@6b21000 { 2819 compatible = "arm,coresight-cti", "arm,primecell"; 2820 reg = <0x0 0x06b21000 0x0 0x1000>; 2821 2822 clocks = <&aoss_qmp>; 2823 clock-names = "apb_pclk"; 2824 }; 2825 2826 tpdm@6b48000 { 2827 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2828 reg = <0x0 0x06b48000 0x0 0x1000>; 2829 2830 clocks = <&aoss_qmp>; 2831 clock-names = "apb_pclk"; 2832 2833 qcom,dsb-element-bits = <32>; 2834 qcom,dsb-msrs-num = <32>; 2835 2836 out-ports { 2837 port { 2838 tpdm_west_out: endpoint { 2839 remote-endpoint = <&tpda_qdss_in12>; 2840 }; 2841 }; 2842 }; 2843 }; 2844 2845 cti@6c13000 { 2846 compatible = "arm,coresight-cti", "arm,primecell"; 2847 reg = <0x0 0x06c13000 0x0 0x1000>; 2848 2849 clocks = <&aoss_qmp>; 2850 clock-names = "apb_pclk"; 2851 2852 /* Not all required clocks can be enabled from the OS */ 2853 status = "fail"; 2854 }; 2855 2856 cti@6c20000 { 2857 compatible = "arm,coresight-cti", "arm,primecell"; 2858 reg = <0x0 0x06c20000 0x0 0x1000>; 2859 2860 clocks = <&aoss_qmp>; 2861 clock-names = "apb_pclk"; 2862 status = "disabled"; 2863 }; 2864 2865 tpdm@6c28000 { 2866 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2867 reg = <0x0 0x06c28000 0x0 0x1000>; 2868 2869 clocks = <&aoss_qmp>; 2870 clock-names = "apb_pclk"; 2871 2872 qcom,dsb-element-bits = <32>; 2873 qcom,dsb-msrs-num = <32>; 2874 2875 out-ports { 2876 port { 2877 tpdm_center_out: endpoint { 2878 remote-endpoint = <&tpda_qdss_in0>; 2879 }; 2880 }; 2881 }; 2882 }; 2883 2884 cti@6c29000 { 2885 compatible = "arm,coresight-cti", "arm,primecell"; 2886 reg = <0x0 0x06c29000 0x0 0x1000>; 2887 2888 clocks = <&aoss_qmp>; 2889 clock-names = "apb_pclk"; 2890 }; 2891 2892 cti@6c2a000 { 2893 compatible = "arm,coresight-cti", "arm,primecell"; 2894 reg = <0x0 0x06c2a000 0x0 0x1000>; 2895 2896 clocks = <&aoss_qmp>; 2897 clock-names = "apb_pclk"; 2898 }; 2899 2900 cti@7020000 { 2901 compatible = "arm,coresight-cti", "arm,primecell"; 2902 reg = <0x0 0x07020000 0x0 0x1000>; 2903 2904 clocks = <&aoss_qmp>; 2905 clock-names = "apb_pclk"; 2906 }; 2907 2908 etm@7040000 { 2909 compatible = "arm,primecell"; 2910 reg = <0x0 0x07040000 0x0 0x1000>; 2911 cpu = <&cpu0>; 2912 2913 clocks = <&aoss_qmp>; 2914 clock-names = "apb_pclk"; 2915 2916 arm,coresight-loses-context-with-cpu; 2917 qcom,skip-power-up; 2918 2919 out-ports { 2920 port { 2921 etm0_out: endpoint { 2922 remote-endpoint = <&funnel_apss_in0>; 2923 }; 2924 }; 2925 }; 2926 }; 2927 2928 cti@7120000 { 2929 compatible = "arm,coresight-cti", "arm,primecell"; 2930 reg = <0x0 0x07120000 0x0 0x1000>; 2931 2932 clocks = <&aoss_qmp>; 2933 clock-names = "apb_pclk"; 2934 }; 2935 2936 etm@7140000 { 2937 compatible = "arm,primecell"; 2938 reg = <0x0 0x07140000 0x0 0x1000>; 2939 cpu = <&cpu1>; 2940 2941 clocks = <&aoss_qmp>; 2942 clock-names = "apb_pclk"; 2943 2944 arm,coresight-loses-context-with-cpu; 2945 qcom,skip-power-up; 2946 2947 out-ports { 2948 port { 2949 etm1_out: endpoint { 2950 remote-endpoint = <&funnel_apss_in1>; 2951 }; 2952 }; 2953 }; 2954 }; 2955 2956 cti@7220000 { 2957 compatible = "arm,coresight-cti", "arm,primecell"; 2958 reg = <0x0 0x07220000 0x0 0x1000>; 2959 2960 clocks = <&aoss_qmp>; 2961 clock-names = "apb_pclk"; 2962 }; 2963 2964 etm@7240000 { 2965 compatible = "arm,primecell"; 2966 reg = <0x0 0x07240000 0x0 0x1000>; 2967 cpu = <&cpu2>; 2968 2969 clocks = <&aoss_qmp>; 2970 clock-names = "apb_pclk"; 2971 2972 arm,coresight-loses-context-with-cpu; 2973 qcom,skip-power-up; 2974 2975 out-ports { 2976 port { 2977 etm2_out: endpoint { 2978 remote-endpoint = <&funnel_apss_in2>; 2979 }; 2980 }; 2981 }; 2982 }; 2983 2984 cti@7320000 { 2985 compatible = "arm,coresight-cti", "arm,primecell"; 2986 reg = <0x0 0x07320000 0x0 0x1000>; 2987 2988 clocks = <&aoss_qmp>; 2989 clock-names = "apb_pclk"; 2990 }; 2991 2992 etm@7340000 { 2993 compatible = "arm,primecell"; 2994 reg = <0x0 0x07340000 0x0 0x1000>; 2995 cpu = <&cpu3>; 2996 2997 clocks = <&aoss_qmp>; 2998 clock-names = "apb_pclk"; 2999 3000 arm,coresight-loses-context-with-cpu; 3001 qcom,skip-power-up; 3002 3003 out-ports { 3004 port { 3005 etm3_out: endpoint { 3006 remote-endpoint = <&funnel_apss_in3>; 3007 }; 3008 }; 3009 }; 3010 }; 3011 3012 cti@7420000 { 3013 compatible = "arm,coresight-cti", "arm,primecell"; 3014 reg = <0x0 0x07420000 0x0 0x1000>; 3015 3016 clocks = <&aoss_qmp>; 3017 clock-names = "apb_pclk"; 3018 }; 3019 3020 etm@7440000 { 3021 compatible = "arm,primecell"; 3022 reg = <0x0 0x07440000 0x0 0x1000>; 3023 cpu = <&cpu4>; 3024 3025 clocks = <&aoss_qmp>; 3026 clock-names = "apb_pclk"; 3027 3028 arm,coresight-loses-context-with-cpu; 3029 qcom,skip-power-up; 3030 3031 out-ports { 3032 port { 3033 etm4_out: endpoint { 3034 remote-endpoint = <&funnel_apss_in4>; 3035 }; 3036 }; 3037 }; 3038 }; 3039 3040 cti@7520000 { 3041 compatible = "arm,coresight-cti", "arm,primecell"; 3042 reg = <0x0 0x07520000 0x0 0x1000>; 3043 3044 clocks = <&aoss_qmp>; 3045 clock-names = "apb_pclk"; 3046 }; 3047 3048 etm@7540000 { 3049 compatible = "arm,primecell"; 3050 reg = <0x0 0x07540000 0x0 0x1000>; 3051 cpu = <&cpu5>; 3052 3053 clocks = <&aoss_qmp>; 3054 clock-names = "apb_pclk"; 3055 3056 arm,coresight-loses-context-with-cpu; 3057 qcom,skip-power-up; 3058 3059 out-ports { 3060 port { 3061 etm5_out: endpoint { 3062 remote-endpoint = <&funnel_apss_in5>; 3063 }; 3064 }; 3065 }; 3066 }; 3067 3068 cti@7620000 { 3069 compatible = "arm,coresight-cti", "arm,primecell"; 3070 reg = <0x0 0x07620000 0x0 0x1000>; 3071 3072 clocks = <&aoss_qmp>; 3073 clock-names = "apb_pclk"; 3074 }; 3075 3076 etm@7640000 { 3077 compatible = "arm,primecell"; 3078 reg = <0x0 0x07640000 0x0 0x1000>; 3079 cpu = <&cpu6>; 3080 3081 clocks = <&aoss_qmp>; 3082 clock-names = "apb_pclk"; 3083 3084 arm,coresight-loses-context-with-cpu; 3085 qcom,skip-power-up; 3086 3087 out-ports { 3088 port { 3089 etm6_out: endpoint { 3090 remote-endpoint = <&funnel_apss_in6>; 3091 }; 3092 }; 3093 }; 3094 }; 3095 3096 cti@7720000 { 3097 compatible = "arm,coresight-cti", "arm,primecell"; 3098 reg = <0x0 0x07720000 0x0 0x1000>; 3099 3100 clocks = <&aoss_qmp>; 3101 clock-names = "apb_pclk"; 3102 }; 3103 3104 etm@7740000 { 3105 compatible = "arm,primecell"; 3106 reg = <0x0 0x07740000 0x0 0x1000>; 3107 cpu = <&cpu7>; 3108 3109 clocks = <&aoss_qmp>; 3110 clock-names = "apb_pclk"; 3111 3112 arm,coresight-loses-context-with-cpu; 3113 qcom,skip-power-up; 3114 3115 out-ports { 3116 port { 3117 etm7_out: endpoint { 3118 remote-endpoint = <&funnel_apss_in7>; 3119 }; 3120 }; 3121 }; 3122 }; 3123 3124 funnel@7800000 { 3125 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3126 reg = <0x0 0x07800000 0x0 0x1000>; 3127 3128 clocks = <&aoss_qmp>; 3129 clock-names = "apb_pclk"; 3130 3131 in-ports { 3132 #address-cells = <1>; 3133 #size-cells = <0>; 3134 3135 port@0 { 3136 reg = <0>; 3137 3138 funnel_apss_in0: endpoint { 3139 remote-endpoint = <&etm0_out>; 3140 }; 3141 }; 3142 3143 port@1 { 3144 reg = <1>; 3145 3146 funnel_apss_in1: endpoint { 3147 remote-endpoint = <&etm1_out>; 3148 }; 3149 }; 3150 3151 port@2 { 3152 reg = <2>; 3153 3154 funnel_apss_in2: endpoint { 3155 remote-endpoint = <&etm2_out>; 3156 }; 3157 }; 3158 3159 port@3 { 3160 reg = <3>; 3161 3162 funnel_apss_in3: endpoint { 3163 remote-endpoint = <&etm3_out>; 3164 }; 3165 }; 3166 3167 port@4 { 3168 reg = <4>; 3169 3170 funnel_apss_in4: endpoint { 3171 remote-endpoint = <&etm4_out>; 3172 }; 3173 }; 3174 3175 port@5 { 3176 reg = <5>; 3177 3178 funnel_apss_in5: endpoint { 3179 remote-endpoint = <&etm5_out>; 3180 }; 3181 }; 3182 3183 port@6 { 3184 reg = <6>; 3185 3186 funnel_apss_in6: endpoint { 3187 remote-endpoint = <&etm6_out>; 3188 }; 3189 }; 3190 3191 port@7 { 3192 reg = <7>; 3193 3194 funnel_apss_in7: endpoint { 3195 remote-endpoint = <&etm7_out>; 3196 }; 3197 }; 3198 }; 3199 3200 out-ports { 3201 port { 3202 funnel_apss_out: endpoint { 3203 remote-endpoint = <&funnel_apss_merg_in0>; 3204 }; 3205 }; 3206 }; 3207 }; 3208 3209 funnel@7810000 { 3210 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3211 reg = <0x0 0x07810000 0x0 0x1000>; 3212 3213 clocks = <&aoss_qmp>; 3214 clock-names = "apb_pclk"; 3215 3216 in-ports { 3217 #address-cells = <1>; 3218 #size-cells = <0>; 3219 3220 port@0 { 3221 reg = <0>; 3222 3223 funnel_apss_merg_in0: endpoint { 3224 remote-endpoint = <&funnel_apss_out>; 3225 }; 3226 }; 3227 3228 port@2 { 3229 reg = <2>; 3230 3231 funnel_apss_merg_in2: endpoint { 3232 remote-endpoint = <&tpda_olc_out>; 3233 }; 3234 }; 3235 3236 port@3 { 3237 reg = <3>; 3238 3239 funnel_apss_merg_in3: endpoint { 3240 remote-endpoint = <&tpda_llm_silver_out>; 3241 }; 3242 }; 3243 3244 port@4 { 3245 reg = <4>; 3246 3247 funnel_apss_merg_in4: endpoint { 3248 remote-endpoint = <&tpda_llm_gold_out>; 3249 }; 3250 }; 3251 3252 port@5 { 3253 reg = <5>; 3254 3255 funnel_apss_merg_in5: endpoint { 3256 remote-endpoint = <&tpda_apss_out>; 3257 }; 3258 }; 3259 }; 3260 3261 out-ports { 3262 port { 3263 funnel_apss_merg_out: endpoint { 3264 remote-endpoint = <&funnel_in1_in7>; 3265 }; 3266 }; 3267 }; 3268 }; 3269 3270 tpdm@7830000 { 3271 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3272 reg = <0x0 0x07830000 0x0 0x1000>; 3273 3274 clocks = <&aoss_qmp>; 3275 clock-names = "apb_pclk"; 3276 3277 qcom,cmb-element-bits = <64>; 3278 qcom,cmb-msrs-num = <32>; 3279 3280 out-ports { 3281 port { 3282 tpdm_olc_out: endpoint { 3283 remote-endpoint = <&tpda_olc_in>; 3284 }; 3285 }; 3286 }; 3287 }; 3288 3289 tpda@7832000 { 3290 compatible = "qcom,coresight-tpda", "arm,primecell"; 3291 reg = <0x0 0x07832000 0x0 0x1000>; 3292 3293 clocks = <&aoss_qmp>; 3294 clock-names = "apb_pclk"; 3295 3296 in-ports { 3297 port { 3298 tpda_olc_in: endpoint { 3299 remote-endpoint = <&tpdm_olc_out>; 3300 }; 3301 }; 3302 }; 3303 3304 out-ports { 3305 port { 3306 tpda_olc_out: endpoint { 3307 remote-endpoint = <&funnel_apss_merg_in2>; 3308 }; 3309 }; 3310 }; 3311 }; 3312 3313 tpdm@7860000 { 3314 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3315 reg = <0x0 0x07860000 0x0 0x1000>; 3316 3317 clocks = <&aoss_qmp>; 3318 clock-names = "apb_pclk"; 3319 3320 qcom,dsb-element-bits = <32>; 3321 qcom,dsb-msrs-num = <32>; 3322 3323 out-ports { 3324 port { 3325 tpdm_apss_out: endpoint { 3326 remote-endpoint = <&tpda_apss_in>; 3327 }; 3328 }; 3329 }; 3330 }; 3331 3332 tpda@7862000 { 3333 compatible = "qcom,coresight-tpda", "arm,primecell"; 3334 reg = <0x0 0x07862000 0x0 0x1000>; 3335 3336 clocks = <&aoss_qmp>; 3337 clock-names = "apb_pclk"; 3338 3339 in-ports { 3340 port { 3341 tpda_apss_in: endpoint { 3342 remote-endpoint = <&tpdm_apss_out>; 3343 }; 3344 }; 3345 }; 3346 3347 out-ports { 3348 port { 3349 tpda_apss_out: endpoint { 3350 remote-endpoint = <&funnel_apss_merg_in5>; 3351 }; 3352 }; 3353 }; 3354 }; 3355 3356 tpdm@78a0000 { 3357 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3358 reg = <0x0 0x078a0000 0x0 0x1000>; 3359 3360 clocks = <&aoss_qmp>; 3361 clock-names = "apb_pclk"; 3362 3363 qcom,cmb-element-bits = <32>; 3364 qcom,cmb-msrs-num = <32>; 3365 3366 out-ports { 3367 port { 3368 tpdm_llm_silver_out: endpoint { 3369 remote-endpoint = <&tpda_llm_silver_in>; 3370 }; 3371 }; 3372 }; 3373 }; 3374 3375 tpdm@78b0000 { 3376 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3377 reg = <0x0 0x078b0000 0x0 0x1000>; 3378 3379 clocks = <&aoss_qmp>; 3380 clock-names = "apb_pclk"; 3381 3382 qcom,cmb-element-bits = <32>; 3383 qcom,cmb-msrs-num = <32>; 3384 3385 out-ports { 3386 port { 3387 tpdm_llm_gold_out: endpoint { 3388 remote-endpoint = <&tpda_llm_gold_in>; 3389 }; 3390 }; 3391 }; 3392 }; 3393 3394 tpda@78c0000 { 3395 compatible = "qcom,coresight-tpda", "arm,primecell"; 3396 reg = <0x0 0x078c0000 0x0 0x1000>; 3397 3398 clocks = <&aoss_qmp>; 3399 clock-names = "apb_pclk"; 3400 3401 in-ports { 3402 port { 3403 tpda_llm_silver_in: endpoint { 3404 remote-endpoint = <&tpdm_llm_silver_out>; 3405 }; 3406 }; 3407 }; 3408 3409 out-ports { 3410 port { 3411 tpda_llm_silver_out: endpoint { 3412 remote-endpoint = <&funnel_apss_merg_in3>; 3413 }; 3414 }; 3415 }; 3416 }; 3417 3418 tpda@78d0000 { 3419 compatible = "qcom,coresight-tpda", "arm,primecell"; 3420 reg = <0x0 0x078d0000 0x0 0x1000>; 3421 3422 clocks = <&aoss_qmp>; 3423 clock-names = "apb_pclk"; 3424 3425 in-ports { 3426 port { 3427 tpda_llm_gold_in: endpoint { 3428 remote-endpoint = <&tpdm_llm_gold_out>; 3429 }; 3430 }; 3431 }; 3432 3433 out-ports { 3434 port { 3435 tpda_llm_gold_out: endpoint { 3436 remote-endpoint = <&funnel_apss_merg_in4>; 3437 }; 3438 }; 3439 }; 3440 }; 3441 3442 cti@78e0000 { 3443 compatible = "arm,coresight-cti", "arm,primecell"; 3444 reg = <0x0 0x078e0000 0x0 0x1000>; 3445 3446 clocks = <&aoss_qmp>; 3447 clock-names = "apb_pclk"; 3448 }; 3449 3450 cti@78f0000 { 3451 compatible = "arm,coresight-cti", "arm,primecell"; 3452 reg = <0x0 0x078f0000 0x0 0x1000>; 3453 3454 clocks = <&aoss_qmp>; 3455 clock-names = "apb_pclk"; 3456 }; 3457 3458 cti@7900000 { 3459 compatible = "arm,coresight-cti", "arm,primecell"; 3460 reg = <0x0 0x07900000 0x0 0x1000>; 3461 3462 clocks = <&aoss_qmp>; 3463 clock-names = "apb_pclk"; 3464 }; 3465 3466 remoteproc_cdsp: remoteproc@8300000 { 3467 compatible = "qcom,qcs615-cdsp-pas", "qcom,sm8150-cdsp-pas"; 3468 reg = <0x0 0x08300000 0x0 0x4040>; 3469 3470 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 3471 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3472 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3473 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3474 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3475 interrupt-names = "wdog", 3476 "fatal", 3477 "ready", 3478 "handover", 3479 "stop-ack"; 3480 3481 clocks = <&rpmhcc RPMH_CXO_CLK>; 3482 clock-names = "xo"; 3483 3484 power-domains = <&rpmhpd RPMHPD_CX>; 3485 power-domain-names = "cx"; 3486 3487 memory-region = <&rproc_cdsp_mem>; 3488 3489 qcom,qmp = <&aoss_qmp>; 3490 3491 qcom,smem-states = <&cdsp_smp2p_out 0>; 3492 qcom,smem-state-names = "stop"; 3493 3494 status = "disabled"; 3495 3496 glink-edge { 3497 interrupts = <GIC_SPI 574 IRQ_TYPE_EDGE_RISING>; 3498 mboxes = <&apss_shared 4>; 3499 label = "cdsp"; 3500 qcom,remote-pid = <5>; 3501 3502 fastrpc { 3503 compatible = "qcom,fastrpc"; 3504 qcom,glink-channels = "fastrpcglink-apps-dsp"; 3505 label = "cdsp"; 3506 #address-cells = <1>; 3507 #size-cells = <0>; 3508 3509 compute-cb@1 { 3510 compatible = "qcom,fastrpc-compute-cb"; 3511 reg = <1>; 3512 iommus = <&apps_smmu 0x1081 0x0>; 3513 dma-coherent; 3514 }; 3515 3516 compute-cb@2 { 3517 compatible = "qcom,fastrpc-compute-cb"; 3518 reg = <2>; 3519 iommus = <&apps_smmu 0x1082 0x0>; 3520 dma-coherent; 3521 }; 3522 3523 compute-cb@3 { 3524 compatible = "qcom,fastrpc-compute-cb"; 3525 reg = <3>; 3526 iommus = <&apps_smmu 0x1083 0x0>; 3527 dma-coherent; 3528 }; 3529 3530 compute-cb@4 { 3531 compatible = "qcom,fastrpc-compute-cb"; 3532 reg = <4>; 3533 iommus = <&apps_smmu 0x1084 0x0>; 3534 dma-coherent; 3535 }; 3536 3537 compute-cb@5 { 3538 compatible = "qcom,fastrpc-compute-cb"; 3539 reg = <5>; 3540 iommus = <&apps_smmu 0x1085 0x0>; 3541 dma-coherent; 3542 }; 3543 3544 compute-cb@6 { 3545 compatible = "qcom,fastrpc-compute-cb"; 3546 reg = <6>; 3547 iommus = <&apps_smmu 0x1086 0x0>; 3548 dma-coherent; 3549 }; 3550 }; 3551 }; 3552 }; 3553 3554 pmu@90b6300 { 3555 compatible = "qcom,qcs615-cpu-bwmon", "qcom,sdm845-bwmon"; 3556 reg = <0x0 0x090b6300 0x0 0x600>; 3557 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3558 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3559 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 3560 3561 operating-points-v2 = <&cpu_bwmon_opp_table>; 3562 3563 cpu_bwmon_opp_table: opp-table { 3564 compatible = "operating-points-v2"; 3565 3566 opp-0 { 3567 opp-peak-kBps = <12896000>; 3568 }; 3569 3570 opp-1 { 3571 opp-peak-kBps = <14928000>; 3572 }; 3573 }; 3574 }; 3575 3576 pmu@90cd000 { 3577 compatible = "qcom,qcs615-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 3578 reg = <0x0 0x090cd000 0x0 0x1000>; 3579 interrupts = <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>; 3580 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 3581 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3582 3583 operating-points-v2 = <&llcc_bwmon_opp_table>; 3584 3585 llcc_bwmon_opp_table: opp-table { 3586 compatible = "operating-points-v2"; 3587 3588 opp-0 { 3589 opp-peak-kBps = <800000>; 3590 }; 3591 3592 opp-1 { 3593 opp-peak-kBps = <1200000>; 3594 }; 3595 3596 opp-2 { 3597 opp-peak-kBps = <1804800>; 3598 }; 3599 3600 opp-3 { 3601 opp-peak-kBps = <2188800>; 3602 }; 3603 3604 opp-4 { 3605 opp-peak-kBps = <2726400>; 3606 }; 3607 3608 opp-5 { 3609 opp-peak-kBps = <3072000>; 3610 }; 3611 3612 opp-6 { 3613 opp-peak-kBps = <4070400>; 3614 }; 3615 3616 opp-7 { 3617 opp-peak-kBps = <5414400>; 3618 }; 3619 3620 opp-8 { 3621 opp-peak-kBps = <6220800>; 3622 }; 3623 }; 3624 }; 3625 3626 sdhc_2: mmc@8804000 { 3627 compatible = "qcom,qcs615-sdhci", "qcom,sdhci-msm-v5"; 3628 reg = <0x0 0x08804000 0x0 0x1000>; 3629 reg-names = "hc"; 3630 3631 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, 3632 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 3633 interrupt-names = "hc_irq", 3634 "pwr_irq"; 3635 3636 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3637 <&gcc GCC_SDCC2_APPS_CLK>, 3638 <&rpmhcc RPMH_CXO_CLK>; 3639 clock-names = "iface", 3640 "core", 3641 "xo"; 3642 3643 power-domains = <&rpmhpd RPMHPD_CX>; 3644 operating-points-v2 = <&sdhc2_opp_table>; 3645 iommus = <&apps_smmu 0x02a0 0x0>; 3646 resets = <&gcc GCC_SDCC2_BCR>; 3647 interconnects = <&aggre1_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3648 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3650 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3651 interconnect-names = "sdhc-ddr", 3652 "cpu-sdhc"; 3653 3654 qcom,dll-config = <0x0007642c>; 3655 qcom,ddr-config = <0x80040868>; 3656 dma-coherent; 3657 3658 status = "disabled"; 3659 3660 sdhc2_opp_table: opp-table { 3661 compatible = "operating-points-v2"; 3662 3663 opp-50000000 { 3664 opp-hz = /bits/ 64 <50000000>; 3665 required-opps = <&rpmhpd_opp_low_svs>; 3666 }; 3667 3668 opp-100000000 { 3669 opp-hz = /bits/ 64 <100000000>; 3670 required-opps = <&rpmhpd_opp_svs>; 3671 }; 3672 3673 opp-202000000 { 3674 opp-hz = /bits/ 64 <202000000>; 3675 required-opps = <&rpmhpd_opp_nom>; 3676 }; 3677 }; 3678 }; 3679 3680 dc_noc: interconnect@9160000 { 3681 reg = <0x0 0x09160000 0x0 0x3200>; 3682 compatible = "qcom,qcs615-dc-noc"; 3683 #interconnect-cells = <2>; 3684 qcom,bcm-voters = <&apps_bcm_voter>; 3685 }; 3686 3687 llcc: system-cache-controller@9200000 { 3688 compatible = "qcom,qcs615-llcc"; 3689 reg = <0x0 0x09200000 0x0 0x50000>, 3690 <0x0 0x09600000 0x0 0x50000>; 3691 reg-names = "llcc0_base", 3692 "llcc_broadcast_base"; 3693 }; 3694 3695 gem_noc: interconnect@9680000 { 3696 reg = <0x0 0x09680000 0x0 0x3e200>; 3697 compatible = "qcom,qcs615-gem-noc"; 3698 #interconnect-cells = <2>; 3699 qcom,bcm-voters = <&apps_bcm_voter>; 3700 }; 3701 3702 venus: video-codec@aa00000 { 3703 compatible = "qcom,qcs615-venus", "qcom,sc7180-venus"; 3704 reg = <0x0 0x0aa00000 0x0 0x100000>; 3705 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 3706 3707 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>, 3708 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 3709 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>, 3710 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>, 3711 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>; 3712 clock-names = "core", 3713 "iface", 3714 "bus", 3715 "vcodec0_core", 3716 "vcodec0_bus"; 3717 3718 power-domains = <&videocc VENUS_GDSC>, 3719 <&videocc VCODEC0_GDSC>, 3720 <&rpmhpd RPMHPD_CX>; 3721 power-domain-names = "venus", 3722 "vcodec0", 3723 "cx"; 3724 3725 operating-points-v2 = <&venus_opp_table>; 3726 3727 interconnects = <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 3728 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3729 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3730 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3731 interconnect-names = "video-mem", 3732 "cpu-cfg"; 3733 3734 iommus = <&apps_smmu 0xe60 0x20>; 3735 3736 memory-region = <&pil_video_mem>; 3737 3738 status = "disabled"; 3739 3740 venus_opp_table: opp-table { 3741 compatible = "operating-points-v2"; 3742 3743 opp-133330000 { 3744 opp-hz = /bits/ 64 <133330000>; 3745 required-opps = <&rpmhpd_opp_low_svs>; 3746 }; 3747 3748 opp-240000000 { 3749 opp-hz = /bits/ 64 <240000000>; 3750 required-opps = <&rpmhpd_opp_svs>; 3751 }; 3752 3753 opp-300000000 { 3754 opp-hz = /bits/ 64 <300000000>; 3755 required-opps = <&rpmhpd_opp_svs_l1>; 3756 }; 3757 3758 opp-380000000 { 3759 opp-hz = /bits/ 64 <380000000>; 3760 required-opps = <&rpmhpd_opp_nom>; 3761 }; 3762 3763 opp-410000000 { 3764 opp-hz = /bits/ 64 <410000000>; 3765 required-opps = <&rpmhpd_opp_nom_l1>; 3766 }; 3767 3768 opp-460000000 { 3769 opp-hz = /bits/ 64 <460000000>; 3770 required-opps = <&rpmhpd_opp_turbo>; 3771 }; 3772 }; 3773 }; 3774 3775 videocc: clock-controller@ab00000 { 3776 compatible = "qcom,qcs615-videocc"; 3777 reg = <0 0x0ab00000 0 0x10000>; 3778 3779 clocks = <&rpmhcc RPMH_CXO_CLK>, 3780 <&sleep_clk>; 3781 3782 #clock-cells = <1>; 3783 #reset-cells = <1>; 3784 #power-domain-cells = <1>; 3785 }; 3786 3787 camcc: clock-controller@ad00000 { 3788 compatible = "qcom,qcs615-camcc"; 3789 reg = <0 0x0ad00000 0 0x10000>; 3790 3791 clocks = <&rpmhcc RPMH_CXO_CLK>; 3792 3793 #clock-cells = <1>; 3794 #reset-cells = <1>; 3795 #power-domain-cells = <1>; 3796 }; 3797 3798 mdss: display-subsystem@ae00000 { 3799 compatible = "qcom,sm6150-mdss"; 3800 reg = <0x0 0x0ae00000 0x0 0x1000>; 3801 reg-names = "mdss"; 3802 3803 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 3804 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3805 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3806 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3807 interconnect-names = "mdp0-mem", 3808 "cpu-cfg"; 3809 3810 power-domains = <&dispcc MDSS_CORE_GDSC>; 3811 3812 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3813 <&gcc GCC_DISP_HF_AXI_CLK>, 3814 <&dispcc DISP_CC_MDSS_MDP_CLK>; 3815 3816 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3817 interrupt-controller; 3818 #interrupt-cells = <1>; 3819 3820 iommus = <&apps_smmu 0x800 0x0>; 3821 3822 #address-cells = <2>; 3823 #size-cells = <2>; 3824 ranges; 3825 3826 status = "disabled"; 3827 3828 mdss_mdp: display-controller@ae01000 { 3829 compatible = "qcom,sm6150-dpu"; 3830 reg = <0x0 0x0ae01000 0x0 0x8f000>, 3831 <0x0 0x0aeb0000 0x0 0x2008>; 3832 reg-names = "mdp", 3833 "vbif"; 3834 3835 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3836 <&gcc GCC_DISP_HF_AXI_CLK>, 3837 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3838 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3839 clock-names = "iface", 3840 "bus", 3841 "core", 3842 "vsync"; 3843 3844 operating-points-v2 = <&mdp_opp_table>; 3845 power-domains = <&rpmhpd RPMHPD_CX>; 3846 3847 interrupts-extended = <&mdss 0>; 3848 3849 ports { 3850 #address-cells = <1>; 3851 #size-cells = <0>; 3852 3853 port@0 { 3854 reg = <0>; 3855 3856 dpu_intf0_out: endpoint { 3857 }; 3858 }; 3859 3860 port@1 { 3861 reg = <1>; 3862 3863 dpu_intf1_out: endpoint { 3864 remote-endpoint = <&mdss_dsi0_in>; 3865 }; 3866 }; 3867 }; 3868 3869 mdp_opp_table: opp-table { 3870 compatible = "operating-points-v2"; 3871 3872 opp-192000000 { 3873 opp-hz = /bits/ 64 <192000000>; 3874 required-opps = <&rpmhpd_opp_low_svs>; 3875 }; 3876 3877 opp-256000000 { 3878 opp-hz = /bits/ 64 <256000000>; 3879 required-opps = <&rpmhpd_opp_svs>; 3880 }; 3881 3882 opp-307200000 { 3883 opp-hz = /bits/ 64 <307200000>; 3884 required-opps = <&rpmhpd_opp_nom>; 3885 }; 3886 }; 3887 }; 3888 3889 mdss_dsi0: dsi@ae94000 { 3890 compatible = "qcom,sm6150-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3891 reg = <0x0 0x0ae94000 0x0 0x400>; 3892 reg-names = "dsi_ctrl"; 3893 3894 interrupts-extended = <&mdss 4>; 3895 3896 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3897 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3898 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3899 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3900 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3901 <&gcc GCC_DISP_HF_AXI_CLK>; 3902 clock-names = "byte", 3903 "byte_intf", 3904 "pixel", 3905 "core", 3906 "iface", 3907 "bus"; 3908 3909 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3910 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3911 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3912 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 3913 3914 operating-points-v2 = <&dsi0_opp_table>; 3915 power-domains = <&rpmhpd RPMHPD_CX>; 3916 3917 phys = <&mdss_dsi0_phy>; 3918 3919 #address-cells = <1>; 3920 #size-cells = <0>; 3921 3922 status = "disabled"; 3923 3924 dsi0_opp_table: opp-table { 3925 compatible = "operating-points-v2"; 3926 3927 opp-164000000 { 3928 opp-hz = /bits/ 64 <164000000>; 3929 required-opps = <&rpmhpd_opp_low_svs>; 3930 }; 3931 }; 3932 3933 ports { 3934 #address-cells = <1>; 3935 #size-cells = <0>; 3936 3937 port@0 { 3938 reg = <0>; 3939 3940 mdss_dsi0_in: endpoint { 3941 remote-endpoint = <&dpu_intf1_out>; 3942 }; 3943 }; 3944 3945 port@1 { 3946 reg = <1>; 3947 3948 mdss_dsi0_out: endpoint { 3949 }; 3950 }; 3951 }; 3952 }; 3953 3954 mdss_dsi0_phy: phy@ae94400 { 3955 compatible = "qcom,sm6150-dsi-phy-14nm"; 3956 reg = <0x0 0x0ae94400 0x0 0x100>, 3957 <0x0 0x0ae94500 0x0 0x300>, 3958 <0x0 0x0ae94800 0x0 0x124>; 3959 reg-names = "dsi_phy", 3960 "dsi_phy_lane", 3961 "dsi_pll"; 3962 3963 #clock-cells = <1>; 3964 #phy-cells = <0>; 3965 3966 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3967 <&rpmhcc RPMH_CXO_CLK>; 3968 clock-names = "iface", 3969 "ref"; 3970 3971 status = "disabled"; 3972 }; 3973 }; 3974 3975 dispcc: clock-controller@af00000 { 3976 compatible = "qcom,qcs615-dispcc"; 3977 reg = <0 0x0af00000 0 0x20000>; 3978 3979 clocks = <&rpmhcc RPMH_CXO_CLK>, 3980 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 3981 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3982 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3983 <0>, 3984 <0>, 3985 <0>; 3986 3987 #clock-cells = <1>; 3988 #reset-cells = <1>; 3989 #power-domain-cells = <1>; 3990 }; 3991 3992 pdc: interrupt-controller@b220000 { 3993 compatible = "qcom,qcs615-pdc", "qcom,pdc"; 3994 reg = <0x0 0x0b220000 0x0 0x30000>, 3995 <0x0 0x17c000f0 0x0 0x64>; 3996 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>; 3997 interrupt-parent = <&intc>; 3998 #interrupt-cells = <2>; 3999 interrupt-controller; 4000 }; 4001 4002 aoss_qmp: power-management@c300000 { 4003 compatible = "qcom,qcs615-aoss-qmp", "qcom,aoss-qmp"; 4004 reg = <0x0 0x0c300000 0x0 0x400>; 4005 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>; 4006 mboxes = <&apss_shared 0>; 4007 4008 #clock-cells = <0>; 4009 }; 4010 4011 sram@c3f0000 { 4012 compatible = "qcom,rpmh-stats"; 4013 reg = <0x0 0x0c3f0000 0x0 0x400>; 4014 }; 4015 4016 sram@14680000 { 4017 compatible = "qcom,qcs615-imem", "syscon", "simple-mfd"; 4018 reg = <0x0 0x14680000 0x0 0x2c000>; 4019 ranges = <0 0 0x14680000 0x2c000>; 4020 4021 #address-cells = <1>; 4022 #size-cells = <1>; 4023 4024 pil-reloc@2a94c { 4025 compatible = "qcom,pil-reloc-info"; 4026 reg = <0x2a94c 0xc8>; 4027 }; 4028 }; 4029 4030 apps_smmu: iommu@15000000 { 4031 compatible = "qcom,qcs615-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 4032 reg = <0x0 0x15000000 0x0 0x80000>; 4033 #iommu-cells = <2>; 4034 #global-interrupts = <1>; 4035 dma-coherent; 4036 4037 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 4038 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 4039 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 4040 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 4041 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 4042 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 4043 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 4044 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 4045 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 4046 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 4047 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 4048 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 4049 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 4050 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 4051 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 4052 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 4053 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 4054 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 4055 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 4056 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 4057 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 4058 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 4059 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 4060 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 4061 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 4062 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 4063 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 4064 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 4065 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 4066 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 4067 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 4068 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 4069 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 4070 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 4071 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 4072 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 4073 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 4074 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 4075 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 4076 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 4077 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 4078 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 4079 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 4080 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 4081 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 4082 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 4083 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 4084 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 4085 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 4086 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 4087 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 4088 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 4089 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 4090 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 4091 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 4092 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 4093 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 4094 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 4095 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 4096 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 4097 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 4098 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 4099 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 4100 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 4101 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 4102 }; 4103 4104 spmi_bus: spmi@c440000 { 4105 compatible = "qcom,spmi-pmic-arb"; 4106 reg = <0x0 0x0c440000 0x0 0x1100>, 4107 <0x0 0x0c600000 0x0 0x2000000>, 4108 <0x0 0x0e600000 0x0 0x100000>, 4109 <0x0 0x0e700000 0x0 0xa0000>, 4110 <0x0 0x0c40a000 0x0 0x26000>; 4111 reg-names = "core", 4112 "chnls", 4113 "obsrvr", 4114 "intr", 4115 "cnfg"; 4116 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4117 interrupt-names = "periph_irq"; 4118 interrupt-controller; 4119 #interrupt-cells = <4>; 4120 #address-cells = <2>; 4121 #size-cells = <0>; 4122 qcom,channel = <0>; 4123 qcom,ee = <0>; 4124 }; 4125 4126 intc: interrupt-controller@17a00000 { 4127 compatible = "arm,gic-v3"; 4128 reg = <0x0 0x17a00000 0x0 0x10000>, /* GICD */ 4129 <0x0 0x17a60000 0x0 0x100000>; /* GICR * 8 */ 4130 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 4131 #address-cells = <0>; 4132 #interrupt-cells = <3>; 4133 interrupt-controller; 4134 #redistributor-regions = <1>; 4135 redistributor-stride = <0x0 0x20000>; 4136 }; 4137 4138 apss_shared: mailbox@17c00000 { 4139 compatible = "qcom,qcs615-apss-shared", 4140 "qcom,sdm845-apss-shared"; 4141 reg = <0x0 0x17c00000 0x0 0x1000>; 4142 #mbox-cells = <1>; 4143 }; 4144 4145 watchdog: watchdog@17c10000 { 4146 compatible = "qcom,apss-wdt-qcs615", "qcom,kpss-wdt"; 4147 reg = <0x0 0x17c10000 0x0 0x1000>; 4148 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 4149 clocks = <&sleep_clk>; 4150 }; 4151 4152 timer@17c20000 { 4153 compatible = "arm,armv7-timer-mem"; 4154 reg = <0x0 0x17c20000 0x0 0x1000>; 4155 ranges = <0 0 0 0x20000000>; 4156 #address-cells = <1>; 4157 #size-cells = <1>; 4158 4159 frame@17c21000 { 4160 reg = <0x17c21000 0x1000>, 4161 <0x17c22000 0x1000>; 4162 frame-number = <0>; 4163 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 4164 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 4165 }; 4166 4167 frame@17c23000 { 4168 reg = <0x17c23000 0x1000>; 4169 frame-number = <1>; 4170 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 4171 status = "disabled"; 4172 }; 4173 4174 frame@17c25000 { 4175 reg = <0x17c25000 0x1000>; 4176 frame-number = <2>; 4177 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 4178 status = "disabled"; 4179 }; 4180 4181 frame@17c27000 { 4182 reg = <0x17c27000 0x1000>; 4183 frame-number = <3>; 4184 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 4185 status = "disabled"; 4186 }; 4187 4188 frame@17c29000 { 4189 reg = <0x17c29000 0x1000>; 4190 frame-number = <4>; 4191 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 4192 status = "disabled"; 4193 }; 4194 4195 frame@17c2b000 { 4196 reg = <0x17c2b000 0x1000>; 4197 frame-number = <5>; 4198 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 4199 status = "disabled"; 4200 }; 4201 4202 frame@17c2d000 { 4203 reg = <0x17c2d000 0x1000>; 4204 frame-number = <6>; 4205 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 4206 status = "disabled"; 4207 }; 4208 }; 4209 4210 apps_rsc: rsc@18200000 { 4211 compatible = "qcom,rpmh-rsc"; 4212 reg = <0x0 0x18200000 0x0 0x10000>, 4213 <0x0 0x18210000 0x0 0x10000>, 4214 <0x0 0x18220000 0x0 0x10000>; 4215 reg-names = "drv-0", 4216 "drv-1", 4217 "drv-2"; 4218 4219 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 4220 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 4221 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 4222 4223 qcom,drv-id = <2>; 4224 qcom,tcs-offset = <0xd00>; 4225 qcom,tcs-config = <ACTIVE_TCS 2>, 4226 <SLEEP_TCS 3>, 4227 <WAKE_TCS 3>, 4228 <CONTROL_TCS 1>; 4229 4230 label = "apps_rsc"; 4231 power-domains = <&cluster_pd>; 4232 4233 apps_bcm_voter: bcm-voter { 4234 compatible = "qcom,bcm-voter"; 4235 }; 4236 4237 rpmhcc: clock-controller { 4238 compatible = "qcom,qcs615-rpmh-clk"; 4239 clocks = <&xo_board_clk>; 4240 clock-names = "xo"; 4241 4242 #clock-cells = <1>; 4243 }; 4244 4245 rpmhpd: power-controller { 4246 compatible = "qcom,qcs615-rpmhpd"; 4247 #power-domain-cells = <1>; 4248 operating-points-v2 = <&rpmhpd_opp_table>; 4249 4250 rpmhpd_opp_table: opp-table { 4251 compatible = "operating-points-v2"; 4252 4253 rpmhpd_opp_ret: opp-0 { 4254 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 4255 }; 4256 4257 rpmhpd_opp_min_svs: opp-1 { 4258 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 4259 }; 4260 4261 rpmhpd_opp_low_svs: opp-2 { 4262 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 4263 }; 4264 4265 rpmhpd_opp_svs: opp-3 { 4266 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4267 }; 4268 4269 rpmhpd_opp_svs_l1: opp-4 { 4270 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4271 }; 4272 4273 rpmhpd_opp_nom: opp-5 { 4274 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4275 }; 4276 4277 rpmhpd_opp_nom_l1: opp-6 { 4278 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 4279 }; 4280 4281 rpmhpd_opp_nom_l2: opp-7 { 4282 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 4283 }; 4284 4285 rpmhpd_opp_turbo: opp-8 { 4286 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4287 }; 4288 4289 rpmhpd_opp_turbo_l1: opp-9 { 4290 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4291 }; 4292 }; 4293 }; 4294 }; 4295 4296 osm_l3: interconnect@18321000 { 4297 compatible = "qcom,qcs615-osm-l3", "qcom,sm8150-osm-l3", "qcom,osm-l3"; 4298 reg = <0x0 0x18321000 0x0 0x1400>; 4299 4300 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4301 clock-names = "xo", "alternate"; 4302 4303 #interconnect-cells = <1>; 4304 }; 4305 4306 usb_1_hsphy: phy@88e2000 { 4307 compatible = "qcom,qcs615-qusb2-phy"; 4308 reg = <0x0 0x88e2000 0x0 0x180>; 4309 4310 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, <&rpmhcc RPMH_CXO_CLK>; 4311 clock-names = "cfg_ahb", "ref"; 4312 4313 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4314 nvmem-cells = <&qusb2_hstx_trim>; 4315 4316 #phy-cells = <0>; 4317 4318 status = "disabled"; 4319 }; 4320 4321 usb_hsphy_2: phy@88e3000 { 4322 compatible = "qcom,qcs615-qusb2-phy"; 4323 reg = <0x0 0x088e3000 0x0 0x180>; 4324 4325 clocks = <&gcc GCC_AHB2PHY_WEST_CLK>, 4326 <&rpmhcc RPMH_CXO_CLK>; 4327 clock-names = "cfg_ahb", 4328 "ref"; 4329 4330 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4331 4332 #phy-cells = <0>; 4333 4334 status = "disabled"; 4335 }; 4336 4337 usb_qmpphy: phy@88e6000 { 4338 compatible = "qcom,qcs615-qmp-usb3-phy"; 4339 reg = <0x0 0x88e6000 0x0 0x1000>; 4340 4341 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4342 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 4343 <&gcc GCC_AHB2PHY_WEST_CLK>, 4344 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4345 clock-names = "aux", 4346 "ref", 4347 "cfg_ahb", 4348 "pipe"; 4349 4350 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 4351 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 4352 reset-names = "phy", "phy_phy"; 4353 4354 qcom,tcsr-reg = <&tcsr 0xb244>; 4355 4356 clock-output-names = "usb3_phy_pipe_clk_src"; 4357 #clock-cells = <0>; 4358 4359 #phy-cells = <0>; 4360 4361 status = "disabled"; 4362 }; 4363 4364 usb_1: usb@a6f8800 { 4365 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 4366 reg = <0x0 0x0a6f8800 0x0 0x400>; 4367 4368 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4369 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4370 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4371 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4372 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4373 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 4374 clock-names = "cfg_noc", 4375 "core", 4376 "iface", 4377 "sleep", 4378 "mock_utmi", 4379 "xo"; 4380 4381 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4382 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4383 assigned-clock-rates = <19200000>, <200000000>; 4384 4385 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4386 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4387 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 4388 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 4389 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 4390 interrupt-names = "pwr_event", 4391 "hs_phy_irq", 4392 "dp_hs_phy_irq", 4393 "dm_hs_phy_irq", 4394 "ss_phy_irq"; 4395 4396 power-domains = <&gcc USB30_PRIM_GDSC>; 4397 required-opps = <&rpmhpd_opp_nom>; 4398 4399 resets = <&gcc GCC_USB30_PRIM_BCR>; 4400 4401 #address-cells = <2>; 4402 #size-cells = <2>; 4403 ranges; 4404 4405 status = "disabled"; 4406 4407 usb_1_dwc3: usb@a600000 { 4408 compatible = "snps,dwc3"; 4409 reg = <0x0 0x0a600000 0x0 0xcd00>; 4410 4411 iommus = <&apps_smmu 0x140 0x0>; 4412 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 4413 4414 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 4415 phy-names = "usb2-phy", "usb3-phy"; 4416 4417 snps,dis-u1-entry-quirk; 4418 snps,dis-u2-entry-quirk; 4419 snps,dis_u2_susphy_quirk; 4420 snps,dis_u3_susphy_quirk; 4421 snps,dis_enblslpm_quirk; 4422 snps,has-lpm-erratum; 4423 snps,hird-threshold = /bits/ 8 <0x10>; 4424 snps,usb3_lpm_capable; 4425 }; 4426 }; 4427 4428 usb_2: usb@a8f8800 { 4429 compatible = "qcom,qcs615-dwc3", "qcom,dwc3"; 4430 reg = <0x0 0x0a8f8800 0x0 0x400>; 4431 4432 clocks = <&gcc GCC_CFG_NOC_USB2_SEC_AXI_CLK>, 4433 <&gcc GCC_USB20_SEC_MASTER_CLK>, 4434 <&gcc GCC_AGGRE_USB2_SEC_AXI_CLK>, 4435 <&gcc GCC_USB20_SEC_SLEEP_CLK>, 4436 <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 4437 <&gcc GCC_USB2_PRIM_CLKREF_CLK>; 4438 clock-names = "cfg_noc", 4439 "core", 4440 "iface", 4441 "sleep", 4442 "mock_utmi", 4443 "xo"; 4444 4445 assigned-clocks = <&gcc GCC_USB20_SEC_MOCK_UTMI_CLK>, 4446 <&gcc GCC_USB20_SEC_MASTER_CLK>; 4447 assigned-clock-rates = <19200000>, <200000000>; 4448 4449 interrupts-extended = <&intc GIC_SPI 663 IRQ_TYPE_LEVEL_HIGH>, 4450 <&intc GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>, 4451 <&pdc 11 IRQ_TYPE_EDGE_BOTH>, 4452 <&pdc 10 IRQ_TYPE_EDGE_BOTH>; 4453 interrupt-names = "pwr_event", 4454 "hs_phy_irq", 4455 "dp_hs_phy_irq", 4456 "dm_hs_phy_irq"; 4457 4458 power-domains = <&gcc USB20_SEC_GDSC>; 4459 required-opps = <&rpmhpd_opp_nom>; 4460 4461 resets = <&gcc GCC_USB20_SEC_BCR>; 4462 4463 qcom,select-utmi-as-pipe-clk; 4464 4465 #address-cells = <2>; 4466 #size-cells = <2>; 4467 ranges; 4468 4469 status = "disabled"; 4470 4471 usb_2_dwc3: usb@a800000 { 4472 compatible = "snps,dwc3"; 4473 reg = <0x0 0x0a800000 0x0 0xcd00>; 4474 4475 iommus = <&apps_smmu 0xe0 0x0>; 4476 interrupts = <GIC_SPI 664 IRQ_TYPE_LEVEL_HIGH>; 4477 4478 phys = <&usb_hsphy_2>; 4479 phy-names = "usb2-phy"; 4480 4481 snps,dis_u2_susphy_quirk; 4482 snps,dis_u3_susphy_quirk; 4483 snps,dis_enblslpm_quirk; 4484 snps,has-lpm-erratum; 4485 snps,hird-threshold = /bits/ 8 <0x10>; 4486 4487 maximum-speed = "high-speed"; 4488 }; 4489 }; 4490 4491 tsens0: thermal-sensor@c263000 { 4492 compatible = "qcom,qcs615-tsens", "qcom,tsens-v2"; 4493 reg = <0x0 0x0c263000 0x0 0x1000>, 4494 <0x0 0x0c222000 0x0 0x1000>; 4495 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 4496 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 4497 interrupt-names = "uplow", "critical"; 4498 #qcom,sensors = <16>; 4499 #thermal-sensor-cells = <1>; 4500 }; 4501 4502 remoteproc_adsp: remoteproc@62400000 { 4503 compatible = "qcom,qcs615-adsp-pas", "qcom,sm8150-adsp-pas"; 4504 reg = <0x0 0x62400000 0x0 0x4040>; 4505 4506 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 4507 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4508 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4509 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4510 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 4511 interrupt-names = "wdog", 4512 "fatal", 4513 "ready", 4514 "handover", 4515 "stop-ack"; 4516 4517 clocks = <&rpmhcc RPMH_CXO_CLK>; 4518 clock-names = "xo"; 4519 4520 power-domains = <&rpmhpd RPMHPD_CX>; 4521 power-domain-names = "cx"; 4522 4523 memory-region = <&rproc_adsp_mem>; 4524 4525 qcom,qmp = <&aoss_qmp>; 4526 4527 qcom,smem-states = <&adsp_smp2p_out 0>; 4528 qcom,smem-state-names = "stop"; 4529 4530 status = "disabled"; 4531 4532 glink_edge: glink-edge { 4533 interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>; 4534 mboxes = <&apss_shared 24>; 4535 label = "lpass"; 4536 qcom,remote-pid = <2>; 4537 4538 fastrpc { 4539 compatible = "qcom,fastrpc"; 4540 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4541 label = "adsp"; 4542 #address-cells = <1>; 4543 #size-cells = <0>; 4544 4545 compute-cb@3 { 4546 compatible = "qcom,fastrpc-compute-cb"; 4547 reg = <3>; 4548 iommus = <&apps_smmu 0x1723 0x0>; 4549 dma-coherent; 4550 }; 4551 4552 compute-cb@4 { 4553 compatible = "qcom,fastrpc-compute-cb"; 4554 reg = <4>; 4555 iommus = <&apps_smmu 0x1724 0x0>; 4556 dma-coherent; 4557 }; 4558 4559 compute-cb@5 { 4560 compatible = "qcom,fastrpc-compute-cb"; 4561 reg = <5>; 4562 iommus = <&apps_smmu 0x1725 0x0>; 4563 dma-coherent; 4564 }; 4565 4566 compute-cb@6 { 4567 compatible = "qcom,fastrpc-compute-cb"; 4568 reg = <6>; 4569 iommus = <&apps_smmu 0x1726 0x0>; 4570 qcom,nsessions = <5>; 4571 dma-coherent; 4572 }; 4573 }; 4574 }; 4575 }; 4576 4577 cpufreq_hw: cpufreq@18323000 { 4578 compatible = "qcom,qcs615-cpufreq-hw", "qcom,cpufreq-hw"; 4579 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>; 4580 reg-names = "freq-domain0", "freq-domain1"; 4581 4582 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 4583 clock-names = "xo", "alternate"; 4584 4585 #freq-domain-cells = <1>; 4586 #clock-cells = <1>; 4587 }; 4588 }; 4589 4590 arch_timer: timer { 4591 compatible = "arm,armv8-timer"; 4592 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4593 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4594 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 4595 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 4596 }; 4597 4598 thermal-zones { 4599 aoss-thermal { 4600 thermal-sensors = <&tsens0 0>; 4601 4602 trips { 4603 aoss-critical { 4604 temperature = <115000>; 4605 hysteresis = <1000>; 4606 type = "critical"; 4607 }; 4608 }; 4609 }; 4610 4611 cpuss-0-thermal { 4612 thermal-sensors = <&tsens0 1>; 4613 4614 trips { 4615 cpuss0-critical { 4616 temperature = <115000>; 4617 hysteresis = <1000>; 4618 type = "critical"; 4619 }; 4620 }; 4621 }; 4622 4623 cpuss-1-thermal { 4624 thermal-sensors = <&tsens0 2>; 4625 4626 trips { 4627 cpuss1-critical { 4628 temperature = <115000>; 4629 hysteresis = <1000>; 4630 type = "critical"; 4631 }; 4632 }; 4633 }; 4634 4635 cpuss-2-thermal { 4636 thermal-sensors = <&tsens0 3>; 4637 4638 trips { 4639 cpuss2-critical { 4640 temperature = <115000>; 4641 hysteresis = <1000>; 4642 type = "critical"; 4643 }; 4644 }; 4645 }; 4646 4647 cpuss-3-thermal { 4648 thermal-sensors = <&tsens0 4>; 4649 4650 trips { 4651 cpuss3-critical { 4652 temperature = <115000>; 4653 hysteresis = <1000>; 4654 type = "critical"; 4655 }; 4656 }; 4657 }; 4658 4659 cpu-1-0-thermal { 4660 thermal-sensors = <&tsens0 5>; 4661 4662 trips { 4663 cpu-critical { 4664 temperature = <115000>; 4665 hysteresis = <1000>; 4666 type = "critical"; 4667 }; 4668 }; 4669 }; 4670 4671 cpu-1-1-thermal { 4672 thermal-sensors = <&tsens0 6>; 4673 4674 trips { 4675 cpu-critical { 4676 temperature = <115000>; 4677 hysteresis = <1000>; 4678 type = "critical"; 4679 }; 4680 }; 4681 }; 4682 4683 cpu-1-2-thermal { 4684 thermal-sensors = <&tsens0 7>; 4685 4686 trips { 4687 cpu-critical { 4688 temperature = <115000>; 4689 hysteresis = <1000>; 4690 type = "critical"; 4691 }; 4692 }; 4693 }; 4694 4695 cpu-1-3-thermal { 4696 thermal-sensors = <&tsens0 8>; 4697 4698 trips { 4699 cpu-critical { 4700 temperature = <115000>; 4701 hysteresis = <1000>; 4702 type = "critical"; 4703 }; 4704 }; 4705 }; 4706 4707 gpu-thermal { 4708 thermal-sensors = <&tsens0 9>; 4709 4710 trips { 4711 gpu-critical { 4712 temperature = <115000>; 4713 hysteresis = <1000>; 4714 type = "critical"; 4715 }; 4716 }; 4717 }; 4718 4719 q6-hvx-thermal { 4720 thermal-sensors = <&tsens0 10>; 4721 4722 trips { 4723 q6-hvx-critical { 4724 temperature = <115000>; 4725 hysteresis = <1000>; 4726 type = "critical"; 4727 }; 4728 }; 4729 }; 4730 4731 mdm-core-thermal { 4732 thermal-sensors = <&tsens0 11>; 4733 4734 trips { 4735 mdm-core-critical { 4736 temperature = <115000>; 4737 hysteresis = <1000>; 4738 type = "critical"; 4739 }; 4740 }; 4741 }; 4742 4743 camera-thermal { 4744 thermal-sensors = <&tsens0 12>; 4745 4746 trips { 4747 camera-critical { 4748 temperature = <115000>; 4749 hysteresis = <1000>; 4750 type = "critical"; 4751 }; 4752 }; 4753 }; 4754 4755 wlan-thermal { 4756 thermal-sensors = <&tsens0 13>; 4757 4758 trips { 4759 wlan-critical { 4760 temperature = <115000>; 4761 hysteresis = <1000>; 4762 type = "critical"; 4763 }; 4764 }; 4765 }; 4766 4767 display-thermal { 4768 thermal-sensors = <&tsens0 14>; 4769 4770 trips { 4771 display-critical { 4772 temperature = <115000>; 4773 hysteresis = <1000>; 4774 type = "critical"; 4775 }; 4776 }; 4777 }; 4778 4779 video-thermal { 4780 thermal-sensors = <&tsens0 15>; 4781 4782 trips { 4783 video-critical { 4784 temperature = <115000>; 4785 hysteresis = <1000>; 4786 type = "critical"; 4787 }; 4788 }; 4789 }; 4790 }; 4791};
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