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sm8750.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/sm8750.dtsi
1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,rpmh.h> 7#include <dt-bindings/clock/qcom,sm8750-gcc.h> 8#include <dt-bindings/clock/qcom,sm8750-tcsr.h> 9#include <dt-bindings/dma/qcom-gpi.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/interconnect/qcom,icc.h> 12#include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/mailbox/qcom-ipcc.h> 15#include <dt-bindings/phy/phy-qcom-qmp.h> 16#include <dt-bindings/power/qcom,rpmhpd.h> 17#include <dt-bindings/power/qcom-rpmpd.h> 18#include <dt-bindings/soc/qcom,gpr.h> 19#include <dt-bindings/soc/qcom,rpmh-rsc.h> 20#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 21 22/ { 23 interrupt-parent = <&intc>; 24 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 cpus { 29 #address-cells = <2>; 30 #size-cells = <0>; 31 32 cpu0: cpu@0 { 33 device_type = "cpu"; 34 compatible = "qcom,oryon"; 35 reg = <0x0 0x0>; 36 enable-method = "psci"; 37 next-level-cache = <&l2_0>; 38 power-domains = <&cpu_pd0>; 39 power-domain-names = "psci"; 40 41 l2_0: l2-cache { 42 compatible = "cache"; 43 cache-level = <2>; 44 cache-unified; 45 }; 46 }; 47 48 cpu1: cpu@100 { 49 device_type = "cpu"; 50 compatible = "qcom,oryon"; 51 reg = <0x0 0x100>; 52 enable-method = "psci"; 53 next-level-cache = <&l2_0>; 54 power-domains = <&cpu_pd1>; 55 power-domain-names = "psci"; 56 }; 57 58 cpu2: cpu@200 { 59 device_type = "cpu"; 60 compatible = "qcom,oryon"; 61 reg = <0x0 0x200>; 62 enable-method = "psci"; 63 next-level-cache = <&l2_0>; 64 power-domains = <&cpu_pd2>; 65 power-domain-names = "psci"; 66 }; 67 68 cpu3: cpu@300 { 69 device_type = "cpu"; 70 compatible = "qcom,oryon"; 71 reg = <0x0 0x300>; 72 enable-method = "psci"; 73 next-level-cache = <&l2_0>; 74 power-domains = <&cpu_pd3>; 75 power-domain-names = "psci"; 76 }; 77 78 cpu4: cpu@400 { 79 device_type = "cpu"; 80 compatible = "qcom,oryon"; 81 reg = <0x0 0x400>; 82 enable-method = "psci"; 83 next-level-cache = <&l2_0>; 84 power-domains = <&cpu_pd4>; 85 power-domain-names = "psci"; 86 }; 87 88 cpu5: cpu@500 { 89 device_type = "cpu"; 90 compatible = "qcom,oryon"; 91 reg = <0x0 0x500>; 92 enable-method = "psci"; 93 next-level-cache = <&l2_0>; 94 power-domains = <&cpu_pd5>; 95 power-domain-names = "psci"; 96 }; 97 98 cpu6: cpu@10000 { 99 device_type = "cpu"; 100 compatible = "qcom,oryon"; 101 reg = <0x0 0x10000>; 102 enable-method = "psci"; 103 next-level-cache = <&l2_1>; 104 power-domains = <&cpu_pd6>; 105 power-domain-names = "psci"; 106 107 l2_1: l2-cache { 108 compatible = "cache"; 109 cache-level = <2>; 110 cache-unified; 111 }; 112 }; 113 114 cpu7: cpu@10100 { 115 device_type = "cpu"; 116 compatible = "qcom,oryon"; 117 reg = <0x0 0x10100>; 118 enable-method = "psci"; 119 next-level-cache = <&l2_1>; 120 power-domains = <&cpu_pd7>; 121 power-domain-names = "psci"; 122 }; 123 124 cpu-map { 125 cluster0 { 126 core0 { 127 cpu = <&cpu0>; 128 }; 129 130 core1 { 131 cpu = <&cpu1>; 132 }; 133 134 core2 { 135 cpu = <&cpu2>; 136 }; 137 138 core3 { 139 cpu = <&cpu3>; 140 }; 141 142 core4 { 143 cpu = <&cpu4>; 144 }; 145 146 core5 { 147 cpu = <&cpu5>; 148 }; 149 }; 150 151 cluster1 { 152 core0 { 153 cpu = <&cpu6>; 154 }; 155 156 core1 { 157 cpu = <&cpu7>; 158 }; 159 }; 160 }; 161 162 idle-states { 163 entry-method = "psci"; 164 165 cluster0_c4: cpu-sleep-0 { 166 compatible = "arm,idle-state"; 167 idle-state-name = "ret"; 168 arm,psci-suspend-param = <0x00000004>; 169 entry-latency-us = <93>; 170 exit-latency-us = <129>; 171 min-residency-us = <560>; 172 }; 173 174 cluster1_c4: cpu-sleep-1 { 175 compatible = "arm,idle-state"; 176 idle-state-name = "ret"; 177 arm,psci-suspend-param = <0x00000004>; 178 entry-latency-us = <172>; 179 exit-latency-us = <130>; 180 min-residency-us = <686>; 181 }; 182 }; 183 184 domain-idle-states { 185 cluster_cl5: cluster-sleep-0 { 186 compatible = "domain-idle-state"; 187 arm,psci-suspend-param = <0x01000054>; 188 entry-latency-us = <2150>; 189 exit-latency-us = <1983>; 190 min-residency-us = <9144>; 191 }; 192 193 domain_ss3: domain-sleep-0 { 194 compatible = "domain-idle-state"; 195 arm,psci-suspend-param = <0x0200c354>; 196 entry-latency-us = <2800>; 197 exit-latency-us = <4400>; 198 min-residency-us = <10150>; 199 }; 200 }; 201 }; 202 203 firmware { 204 scm: scm { 205 compatible = "qcom,scm-sm8750", "qcom,scm"; 206 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 207 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 208 }; 209 }; 210 211 clk_virt: interconnect-0 { 212 compatible = "qcom,sm8750-clk-virt"; 213 #interconnect-cells = <2>; 214 qcom,bcm-voters = <&apps_bcm_voter>; 215 }; 216 217 mc_virt: interconnect-1 { 218 compatible = "qcom,sm8750-mc-virt"; 219 #interconnect-cells = <2>; 220 qcom,bcm-voters = <&apps_bcm_voter>; 221 }; 222 223 memory@a0000000 { 224 device_type = "memory"; 225 /* We expect the bootloader to fill in the size */ 226 reg = <0x0 0xa0000000 0x0 0x0>; 227 }; 228 229 pmu { 230 compatible = "arm,armv8-pmuv3"; 231 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 232 }; 233 234 psci { 235 compatible = "arm,psci-1.0"; 236 method = "smc"; 237 238 cpu_pd0: power-domain-cpu0 { 239 #power-domain-cells = <0>; 240 power-domains = <&cluster0_pd>; 241 domain-idle-states = <&cluster0_c4>; 242 }; 243 244 cpu_pd1: power-domain-cpu1 { 245 #power-domain-cells = <0>; 246 power-domains = <&cluster0_pd>; 247 domain-idle-states = <&cluster0_c4>; 248 }; 249 250 cpu_pd2: power-domain-cpu2 { 251 #power-domain-cells = <0>; 252 power-domains = <&cluster0_pd>; 253 domain-idle-states = <&cluster0_c4>; 254 }; 255 256 cpu_pd3: power-domain-cpu3 { 257 #power-domain-cells = <0>; 258 power-domains = <&cluster0_pd>; 259 domain-idle-states = <&cluster0_c4>; 260 }; 261 262 cpu_pd4: power-domain-cpu4 { 263 #power-domain-cells = <0>; 264 power-domains = <&cluster0_pd>; 265 domain-idle-states = <&cluster0_c4>; 266 }; 267 268 cpu_pd5: power-domain-cpu5 { 269 #power-domain-cells = <0>; 270 power-domains = <&cluster0_pd>; 271 domain-idle-states = <&cluster0_c4>; 272 }; 273 274 cpu_pd6: power-domain-cpu6 { 275 #power-domain-cells = <0>; 276 power-domains = <&cluster1_pd>; 277 domain-idle-states = <&cluster1_c4>; 278 }; 279 280 cpu_pd7: power-domain-cpu7 { 281 #power-domain-cells = <0>; 282 power-domains = <&cluster1_pd>; 283 domain-idle-states = <&cluster1_c4>; 284 }; 285 286 cluster0_pd: power-domain-cluster0 { 287 #power-domain-cells = <0>; 288 domain-idle-states = <&cluster_cl5>; 289 power-domains = <&system_pd>; 290 }; 291 292 cluster1_pd: power-domain-cluster1 { 293 #power-domain-cells = <0>; 294 domain-idle-states = <&cluster_cl5>; 295 power-domains = <&system_pd>; 296 }; 297 298 system_pd: power-domain-system { 299 #power-domain-cells = <0>; 300 domain-idle-states = <&domain_ss3>; 301 }; 302 }; 303 304 reserved-memory { 305 #address-cells = <2>; 306 #size-cells = <2>; 307 ranges; 308 309 gunyah_hyp_mem: gunyah-hyp@80000000 { 310 reg = <0x0 0x80000000 0x0 0xe00000>; 311 no-map; 312 }; 313 314 cpusys_vm_mem: cpusys-vm-mem@80e00000 { 315 reg = <0x0 0x80e00000 0x0 0x40000>; 316 no-map; 317 }; 318 319 cpucp_mem: cpucp@81200000 { 320 reg = <0x0 0x81200000 0x0 0x200000>; 321 no-map; 322 }; 323 324 xbl_dtlog_mem: xbl-dtlog@81a00000 { 325 reg = <0x0 0x81a00000 0x0 0x40000>; 326 no-map; 327 }; 328 329 aop_image_mem: aop-image@81c00000 { 330 reg = <0x0 0x81c00000 0x0 0x60000>; 331 no-map; 332 }; 333 334 aop_cmd_db_mem: aop-cmd-db@81c60000 { 335 compatible = "qcom,cmd-db"; 336 reg = <0x0 0x81c60000 0x0 0x20000>; 337 no-map; 338 }; 339 340 /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ 341 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 342 reg = <0x0 0x81c80000 0x0 0x74000>; 343 no-map; 344 }; 345 346 /* Secdata region can be reused by apps */ 347 348 smem_mem: smem@81d00000 { 349 compatible = "qcom,smem"; 350 reg = <0x0 0x81d00000 0x0 0x200000>; 351 hwlocks = <&tcsr_mutex 3>; 352 no-map; 353 }; 354 355 pdp_ns_shared_mem: pdp-ns-shared@81f00000 { 356 reg = <0x0 0x81f00000 0x0 0x100000>; 357 no-map; 358 }; 359 360 cpucp_scandump_mem: cpucp-scandump@82000000 { 361 reg = <0x0 0x82000000 0x0 0x380000>; 362 no-map; 363 }; 364 365 adsp_mhi_mem: adsp-mhi@82380000 { 366 reg = <0x0 0x82380000 0x0 0x20000>; 367 no-map; 368 }; 369 370 soccp_sdi_mem: soccp-sdi@823a0000 { 371 reg = <0x0 0x823a0000 0x0 0x40000>; 372 no-map; 373 }; 374 375 pmic_minii_dump_mem: pmic-minii-dump@823e0000 { 376 reg = <0x0 0x823e0000 0x0 0x80000>; 377 no-map; 378 }; 379 380 pvmfw_mem: pvmfw@824a0000 { 381 reg = <0x0 0x824a0000 0x0 0x100000>; 382 no-map; 383 }; 384 385 global_sync_mem: global-sync@82600000 { 386 reg = <0x0 0x82600000 0x0 0x100000>; 387 no-map; 388 }; 389 390 tz_stat_mem: tz-stat@82700000 { 391 reg = <0x0 0x82700000 0x0 0x100000>; 392 no-map; 393 }; 394 395 qdss_mem: qdss@82800000 { 396 reg = <0x0 0x82800000 0x0 0x2000000>; 397 no-map; 398 }; 399 400 dsm_partition_1_mem: dsm-partition-1@84a00000 { 401 reg = <0x0 0x84a00000 0x0 0x4900000>; 402 no-map; 403 }; 404 405 dsm_partition_2_mem: dsm-partition-2@89300000 { 406 reg = <0x0 0x89300000 0x0 0xa80000>; 407 no-map; 408 }; 409 410 mpss_mem: mpss@8ba00000 { 411 reg = <0x0 0x8ba00000 0x0 0xf600000>; 412 no-map; 413 }; 414 415 q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { 416 reg = <0x0 0x9b000000 0x0 0x80000>; 417 no-map; 418 }; 419 420 ipa_fw_mem: ipa-fw@9b080000 { 421 reg = <0x0 0x9b080000 0x0 0x10000>; 422 no-map; 423 }; 424 425 ipa_gsi_mem: ipa-gsi@9b090000 { 426 reg = <0x0 0x9b090000 0x0 0xa000>; 427 no-map; 428 }; 429 430 gpu_micro_code_mem: gpu-micro-code@9b09a000 { 431 reg = <0x0 0x9b09a000 0x0 0x2000>; 432 no-map; 433 }; 434 435 spss_region_mem: spss@9b0a0000 { 436 reg = <0x0 0x9b0a0000 0x0 0x1e0000>; 437 no-map; 438 }; 439 440 /* First part of the "SPU secure shared memory" region */ 441 spu_tz_shared_mem: spu-tz-shared@9b280000 { 442 reg = <0x0 0x9b280000 0x0 0x40000>; 443 no-map; 444 }; 445 446 /* Second part of the "SPU secure shared memory" region */ 447 spu_modem_shared_mem: spu-modem-shared@9b2c0000 { 448 reg = <0x0 0x9b2c0000 0x0 0x40000>; 449 no-map; 450 }; 451 452 camera_mem: camera@9b300000 { 453 reg = <0x0 0x9b300000 0x0 0x800000>; 454 no-map; 455 }; 456 457 camera_2_mem: camera-2@9bb00000 { 458 reg = <0x0 0x9bb00000 0x0 0x800000>; 459 no-map; 460 }; 461 462 video_mem: video@9c300000 { 463 reg = <0x0 0x9c300000 0x0 0x800000>; 464 no-map; 465 }; 466 467 cvp_mem: cvp@9cb00000 { 468 reg = <0x0 0x9cb00000 0x0 0x700000>; 469 no-map; 470 }; 471 472 cdsp_mem: cdsp@9d200000 { 473 reg = <0x0 0x9d200000 0x0 0x1900000>; 474 no-map; 475 }; 476 477 q6_cdsp_dtb_mem: q6-cdsp-dtb@9eb00000 { 478 reg = <0x0 0x9eb00000 0x0 0x80000>; 479 no-map; 480 }; 481 482 soccp_mem: soccp@9ec00000 { 483 reg = <0x0 0x9ec00000 0x0 0x180000>; 484 no-map; 485 }; 486 487 q6_adsp_dtb_mem: q6-adsp-dtb@9ed80000 { 488 reg = <0x0 0x9ed80000 0x0 0x80000>; 489 no-map; 490 }; 491 492 adspslpi_mem: adspslpi@9ee00000 { 493 reg = <0x0 0x9ee00000 0x0 0x3a80000>; 494 no-map; 495 }; 496 497 xbl_ramdump_mem: xbl-ramdump@b8000000 { 498 reg = <0x0 0xb8000000 0x0 0x1c0000>; 499 no-map; 500 }; 501 502 hwfence_shbuf: hwfence-shbuf@d4e23000 { 503 no-map; 504 reg = <0x0 0xd4e23000 0x0 0x2dd000>; 505 }; 506 507 /* Merged tz_reserved, xbl_sc, and qtee regions */ 508 tz_merged_mem: tz-merged@d8000000 { 509 reg = <0x0 0xd8000000 0x0 0x600000>; 510 no-map; 511 }; 512 513 trust_ui_vm_mem: trust-ui-vm@f3800000 { 514 reg = <0x0 0xf3800000 0x0 0x4400000>; 515 no-map; 516 }; 517 518 oem_vm_mem: oem-vm@f7c00000 { 519 reg = <0x0 0xf7c00000 0x0 0x4c00000>; 520 no-map; 521 }; 522 523 llcc_lpi_mem: llcc-lpi@ff800000 { 524 reg = <0x0 0xff800000 0x0 0x800000>; 525 no-map; 526 }; 527 }; 528 529 smp2p-adsp { 530 compatible = "qcom,smp2p"; 531 532 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 533 IPCC_MPROC_SIGNAL_SMP2P 534 IRQ_TYPE_EDGE_RISING>; 535 536 mboxes = <&ipcc IPCC_CLIENT_LPASS 537 IPCC_MPROC_SIGNAL_SMP2P>; 538 539 qcom,smem = <443>, <429>; 540 qcom,local-pid = <0>; 541 qcom,remote-pid = <2>; 542 543 smp2p_adsp_out: master-kernel { 544 qcom,entry-name = "master-kernel"; 545 #qcom,smem-state-cells = <1>; 546 }; 547 548 smp2p_adsp_in: slave-kernel { 549 qcom,entry-name = "slave-kernel"; 550 interrupt-controller; 551 #interrupt-cells = <2>; 552 }; 553 }; 554 555 smp2p-cdsp { 556 compatible = "qcom,smp2p"; 557 558 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 559 IPCC_MPROC_SIGNAL_SMP2P 560 IRQ_TYPE_EDGE_RISING>; 561 562 mboxes = <&ipcc IPCC_CLIENT_CDSP 563 IPCC_MPROC_SIGNAL_SMP2P>; 564 565 qcom,smem = <94>, <432>; 566 qcom,local-pid = <0>; 567 qcom,remote-pid = <5>; 568 569 smp2p_cdsp_out: master-kernel { 570 qcom,entry-name = "master-kernel"; 571 #qcom,smem-state-cells = <1>; 572 }; 573 574 smp2p_cdsp_in: slave-kernel { 575 qcom,entry-name = "slave-kernel"; 576 interrupt-controller; 577 #interrupt-cells = <2>; 578 }; 579 }; 580 581 smp2p-modem { 582 compatible = "qcom,smp2p"; 583 584 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 585 IPCC_MPROC_SIGNAL_SMP2P 586 IRQ_TYPE_EDGE_RISING>; 587 588 mboxes = <&ipcc IPCC_CLIENT_MPSS 589 IPCC_MPROC_SIGNAL_SMP2P>; 590 591 qcom,smem = <435>, <428>; 592 qcom,local-pid = <0>; 593 qcom,remote-pid = <1>; 594 595 smp2p_modem_out: master-kernel { 596 qcom,entry-name = "master-kernel"; 597 #qcom,smem-state-cells = <1>; 598 }; 599 600 smp2p_modem_in: slave-kernel { 601 qcom,entry-name = "slave-kernel"; 602 interrupt-controller; 603 #interrupt-cells = <2>; 604 }; 605 606 ipa_smp2p_out: ipa-ap-to-modem { 607 qcom,entry-name = "ipa"; 608 #qcom,smem-state-cells = <1>; 609 }; 610 611 ipa_smp2p_in: ipa-modem-to-ap { 612 qcom,entry-name = "ipa"; 613 interrupt-controller; 614 #interrupt-cells = <2>; 615 }; 616 617 /* TODO: smem mailbox in and out */ 618 }; 619 620 soc: soc@0 { 621 compatible = "simple-bus"; 622 623 #address-cells = <2>; 624 #size-cells = <2>; 625 dma-ranges = <0 0 0 0 0x10 0>; 626 ranges = <0 0 0 0 0x10 0>; 627 628 gcc: clock-controller@100000 { 629 compatible = "qcom,sm8750-gcc"; 630 reg = <0x0 0x00100000 0x0 0x1f4200>; 631 632 clocks = <&bi_tcxo_div2>, 633 <0>, 634 <&sleep_clk>, 635 <&pcie0_phy>, 636 <0>, 637 <0>, 638 <0>, 639 <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 640 641 #clock-cells = <1>; 642 #reset-cells = <1>; 643 #power-domain-cells = <1>; 644 }; 645 646 ipcc: mailbox@406000 { 647 compatible = "qcom,sm8750-ipcc", "qcom,ipcc"; 648 reg = <0x0 0x00406000 0x0 0x1000>; 649 650 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 651 interrupt-controller; 652 #interrupt-cells = <3>; 653 654 #mbox-cells = <2>; 655 }; 656 657 gpi_dma2: dma-controller@800000 { 658 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; 659 reg = <0x0 0x00800000 0x0 0x60000>; 660 661 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 673 674 dma-channels = <12>; 675 dma-channel-mask = <0x1e>; 676 #dma-cells = <3>; 677 678 iommus = <&apps_smmu 0x436 0x0>; 679 680 status = "disabled"; 681 }; 682 683 qupv3_2: geniqup@8c0000 { 684 compatible = "qcom,geni-se-qup"; 685 reg = <0x0 0x008c0000 0x0 0x2000>; 686 687 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 688 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 689 clock-names = "m-ahb", 690 "s-ahb"; 691 692 iommus = <&apps_smmu 0x423 0x0>; 693 694 #address-cells = <2>; 695 #size-cells = <2>; 696 ranges; 697 698 status = "disabled"; 699 700 i2c8: i2c@880000 { 701 compatible = "qcom,geni-i2c"; 702 reg = <0x0 0x00880000 0x0 0x4000>; 703 704 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 705 706 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 707 clock-names = "se"; 708 709 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 710 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 711 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 712 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 713 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 714 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 715 interconnect-names = "qup-core", 716 "qup-config", 717 "qup-memory"; 718 719 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 720 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 721 dma-names = "tx", 722 "rx"; 723 724 pinctrl-0 = <&qup_i2c8_data_clk>; 725 pinctrl-names = "default"; 726 727 #address-cells = <1>; 728 #size-cells = <0>; 729 730 status = "disabled"; 731 }; 732 733 spi8: spi@880000 { 734 compatible = "qcom,geni-spi"; 735 reg = <0x0 0x00880000 0x0 0x4000>; 736 737 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 738 739 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 740 clock-names = "se"; 741 742 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 743 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 744 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 745 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 746 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 747 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 748 interconnect-names = "qup-core", 749 "qup-config", 750 "qup-memory"; 751 752 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 753 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 754 dma-names = "tx", 755 "rx"; 756 757 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 758 pinctrl-names = "default"; 759 760 #address-cells = <1>; 761 #size-cells = <0>; 762 763 status = "disabled"; 764 }; 765 766 i2c9: i2c@884000 { 767 compatible = "qcom,geni-i2c"; 768 reg = <0x0 0x00884000 0x0 0x4000>; 769 770 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 771 772 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 773 clock-names = "se"; 774 775 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 776 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 777 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 778 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 779 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 780 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 781 interconnect-names = "qup-core", 782 "qup-config", 783 "qup-memory"; 784 785 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 786 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 787 dma-names = "tx", 788 "rx"; 789 790 pinctrl-0 = <&qup_i2c9_data_clk>; 791 pinctrl-names = "default"; 792 793 #address-cells = <1>; 794 #size-cells = <0>; 795 796 status = "disabled"; 797 }; 798 799 spi9: spi@884000 { 800 compatible = "qcom,geni-spi"; 801 reg = <0x0 0x00884000 0x0 0x4000>; 802 803 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 804 805 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 806 clock-names = "se"; 807 808 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 809 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 810 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 811 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 812 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 813 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 814 interconnect-names = "qup-core", 815 "qup-config", 816 "qup-memory"; 817 818 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 819 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 820 dma-names = "tx", 821 "rx"; 822 823 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 824 pinctrl-names = "default"; 825 826 #address-cells = <1>; 827 #size-cells = <0>; 828 829 status = "disabled"; 830 }; 831 832 i2c10: i2c@888000 { 833 compatible = "qcom,geni-i2c"; 834 reg = <0x0 0x00888000 0x0 0x4000>; 835 836 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 837 838 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 839 clock-names = "se"; 840 841 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 842 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 843 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 844 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 845 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 846 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 847 interconnect-names = "qup-core", 848 "qup-config", 849 "qup-memory"; 850 851 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 852 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 853 dma-names = "tx", 854 "rx"; 855 856 pinctrl-0 = <&qup_i2c10_data_clk>; 857 pinctrl-names = "default"; 858 859 #address-cells = <1>; 860 #size-cells = <0>; 861 862 status = "disabled"; 863 }; 864 865 spi10: spi@888000 { 866 compatible = "qcom,geni-spi"; 867 reg = <0x0 0x00888000 0x0 0x4000>; 868 869 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 870 871 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 872 clock-names = "se"; 873 874 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 875 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 876 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 877 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 878 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 879 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 880 interconnect-names = "qup-core", 881 "qup-config", 882 "qup-memory"; 883 884 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 885 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 886 dma-names = "tx", 887 "rx"; 888 889 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 890 pinctrl-names = "default"; 891 892 #address-cells = <1>; 893 #size-cells = <0>; 894 895 status = "disabled"; 896 }; 897 898 i2c11: i2c@88c000 { 899 compatible = "qcom,geni-i2c"; 900 reg = <0x0 0x0088c000 0x0 0x4000>; 901 902 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 903 904 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 905 clock-names = "se"; 906 907 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 908 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 909 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 910 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 911 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 912 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 913 interconnect-names = "qup-core", 914 "qup-config", 915 "qup-memory"; 916 917 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 918 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 919 dma-names = "tx", 920 "rx"; 921 922 pinctrl-0 = <&qup_i2c11_data_clk>; 923 pinctrl-names = "default"; 924 925 #address-cells = <1>; 926 #size-cells = <0>; 927 928 status = "disabled"; 929 }; 930 931 spi11: spi@88c000 { 932 compatible = "qcom,geni-spi"; 933 reg = <0x0 0x0088c000 0x0 0x4000>; 934 935 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 936 937 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 938 clock-names = "se"; 939 940 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 941 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 942 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 943 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 944 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 945 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 946 interconnect-names = "qup-core", 947 "qup-config", 948 "qup-memory"; 949 950 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 951 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 952 dma-names = "tx", 953 "rx"; 954 955 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 956 pinctrl-names = "default"; 957 958 #address-cells = <1>; 959 #size-cells = <0>; 960 961 status = "disabled"; 962 }; 963 964 i2c12: i2c@890000 { 965 compatible = "qcom,geni-i2c"; 966 reg = <0x0 0x00890000 0x0 0x4000>; 967 968 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 969 970 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 971 clock-names = "se"; 972 973 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 974 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 975 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 976 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 977 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 978 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 979 interconnect-names = "qup-core", 980 "qup-config", 981 "qup-memory"; 982 983 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 984 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 985 dma-names = "tx", 986 "rx"; 987 988 pinctrl-0 = <&qup_i2c12_data_clk>; 989 pinctrl-names = "default"; 990 991 #address-cells = <1>; 992 #size-cells = <0>; 993 994 status = "disabled"; 995 }; 996 997 spi12: spi@890000 { 998 compatible = "qcom,geni-spi"; 999 reg = <0x0 0x00890000 0x0 0x4000>; 1000 1001 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1002 1003 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 1004 clock-names = "se"; 1005 1006 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1007 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1008 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1009 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1010 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1011 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1012 interconnect-names = "qup-core", 1013 "qup-config", 1014 "qup-memory"; 1015 1016 dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, 1017 <&gpi_dma2 1 4 QCOM_GPI_SPI>; 1018 dma-names = "tx", 1019 "rx"; 1020 1021 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1022 pinctrl-names = "default"; 1023 1024 #address-cells = <1>; 1025 #size-cells = <0>; 1026 1027 status = "disabled"; 1028 }; 1029 1030 i2c13: i2c@894000 { 1031 compatible = "qcom,geni-i2c"; 1032 reg = <0x0 0x00894000 0x0 0x4000>; 1033 1034 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1035 1036 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1037 clock-names = "se"; 1038 1039 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1040 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1041 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1042 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1043 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1044 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1045 interconnect-names = "qup-core", 1046 "qup-config", 1047 "qup-memory"; 1048 1049 dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, 1050 <&gpi_dma2 1 5 QCOM_GPI_I2C>; 1051 dma-names = "tx", 1052 "rx"; 1053 1054 pinctrl-0 = <&qup_i2c13_data_clk>; 1055 pinctrl-names = "default"; 1056 1057 #address-cells = <1>; 1058 #size-cells = <0>; 1059 1060 status = "disabled"; 1061 }; 1062 1063 spi13: spi@894000 { 1064 compatible = "qcom,geni-spi"; 1065 reg = <0x0 0x00894000 0x0 0x4000>; 1066 1067 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1068 1069 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 1070 clock-names = "se"; 1071 1072 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1073 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1074 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1075 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1076 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1077 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1078 interconnect-names = "qup-core", 1079 "qup-config", 1080 "qup-memory"; 1081 1082 dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, 1083 <&gpi_dma2 1 5 QCOM_GPI_SPI>; 1084 dma-names = "tx", 1085 "rx"; 1086 1087 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1088 pinctrl-names = "default"; 1089 1090 #address-cells = <1>; 1091 #size-cells = <0>; 1092 1093 status = "disabled"; 1094 }; 1095 1096 uart14: serial@898000 { 1097 compatible = "qcom,geni-uart"; 1098 reg = <0x0 0x00898000 0x0 0x4000>; 1099 1100 interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 1101 1102 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; 1103 clock-names = "se"; 1104 1105 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1106 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1107 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1108 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 1109 interconnect-names = "qup-core", 1110 "qup-config"; 1111 1112 pinctrl-0 = <&qup_uart14_default>; 1113 pinctrl-names = "default"; 1114 1115 status = "disabled"; 1116 }; 1117 1118 i2c15: i2c@89c000 { 1119 compatible = "qcom,geni-i2c"; 1120 reg = <0x0 0x0089c000 0x0 0x4000>; 1121 1122 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1123 1124 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1125 clock-names = "se"; 1126 1127 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1128 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1129 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1130 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1131 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1132 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1133 interconnect-names = "qup-core", 1134 "qup-config", 1135 "qup-memory"; 1136 1137 dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>, 1138 <&gpi_dma2 1 7 QCOM_GPI_I2C>; 1139 dma-names = "tx", 1140 "rx"; 1141 1142 pinctrl-0 = <&qup_i2c15_data_clk>; 1143 pinctrl-names = "default"; 1144 1145 #address-cells = <1>; 1146 #size-cells = <0>; 1147 1148 status = "disabled"; 1149 }; 1150 1151 spi15: spi@89c000 { 1152 compatible = "qcom,geni-spi"; 1153 reg = <0x0 0x0089c000 0x0 0x4000>; 1154 1155 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 1156 1157 clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; 1158 clock-names = "se"; 1159 1160 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1161 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1162 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1163 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, 1164 <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 1165 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1166 interconnect-names = "qup-core", 1167 "qup-config", 1168 "qup-memory"; 1169 1170 dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>, 1171 <&gpi_dma2 1 7 QCOM_GPI_SPI>; 1172 dma-names = "tx", 1173 "rx"; 1174 1175 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1176 pinctrl-names = "default"; 1177 1178 #address-cells = <1>; 1179 #size-cells = <0>; 1180 1181 status = "disabled"; 1182 }; 1183 }; 1184 1185 i2c_master_hub_0: geniqup@9c0000 { 1186 compatible = "qcom,geni-se-i2c-master-hub"; 1187 reg = <0x0 0x009c0000 0x0 0x2000>; 1188 1189 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 1190 clock-names = "s-ahb"; 1191 1192 #address-cells = <2>; 1193 #size-cells = <2>; 1194 ranges; 1195 1196 status = "disabled"; 1197 1198 i2c_hub_0: i2c@980000 { 1199 compatible = "qcom,geni-i2c-master-hub"; 1200 reg = <0x0 0x00980000 0x0 0x4000>; 1201 1202 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 1203 1204 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 1205 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1206 clock-names = "se", 1207 "core"; 1208 1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1210 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1211 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1212 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1213 interconnect-names = "qup-core", 1214 "qup-config"; 1215 1216 pinctrl-0 = <&hub_i2c0_data_clk>; 1217 pinctrl-names = "default"; 1218 1219 #address-cells = <1>; 1220 #size-cells = <0>; 1221 1222 status = "disabled"; 1223 }; 1224 1225 i2c_hub_1: i2c@984000 { 1226 compatible = "qcom,geni-i2c-master-hub"; 1227 reg = <0x0 0x00984000 0x0 0x4000>; 1228 1229 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 1230 1231 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 1232 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1233 clock-names = "se", 1234 "core"; 1235 1236 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1237 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1238 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1239 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1240 interconnect-names = "qup-core", 1241 "qup-config"; 1242 1243 pinctrl-0 = <&hub_i2c1_data_clk>; 1244 pinctrl-names = "default"; 1245 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 1249 status = "disabled"; 1250 }; 1251 1252 i2c_hub_2: i2c@988000 { 1253 compatible = "qcom,geni-i2c-master-hub"; 1254 reg = <0x0 0x00988000 0x0 0x4000>; 1255 1256 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 1257 1258 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 1259 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1260 clock-names = "se", 1261 "core"; 1262 1263 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1264 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1265 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1266 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1267 interconnect-names = "qup-core", 1268 "qup-config"; 1269 1270 pinctrl-0 = <&hub_i2c2_data_clk>; 1271 pinctrl-names = "default"; 1272 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 1276 status = "disabled"; 1277 }; 1278 1279 i2c_hub_3: i2c@98c000 { 1280 compatible = "qcom,geni-i2c-master-hub"; 1281 reg = <0x0 0x0098c000 0x0 0x4000>; 1282 1283 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 1284 1285 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 1286 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1287 clock-names = "se", 1288 "core"; 1289 1290 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1291 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1292 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1293 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1294 interconnect-names = "qup-core", 1295 "qup-config"; 1296 1297 pinctrl-0 = <&hub_i2c3_data_clk>; 1298 pinctrl-names = "default"; 1299 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 1303 status = "disabled"; 1304 }; 1305 1306 i2c_hub_4: i2c@990000 { 1307 compatible = "qcom,geni-i2c-master-hub"; 1308 reg = <0x0 0x00990000 0x0 0x4000>; 1309 1310 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 1311 1312 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 1313 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1314 clock-names = "se", 1315 "core"; 1316 1317 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1318 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1319 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1320 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1321 interconnect-names = "qup-core", 1322 "qup-config"; 1323 1324 pinctrl-0 = <&hub_i2c4_data_clk>; 1325 pinctrl-names = "default"; 1326 1327 #address-cells = <1>; 1328 #size-cells = <0>; 1329 1330 status = "disabled"; 1331 }; 1332 1333 i2c_hub_5: i2c@994000 { 1334 compatible = "qcom,geni-i2c-master-hub"; 1335 reg = <0x0 0x00994000 0x0 0x4000>; 1336 1337 interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; 1338 1339 clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, 1340 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1341 clock-names = "se", 1342 "core"; 1343 1344 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1345 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1346 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1347 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1348 interconnect-names = "qup-core", 1349 "qup-config"; 1350 1351 pinctrl-0 = <&hub_i2c5_data_clk>; 1352 pinctrl-names = "default"; 1353 1354 #address-cells = <1>; 1355 #size-cells = <0>; 1356 1357 status = "disabled"; 1358 }; 1359 1360 i2c_hub_6: i2c@998000 { 1361 compatible = "qcom,geni-i2c-master-hub"; 1362 reg = <0x0 0x00998000 0x0 0x4000>; 1363 1364 interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; 1365 1366 clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, 1367 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1368 clock-names = "se", 1369 "core"; 1370 1371 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1372 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1373 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1374 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1375 interconnect-names = "qup-core", 1376 "qup-config"; 1377 1378 pinctrl-0 = <&hub_i2c6_data_clk>; 1379 pinctrl-names = "default"; 1380 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 1384 status = "disabled"; 1385 }; 1386 1387 i2c_hub_7: i2c@99c000 { 1388 compatible = "qcom,geni-i2c-master-hub"; 1389 reg = <0x0 0x0099c000 0x0 0x4000>; 1390 1391 interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 1392 1393 clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, 1394 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1395 clock-names = "se", 1396 "core"; 1397 1398 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1399 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1400 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1401 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1402 interconnect-names = "qup-core", 1403 "qup-config"; 1404 1405 pinctrl-0 = <&hub_i2c7_data_clk>; 1406 pinctrl-names = "default"; 1407 1408 #address-cells = <1>; 1409 #size-cells = <0>; 1410 1411 status = "disabled"; 1412 }; 1413 1414 i2c_hub_8: i2c@9a0000 { 1415 compatible = "qcom,geni-i2c-master-hub"; 1416 reg = <0x0 0x009a0000 0x0 0x4000>; 1417 1418 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; 1419 1420 clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, 1421 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1422 clock-names = "se", 1423 "core"; 1424 1425 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1426 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1427 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1428 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1429 interconnect-names = "qup-core", 1430 "qup-config"; 1431 1432 pinctrl-0 = <&hub_i2c8_data_clk>; 1433 pinctrl-names = "default"; 1434 1435 #address-cells = <1>; 1436 #size-cells = <0>; 1437 1438 status = "disabled"; 1439 }; 1440 1441 i2c_hub_9: i2c@9a4000 { 1442 compatible = "qcom,geni-i2c-master-hub"; 1443 reg = <0x0 0x009a4000 0x0 0x4000>; 1444 1445 interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; 1446 1447 clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, 1448 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 1449 clock-names = "se", 1450 "core"; 1451 1452 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1453 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1454 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1455 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 1456 interconnect-names = "qup-core", 1457 "qup-config"; 1458 1459 pinctrl-0 = <&hub_i2c9_data_clk>; 1460 pinctrl-names = "default"; 1461 1462 #address-cells = <1>; 1463 #size-cells = <0>; 1464 1465 status = "disabled"; 1466 }; 1467 }; 1468 1469 gpi_dma1: dma-controller@a00000 { 1470 compatible = "qcom,sm8750-gpi-dma", "qcom,sm6350-gpi-dma"; 1471 reg = <0x0 0x00a00000 0x0 0x60000>; 1472 1473 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1485 1486 dma-channels = <12>; 1487 dma-channel-mask = <0x1e>; 1488 #dma-cells = <3>; 1489 1490 iommus = <&apps_smmu 0xb6 0x0>; 1491 1492 status = "disabled"; 1493 }; 1494 1495 qupv3_1: geniqup@ac0000 { 1496 compatible = "qcom,geni-se-qup"; 1497 reg = <0x0 0x00ac0000 0x0 0x2000>; 1498 1499 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1500 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1501 clock-names = "m-ahb", 1502 "s-ahb"; 1503 1504 iommus = <&apps_smmu 0xa3 0x0>; 1505 1506 #address-cells = <2>; 1507 #size-cells = <2>; 1508 ranges; 1509 1510 status = "disabled"; 1511 1512 i2c0: i2c@a80000 { 1513 compatible = "qcom,geni-i2c"; 1514 reg = <0x0 0x00a80000 0x0 0x4000>; 1515 1516 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1517 1518 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1519 clock-names = "se"; 1520 1521 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1522 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1523 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1524 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1525 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1526 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1527 interconnect-names = "qup-core", 1528 "qup-config", 1529 "qup-memory"; 1530 1531 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1532 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1533 dma-names = "tx", 1534 "rx"; 1535 1536 pinctrl-0 = <&qup_i2c0_data_clk>; 1537 pinctrl-names = "default"; 1538 1539 #address-cells = <1>; 1540 #size-cells = <0>; 1541 1542 status = "disabled"; 1543 }; 1544 1545 spi0: spi@a80000 { 1546 compatible = "qcom,geni-spi"; 1547 reg = <0x0 0x00a80000 0x0 0x4000>; 1548 1549 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1550 1551 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1552 clock-names = "se"; 1553 1554 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1555 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1556 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1557 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1558 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1559 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1560 interconnect-names = "qup-core", 1561 "qup-config", 1562 "qup-memory"; 1563 1564 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1565 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1566 dma-names = "tx", 1567 "rx"; 1568 1569 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1570 pinctrl-names = "default"; 1571 1572 #address-cells = <1>; 1573 #size-cells = <0>; 1574 1575 status = "disabled"; 1576 }; 1577 1578 i2c1: i2c@a84000 { 1579 compatible = "qcom,geni-i2c"; 1580 reg = <0x0 0x00a84000 0x0 0x4000>; 1581 1582 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1583 1584 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1585 clock-names = "se"; 1586 1587 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1588 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1589 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1590 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1591 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1592 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1593 interconnect-names = "qup-core", 1594 "qup-config", 1595 "qup-memory"; 1596 1597 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1598 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1599 dma-names = "tx", 1600 "rx"; 1601 1602 pinctrl-0 = <&qup_i2c1_data_clk>; 1603 pinctrl-names = "default"; 1604 1605 #address-cells = <1>; 1606 #size-cells = <0>; 1607 1608 status = "disabled"; 1609 }; 1610 1611 spi1: spi@a84000 { 1612 compatible = "qcom,geni-spi"; 1613 reg = <0x0 0x00a84000 0x0 0x4000>; 1614 1615 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1616 1617 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1618 clock-names = "se"; 1619 1620 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1621 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1622 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1623 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1624 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1625 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1626 interconnect-names = "qup-core", 1627 "qup-config", 1628 "qup-memory"; 1629 1630 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1631 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1632 dma-names = "tx", 1633 "rx"; 1634 1635 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1636 pinctrl-names = "default"; 1637 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 1641 status = "disabled"; 1642 }; 1643 1644 i2c2: i2c@a88000 { 1645 compatible = "qcom,geni-i2c"; 1646 reg = <0x0 0x00a88000 0x0 0x4000>; 1647 1648 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1649 1650 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1651 clock-names = "se"; 1652 1653 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1654 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1655 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1656 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1657 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1658 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1659 interconnect-names = "qup-core", 1660 "qup-config", 1661 "qup-memory"; 1662 1663 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1664 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1665 dma-names = "tx", 1666 "rx"; 1667 1668 pinctrl-0 = <&qup_i2c2_data_clk>; 1669 pinctrl-names = "default"; 1670 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 1674 status = "disabled"; 1675 }; 1676 1677 spi2: spi@a88000 { 1678 compatible = "qcom,geni-spi"; 1679 reg = <0x0 0x00a88000 0x0 0x4000>; 1680 1681 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1682 1683 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1684 clock-names = "se"; 1685 1686 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1687 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1688 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1689 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1690 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1691 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1692 interconnect-names = "qup-core", 1693 "qup-config", 1694 "qup-memory"; 1695 1696 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1697 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1698 dma-names = "tx", 1699 "rx"; 1700 1701 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1702 pinctrl-names = "default"; 1703 1704 #address-cells = <1>; 1705 #size-cells = <0>; 1706 1707 status = "disabled"; 1708 }; 1709 1710 i2c3: i2c@a8c000 { 1711 compatible = "qcom,geni-i2c"; 1712 reg = <0x0 0x00a8c000 0x0 0x4000>; 1713 1714 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1715 1716 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1717 clock-names = "se"; 1718 1719 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1720 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1721 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1722 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1723 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1724 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1725 interconnect-names = "qup-core", 1726 "qup-config", 1727 "qup-memory"; 1728 1729 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1730 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1731 dma-names = "tx", 1732 "rx"; 1733 1734 pinctrl-0 = <&qup_i2c3_data_clk>; 1735 pinctrl-names = "default"; 1736 1737 #address-cells = <1>; 1738 #size-cells = <0>; 1739 1740 status = "disabled"; 1741 }; 1742 1743 spi3: spi@a8c000 { 1744 compatible = "qcom,geni-spi"; 1745 reg = <0x0 0x00a8c000 0x0 0x4000>; 1746 1747 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1748 1749 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1750 clock-names = "se"; 1751 1752 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1753 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1754 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1755 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1756 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1757 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1758 interconnect-names = "qup-core", 1759 "qup-config", 1760 "qup-memory"; 1761 1762 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1763 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1764 dma-names = "tx", 1765 "rx"; 1766 1767 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1768 pinctrl-names = "default"; 1769 1770 #address-cells = <1>; 1771 #size-cells = <0>; 1772 1773 status = "disabled"; 1774 }; 1775 1776 i2c4: i2c@a90000 { 1777 compatible = "qcom,geni-i2c"; 1778 reg = <0x0 0x00a90000 0x0 0x4000>; 1779 1780 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1781 1782 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1783 clock-names = "se"; 1784 1785 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1786 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1787 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1788 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1789 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1790 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1791 interconnect-names = "qup-core", 1792 "qup-config", 1793 "qup-memory"; 1794 1795 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1796 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1797 dma-names = "tx", 1798 "rx"; 1799 1800 pinctrl-0 = <&qup_i2c4_data_clk>; 1801 pinctrl-names = "default"; 1802 1803 #address-cells = <1>; 1804 #size-cells = <0>; 1805 1806 status = "disabled"; 1807 }; 1808 1809 spi4: spi@a90000 { 1810 compatible = "qcom,geni-spi"; 1811 reg = <0x0 0x00a90000 0x0 0x4000>; 1812 1813 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1814 1815 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1816 clock-names = "se"; 1817 1818 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1819 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1820 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1821 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1822 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1823 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1824 interconnect-names = "qup-core", 1825 "qup-config", 1826 "qup-memory"; 1827 1828 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1829 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1830 dma-names = "tx", 1831 "rx"; 1832 1833 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1834 pinctrl-names = "default"; 1835 1836 #address-cells = <1>; 1837 #size-cells = <0>; 1838 1839 status = "disabled"; 1840 }; 1841 1842 i2c5: i2c@a94000 { 1843 compatible = "qcom,geni-i2c"; 1844 reg = <0x0 0x00a94000 0x0 0x4000>; 1845 1846 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1847 1848 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1849 clock-names = "se"; 1850 1851 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1852 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1853 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1854 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1855 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1856 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1857 interconnect-names = "qup-core", 1858 "qup-config", 1859 "qup-memory"; 1860 1861 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1862 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1863 dma-names = "tx", 1864 "rx"; 1865 1866 pinctrl-0 = <&qup_i2c5_data_clk>; 1867 pinctrl-names = "default"; 1868 1869 #address-cells = <1>; 1870 #size-cells = <0>; 1871 1872 status = "disabled"; 1873 }; 1874 1875 spi5: spi@a94000 { 1876 compatible = "qcom,geni-spi"; 1877 reg = <0x0 0x00a94000 0x0 0x4000>; 1878 1879 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1880 1881 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1882 clock-names = "se"; 1883 1884 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1885 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1886 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1887 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1888 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1889 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1890 interconnect-names = "qup-core", 1891 "qup-config", 1892 "qup-memory"; 1893 1894 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1895 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1896 dma-names = "tx", 1897 "rx"; 1898 1899 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1900 pinctrl-names = "default"; 1901 1902 #address-cells = <1>; 1903 #size-cells = <0>; 1904 1905 status = "disabled"; 1906 }; 1907 1908 i2c6: i2c@a98000 { 1909 compatible = "qcom,geni-i2c"; 1910 reg = <0x0 0x00a98000 0x0 0x4000>; 1911 1912 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1913 1914 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1915 clock-names = "se"; 1916 1917 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1918 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1919 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1920 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1921 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1922 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1923 interconnect-names = "qup-core", 1924 "qup-config", 1925 "qup-memory"; 1926 1927 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1928 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1929 dma-names = "tx", 1930 "rx"; 1931 1932 pinctrl-0 = <&qup_i2c6_data_clk>; 1933 pinctrl-names = "default"; 1934 1935 #address-cells = <1>; 1936 #size-cells = <0>; 1937 1938 status = "disabled"; 1939 }; 1940 1941 spi6: spi@a98000 { 1942 compatible = "qcom,geni-spi"; 1943 reg = <0x0 0x00a98000 0x0 0x4000>; 1944 1945 interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; 1946 1947 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1948 clock-names = "se"; 1949 1950 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1951 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1952 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1953 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1954 <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1955 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1956 interconnect-names = "qup-core", 1957 "qup-config", 1958 "qup-memory"; 1959 1960 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1961 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1962 dma-names = "tx", 1963 "rx"; 1964 1965 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1966 pinctrl-names = "default"; 1967 1968 #address-cells = <1>; 1969 #size-cells = <0>; 1970 1971 status = "disabled"; 1972 }; 1973 1974 uart7: serial@a9c000 { 1975 compatible = "qcom,geni-debug-uart"; 1976 reg = <0x0 0x00a9c000 0x0 0x4000>; 1977 1978 interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; 1979 1980 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1981 clock-names = "se"; 1982 1983 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1984 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1985 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1986 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1987 interconnect-names = "qup-core", 1988 "qup-config"; 1989 1990 pinctrl-0 = <&qup_uart7_default>; 1991 pinctrl-names = "default"; 1992 1993 status = "disabled"; 1994 }; 1995 }; 1996 1997 rng: rng@10c3000 { 1998 compatible = "qcom,sm8750-trng", "qcom,trng"; 1999 reg = <0x0 0x010c3000 0x0 0x1000>; 2000 }; 2001 2002 cnoc_main: interconnect@1500000 { 2003 compatible = "qcom,sm8750-cnoc-main"; 2004 reg = <0x0 0x01500000 0x0 0x16080>; 2005 qcom,bcm-voters = <&apps_bcm_voter>; 2006 #interconnect-cells = <2>; 2007 }; 2008 2009 config_noc: interconnect@1600000 { 2010 compatible = "qcom,sm8750-config-noc"; 2011 reg = <0x0 0x01600000 0x0 0x6200>; 2012 qcom,bcm-voters = <&apps_bcm_voter>; 2013 #interconnect-cells = <2>; 2014 }; 2015 2016 system_noc: interconnect@1680000 { 2017 compatible = "qcom,sm8750-system-noc"; 2018 reg = <0x0 0x01680000 0x0 0x1d080>; 2019 qcom,bcm-voters = <&apps_bcm_voter>; 2020 #interconnect-cells = <2>; 2021 }; 2022 2023 pcie_noc: interconnect@16c0000 { 2024 compatible = "qcom,sm8750-pcie-anoc"; 2025 reg = <0x0 0x016c0000 0x0 0x11400>; 2026 qcom,bcm-voters = <&apps_bcm_voter>; 2027 #interconnect-cells = <2>; 2028 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2029 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2030 }; 2031 2032 aggre1_noc: interconnect@16e0000 { 2033 compatible = "qcom,sm8750-aggre1-noc"; 2034 reg = <0x0 0x016e0000 0x0 0x16400>; 2035 qcom,bcm-voters = <&apps_bcm_voter>; 2036 #interconnect-cells = <2>; 2037 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2038 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2039 }; 2040 2041 aggre2_noc: interconnect@1700000 { 2042 compatible = "qcom,sm8750-aggre2-noc"; 2043 reg = <0x0 0x01700000 0x0 0x1f400>; 2044 qcom,bcm-voters = <&apps_bcm_voter>; 2045 #interconnect-cells = <2>; 2046 clocks = <&rpmhcc RPMH_IPA_CLK>; 2047 }; 2048 2049 mmss_noc: interconnect@1780000 { 2050 compatible = "qcom,sm8750-mmss-noc"; 2051 reg = <0x0 0x01780000 0x0 0x5b800>; 2052 qcom,bcm-voters = <&apps_bcm_voter>; 2053 #interconnect-cells = <2>; 2054 }; 2055 2056 ice: crypto@1d88000 { 2057 compatible = "qcom,sm8750-inline-crypto-engine", 2058 "qcom,inline-crypto-engine"; 2059 reg = <0x0 0x01d88000 0x0 0x18000>; 2060 2061 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2062 }; 2063 2064 cryptobam: dma-controller@1dc4000 { 2065 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2066 reg = <0x0 0x01dc4000 0x0 0x28000>; 2067 2068 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2069 2070 #dma-cells = <1>; 2071 2072 iommus = <&apps_smmu 0x480 0>, 2073 <&apps_smmu 0x481 0>; 2074 2075 qcom,ee = <0>; 2076 qcom,num-ees = <4>; 2077 num-channels = <20>; 2078 qcom,controlled-remotely; 2079 }; 2080 2081 crypto: crypto@1dfa000 { 2082 compatible = "qcom,sm8750-qce", "qcom,sm8150-qce", "qcom,qce"; 2083 reg = <0x0 0x01dfa000 0x0 0x6000>; 2084 2085 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 2086 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2087 interconnect-names = "memory"; 2088 2089 dmas = <&cryptobam 4>, <&cryptobam 5>; 2090 dma-names = "rx", "tx"; 2091 2092 iommus = <&apps_smmu 0x480 0>, 2093 <&apps_smmu 0x481 0>; 2094 }; 2095 2096 tcsr_mutex: hwlock@1f40000 { 2097 compatible = "qcom,tcsr-mutex"; 2098 reg = <0x0 0x01f40000 0x0 0x20000>; 2099 #hwlock-cells = <1>; 2100 }; 2101 2102 remoteproc_mpss: remoteproc@4080000 { 2103 compatible = "qcom,sm8750-mpss-pas"; 2104 reg = <0x0 0x04080000 0x0 0x10000>; 2105 2106 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 2107 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 2108 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 2109 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 2110 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, 2111 <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; 2112 interrupt-names = "wdog", 2113 "fatal", 2114 "ready", 2115 "handover", 2116 "stop-ack", 2117 "shutdown-ack"; 2118 2119 clocks = <&rpmhcc RPMH_CXO_CLK>; 2120 clock-names = "xo"; 2121 2122 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS 2123 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2124 2125 power-domains = <&rpmhpd RPMHPD_CX>, 2126 <&rpmhpd RPMHPD_MSS>; 2127 power-domain-names = "cx", 2128 "mss"; 2129 2130 memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, 2131 <&dsm_partition_1_mem>, 2132 <&dsm_partition_2_mem>; 2133 2134 qcom,qmp = <&aoss_qmp>; 2135 2136 qcom,smem-states = <&smp2p_modem_out 0>; 2137 qcom,smem-state-names = "stop"; 2138 2139 status = "disabled"; 2140 2141 glink-edge { 2142 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 2143 IPCC_MPROC_SIGNAL_GLINK_QMP 2144 IRQ_TYPE_EDGE_RISING>; 2145 2146 mboxes = <&ipcc IPCC_CLIENT_MPSS 2147 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2148 2149 qcom,remote-pid = <1>; 2150 2151 label = "mpss"; 2152 }; 2153 }; 2154 2155 remoteproc_adsp: remoteproc@6800000 { 2156 compatible = "qcom,sm8750-adsp-pas", "qcom,sm8550-adsp-pas"; 2157 reg = <0x0 0x06800000 0x0 0x10000>; 2158 2159 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2160 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2161 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2162 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2163 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2164 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2165 interrupt-names = "wdog", 2166 "fatal", 2167 "ready", 2168 "handover", 2169 "stop-ack", 2170 "shutdown-ack"; 2171 2172 clocks = <&rpmhcc RPMH_CXO_CLK>; 2173 clock-names = "xo"; 2174 2175 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2176 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2177 2178 power-domains = <&rpmhpd RPMHPD_LCX>, 2179 <&rpmhpd RPMHPD_LMX>; 2180 power-domain-names = "lcx", 2181 "lmx"; 2182 2183 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2184 2185 qcom,qmp = <&aoss_qmp>; 2186 2187 qcom,smem-states = <&smp2p_adsp_out 0>; 2188 qcom,smem-state-names = "stop"; 2189 2190 status = "disabled"; 2191 2192 remoteproc_adsp_glink: glink-edge { 2193 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2194 IPCC_MPROC_SIGNAL_GLINK_QMP 2195 IRQ_TYPE_EDGE_RISING>; 2196 mboxes = <&ipcc IPCC_CLIENT_LPASS 2197 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2198 qcom,remote-pid = <2>; 2199 label = "lpass"; 2200 2201 gpr { 2202 compatible = "qcom,gpr"; 2203 qcom,glink-channels = "adsp_apps"; 2204 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2205 qcom,intents = <512 20>; 2206 #address-cells = <1>; 2207 #size-cells = <0>; 2208 2209 q6apm: service@1 { 2210 compatible = "qcom,q6apm"; 2211 reg = <GPR_APM_MODULE_IID>; 2212 #sound-dai-cells = <0>; 2213 qcom,protection-domain = "avs/audio", 2214 "msm/adsp/audio_pd"; 2215 2216 q6apmbedai: bedais { 2217 compatible = "qcom,q6apm-lpass-dais"; 2218 #sound-dai-cells = <1>; 2219 }; 2220 2221 q6apmdai: dais { 2222 compatible = "qcom,q6apm-dais"; 2223 iommus = <&apps_smmu 0x1001 0x80>, 2224 <&apps_smmu 0x1041 0x20>; 2225 }; 2226 }; 2227 2228 q6prm: service@2 { 2229 compatible = "qcom,q6prm"; 2230 reg = <GPR_PRM_MODULE_IID>; 2231 qcom,protection-domain = "avs/audio", 2232 "msm/adsp/audio_pd"; 2233 2234 q6prmcc: clock-controller { 2235 compatible = "qcom,q6prm-lpass-clocks"; 2236 #clock-cells = <2>; 2237 }; 2238 }; 2239 }; 2240 }; 2241 }; 2242 2243 lpass_wsa2macro: codec@6aa0000 { 2244 compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2245 reg = <0x0 0x06aa0000 0x0 0x1000>; 2246 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2247 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2248 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2249 <&lpass_vamacro>; 2250 clock-names = "mclk", 2251 "macro", 2252 "dcodec", 2253 "fsgen"; 2254 2255 #clock-cells = <0>; 2256 clock-output-names = "wsa2-mclk"; 2257 #sound-dai-cells = <1>; 2258 }; 2259 2260 swr3: soundwire@6ab0000 { 2261 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2262 reg = <0x0 0x06ab0000 0x0 0x10000>; 2263 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2264 clocks = <&lpass_wsa2macro>; 2265 clock-names = "iface"; 2266 label = "WSA2"; 2267 2268 pinctrl-0 = <&wsa2_swr_active>; 2269 pinctrl-names = "default"; 2270 2271 qcom,din-ports = <4>; 2272 qcom,dout-ports = <9>; 2273 2274 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>; 2275 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>; 2276 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2277 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2278 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2279 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>; 2280 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>; 2281 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2282 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2283 2284 #address-cells = <2>; 2285 #size-cells = <0>; 2286 #sound-dai-cells = <1>; 2287 status = "disabled"; 2288 }; 2289 2290 lpass_rxmacro: codec@6ac0000 { 2291 compatible = "qcom,sm8750-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 2292 reg = <0x0 0x06ac0000 0x0 0x1000>; 2293 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2294 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2295 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2296 <&lpass_vamacro>; 2297 clock-names = "mclk", 2298 "macro", 2299 "dcodec", 2300 "fsgen"; 2301 2302 #clock-cells = <0>; 2303 clock-output-names = "mclk"; 2304 #sound-dai-cells = <1>; 2305 }; 2306 2307 swr1: soundwire@6ad0000 { 2308 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2309 reg = <0x0 0x06ad0000 0x0 0x10000>; 2310 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2311 clocks = <&lpass_rxmacro>; 2312 clock-names = "iface"; 2313 label = "RX"; 2314 2315 pinctrl-0 = <&rx_swr_active>; 2316 pinctrl-names = "default"; 2317 2318 qcom,din-ports = <1>; 2319 qcom,dout-ports = <11>; 2320 2321 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0x31 0xff 0xff 0xff>; 2322 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2323 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2324 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0x00 0xff 0xff 0xff>; 2325 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0x0f 0xff 0xff 0xff>; 2326 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0x18 0xff 0xff 0xff>; 2327 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 2328 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0x00 0xff 0xff 0xff>; 2329 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0x01 0xff 0xff 0xff>; 2330 2331 #address-cells = <2>; 2332 #size-cells = <0>; 2333 #sound-dai-cells = <1>; 2334 status = "disabled"; 2335 }; 2336 2337 lpass_txmacro: codec@6ae0000 { 2338 compatible = "qcom,sm8750-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 2339 reg = <0x0 0x06ae0000 0x0 0x1000>; 2340 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2341 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2342 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2343 <&lpass_vamacro>; 2344 clock-names = "mclk", 2345 "macro", 2346 "dcodec", 2347 "fsgen"; 2348 2349 #clock-cells = <0>; 2350 clock-output-names = "mclk"; 2351 #sound-dai-cells = <1>; 2352 }; 2353 2354 lpass_wsamacro: codec@6b00000 { 2355 compatible = "qcom,sm8750-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro"; 2356 reg = <0x0 0x06b00000 0x0 0x1000>; 2357 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2358 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2359 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2360 <&lpass_vamacro>; 2361 clock-names = "mclk", 2362 "macro", 2363 "dcodec", 2364 "fsgen"; 2365 2366 #clock-cells = <0>; 2367 clock-output-names = "mclk"; 2368 #sound-dai-cells = <1>; 2369 }; 2370 2371 swr0: soundwire@6b10000 { 2372 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2373 reg = <0x0 0x06b10000 0x0 0x10000>; 2374 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2375 clocks = <&lpass_wsamacro>; 2376 clock-names = "iface"; 2377 label = "WSA"; 2378 2379 pinctrl-0 = <&wsa_swr_active>; 2380 pinctrl-names = "default"; 2381 2382 qcom,din-ports = <4>; 2383 qcom,dout-ports = <9>; 2384 2385 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0x18f 0x18f 0x0f 0x0f 0xff 0x31f>; 2386 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0x00 0x00 0x06 0x0d 0xff 0x00>; 2387 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2388 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2389 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0e 0x0e 0xff 0xff 0xff 0x0f>; 2390 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0x0f 0x0f 0x00 0xff 0xff 0x18>; 2391 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x01 0x01 0x01 0x01 0x00 0x00>; 2392 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2393 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff>; 2394 2395 #address-cells = <2>; 2396 #size-cells = <0>; 2397 #sound-dai-cells = <1>; 2398 status = "disabled"; 2399 }; 2400 2401 lpass_ag_noc: interconnect@7e40000 { 2402 compatible = "qcom,sm8750-lpass-ag-noc"; 2403 reg = <0x0 0x07e40000 0x0 0xe080>; 2404 qcom,bcm-voters = <&apps_bcm_voter>; 2405 #interconnect-cells = <2>; 2406 }; 2407 2408 lpass_lpiaon_noc: interconnect@7400000 { 2409 compatible = "qcom,sm8750-lpass-lpiaon-noc"; 2410 reg = <0x0 0x07400000 0x0 0x19080>; 2411 qcom,bcm-voters = <&apps_bcm_voter>; 2412 #interconnect-cells = <2>; 2413 }; 2414 2415 lpass_lpicx_noc: interconnect@7420000 { 2416 compatible = "qcom,sm8750-lpass-lpicx-noc"; 2417 reg = <0x0 0x07420000 0x0 0x44080>; 2418 qcom,bcm-voters = <&apps_bcm_voter>; 2419 #interconnect-cells = <2>; 2420 }; 2421 2422 swr2: soundwire@7630000 { 2423 compatible = "qcom,soundwire-v2.1.0", "qcom,soundwire-v2.0.0"; 2424 reg = <0x0 0x07630000 0x0 0x10000>; 2425 interrupts = <GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 2426 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 2427 interrupt-names = "core", "wakeup"; 2428 clocks = <&lpass_txmacro>; 2429 clock-names = "iface"; 2430 label = "TX"; 2431 2432 pinctrl-0 = <&tx_swr_active>; 2433 pinctrl-names = "default"; 2434 2435 qcom,din-ports = <4>; 2436 qcom,dout-ports = <0>; 2437 2438 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2439 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2440 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2441 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2442 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2443 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2444 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2445 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2446 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2447 2448 #address-cells = <2>; 2449 #size-cells = <0>; 2450 #sound-dai-cells = <1>; 2451 status = "disabled"; 2452 }; 2453 2454 lpass_vamacro: codec@7660000 { 2455 compatible = "qcom,sm8750-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 2456 reg = <0x0 0x07660000 0x0 0x2000>; 2457 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2458 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2459 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2460 clock-names = "mclk", 2461 "macro", 2462 "dcodec"; 2463 2464 #clock-cells = <0>; 2465 clock-output-names = "fsgen"; 2466 #sound-dai-cells = <1>; 2467 }; 2468 2469 lpass_tlmm: pinctrl@7760000 { 2470 compatible = "qcom,sm8750-lpass-lpi-pinctrl", 2471 "qcom,sm8650-lpass-lpi-pinctrl"; 2472 reg = <0x0 0x07760000 0x0 0x20000>; 2473 2474 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2475 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2476 clock-names = "core", "audio"; 2477 2478 gpio-controller; 2479 #gpio-cells = <2>; 2480 gpio-ranges = <&lpass_tlmm 0 0 23>; 2481 2482 tx_swr_active: tx-swr-active-state { 2483 clk-pins { 2484 pins = "gpio0"; 2485 function = "swr_tx_clk"; 2486 drive-strength = <2>; 2487 slew-rate = <1>; 2488 bias-disable; 2489 }; 2490 2491 data-pins { 2492 pins = "gpio1", "gpio2", "gpio14"; 2493 function = "swr_tx_data"; 2494 drive-strength = <2>; 2495 slew-rate = <1>; 2496 bias-bus-hold; 2497 }; 2498 }; 2499 2500 rx_swr_active: rx-swr-active-state { 2501 clk-pins { 2502 pins = "gpio3"; 2503 function = "swr_rx_clk"; 2504 drive-strength = <2>; 2505 slew-rate = <1>; 2506 bias-disable; 2507 }; 2508 2509 data-pins { 2510 pins = "gpio4", "gpio5"; 2511 function = "swr_rx_data"; 2512 drive-strength = <2>; 2513 slew-rate = <1>; 2514 bias-bus-hold; 2515 }; 2516 }; 2517 2518 dmic01_default: dmic01-default-state { 2519 clk-pins { 2520 pins = "gpio6"; 2521 function = "dmic1_clk"; 2522 drive-strength = <8>; 2523 output-high; 2524 }; 2525 2526 data-pins { 2527 pins = "gpio7"; 2528 function = "dmic1_data"; 2529 drive-strength = <8>; 2530 input-enable; 2531 }; 2532 }; 2533 2534 dmic23_default: dmic23-default-state { 2535 clk-pins { 2536 pins = "gpio8"; 2537 function = "dmic2_clk"; 2538 drive-strength = <8>; 2539 output-high; 2540 }; 2541 2542 data-pins { 2543 pins = "gpio9"; 2544 function = "dmic2_data"; 2545 drive-strength = <8>; 2546 input-enable; 2547 }; 2548 }; 2549 2550 wsa_swr_active: wsa-swr-active-state { 2551 clk-pins { 2552 pins = "gpio10"; 2553 function = "wsa_swr_clk"; 2554 drive-strength = <2>; 2555 slew-rate = <1>; 2556 bias-disable; 2557 }; 2558 2559 data-pins { 2560 pins = "gpio11"; 2561 function = "wsa_swr_data"; 2562 drive-strength = <2>; 2563 slew-rate = <1>; 2564 bias-bus-hold; 2565 }; 2566 }; 2567 2568 wsa2_swr_active: wsa2-swr-active-state { 2569 clk-pins { 2570 pins = "gpio15"; 2571 function = "wsa2_swr_clk"; 2572 drive-strength = <2>; 2573 slew-rate = <1>; 2574 bias-disable; 2575 }; 2576 2577 data-pins { 2578 pins = "gpio16"; 2579 function = "wsa2_swr_data"; 2580 drive-strength = <2>; 2581 slew-rate = <1>; 2582 bias-bus-hold; 2583 }; 2584 }; 2585 }; 2586 2587 usb_hsphy: phy@88e3000 { 2588 compatible = "qcom,sm8750-m31-eusb2-phy"; 2589 reg = <0x0 0x88e3000 0x0 0x29c>; 2590 2591 clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; 2592 clock-names = "ref"; 2593 2594 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2595 2596 #phy-cells = <0>; 2597 2598 status = "disabled"; 2599 }; 2600 2601 usb_dp_qmpphy: phy@88e8000 { 2602 compatible = "qcom,sm8750-qmp-usb3-dp-phy"; 2603 reg = <0x0 0x088e8000 0x0 0x4000>; 2604 2605 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 2606 <&tcsrcc TCSR_USB3_CLKREF_EN>, 2607 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 2608 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 2609 clock-names = "aux", 2610 "ref", 2611 "com_aux", 2612 "usb3_pipe"; 2613 2614 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 2615 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; 2616 reset-names = "phy", 2617 "common"; 2618 2619 power-domains = <&gcc GCC_USB3_PHY_GDSC>; 2620 2621 #clock-cells = <1>; 2622 #phy-cells = <1>; 2623 2624 orientation-switch; 2625 2626 status = "disabled"; 2627 2628 ports { 2629 #address-cells = <1>; 2630 #size-cells = <0>; 2631 2632 port@0 { 2633 reg = <0>; 2634 2635 usb_dp_qmpphy_out: endpoint { 2636 }; 2637 }; 2638 2639 port@1 { 2640 reg = <1>; 2641 2642 usb_dp_qmpphy_usb_ss_in: endpoint { 2643 remote-endpoint = <&usb_dwc3_ss>; 2644 }; 2645 }; 2646 2647 port@2 { 2648 reg = <2>; 2649 2650 usb_dp_qmpphy_dp_in: endpoint { 2651 }; 2652 }; 2653 }; 2654 }; 2655 2656 usb: usb@a600000 { 2657 compatible = "qcom,sm8750-dwc3", "qcom,snps-dwc3"; 2658 reg = <0x0 0x0a600000 0x0 0xfc100>; 2659 2660 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 2661 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 2662 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 2663 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 2664 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 2665 clock-names = "cfg_noc", 2666 "core", 2667 "iface", 2668 "sleep", 2669 "mock_utmi"; 2670 2671 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 2672 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 2673 assigned-clock-rates = <19200000>, 2674 <200000000>; 2675 2676 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2677 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2678 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2679 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 2680 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 2681 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 2682 interrupt-names = "dwc_usb3", 2683 "pwr_event", 2684 "hs_phy_irq", 2685 "dp_hs_phy_irq", 2686 "dm_hs_phy_irq", 2687 "ss_phy_irq"; 2688 2689 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 2690 required-opps = <&rpmhpd_opp_nom>; 2691 2692 resets = <&gcc GCC_USB30_PRIM_BCR>; 2693 2694 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 2695 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2696 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2697 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2698 interconnect-names = "usb-ddr", "apps-usb"; 2699 2700 iommus = <&apps_smmu 0x40 0x0>; 2701 2702 phys = <&usb_hsphy>, 2703 <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; 2704 phy-names = "usb2-phy", 2705 "usb3-phy"; 2706 2707 snps,hird-threshold = /bits/ 8 <0x0>; 2708 snps,usb2-gadget-lpm-disable; 2709 snps,dis_u2_susphy_quirk; 2710 snps,dis_enblslpm_quirk; 2711 snps,dis-u1-entry-quirk; 2712 snps,dis-u2-entry-quirk; 2713 snps,is-utmi-l1-suspend; 2714 snps,usb3_lpm_capable; 2715 snps,usb2-lpm-disable; 2716 snps,has-lpm-erratum; 2717 tx-fifo-resize; 2718 2719 dma-coherent; 2720 usb-role-switch; 2721 2722 status = "disabled"; 2723 2724 ports { 2725 #address-cells = <1>; 2726 #size-cells = <0>; 2727 2728 port@0 { 2729 reg = <0>; 2730 2731 usb_dwc3_hs: endpoint { 2732 }; 2733 }; 2734 2735 port@1 { 2736 reg = <1>; 2737 2738 usb_dwc3_ss: endpoint { 2739 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 2740 }; 2741 }; 2742 }; 2743 }; 2744 2745 pdc: interrupt-controller@b220000 { 2746 compatible = "qcom,sm8750-pdc", "qcom,pdc"; 2747 reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; 2748 2749 qcom,pdc-ranges = <0 745 51>, <51 527 47>, 2750 <98 609 32>, <130 717 12>, 2751 <142 251 5>, <147 796 16>; 2752 #interrupt-cells = <2>; 2753 interrupt-parent = <&intc>; 2754 interrupt-controller; 2755 }; 2756 2757 aoss_qmp: power-management@c300000 { 2758 compatible = "qcom,sm8750-aoss-qmp", "qcom,aoss-qmp"; 2759 reg = <0x0 0x0c300000 0x0 0x400>; 2760 2761 interrupt-parent = <&ipcc>; 2762 interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP 2763 IRQ_TYPE_EDGE_RISING>; 2764 2765 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 2766 2767 #clock-cells = <0>; 2768 }; 2769 2770 sram@c3f0000 { 2771 compatible = "qcom,rpmh-stats"; 2772 reg = <0x0 0x0c3f0000 0x0 0x400>; 2773 qcom,qmp = <&aoss_qmp>; 2774 }; 2775 2776 spmi_bus: spmi@c400000 { 2777 compatible = "qcom,spmi-pmic-arb"; 2778 reg = <0x0 0x0c400000 0x0 0x3000>, 2779 <0x0 0x0c500000 0x0 0x400000>, 2780 <0x0 0x0c440000 0x0 0x80000>, 2781 <0x0 0x0c4c0000 0x0 0x10000>, 2782 <0x0 0x0c42d000 0x0 0x4000>; 2783 reg-names = "core", 2784 "chnls", 2785 "obsrvr", 2786 "intr", 2787 "cnfg"; 2788 2789 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 2790 interrupt-names = "periph_irq"; 2791 2792 qcom,ee = <0>; 2793 qcom,channel = <0>; 2794 qcom,bus-id = <0>; 2795 2796 interrupt-controller; 2797 #interrupt-cells = <4>; 2798 2799 #address-cells = <2>; 2800 #size-cells = <0>; 2801 }; 2802 2803 tlmm: pinctrl@f100000 { 2804 compatible = "qcom,sm8750-tlmm"; 2805 reg = <0x0 0x0f100000 0x0 0x102000>; 2806 2807 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 2808 2809 gpio-controller; 2810 #gpio-cells = <2>; 2811 2812 interrupt-controller; 2813 #interrupt-cells = <2>; 2814 2815 gpio-ranges = <&tlmm 0 0 216>; 2816 wakeup-parent = <&pdc>; 2817 2818 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 2819 /* SDA, SCL */ 2820 pins = "gpio64", "gpio65"; 2821 function = "i2chub0_se0"; 2822 drive-strength = <2>; 2823 bias-pull-up; 2824 }; 2825 2826 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 2827 /* SDA, SCL */ 2828 pins = "gpio66", "gpio67"; 2829 function = "i2chub0_se1"; 2830 drive-strength = <2>; 2831 bias-pull-up; 2832 }; 2833 2834 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 2835 /* SDA, SCL */ 2836 pins = "gpio68", "gpio69"; 2837 function = "i2chub0_se2"; 2838 drive-strength = <2>; 2839 bias-pull-up; 2840 }; 2841 2842 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 2843 /* SDA, SCL */ 2844 pins = "gpio70", "gpio71"; 2845 function = "i2chub0_se3"; 2846 drive-strength = <2>; 2847 bias-pull-up; 2848 }; 2849 2850 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 2851 /* SDA, SCL */ 2852 pins = "gpio72", "gpio73"; 2853 function = "i2chub0_se4"; 2854 drive-strength = <2>; 2855 bias-pull-up; 2856 }; 2857 2858 hub_i2c5_data_clk: hub-i2c5-data-clk-state { 2859 /* SDA, SCL */ 2860 pins = "gpio74", "gpio75"; 2861 function = "i2chub0_se5"; 2862 drive-strength = <2>; 2863 bias-pull-up; 2864 }; 2865 2866 hub_i2c6_data_clk: hub-i2c6-data-clk-state { 2867 /* SDA, SCL */ 2868 pins = "gpio76", "gpio77"; 2869 function = "i2chub0_se6"; 2870 drive-strength = <2>; 2871 bias-pull-up; 2872 }; 2873 2874 hub_i2c7_data_clk: hub-i2c7-data-clk-state { 2875 /* SDA, SCL */ 2876 pins = "gpio82", "gpio83"; 2877 function = "i2chub0_se7"; 2878 drive-strength = <2>; 2879 bias-pull-up; 2880 }; 2881 2882 hub_i2c8_data_clk: hub-i2c8-data-clk-state { 2883 /* SDA, SCL */ 2884 pins = "gpio206", "gpio207"; 2885 function = "i2chub0_se8"; 2886 drive-strength = <2>; 2887 bias-pull-up; 2888 }; 2889 2890 hub_i2c9_data_clk: hub-i2c9-data-clk-state { 2891 /* SDA, SCL */ 2892 pins = "gpio80", "gpio81"; 2893 function = "i2chub0_se9"; 2894 drive-strength = <2>; 2895 bias-pull-up; 2896 }; 2897 2898 pcie0_default_state: pcie0-default-state { 2899 perst-pins { 2900 pins = "gpio102"; 2901 function = "gpio"; 2902 drive-strength = <2>; 2903 bias-pull-down; 2904 }; 2905 2906 clkreq-pins { 2907 pins = "gpio103"; 2908 function = "pcie0_clk_req_n"; 2909 drive-strength = <2>; 2910 bias-pull-up; 2911 }; 2912 2913 wake-pins { 2914 pins = "gpio104"; 2915 function = "gpio"; 2916 drive-strength = <2>; 2917 bias-pull-up; 2918 }; 2919 }; 2920 2921 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 2922 /* SDA, SCL */ 2923 pins = "gpio32", "gpio33"; 2924 function = "qup1_se0"; 2925 drive-strength = <2>; 2926 bias-pull-up; 2927 }; 2928 2929 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 2930 /* SDA, SCL */ 2931 pins = "gpio36", "gpio37"; 2932 function = "qup1_se1"; 2933 drive-strength = <2>; 2934 bias-pull-up; 2935 }; 2936 2937 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 2938 /* SDA, SCL */ 2939 pins = "gpio40", "gpio41"; 2940 function = "qup1_se2"; 2941 drive-strength = <2>; 2942 bias-pull-up; 2943 }; 2944 2945 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 2946 /* SDA, SCL */ 2947 pins = "gpio44", "gpio45"; 2948 function = "qup1_se3"; 2949 drive-strength = <2>; 2950 bias-pull-up; 2951 }; 2952 2953 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 2954 /* SDA, SCL */ 2955 pins = "gpio48", "gpio49"; 2956 function = "qup1_se4"; 2957 drive-strength = <2>; 2958 bias-pull-up; 2959 }; 2960 2961 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 2962 /* SDA, SCL */ 2963 pins = "gpio52", "gpio53"; 2964 function = "qup1_se5"; 2965 drive-strength = <2>; 2966 bias-pull-up; 2967 }; 2968 2969 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 2970 /* SDA, SCL */ 2971 pins = "gpio56", "gpio57"; 2972 function = "qup1_se6"; 2973 drive-strength = <2>; 2974 bias-pull-up; 2975 }; 2976 2977 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 2978 /* SDA, SCL */ 2979 pins = "gpio0", "gpio1"; 2980 function = "qup2_se0"; 2981 drive-strength = <2>; 2982 bias-pull-up; 2983 }; 2984 2985 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 2986 /* SDA, SCL */ 2987 pins = "gpio4", "gpio5"; 2988 function = "qup2_se1"; 2989 drive-strength = <2>; 2990 bias-pull-up; 2991 }; 2992 2993 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 2994 /* SDA, SCL */ 2995 pins = "gpio8", "gpio9"; 2996 function = "qup2_se2"; 2997 drive-strength = <2>; 2998 bias-pull-up; 2999 }; 3000 3001 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3002 /* SDA, SCL */ 3003 pins = "gpio12", "gpio13"; 3004 function = "qup2_se3"; 3005 drive-strength = <2>; 3006 bias-pull-up; 3007 }; 3008 3009 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3010 /* SDA, SCL */ 3011 pins = "gpio16", "gpio17"; 3012 function = "qup2_se4"; 3013 drive-strength = <2>; 3014 bias-pull-up; 3015 }; 3016 3017 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3018 /* SDA, SCL */ 3019 pins = "gpio20", "gpio21"; 3020 function = "qup2_se5"; 3021 drive-strength = <2>; 3022 bias-pull-up; 3023 }; 3024 3025 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3026 /* SDA, SCL */ 3027 pins = "gpio28", "gpio29"; 3028 function = "qup2_se7"; 3029 drive-strength = <2>; 3030 bias-pull-up; 3031 }; 3032 3033 qup_spi0_cs: qup-spi0-cs-state { 3034 pins = "gpio35"; 3035 function = "qup1_se0"; 3036 drive-strength = <6>; 3037 bias-disable; 3038 }; 3039 3040 qup_spi0_data_clk: qup-spi0-data-clk-state { 3041 /* MISO, MOSI, CLK */ 3042 pins = "gpio32", "gpio33", "gpio34"; 3043 function = "qup1_se0"; 3044 drive-strength = <6>; 3045 bias-disable; 3046 }; 3047 3048 qup_spi1_cs: qup-spi1-cs-state { 3049 pins = "gpio39"; 3050 function = "qup1_se1"; 3051 drive-strength = <6>; 3052 bias-disable; 3053 }; 3054 3055 qup_spi1_data_clk: qup-spi1-data-clk-state { 3056 /* MISO, MOSI, CLK */ 3057 pins = "gpio36", "gpio37", "gpio38"; 3058 function = "qup1_se1"; 3059 drive-strength = <6>; 3060 bias-disable; 3061 }; 3062 3063 qup_spi2_cs: qup-spi2-cs-state { 3064 pins = "gpio43"; 3065 function = "qup1_se2"; 3066 drive-strength = <6>; 3067 bias-disable; 3068 }; 3069 3070 qup_spi2_data_clk: qup-spi2-data-clk-state { 3071 /* MISO, MOSI, CLK */ 3072 pins = "gpio40", "gpio41", "gpio42"; 3073 function = "qup1_se2"; 3074 drive-strength = <6>; 3075 bias-disable; 3076 }; 3077 3078 qup_spi3_cs: qup-spi3-cs-state { 3079 pins = "gpio47"; 3080 function = "qup1_se3"; 3081 drive-strength = <6>; 3082 bias-disable; 3083 }; 3084 3085 qup_spi3_data_clk: qup-spi3-data-clk-state { 3086 /* MISO, MOSI, CLK */ 3087 pins = "gpio44", "gpio45", "gpio46"; 3088 function = "qup1_se3"; 3089 drive-strength = <6>; 3090 bias-disable; 3091 }; 3092 3093 qup_spi4_cs: qup-spi4-cs-state { 3094 pins = "gpio51"; 3095 function = "qup1_se4"; 3096 drive-strength = <6>; 3097 bias-disable; 3098 }; 3099 3100 qup_spi4_data_clk: qup-spi4-data-clk-state { 3101 /* MISO, MOSI, CLK */ 3102 pins = "gpio48", "gpio49", "gpio50"; 3103 function = "qup1_se4"; 3104 drive-strength = <6>; 3105 bias-disable; 3106 }; 3107 3108 qup_spi5_cs: qup-spi5-cs-state { 3109 pins = "gpio55"; 3110 function = "qup1_se5"; 3111 drive-strength = <6>; 3112 bias-disable; 3113 }; 3114 3115 qup_spi5_data_clk: qup-spi5-data-clk-state { 3116 /* MISO, MOSI, CLK */ 3117 pins = "gpio52", "gpio53", "gpio54"; 3118 function = "qup1_se5"; 3119 drive-strength = <6>; 3120 bias-disable; 3121 }; 3122 3123 qup_spi6_cs: qup-spi6-cs-state { 3124 pins = "gpio59"; 3125 function = "qup1_se6"; 3126 drive-strength = <6>; 3127 bias-disable; 3128 }; 3129 3130 qup_spi6_data_clk: qup-spi6-data-clk-state { 3131 /* MISO, MOSI, CLK */ 3132 pins = "gpio56", "gpio57", "gpio58"; 3133 function = "qup1_se6"; 3134 drive-strength = <6>; 3135 bias-disable; 3136 }; 3137 3138 qup_spi8_cs: qup-spi8-cs-state { 3139 pins = "gpio3"; 3140 function = "qup2_se0"; 3141 drive-strength = <6>; 3142 bias-disable; 3143 }; 3144 3145 qup_spi8_data_clk: qup-spi8-data-clk-state { 3146 /* MISO, MOSI, CLK */ 3147 pins = "gpio0", "gpio1", "gpio2"; 3148 function = "qup2_se0"; 3149 drive-strength = <6>; 3150 bias-disable; 3151 }; 3152 3153 qup_spi9_cs: qup-spi9-cs-state { 3154 pins = "gpio7"; 3155 function = "qup2_se1"; 3156 drive-strength = <6>; 3157 bias-disable; 3158 }; 3159 3160 qup_spi9_data_clk: qup-spi9-data-clk-state { 3161 /* MISO, MOSI, CLK */ 3162 pins = "gpio4", "gpio5", "gpio6"; 3163 function = "qup2_se1"; 3164 drive-strength = <6>; 3165 bias-disable; 3166 }; 3167 3168 qup_spi10_cs: qup-spi10-cs-state { 3169 pins = "gpio11"; 3170 function = "qup2_se2"; 3171 drive-strength = <6>; 3172 bias-disable; 3173 }; 3174 3175 qup_spi10_data_clk: qup-spi10-data-clk-state { 3176 /* MISO, MOSI, CLK */ 3177 pins = "gpio8", "gpio9", "gpio10"; 3178 function = "qup2_se2"; 3179 drive-strength = <6>; 3180 bias-disable; 3181 }; 3182 3183 qup_spi11_cs: qup-spi11-cs-state { 3184 pins = "gpio15"; 3185 function = "qup2_se3"; 3186 drive-strength = <6>; 3187 bias-disable; 3188 }; 3189 3190 qup_spi11_data_clk: qup-spi11-data-clk-state { 3191 /* MISO, MOSI, CLK */ 3192 pins = "gpio12", "gpio13", "gpio14"; 3193 function = "qup2_se3"; 3194 drive-strength = <6>; 3195 bias-disable; 3196 }; 3197 3198 qup_spi12_cs: qup-spi12-cs-state { 3199 pins = "gpio19"; 3200 function = "qup2_se4"; 3201 drive-strength = <6>; 3202 bias-disable; 3203 }; 3204 3205 qup_spi12_data_clk: qup-spi12-data-clk-state { 3206 /* MISO, MOSI, CLK */ 3207 pins = "gpio16", "gpio17", "gpio18"; 3208 function = "qup2_se4"; 3209 drive-strength = <6>; 3210 bias-disable; 3211 }; 3212 3213 qup_spi13_cs: qup-spi13-cs-state { 3214 pins = "gpio23"; 3215 function = "qup2_se5"; 3216 drive-strength = <6>; 3217 bias-pull-up; 3218 }; 3219 3220 qup_spi13_data_clk: qup-spi13-data-clk-state { 3221 /* MISO, MOSI, CLK */ 3222 pins = "gpio20", "gpio21", "gpio22"; 3223 function = "qup2_se5"; 3224 drive-strength = <6>; 3225 bias-disable; 3226 }; 3227 3228 qup_spi15_cs: qup-spi15-cs-state { 3229 pins = "gpio31"; 3230 function = "qup2_se7"; 3231 drive-strength = <6>; 3232 bias-disable; 3233 }; 3234 3235 qup_spi15_data_clk: qup-spi15-data-clk-state { 3236 /* MISO, MOSI, CLK */ 3237 pins = "gpio28", "gpio29", "gpio30"; 3238 function = "qup2_se7"; 3239 drive-strength = <6>; 3240 bias-disable; 3241 }; 3242 3243 qup_uart7_default: qup-uart7-default-state { 3244 /* TX, RX */ 3245 pins = "gpio62", "gpio63"; 3246 function = "qup1_se7"; 3247 drive-strength = <2>; 3248 bias-disable; 3249 }; 3250 3251 qup_uart14_default: qup-uart14-default-state { 3252 /* TX, RX */ 3253 pins = "gpio26", "gpio27"; 3254 function = "qup2_se6"; 3255 drive-strength = <2>; 3256 bias-pull-up; 3257 }; 3258 3259 qup_uart14_cts_rts: qup-uart14-cts-rts-state { 3260 /* CTS, RTS */ 3261 pins = "gpio24", "gpio25"; 3262 function = "qup2_se6"; 3263 drive-strength = <2>; 3264 bias-pull-down; 3265 }; 3266 3267 sdc2_sleep: sdc2-sleep-state { 3268 clk-pins { 3269 pins = "sdc2_clk"; 3270 drive-strength = <2>; 3271 bias-disable; 3272 }; 3273 3274 cmd-pins { 3275 pins = "sdc2_cmd"; 3276 drive-strength = <2>; 3277 bias-pull-up; 3278 }; 3279 3280 data-pins { 3281 pins = "sdc2_data"; 3282 drive-strength = <2>; 3283 bias-pull-up; 3284 }; 3285 }; 3286 3287 sdc2_default: sdc2-default-state { 3288 clk-pins { 3289 pins = "sdc2_clk"; 3290 drive-strength = <16>; 3291 bias-disable; 3292 }; 3293 3294 cmd-pins { 3295 pins = "sdc2_cmd"; 3296 drive-strength = <10>; 3297 bias-pull-up; 3298 }; 3299 3300 data-pins { 3301 pins = "sdc2_data"; 3302 drive-strength = <10>; 3303 bias-pull-up; 3304 }; 3305 }; 3306 }; 3307 3308 tcsrcc: clock-controller@f204008 { 3309 compatible = "qcom,sm8750-tcsr", "syscon"; 3310 reg = <0x0 0x0f204008 0x0 0x3004>; 3311 3312 clocks = <&rpmhcc RPMH_CXO_CLK>; 3313 3314 #clock-cells = <1>; 3315 #reset-cells = <1>; 3316 }; 3317 3318 apps_smmu: iommu@15000000 { 3319 compatible = "qcom,sm8750-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 3320 reg = <0x0 0x15000000 0x0 0x100000>; 3321 3322 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 3323 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 3324 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 3325 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 3326 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 3327 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 3328 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 3329 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 3330 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 3331 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 3332 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 3333 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 3334 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 3335 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 3336 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 3337 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 3338 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 3339 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 3340 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 3341 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 3342 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 3343 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 3344 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 3345 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 3346 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 3347 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 3348 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 3349 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 3350 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 3351 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 3352 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 3353 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 3354 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 3355 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 3367 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 3368 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 3369 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 3370 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 3371 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 3372 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 3373 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 3374 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 3375 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 3376 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 3377 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 3378 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 3379 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 3380 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 3381 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 3382 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 3394 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 3395 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 3396 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 3397 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 3398 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 3399 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 3400 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 3401 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 3402 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 3403 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3404 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 3405 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 3406 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3407 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 3408 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3409 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3410 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 3411 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 3412 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 3413 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 3414 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 3415 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 3416 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 3417 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 3418 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 3419 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 3420 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 3421 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 3422 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 3423 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 3424 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 3425 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 3426 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 3427 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 3428 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 3429 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 3430 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 3431 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 3432 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 3433 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 3434 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 3435 3436 #iommu-cells = <2>; 3437 #global-interrupts = <1>; 3438 3439 dma-coherent; 3440 }; 3441 3442 intc: interrupt-controller@16000000 { 3443 compatible = "arm,gic-v3"; 3444 reg = <0x0 0x16000000 0x0 0x10000>, 3445 <0x0 0x16080000 0x0 0x200000>; 3446 3447 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3448 3449 #interrupt-cells = <3>; 3450 interrupt-controller; 3451 3452 #redistributor-regions = <1>; 3453 redistributor-stride = <0x0 0x40000>; 3454 3455 #address-cells = <2>; 3456 #size-cells = <2>; 3457 ranges; 3458 3459 gic_its: msi-controller@16040000 { 3460 compatible = "arm,gic-v3-its"; 3461 reg = <0x0 0x16040000 0x0 0x20000>; 3462 3463 msi-controller; 3464 #msi-cells = <1>; 3465 }; 3466 }; 3467 3468 pcie0: pcie@1c00000 { 3469 device_type = "pci"; 3470 compatible = "qcom,pcie-sm8750", "qcom,pcie-sm8550"; 3471 reg = <0x0 0x01c00000 0x0 0x3000>, 3472 <0x0 0x40000000 0x0 0xf1d>, 3473 <0x0 0x40000f20 0x0 0xa8>, 3474 <0x0 0x40001000 0x0 0x1000>, 3475 <0x0 0x40100000 0x0 0x100000>, 3476 <0x0 0x01C03000 0x0 0x1000>; 3477 reg-names = "parf", 3478 "dbi", 3479 "elbi", 3480 "atu", 3481 "config", 3482 "mhi"; 3483 3484 #address-cells = <3>; 3485 #size-cells = <2>; 3486 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 3487 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>, 3488 <0x03000000 0x4 0x00000000 0x4 0x00000000 0x3 0x00000000>; 3489 bus-range = <0x00 0xff>; 3490 3491 dma-coherent; 3492 3493 linux,pci-domain = <0>; 3494 3495 msi-map = <0x0 &gic_its 0x1400 0x1>, 3496 <0x100 &gic_its 0x1401 0x1>; 3497 msi-map-mask = <0xff00>; 3498 3499 num-lanes = <2>; 3500 3501 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 3502 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 3503 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 3504 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 3505 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 3506 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 3507 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 3508 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 3509 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 3510 interrupt-names = "msi0", 3511 "msi1", 3512 "msi2", 3513 "msi3", 3514 "msi4", 3515 "msi5", 3516 "msi6", 3517 "msi7", 3518 "global"; 3519 3520 #interrupt-cells = <1>; 3521 interrupt-map-mask = <0 0 0 0x7>; 3522 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 3523 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 3524 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 3525 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 3526 3527 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3528 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3529 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 3530 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 3531 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 3532 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 3533 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 3534 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 3535 clock-names = "aux", 3536 "cfg", 3537 "bus_master", 3538 "bus_slave", 3539 "slave_q2a", 3540 "ddrss_sf_tbu", 3541 "noc_aggr", 3542 "cnoc_sf_axi"; 3543 3544 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 3545 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3546 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 3547 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; 3548 interconnect-names = "pcie-mem", 3549 "cpu-pcie"; 3550 3551 iommu-map = <0x0 &apps_smmu 0x1400 0x1>, 3552 <0x100 &apps_smmu 0x1401 0x1>; 3553 3554 resets = <&gcc GCC_PCIE_0_BCR>; 3555 reset-names = "pci"; 3556 3557 power-domains = <&gcc GCC_PCIE_0_GDSC>; 3558 3559 operating-points-v2 = <&pcie0_opp_table>; 3560 3561 status = "disabled"; 3562 3563 pcie0_opp_table: opp-table { 3564 compatible = "operating-points-v2"; 3565 3566 /* GEN 1 x1 */ 3567 opp-2500000 { 3568 opp-hz = /bits/ 64 <2500000>; 3569 required-opps = <&rpmhpd_opp_low_svs>; 3570 opp-peak-kBps = <250000 1>; 3571 }; 3572 3573 /* GEN 1 x2 and GEN 2 x1 */ 3574 opp-5000000 { 3575 opp-hz = /bits/ 64 <5000000>; 3576 required-opps = <&rpmhpd_opp_low_svs>; 3577 opp-peak-kBps = <500000 1>; 3578 }; 3579 3580 /* GEN 2 x2 */ 3581 opp-10000000 { 3582 opp-hz = /bits/ 64 <10000000>; 3583 required-opps = <&rpmhpd_opp_low_svs>; 3584 opp-peak-kBps = <1000000 1>; 3585 }; 3586 3587 /* GEN 3 x1 */ 3588 opp-8000000 { 3589 opp-hz = /bits/ 64 <8000000>; 3590 required-opps = <&rpmhpd_opp_nom>; 3591 opp-peak-kBps = <984500 1>; 3592 }; 3593 3594 /* GEN 3 x2 */ 3595 opp-16000000 { 3596 opp-hz = /bits/ 64 <16000000>; 3597 required-opps = <&rpmhpd_opp_nom>; 3598 opp-peak-kBps = <1969000 1>; 3599 }; 3600 3601 }; 3602 3603 pcieport0: pcie@0 { 3604 device_type = "pci"; 3605 reg = <0x0 0x0 0x0 0x0 0x0>; 3606 bus-range = <0x01 0xff>; 3607 3608 #address-cells = <3>; 3609 #size-cells = <2>; 3610 ranges; 3611 phys = <&pcie0_phy>; 3612 }; 3613 }; 3614 3615 pcie0_phy: phy@1c06000 { 3616 compatible = "qcom,sm8750-qmp-gen3x2-pcie-phy"; 3617 reg = <0 0x01c06000 0 0x2000>; 3618 3619 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 3620 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 3621 <&tcsrcc TCSR_PCIE_0_CLKREF_EN>, 3622 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 3623 <&gcc GCC_PCIE_0_PIPE_CLK>; 3624 clock-names = "aux", 3625 "cfg_ahb", 3626 "ref", 3627 "rchng", 3628 "pipe"; 3629 3630 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 3631 assigned-clock-rates = <100000000>; 3632 3633 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 3634 reset-names = "phy"; 3635 3636 power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>; 3637 3638 #clock-cells = <0>; 3639 clock-output-names = "pcie0_pipe_clk"; 3640 3641 #phy-cells = <0>; 3642 3643 status = "disabled"; 3644 }; 3645 3646 ufs_mem_phy: phy@1d80000 { 3647 compatible = "qcom,sm8750-qmp-ufs-phy"; 3648 reg = <0x0 0x01d80000 0x0 0x2000>; 3649 3650 clocks = <&rpmhcc RPMH_CXO_CLK>, 3651 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 3652 <&tcsrcc TCSR_UFS_CLKREF_EN>; 3653 3654 clock-names = "ref", 3655 "ref_aux", 3656 "qref"; 3657 3658 resets = <&ufs_mem_hc 0>; 3659 reset-names = "ufsphy"; 3660 3661 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; 3662 3663 #clock-cells = <1>; 3664 #phy-cells = <0>; 3665 3666 status = "disabled"; 3667 }; 3668 3669 ufs_mem_hc: ufs@1d84000 { 3670 compatible = "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 3671 reg = <0x0 0x01d84000 0x0 0x3000>; 3672 3673 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 3674 3675 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 3676 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 3677 <&gcc GCC_UFS_PHY_AHB_CLK>, 3678 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 3679 <&rpmhcc RPMH_LN_BB_CLK3>, 3680 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 3681 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 3682 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 3683 clock-names = "core_clk", 3684 "bus_aggr_clk", 3685 "iface_clk", 3686 "core_clk_unipro", 3687 "ref_clk", 3688 "tx_lane0_sync_clk", 3689 "rx_lane0_sync_clk", 3690 "rx_lane1_sync_clk"; 3691 3692 operating-points-v2 = <&ufs_opp_table>; 3693 3694 resets = <&gcc GCC_UFS_PHY_BCR>; 3695 reset-names = "rst"; 3696 3697 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 3698 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3699 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3700 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3701 interconnect-names = "ufs-ddr", 3702 "cpu-ufs"; 3703 3704 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 3705 required-opps = <&rpmhpd_opp_nom>; 3706 3707 iommus = <&apps_smmu 0x60 0>; 3708 dma-coherent; 3709 3710 lanes-per-direction = <2>; 3711 3712 phys = <&ufs_mem_phy>; 3713 phy-names = "ufsphy"; 3714 3715 #reset-cells = <1>; 3716 3717 status = "disabled"; 3718 3719 ufs_opp_table: opp-table { 3720 compatible = "operating-points-v2"; 3721 3722 opp-100000000 { 3723 opp-hz = /bits/ 64 <100000000>, 3724 /bits/ 64 <0>, 3725 /bits/ 64 <0>, 3726 /bits/ 64 <100000000>, 3727 /bits/ 64 <0>, 3728 /bits/ 64 <0>, 3729 /bits/ 64 <0>, 3730 /bits/ 64 <0>; 3731 required-opps = <&rpmhpd_opp_low_svs>; 3732 }; 3733 3734 opp-403000000 { 3735 opp-hz = /bits/ 64 <403000000>, 3736 /bits/ 64 <0>, 3737 /bits/ 64 <0>, 3738 /bits/ 64 <403000000>, 3739 /bits/ 64 <0>, 3740 /bits/ 64 <0>, 3741 /bits/ 64 <0>, 3742 /bits/ 64 <0>; 3743 required-opps = <&rpmhpd_opp_nom>; 3744 }; 3745 }; 3746 }; 3747 3748 apps_rsc: rsc@16500000 { 3749 compatible = "qcom,rpmh-rsc"; 3750 reg = <0x0 0x16500000 0x0 0x10000>, 3751 <0x0 0x16510000 0x0 0x10000>, 3752 <0x0 0x16520000 0x0 0x10000>; 3753 reg-names = "drv-0", 3754 "drv-1", 3755 "drv-2"; 3756 3757 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 3758 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 3759 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 3760 qcom,tcs-offset = <0xd00>; 3761 qcom,drv-id = <2>; 3762 qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, 3763 <WAKE_TCS 2>, <CONTROL_TCS 0>; 3764 3765 label = "apps_rsc"; 3766 3767 power-domains = <&system_pd>; 3768 3769 apps_bcm_voter: bcm-voter { 3770 compatible = "qcom,bcm-voter"; 3771 }; 3772 3773 rpmhcc: clock-controller { 3774 compatible = "qcom,sm8750-rpmh-clk"; 3775 3776 clocks = <&xo_board>; 3777 clock-names = "xo"; 3778 3779 #clock-cells = <1>; 3780 }; 3781 3782 rpmhpd: power-controller { 3783 compatible = "qcom,sm8750-rpmhpd"; 3784 3785 operating-points-v2 = <&rpmhpd_opp_table>; 3786 3787 #power-domain-cells = <1>; 3788 3789 rpmhpd_opp_table: opp-table { 3790 compatible = "operating-points-v2"; 3791 3792 rpmhpd_opp_ret: opp-16 { 3793 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 3794 }; 3795 3796 rpmhpd_opp_min_svs: opp-48 { 3797 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3798 }; 3799 3800 rpmhpd_opp_low_svs_d3: opp-50 { 3801 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; 3802 }; 3803 3804 rpmhpd_opp_low_svs_d2: opp-52 { 3805 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 3806 }; 3807 3808 rpmhpd_opp_low_svs_d1: opp-56 { 3809 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 3810 }; 3811 3812 rpmhpd_opp_low_svs_d0: opp-60 { 3813 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 3814 }; 3815 3816 rpmhpd_opp_low_svs: opp-64 { 3817 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3818 }; 3819 3820 rpmhpd_opp_low_svs_l1: opp-80 { 3821 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 3822 }; 3823 3824 rpmhpd_opp_svs: opp-128 { 3825 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3826 }; 3827 3828 rpmhpd_opp_svs_l0: opp-144 { 3829 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 3830 }; 3831 3832 rpmhpd_opp_svs_l1: opp-192 { 3833 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3834 }; 3835 3836 rpmhpd_opp_svs_l2: opp-224 { 3837 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3838 }; 3839 3840 rpmhpd_opp_nom: opp-256 { 3841 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3842 }; 3843 3844 rpmhpd_opp_nom_l1: opp-320 { 3845 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3846 }; 3847 3848 rpmhpd_opp_nom_l2: opp-336 { 3849 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 3850 }; 3851 3852 rpmhpd_opp_turbo: opp-384 { 3853 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3854 }; 3855 3856 rpmhpd_opp_turbo_l1: opp-416 { 3857 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3858 }; 3859 3860 rpmhpd_opp_turbo_l2: opp-432 { 3861 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 3862 }; 3863 3864 rpmhpd_opp_turbo_l3: opp-448 { 3865 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 3866 }; 3867 3868 rpmhpd_opp_turbo_l4: opp-452 { 3869 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 3870 }; 3871 3872 rpmhpd_opp_super_turbo_no_cpr: opp-480 { 3873 opp-level = 3874 <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; 3875 }; 3876 }; 3877 }; 3878 }; 3879 3880 timer@16800000 { 3881 compatible = "arm,armv7-timer-mem"; 3882 reg = <0x0 0x16800000 0x0 0x1000>; 3883 3884 #address-cells = <2>; 3885 #size-cells = <1>; 3886 ranges = <0 0 0 0 0x20000000>; 3887 3888 frame@16801000 { 3889 reg = <0x0 0x16801000 0x1000>, 3890 <0x0 0x16802000 0x1000>; 3891 3892 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3893 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 3894 3895 frame-number = <0>; 3896 }; 3897 3898 frame@16803000 { 3899 reg = <0x0 0x16803000 0x1000>; 3900 3901 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3902 3903 frame-number = <1>; 3904 3905 status = "disabled"; 3906 }; 3907 3908 frame@16805000 { 3909 reg = <0x0 0x16805000 0x1000>; 3910 3911 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3912 3913 frame-number = <2>; 3914 3915 status = "disabled"; 3916 }; 3917 3918 frame@16807000 { 3919 reg = <0x0 0x16807000 0x1000>; 3920 3921 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3922 3923 frame-number = <3>; 3924 3925 status = "disabled"; 3926 }; 3927 3928 frame@16809000 { 3929 reg = <0x0 0x16809000 0x1000>; 3930 3931 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3932 3933 frame-number = <4>; 3934 3935 status = "disabled"; 3936 }; 3937 3938 frame@1680b000 { 3939 reg = <0x0 0x1680b000 0x1000>; 3940 3941 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3942 3943 frame-number = <5>; 3944 3945 status = "disabled"; 3946 }; 3947 3948 frame@1680d000 { 3949 reg = <0x0 0x1680d000 0x1000>; 3950 3951 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3952 3953 frame-number = <6>; 3954 3955 status = "disabled"; 3956 }; 3957 }; 3958 3959 /* cluster0 */ 3960 pmu@240b3400 { 3961 compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon"; 3962 reg = <0x0 0x240b3400 0x0 0x600>; 3963 3964 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 3965 3966 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3967 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 3968 3969 operating-points-v2 = <&cpu_bwmon_opp_table>; 3970 3971 nonposted-mmio; 3972 3973 cpu_bwmon_opp_table: opp-table { 3974 compatible = "operating-points-v2"; 3975 3976 opp-0 { 3977 opp-peak-kBps = <800000>; 3978 }; 3979 3980 opp-1 { 3981 opp-peak-kBps = <2188000>; 3982 }; 3983 3984 opp-2 { 3985 opp-peak-kBps = <5414400>; 3986 }; 3987 3988 opp-3 { 3989 opp-peak-kBps = <6220800>; 3990 }; 3991 3992 opp-4 { 3993 opp-peak-kBps = <6835200>; 3994 }; 3995 3996 opp-5 { 3997 opp-peak-kBps = <8371200>; 3998 }; 3999 4000 opp-6 { 4001 opp-peak-kBps = <10944000>; 4002 }; 4003 4004 opp-7 { 4005 opp-peak-kBps = <12748800>; 4006 }; 4007 4008 opp-8 { 4009 opp-peak-kBps = <14745600>; 4010 }; 4011 4012 opp-9 { 4013 opp-peak-kBps = <16896000>; 4014 }; 4015 4016 opp-10 { 4017 opp-peak-kBps = <19046400>; 4018 }; 4019 }; 4020 }; 4021 4022 /* cluster1 */ 4023 pmu@240b7400 { 4024 compatible = "qcom,sm8750-cpu-bwmon", "qcom,sdm845-bwmon"; 4025 reg = <0x0 0x240b7400 0x0 0x600>; 4026 4027 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4028 4029 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4030 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4031 4032 operating-points-v2 = <&cpu_bwmon_opp_table>; 4033 }; 4034 4035 gem_noc: interconnect@24100000 { 4036 compatible = "qcom,sm8750-gem-noc"; 4037 reg = <0x0 0x24100000 0x0 0x14b080>; 4038 qcom,bcm-voters = <&apps_bcm_voter>; 4039 #interconnect-cells = <2>; 4040 }; 4041 4042 system-cache-controller@24800000 { 4043 compatible = "qcom,sm8750-llcc"; 4044 reg = <0x0 0x24800000 0x0 0x200000>, 4045 <0x0 0x25800000 0x0 0x200000>, 4046 <0x0 0x24c00000 0x0 0x200000>, 4047 <0x0 0x25c00000 0x0 0x200000>, 4048 <0x0 0x26800000 0x0 0x200000>, 4049 <0x0 0x26c00000 0x0 0x200000>; 4050 reg-names = "llcc0_base", 4051 "llcc1_base", 4052 "llcc2_base", 4053 "llcc3_base", 4054 "llcc_broadcast_base", 4055 "llcc_broadcast_and_base"; 4056 4057 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 4058 }; 4059 4060 nsp_noc: interconnect@320c0000 { 4061 compatible = "qcom,sm8750-nsp-noc"; 4062 reg = <0x0 0x320c0000 0x0 0x13080>; 4063 qcom,bcm-voters = <&apps_bcm_voter>; 4064 #interconnect-cells = <2>; 4065 }; 4066 4067 remoteproc_cdsp: remoteproc@32300000 { 4068 compatible = "qcom,sm8750-cdsp-pas", "qcom,sm8650-cdsp-pas"; 4069 reg = <0x0 0x32300000 0x0 0x10000>; 4070 4071 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4072 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 4073 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 4074 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 4075 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 4076 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 4077 interrupt-names = "wdog", 4078 "fatal", 4079 "ready", 4080 "handover", 4081 "stop-ack", 4082 "shutdown-ack"; 4083 4084 clocks = <&rpmhcc RPMH_CXO_CLK>; 4085 clock-names = "xo"; 4086 4087 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 4088 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4089 4090 power-domains = <&rpmhpd RPMHPD_CX>, 4091 <&rpmhpd RPMHPD_MXC>, 4092 <&rpmhpd RPMHPD_NSP>; 4093 power-domain-names = "cx", 4094 "mxc", 4095 "nsp"; 4096 4097 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; 4098 qcom,qmp = <&aoss_qmp>; 4099 qcom,smem-states = <&smp2p_cdsp_out 0>; 4100 qcom,smem-state-names = "stop"; 4101 4102 status = "disabled"; 4103 4104 glink-edge { 4105 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4106 IPCC_MPROC_SIGNAL_GLINK_QMP 4107 IRQ_TYPE_EDGE_RISING>; 4108 mboxes = <&ipcc IPCC_CLIENT_CDSP 4109 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4110 qcom,remote-pid = <5>; 4111 label = "cdsp"; 4112 4113 fastrpc { 4114 compatible = "qcom,fastrpc"; 4115 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4116 label = "cdsp"; 4117 qcom,non-secure-domain; 4118 #address-cells = <1>; 4119 #size-cells = <0>; 4120 4121 compute-cb@1 { 4122 compatible = "qcom,fastrpc-compute-cb"; 4123 reg = <1>; 4124 iommus = <&apps_smmu 0x19c1 0x0>, 4125 <&apps_smmu 0x0c21 0x0>, 4126 <&apps_smmu 0x0c01 0x40>; 4127 dma-coherent; 4128 }; 4129 4130 compute-cb@2 { 4131 compatible = "qcom,fastrpc-compute-cb"; 4132 reg = <2>; 4133 iommus = <&apps_smmu 0x1962 0x0>, 4134 <&apps_smmu 0x0c02 0x20>, 4135 <&apps_smmu 0x0c42 0x0>, 4136 <&apps_smmu 0x19c2 0x0>; 4137 dma-coherent; 4138 }; 4139 4140 compute-cb@3 { 4141 compatible = "qcom,fastrpc-compute-cb"; 4142 reg = <3>; 4143 iommus = <&apps_smmu 0x1963 0x0>, 4144 <&apps_smmu 0x0c23 0x0>, 4145 <&apps_smmu 0x0c03 0x40>, 4146 <&apps_smmu 0x19c3 0x0>; 4147 dma-coherent; 4148 }; 4149 4150 compute-cb@4 { 4151 compatible = "qcom,fastrpc-compute-cb"; 4152 reg = <4>; 4153 iommus = <&apps_smmu 0x1964 0x0>, 4154 <&apps_smmu 0x0c24 0x0>, 4155 <&apps_smmu 0x0c04 0x40>, 4156 <&apps_smmu 0x19c4 0x0>; 4157 dma-coherent; 4158 }; 4159 4160 compute-cb@5 { 4161 compatible = "qcom,fastrpc-compute-cb"; 4162 reg = <5>; 4163 iommus = <&apps_smmu 0x1965 0x0>, 4164 <&apps_smmu 0x0c25 0x0>, 4165 <&apps_smmu 0x0c05 0x40>, 4166 <&apps_smmu 0x19c5 0x0>; 4167 dma-coherent; 4168 }; 4169 4170 compute-cb@6 { 4171 compatible = "qcom,fastrpc-compute-cb"; 4172 reg = <6>; 4173 iommus = <&apps_smmu 0x1966 0x0>, 4174 <&apps_smmu 0x0c06 0x20>, 4175 <&apps_smmu 0x0c46 0x0>, 4176 <&apps_smmu 0x19c6 0x0>; 4177 dma-coherent; 4178 }; 4179 4180 compute-cb@7 { 4181 compatible = "qcom,fastrpc-compute-cb"; 4182 reg = <7>; 4183 iommus = <&apps_smmu 0x1967 0x0>, 4184 <&apps_smmu 0x0c27 0x0>, 4185 <&apps_smmu 0x0c07 0x40>, 4186 <&apps_smmu 0x19c7 0x0>; 4187 dma-coherent; 4188 }; 4189 4190 compute-cb@8 { 4191 compatible = "qcom,fastrpc-compute-cb"; 4192 reg = <8>; 4193 iommus = <&apps_smmu 0x1968 0x0>, 4194 <&apps_smmu 0x0c08 0x20>, 4195 <&apps_smmu 0x0c48 0x0>, 4196 <&apps_smmu 0x19c8 0x0>; 4197 dma-coherent; 4198 }; 4199 4200 /* note: secure cb9 in downstream */ 4201 4202 compute-cb@12 { 4203 compatible = "qcom,fastrpc-compute-cb"; 4204 reg = <12>; 4205 iommus = <&apps_smmu 0x196c 0x0>, 4206 <&apps_smmu 0x0c2c 0x20>, 4207 <&apps_smmu 0x0c0c 0x40>, 4208 <&apps_smmu 0x19cc 0x0>; 4209 dma-coherent; 4210 }; 4211 4212 compute-cb@13 { 4213 compatible = "qcom,fastrpc-compute-cb"; 4214 reg = <13>; 4215 iommus = <&apps_smmu 0x196d 0x0>, 4216 <&apps_smmu 0x0c0d 0x20>, 4217 <&apps_smmu 0x0c2e 0x0>, 4218 <&apps_smmu 0x0c4d 0x0>, 4219 <&apps_smmu 0x19cd 0x0>; 4220 dma-coherent; 4221 }; 4222 4223 compute-cb@14 { 4224 compatible = "qcom,fastrpc-compute-cb"; 4225 reg = <14>; 4226 iommus = <&apps_smmu 0x196e 0x0>, 4227 <&apps_smmu 0x0c0e 0x20>, 4228 <&apps_smmu 0x19ce 0x0>; 4229 dma-coherent; 4230 }; 4231 }; 4232 }; 4233 }; 4234 }; 4235 4236 timer { 4237 compatible = "arm,armv8-timer"; 4238 4239 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 4240 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 4241 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 4242 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 4243 }; 4244};
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