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sm6125.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/sm6125.dtsi
1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2021, Martin Botka <martin.botka@somainline.org> 4 */ 5 6#include <dt-bindings/clock/qcom,dispcc-sm6125.h> 7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 8#include <dt-bindings/clock/qcom,gcc-sm6125.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/dma/qcom-gpi.h> 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom-rpmpd.h> 14 15/ { 16 interrupt-parent = <&intc>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 chosen { }; 21 22 clocks { 23 xo_board: xo-board { 24 compatible = "fixed-clock"; 25 #clock-cells = <0>; 26 clock-frequency = <19200000>; 27 }; 28 29 sleep_clk: sleep-clk { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <32764>; 33 clock-output-names = "sleep_clk"; 34 }; 35 }; 36 37 cpus { 38 #address-cells = <2>; 39 #size-cells = <0>; 40 41 cpu0: cpu@0 { 42 device_type = "cpu"; 43 compatible = "qcom,kryo260"; 44 reg = <0x0 0x0>; 45 enable-method = "psci"; 46 capacity-dmips-mhz = <1024>; 47 next-level-cache = <&l2_0>; 48 l2_0: l2-cache { 49 compatible = "cache"; 50 cache-level = <2>; 51 cache-unified; 52 }; 53 }; 54 55 cpu1: cpu@1 { 56 device_type = "cpu"; 57 compatible = "qcom,kryo260"; 58 reg = <0x0 0x1>; 59 enable-method = "psci"; 60 capacity-dmips-mhz = <1024>; 61 next-level-cache = <&l2_0>; 62 }; 63 64 cpu2: cpu@2 { 65 device_type = "cpu"; 66 compatible = "qcom,kryo260"; 67 reg = <0x0 0x2>; 68 enable-method = "psci"; 69 capacity-dmips-mhz = <1024>; 70 next-level-cache = <&l2_0>; 71 }; 72 73 cpu3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "qcom,kryo260"; 76 reg = <0x0 0x3>; 77 enable-method = "psci"; 78 capacity-dmips-mhz = <1024>; 79 next-level-cache = <&l2_0>; 80 }; 81 82 cpu4: cpu@100 { 83 device_type = "cpu"; 84 compatible = "qcom,kryo260"; 85 reg = <0x0 0x100>; 86 enable-method = "psci"; 87 capacity-dmips-mhz = <1638>; 88 next-level-cache = <&l2_1>; 89 l2_1: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 }; 94 }; 95 96 cpu5: cpu@101 { 97 device_type = "cpu"; 98 compatible = "qcom,kryo260"; 99 reg = <0x0 0x101>; 100 enable-method = "psci"; 101 capacity-dmips-mhz = <1638>; 102 next-level-cache = <&l2_1>; 103 }; 104 105 cpu6: cpu@102 { 106 device_type = "cpu"; 107 compatible = "qcom,kryo260"; 108 reg = <0x0 0x102>; 109 enable-method = "psci"; 110 capacity-dmips-mhz = <1638>; 111 next-level-cache = <&l2_1>; 112 }; 113 114 cpu7: cpu@103 { 115 device_type = "cpu"; 116 compatible = "qcom,kryo260"; 117 reg = <0x0 0x103>; 118 enable-method = "psci"; 119 capacity-dmips-mhz = <1638>; 120 next-level-cache = <&l2_1>; 121 }; 122 123 cpu-map { 124 cluster0 { 125 core0 { 126 cpu = <&cpu0>; 127 }; 128 129 core1 { 130 cpu = <&cpu1>; 131 }; 132 133 core2 { 134 cpu = <&cpu2>; 135 }; 136 137 core3 { 138 cpu = <&cpu3>; 139 }; 140 }; 141 142 cluster1 { 143 core0 { 144 cpu = <&cpu4>; 145 }; 146 147 core1 { 148 cpu = <&cpu5>; 149 }; 150 151 core2 { 152 cpu = <&cpu6>; 153 }; 154 155 core3 { 156 cpu = <&cpu7>; 157 }; 158 }; 159 }; 160 }; 161 162 firmware { 163 scm: scm { 164 compatible = "qcom,scm-sm6125", "qcom,scm"; 165 #reset-cells = <1>; 166 }; 167 }; 168 169 memory@40000000 { 170 /* We expect the bootloader to fill in the size */ 171 reg = <0x0 0x40000000 0x0 0x0>; 172 device_type = "memory"; 173 }; 174 175 pmu { 176 compatible = "arm,armv8-pmuv3"; 177 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 178 }; 179 180 psci { 181 compatible = "arm,psci-1.0"; 182 method = "smc"; 183 }; 184 185 rpm: remoteproc { 186 compatible = "qcom,sm6125-rpm-proc", "qcom,rpm-proc"; 187 188 glink-edge { 189 compatible = "qcom,glink-rpm"; 190 191 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 192 qcom,rpm-msg-ram = <&rpm_msg_ram>; 193 mboxes = <&apcs_glb 0>; 194 195 rpm_requests: rpm-requests { 196 compatible = "qcom,rpm-sm6125", "qcom,glink-smd-rpm"; 197 qcom,glink-channels = "rpm_requests"; 198 199 rpmcc: clock-controller { 200 compatible = "qcom,rpmcc-sm6125", "qcom,rpmcc"; 201 #clock-cells = <1>; 202 clocks = <&xo_board>; 203 clock-names = "xo"; 204 }; 205 206 rpmpd: power-controller { 207 compatible = "qcom,sm6125-rpmpd"; 208 #power-domain-cells = <1>; 209 operating-points-v2 = <&rpmpd_opp_table>; 210 211 rpmpd_opp_table: opp-table { 212 compatible = "operating-points-v2"; 213 214 rpmpd_opp_ret: opp1 { 215 opp-level = <RPM_SMD_LEVEL_RETENTION>; 216 }; 217 218 rpmpd_opp_ret_plus: opp2 { 219 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 220 }; 221 222 rpmpd_opp_min_svs: opp3 { 223 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 224 }; 225 226 rpmpd_opp_low_svs: opp4 { 227 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 228 }; 229 230 rpmpd_opp_svs: opp5 { 231 opp-level = <RPM_SMD_LEVEL_SVS>; 232 }; 233 234 rpmpd_opp_svs_plus: opp6 { 235 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 236 }; 237 238 rpmpd_opp_nom: opp7 { 239 opp-level = <RPM_SMD_LEVEL_NOM>; 240 }; 241 242 rpmpd_opp_nom_plus: opp8 { 243 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 244 }; 245 246 rpmpd_opp_turbo: opp9 { 247 opp-level = <RPM_SMD_LEVEL_TURBO>; 248 }; 249 250 rpmpd_opp_turbo_no_cpr: opp10 { 251 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 252 }; 253 }; 254 }; 255 }; 256 }; 257 }; 258 259 reserved_memory: reserved-memory { 260 #address-cells = <2>; 261 #size-cells = <2>; 262 ranges; 263 264 hyp_mem: memory@45700000 { 265 reg = <0x0 0x45700000 0x0 0x600000>; 266 no-map; 267 }; 268 269 xbl_aop_mem: memory@45e00000 { 270 reg = <0x0 0x45e00000 0x0 0x140000>; 271 no-map; 272 }; 273 274 sec_apps_mem: memory@45fff000 { 275 reg = <0x0 0x45fff000 0x0 0x1000>; 276 no-map; 277 }; 278 279 smem_mem: memory@46000000 { 280 reg = <0x0 0x46000000 0x0 0x200000>; 281 no-map; 282 }; 283 284 reserved_mem1: memory@46200000 { 285 reg = <0x0 0x46200000 0x0 0x2d00000>; 286 no-map; 287 }; 288 289 camera_mem: memory@4ab00000 { 290 reg = <0x0 0x4ab00000 0x0 0x500000>; 291 no-map; 292 }; 293 294 modem_mem: memory@4b000000 { 295 reg = <0x0 0x4b000000 0x0 0x7e00000>; 296 no-map; 297 }; 298 299 venus_mem: memory@52e00000 { 300 reg = <0x0 0x52e00000 0x0 0x500000>; 301 no-map; 302 }; 303 304 wlan_msa_mem: memory@53300000 { 305 reg = <0x0 0x53300000 0x0 0x200000>; 306 no-map; 307 }; 308 309 cdsp_mem: memory@53500000 { 310 reg = <0x0 0x53500000 0x0 0x1e00000>; 311 no-map; 312 }; 313 314 adsp_pil_mem: memory@55300000 { 315 reg = <0x0 0x55300000 0x0 0x1e00000>; 316 no-map; 317 }; 318 319 ipa_fw_mem: memory@57100000 { 320 reg = <0x0 0x57100000 0x0 0x10000>; 321 no-map; 322 }; 323 324 ipa_gsi_mem: memory@57110000 { 325 reg = <0x0 0x57110000 0x0 0x5000>; 326 no-map; 327 }; 328 329 gpu_mem: memory@57115000 { 330 reg = <0x0 0x57115000 0x0 0x2000>; 331 no-map; 332 }; 333 334 cont_splash_mem: memory@5c000000 { 335 reg = <0x0 0x5c000000 0x0 0x00f00000>; 336 no-map; 337 }; 338 339 dfps_data_mem: memory@5cf00000 { 340 reg = <0x0 0x5cf00000 0x0 0x0100000>; 341 no-map; 342 }; 343 344 cdsp_sec_mem: memory@5f800000 { 345 reg = <0x0 0x5f800000 0x0 0x1e00000>; 346 no-map; 347 }; 348 349 qseecom_mem: memory@5e400000 { 350 reg = <0x0 0x5e400000 0x0 0x1400000>; 351 no-map; 352 }; 353 354 sdsp_mem: memory@f3000000 { 355 reg = <0x0 0xf3000000 0x0 0x400000>; 356 no-map; 357 }; 358 359 adsp_mem: memory@f3400000 { 360 reg = <0x0 0xf3400000 0x0 0x800000>; 361 no-map; 362 }; 363 364 qseecom_ta_mem: memory@13fc00000 { 365 reg = <0x1 0x3fc00000 0x0 0x400000>; 366 no-map; 367 }; 368 }; 369 370 smem: smem { 371 compatible = "qcom,smem"; 372 memory-region = <&smem_mem>; 373 hwlocks = <&tcsr_mutex 3>; 374 }; 375 376 soc@0 { 377 #address-cells = <1>; 378 #size-cells = <1>; 379 ranges = <0x00 0x00 0x00 0xffffffff>; 380 compatible = "simple-bus"; 381 382 tcsr_mutex: hwlock@340000 { 383 compatible = "qcom,tcsr-mutex"; 384 reg = <0x00340000 0x20000>; 385 #hwlock-cells = <1>; 386 }; 387 388 tlmm: pinctrl@500000 { 389 compatible = "qcom,sm6125-tlmm"; 390 reg = <0x00500000 0x400000>, 391 <0x00900000 0x400000>, 392 <0x00d00000 0x400000>; 393 reg-names = "west", "south", "east"; 394 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 395 gpio-controller; 396 gpio-ranges = <&tlmm 0 0 134>; 397 #gpio-cells = <2>; 398 interrupt-controller; 399 #interrupt-cells = <2>; 400 401 sdc2_off_state: sdc2-off-state { 402 clk-pins { 403 pins = "sdc2_clk"; 404 drive-strength = <2>; 405 bias-disable; 406 }; 407 408 cmd-pins { 409 pins = "sdc2_cmd"; 410 drive-strength = <2>; 411 bias-pull-up; 412 }; 413 414 data-pins { 415 pins = "sdc2_data"; 416 drive-strength = <2>; 417 bias-pull-up; 418 }; 419 }; 420 421 sdc2_on_state: sdc2-on-state { 422 clk-pins { 423 pins = "sdc2_clk"; 424 drive-strength = <16>; 425 bias-disable; 426 }; 427 428 cmd-pins { 429 pins = "sdc2_cmd"; 430 drive-strength = <10>; 431 bias-pull-up; 432 }; 433 434 data-pins { 435 pins = "sdc2_data"; 436 drive-strength = <10>; 437 bias-pull-up; 438 }; 439 }; 440 441 qup_i2c0_default: qup-i2c0-default-state { 442 pins = "gpio0", "gpio1"; 443 function = "qup00"; 444 drive-strength = <2>; 445 bias-disable; 446 }; 447 448 qup_i2c0_sleep: qup-i2c0-sleep-state { 449 pins = "gpio0", "gpio1"; 450 function = "gpio"; 451 drive-strength = <2>; 452 bias-pull-up; 453 }; 454 455 qup_i2c1_default: qup-i2c1-default-state { 456 pins = "gpio4", "gpio5"; 457 function = "qup01"; 458 drive-strength = <2>; 459 bias-disable; 460 }; 461 462 qup_i2c1_sleep: qup-i2c1-sleep-state { 463 pins = "gpio4", "gpio5"; 464 function = "gpio"; 465 drive-strength = <2>; 466 bias-pull-up; 467 }; 468 469 qup_i2c2_default: qup-i2c2-default-state { 470 pins = "gpio6", "gpio7"; 471 function = "qup02"; 472 drive-strength = <2>; 473 bias-disable; 474 }; 475 476 qup_i2c2_sleep: qup-i2c2-sleep-state { 477 pins = "gpio6", "gpio7"; 478 function = "gpio"; 479 drive-strength = <2>; 480 bias-pull-up; 481 }; 482 483 qup_i2c3_default: qup-i2c3-default-state { 484 pins = "gpio14", "gpio15"; 485 function = "qup03"; 486 drive-strength = <2>; 487 bias-disable; 488 }; 489 490 qup_i2c3_sleep: qup-i2c3-sleep-state { 491 pins = "gpio14", "gpio15"; 492 function = "gpio"; 493 drive-strength = <2>; 494 bias-pull-up; 495 }; 496 497 qup_i2c4_default: qup-i2c4-default-state { 498 pins = "gpio16", "gpio17"; 499 function = "qup04"; 500 drive-strength = <2>; 501 bias-disable; 502 }; 503 504 qup_i2c4_sleep: qup-i2c4-sleep-state { 505 pins = "gpio16", "gpio17"; 506 function = "gpio"; 507 drive-strength = <2>; 508 bias-pull-up; 509 }; 510 511 qup_i2c5_default: qup-i2c5-default-state { 512 pins = "gpio22", "gpio23"; 513 function = "qup10"; 514 drive-strength = <2>; 515 bias-disable; 516 }; 517 518 qup_i2c5_sleep: qup-i2c5-sleep-state { 519 pins = "gpio22", "gpio23"; 520 function = "gpio"; 521 drive-strength = <2>; 522 bias-pull-up; 523 }; 524 525 qup_i2c6_default: qup-i2c6-default-state { 526 pins = "gpio30", "gpio31"; 527 function = "qup11"; 528 drive-strength = <2>; 529 bias-disable; 530 }; 531 532 qup_i2c6_sleep: qup-i2c6-sleep-state { 533 pins = "gpio30", "gpio31"; 534 function = "gpio"; 535 drive-strength = <2>; 536 bias-pull-up; 537 }; 538 539 qup_i2c7_default: qup-i2c7-default-state { 540 pins = "gpio28", "gpio29"; 541 function = "qup12"; 542 drive-strength = <2>; 543 bias-disable; 544 }; 545 546 qup_i2c7_sleep: qup-i2c7-sleep-state { 547 pins = "gpio28", "gpio29"; 548 function = "gpio"; 549 drive-strength = <2>; 550 bias-pull-up; 551 }; 552 553 qup_i2c8_default: qup-i2c8-default-state { 554 pins = "gpio18", "gpio19"; 555 function = "qup13"; 556 drive-strength = <2>; 557 bias-disable; 558 }; 559 560 qup_i2c8_sleep: qup-i2c8-sleep-state { 561 pins = "gpio18", "gpio19"; 562 function = "gpio"; 563 drive-strength = <2>; 564 bias-pull-up; 565 }; 566 567 qup_i2c9_default: qup-i2c9-default-state { 568 pins = "gpio10", "gpio11"; 569 function = "qup14"; 570 drive-strength = <2>; 571 bias-disable; 572 }; 573 574 qup_i2c9_sleep: qup-i2c9-sleep-state { 575 pins = "gpio10", "gpio11"; 576 function = "gpio"; 577 drive-strength = <2>; 578 bias-pull-up; 579 }; 580 581 qup_spi0_default: qup-spi0-default-state { 582 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 583 function = "qup00"; 584 drive-strength = <6>; 585 bias-disable; 586 }; 587 588 qup_spi0_sleep: qup-spi0-sleep-state { 589 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 590 function = "gpio"; 591 drive-strength = <6>; 592 bias-disable; 593 }; 594 595 qup_spi2_default: qup-spi2-default-state { 596 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 597 function = "qup02"; 598 drive-strength = <6>; 599 bias-disable; 600 }; 601 602 qup_spi2_sleep: qup-spi2-sleep-state { 603 pins = "gpio6", "gpio7", "gpio8", "gpio9"; 604 function = "gpio"; 605 drive-strength = <6>; 606 bias-disable; 607 }; 608 609 qup_spi5_default: qup-spi5-default-state { 610 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 611 function = "qup10"; 612 drive-strength = <6>; 613 bias-disable; 614 }; 615 616 qup_spi5_sleep: qup-spi5-sleep-state { 617 pins = "gpio22", "gpio23", "gpio24", "gpio25"; 618 function = "gpio"; 619 drive-strength = <6>; 620 bias-disable; 621 }; 622 623 qup_spi6_default: qup-spi6-default-state { 624 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 625 function = "qup11"; 626 drive-strength = <6>; 627 bias-disable; 628 }; 629 630 qup_spi6_sleep: qup-spi6-sleep-state { 631 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 632 function = "gpio"; 633 drive-strength = <6>; 634 bias-disable; 635 }; 636 637 qup_spi8_default: qup-spi8-default-state { 638 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 639 function = "qup13"; 640 drive-strength = <6>; 641 bias-disable; 642 }; 643 644 qup_spi8_sleep: qup-spi8-sleep-state { 645 pins = "gpio18", "gpio19", "gpio20", "gpio21"; 646 function = "gpio"; 647 drive-strength = <6>; 648 bias-disable; 649 }; 650 651 qup_spi9_default: qup-spi9-default-state { 652 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 653 function = "qup14"; 654 drive-strength = <6>; 655 bias-disable; 656 }; 657 658 qup_spi9_sleep: qup-spi9-sleep-state { 659 pins = "gpio10", "gpio11", "gpio12", "gpio13"; 660 function = "gpio"; 661 drive-strength = <6>; 662 bias-disable; 663 }; 664 }; 665 666 gcc: clock-controller@1400000 { 667 compatible = "qcom,gcc-sm6125"; 668 reg = <0x01400000 0x1f0000>; 669 #clock-cells = <1>; 670 #reset-cells = <1>; 671 #power-domain-cells = <1>; 672 clock-names = "bi_tcxo", "sleep_clk"; 673 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 674 }; 675 676 hsusb_phy1: phy@1613000 { 677 compatible = "qcom,msm8996-qusb2-phy"; 678 reg = <0x01613000 0x180>; 679 #phy-cells = <0>; 680 681 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 682 <&rpmcc RPM_SMD_XO_CLK_SRC>; 683 clock-names = "cfg_ahb", "ref"; 684 685 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 686 status = "disabled"; 687 }; 688 689 spmi_bus: spmi@1c40000 { 690 compatible = "qcom,spmi-pmic-arb"; 691 reg = <0x01c40000 0x1100>, 692 <0x01e00000 0x2000000>, 693 <0x03e00000 0x100000>, 694 <0x03f00000 0xa0000>, 695 <0x01c0a000 0x26000>; 696 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 697 interrupt-names = "periph_irq"; 698 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 699 qcom,ee = <0>; 700 qcom,channel = <0>; 701 #address-cells = <2>; 702 #size-cells = <0>; 703 interrupt-controller; 704 #interrupt-cells = <4>; 705 }; 706 707 rpm_msg_ram: sram@45f0000 { 708 compatible = "qcom,rpm-msg-ram"; 709 reg = <0x045f0000 0x7000>; 710 }; 711 712 sdhc_1: mmc@4744000 { 713 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 714 reg = <0x04744000 0x1000>, <0x04745000 0x1000>; 715 reg-names = "hc", "cqhci"; 716 717 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 719 interrupt-names = "hc_irq", "pwr_irq"; 720 721 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 722 <&gcc GCC_SDCC1_APPS_CLK>, 723 <&rpmcc RPM_SMD_XO_CLK_SRC>; 724 clock-names = "iface", "core", "xo"; 725 iommus = <&apps_smmu 0x160 0x0>; 726 727 power-domains = <&rpmpd SM6125_VDDCX>; 728 729 qcom,dll-config = <0x000f642c>; 730 qcom,ddr-config = <0x80040873>; 731 732 bus-width = <8>; 733 non-removable; 734 supports-cqe; 735 736 status = "disabled"; 737 }; 738 739 sdhc_2: mmc@4784000 { 740 compatible = "qcom,sm6125-sdhci", "qcom,sdhci-msm-v5"; 741 reg = <0x04784000 0x1000>; 742 reg-names = "hc"; 743 744 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 746 interrupt-names = "hc_irq", "pwr_irq"; 747 748 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 749 <&gcc GCC_SDCC2_APPS_CLK>, 750 <&rpmcc RPM_SMD_XO_CLK_SRC>; 751 clock-names = "iface", "core", "xo"; 752 iommus = <&apps_smmu 0x180 0x0>; 753 754 pinctrl-0 = <&sdc2_on_state>; 755 pinctrl-1 = <&sdc2_off_state>; 756 pinctrl-names = "default", "sleep"; 757 758 power-domains = <&rpmpd SM6125_VDDCX>; 759 760 qcom,dll-config = <0x0007642c>; 761 qcom,ddr-config = <0x80040873>; 762 763 bus-width = <4>; 764 status = "disabled"; 765 }; 766 767 ufs_mem_hc: ufshc@4804000 { 768 compatible = "qcom,sm6125-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 769 reg = <0x04804000 0x3000>, <0x04810000 0x8000>; 770 reg-names = "std", "ice"; 771 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 772 773 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 774 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>, 775 <&gcc GCC_UFS_PHY_AHB_CLK>, 776 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 777 <&rpmcc RPM_SMD_XO_CLK_SRC>, 778 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 779 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 780 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 781 clock-names = "core_clk", 782 "bus_aggr_clk", 783 "iface_clk", 784 "core_clk_unipro", 785 "ref_clk", 786 "tx_lane0_sync_clk", 787 "rx_lane0_sync_clk", 788 "ice_core_clk"; 789 freq-table-hz = <50000000 240000000>, 790 <0 0>, 791 <0 0>, 792 <37500000 150000000>, 793 <0 0>, 794 <0 0>, 795 <0 0>, 796 <75000000 300000000>; 797 798 resets = <&gcc GCC_UFS_PHY_BCR>; 799 reset-names = "rst"; 800 #reset-cells = <1>; 801 802 phys = <&ufs_mem_phy>; 803 phy-names = "ufsphy"; 804 805 lanes-per-direction = <1>; 806 807 iommus = <&apps_smmu 0x200 0x0>; 808 809 status = "disabled"; 810 }; 811 812 ufs_mem_phy: phy@4807000 { 813 compatible = "qcom,sm6125-qmp-ufs-phy"; 814 reg = <0x04807000 0xdb8>; 815 816 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 817 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 818 <&gcc GCC_UFS_MEM_CLKREF_CLK>; 819 clock-names = "ref", 820 "ref_aux", 821 "qref"; 822 823 resets = <&ufs_mem_hc 0>; 824 reset-names = "ufsphy"; 825 826 power-domains = <&gcc UFS_PHY_GDSC>; 827 828 #phy-cells = <0>; 829 830 status = "disabled"; 831 }; 832 833 gpi_dma0: dma-controller@4a00000 { 834 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 835 reg = <0x04a00000 0x60000>; 836 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 844 dma-channels = <8>; 845 dma-channel-mask = <0x1f>; 846 iommus = <&apps_smmu 0x136 0x0>; 847 #dma-cells = <3>; 848 status = "disabled"; 849 }; 850 851 qupv3_id_0: geniqup@4ac0000 { 852 compatible = "qcom,geni-se-qup"; 853 reg = <0x04ac0000 0x2000>; 854 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 855 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 856 clock-names = "m-ahb", "s-ahb"; 857 iommus = <&apps_smmu 0x123 0x0>; 858 #address-cells = <1>; 859 #size-cells = <1>; 860 ranges; 861 status = "disabled"; 862 863 i2c0: i2c@4a80000 { 864 compatible = "qcom,geni-i2c"; 865 reg = <0x04a80000 0x4000>; 866 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 867 clock-names = "se"; 868 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 869 pinctrl-0 = <&qup_i2c0_default>; 870 pinctrl-1 = <&qup_i2c0_sleep>; 871 pinctrl-names = "default", "sleep"; 872 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 873 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 874 dma-names = "tx", "rx"; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 status = "disabled"; 878 }; 879 880 spi0: spi@4a80000 { 881 compatible = "qcom,geni-spi"; 882 reg = <0x04a80000 0x4000>; 883 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 884 clock-names = "se"; 885 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 886 pinctrl-0 = <&qup_spi0_default>; 887 pinctrl-1 = <&qup_spi0_sleep>; 888 pinctrl-names = "default", "sleep"; 889 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 890 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 891 dma-names = "tx", "rx"; 892 #address-cells = <1>; 893 #size-cells = <0>; 894 status = "disabled"; 895 }; 896 897 i2c1: i2c@4a84000 { 898 compatible = "qcom,geni-i2c"; 899 reg = <0x04a84000 0x4000>; 900 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 901 clock-names = "se"; 902 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 903 pinctrl-0 = <&qup_i2c1_default>; 904 pinctrl-1 = <&qup_i2c1_sleep>; 905 pinctrl-names = "default", "sleep"; 906 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 907 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 908 dma-names = "tx", "rx"; 909 #address-cells = <1>; 910 #size-cells = <0>; 911 status = "disabled"; 912 }; 913 914 i2c2: i2c@4a88000 { 915 compatible = "qcom,geni-i2c"; 916 reg = <0x04a88000 0x4000>; 917 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 918 clock-names = "se"; 919 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 920 pinctrl-0 = <&qup_i2c2_default>; 921 pinctrl-1 = <&qup_i2c2_sleep>; 922 pinctrl-names = "default", "sleep"; 923 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 924 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 925 dma-names = "tx", "rx"; 926 #address-cells = <1>; 927 #size-cells = <0>; 928 status = "disabled"; 929 }; 930 931 spi2: spi@4a88000 { 932 compatible = "qcom,geni-spi"; 933 reg = <0x04a88000 0x4000>; 934 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 935 clock-names = "se"; 936 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 937 pinctrl-0 = <&qup_spi2_default>; 938 pinctrl-1 = <&qup_spi2_sleep>; 939 pinctrl-names = "default", "sleep"; 940 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 941 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 942 dma-names = "tx", "rx"; 943 #address-cells = <1>; 944 #size-cells = <0>; 945 status = "disabled"; 946 }; 947 948 i2c3: i2c@4a8c000 { 949 compatible = "qcom,geni-i2c"; 950 reg = <0x04a8c000 0x4000>; 951 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 952 clock-names = "se"; 953 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 954 pinctrl-0 = <&qup_i2c3_default>; 955 pinctrl-1 = <&qup_i2c3_sleep>; 956 pinctrl-names = "default", "sleep"; 957 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 958 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 959 dma-names = "tx", "rx"; 960 #address-cells = <1>; 961 #size-cells = <0>; 962 status = "disabled"; 963 }; 964 965 i2c4: i2c@4a90000 { 966 compatible = "qcom,geni-i2c"; 967 reg = <0x04a90000 0x4000>; 968 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 969 clock-names = "se"; 970 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 971 pinctrl-0 = <&qup_i2c4_default>; 972 pinctrl-1 = <&qup_i2c4_sleep>; 973 pinctrl-names = "default", "sleep"; 974 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 975 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 976 dma-names = "tx", "rx"; 977 #address-cells = <1>; 978 #size-cells = <0>; 979 status = "disabled"; 980 }; 981 }; 982 983 gpi_dma1: dma-controller@4c00000 { 984 compatible = "qcom,sm6125-gpi-dma", "qcom,sdm845-gpi-dma"; 985 reg = <0x04c00000 0x60000>; 986 interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 987 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 988 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 989 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 991 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 992 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 993 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>; 994 dma-channels = <8>; 995 dma-channel-mask = <0x0f>; 996 iommus = <&apps_smmu 0x156 0x0>; 997 #dma-cells = <3>; 998 status = "disabled"; 999 }; 1000 1001 qupv3_id_1: geniqup@4cc0000 { 1002 compatible = "qcom,geni-se-qup"; 1003 reg = <0x04cc0000 0x2000>; 1004 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1005 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1006 clock-names = "m-ahb", "s-ahb"; 1007 iommus = <&apps_smmu 0x143 0x0>; 1008 #address-cells = <1>; 1009 #size-cells = <1>; 1010 ranges; 1011 status = "disabled"; 1012 1013 i2c5: i2c@4c80000 { 1014 compatible = "qcom,geni-i2c"; 1015 reg = <0x04c80000 0x4000>; 1016 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1017 clock-names = "se"; 1018 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 1019 pinctrl-0 = <&qup_i2c5_default>; 1020 pinctrl-1 = <&qup_i2c5_sleep>; 1021 pinctrl-names = "default", "sleep"; 1022 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1023 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1024 dma-names = "tx", "rx"; 1025 #address-cells = <1>; 1026 #size-cells = <0>; 1027 status = "disabled"; 1028 }; 1029 1030 spi5: spi@4c80000 { 1031 compatible = "qcom,geni-spi"; 1032 reg = <0x04c80000 0x4000>; 1033 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1034 clock-names = "se"; 1035 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 1036 pinctrl-0 = <&qup_spi5_default>; 1037 pinctrl-1 = <&qup_spi5_sleep>; 1038 pinctrl-names = "default", "sleep"; 1039 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1040 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1041 dma-names = "tx", "rx"; 1042 #address-cells = <1>; 1043 #size-cells = <0>; 1044 status = "disabled"; 1045 }; 1046 1047 i2c6: i2c@4c84000 { 1048 compatible = "qcom,geni-i2c"; 1049 reg = <0x04c84000 0x4000>; 1050 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1051 clock-names = "se"; 1052 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1053 pinctrl-0 = <&qup_i2c6_default>; 1054 pinctrl-1 = <&qup_i2c6_sleep>; 1055 pinctrl-names = "default", "sleep"; 1056 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1057 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1058 dma-names = "tx", "rx"; 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 status = "disabled"; 1062 }; 1063 1064 spi6: spi@4c84000 { 1065 compatible = "qcom,geni-spi"; 1066 reg = <0x04c84000 0x4000>; 1067 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1068 clock-names = "se"; 1069 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1070 pinctrl-0 = <&qup_spi6_default>; 1071 pinctrl-1 = <&qup_spi6_sleep>; 1072 pinctrl-names = "default", "sleep"; 1073 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1074 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1075 dma-names = "tx", "rx"; 1076 #address-cells = <1>; 1077 #size-cells = <0>; 1078 status = "disabled"; 1079 }; 1080 1081 i2c7: i2c@4c88000 { 1082 compatible = "qcom,geni-i2c"; 1083 reg = <0x04c88000 0x4000>; 1084 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1085 clock-names = "se"; 1086 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1087 pinctrl-0 = <&qup_i2c7_default>; 1088 pinctrl-1 = <&qup_i2c7_sleep>; 1089 pinctrl-names = "default", "sleep"; 1090 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1091 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1092 dma-names = "tx", "rx"; 1093 #address-cells = <1>; 1094 #size-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 i2c8: i2c@4c8c000 { 1099 compatible = "qcom,geni-i2c"; 1100 reg = <0x04c8c000 0x4000>; 1101 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1102 clock-names = "se"; 1103 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1104 pinctrl-0 = <&qup_i2c8_default>; 1105 pinctrl-1 = <&qup_i2c8_sleep>; 1106 pinctrl-names = "default", "sleep"; 1107 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1108 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1109 dma-names = "tx", "rx"; 1110 #address-cells = <1>; 1111 #size-cells = <0>; 1112 status = "disabled"; 1113 }; 1114 1115 spi8: spi@4c8c000 { 1116 compatible = "qcom,geni-spi"; 1117 reg = <0x04c8c000 0x4000>; 1118 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1119 clock-names = "se"; 1120 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1121 pinctrl-0 = <&qup_spi8_default>; 1122 pinctrl-1 = <&qup_spi8_sleep>; 1123 pinctrl-names = "default", "sleep"; 1124 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1125 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1126 dma-names = "tx", "rx"; 1127 #address-cells = <1>; 1128 #size-cells = <0>; 1129 status = "disabled"; 1130 }; 1131 1132 i2c9: i2c@4c90000 { 1133 compatible = "qcom,geni-i2c"; 1134 reg = <0x04c90000 0x4000>; 1135 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1136 clock-names = "se"; 1137 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1138 pinctrl-0 = <&qup_i2c9_default>; 1139 pinctrl-1 = <&qup_i2c9_sleep>; 1140 pinctrl-names = "default", "sleep"; 1141 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1142 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1143 dma-names = "tx", "rx"; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 status = "disabled"; 1147 }; 1148 1149 spi9: spi@4c90000 { 1150 compatible = "qcom,geni-spi"; 1151 reg = <0x04c90000 0x4000>; 1152 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1153 clock-names = "se"; 1154 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 1155 pinctrl-0 = <&qup_spi9_default>; 1156 pinctrl-1 = <&qup_spi9_sleep>; 1157 pinctrl-names = "default", "sleep"; 1158 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1159 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1160 dma-names = "tx", "rx"; 1161 #address-cells = <1>; 1162 #size-cells = <0>; 1163 status = "disabled"; 1164 }; 1165 }; 1166 1167 usb3: usb@4ef8800 { 1168 compatible = "qcom,sm6125-dwc3", "qcom,dwc3"; 1169 reg = <0x04ef8800 0x400>; 1170 #address-cells = <1>; 1171 #size-cells = <1>; 1172 ranges; 1173 1174 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1175 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1176 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1177 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1178 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1179 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1180 clock-names = "cfg_noc", 1181 "core", 1182 "iface", 1183 "sleep", 1184 "mock_utmi", 1185 "xo"; 1186 1187 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1188 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1189 assigned-clock-rates = <19200000>, <66666667>; 1190 1191 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 1192 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1193 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1194 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>; 1195 interrupt-names = "pwr_event", 1196 "qusb2_phy", 1197 "hs_phy_irq", 1198 "ss_phy_irq"; 1199 1200 power-domains = <&gcc USB30_PRIM_GDSC>; 1201 qcom,select-utmi-as-pipe-clk; 1202 status = "disabled"; 1203 1204 usb3_dwc3: usb@4e00000 { 1205 compatible = "snps,dwc3"; 1206 reg = <0x04e00000 0xcd00>; 1207 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1208 iommus = <&apps_smmu 0x100 0x0>; 1209 phys = <&hsusb_phy1>; 1210 phy-names = "usb2-phy"; 1211 snps,dis_u2_susphy_quirk; 1212 snps,dis_enblslpm_quirk; 1213 snps,dis-u1-entry-quirk; 1214 snps,dis-u2-entry-quirk; 1215 maximum-speed = "high-speed"; 1216 dr_mode = "peripheral"; 1217 }; 1218 }; 1219 1220 sram@4690000 { 1221 compatible = "qcom,rpm-stats"; 1222 reg = <0x04690000 0x10000>; 1223 }; 1224 1225 mdss: display-subsystem@5e00000 { 1226 compatible = "qcom,sm6125-mdss"; 1227 reg = <0x05e00000 0x1000>; 1228 reg-names = "mdss"; 1229 1230 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1231 interrupt-controller; 1232 #interrupt-cells = <1>; 1233 1234 clocks = <&gcc GCC_DISP_AHB_CLK>, 1235 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1236 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1237 clock-names = "iface", 1238 "ahb", 1239 "core"; 1240 1241 power-domains = <&dispcc MDSS_GDSC>; 1242 1243 iommus = <&apps_smmu 0x400 0x0>; 1244 1245 #address-cells = <1>; 1246 #size-cells = <1>; 1247 ranges; 1248 1249 status = "disabled"; 1250 1251 mdss_mdp: display-controller@5e01000 { 1252 compatible = "qcom,sm6125-dpu"; 1253 reg = <0x05e01000 0x83208>, 1254 <0x05eb0000 0x3000>; 1255 reg-names = "mdp", "vbif"; 1256 1257 interrupt-parent = <&mdss>; 1258 interrupts = <0>; 1259 1260 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1261 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1262 <&dispcc DISP_CC_MDSS_ROT_CLK>, 1263 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1264 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1265 <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 1266 <&gcc GCC_DISP_THROTTLE_CORE_CLK>; 1267 clock-names = "bus", 1268 "iface", 1269 "rot", 1270 "lut", 1271 "core", 1272 "vsync", 1273 "throttle"; 1274 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1275 assigned-clock-rates = <19200000>; 1276 1277 operating-points-v2 = <&mdp_opp_table>; 1278 power-domains = <&rpmpd SM6125_VDDCX>; 1279 1280 ports { 1281 #address-cells = <1>; 1282 #size-cells = <0>; 1283 1284 port@0 { 1285 reg = <0>; 1286 dpu_intf1_out: endpoint { 1287 remote-endpoint = <&mdss_dsi0_in>; 1288 }; 1289 }; 1290 }; 1291 1292 mdp_opp_table: opp-table { 1293 compatible = "operating-points-v2"; 1294 1295 opp-192000000 { 1296 opp-hz = /bits/ 64 <192000000>; 1297 required-opps = <&rpmpd_opp_low_svs>; 1298 }; 1299 1300 opp-256000000 { 1301 opp-hz = /bits/ 64 <256000000>; 1302 required-opps = <&rpmpd_opp_svs>; 1303 }; 1304 1305 opp-307200000 { 1306 opp-hz = /bits/ 64 <307200000>; 1307 required-opps = <&rpmpd_opp_svs_plus>; 1308 }; 1309 1310 opp-384000000 { 1311 opp-hz = /bits/ 64 <384000000>; 1312 required-opps = <&rpmpd_opp_nom>; 1313 }; 1314 1315 opp-400000000 { 1316 opp-hz = /bits/ 64 <400000000>; 1317 required-opps = <&rpmpd_opp_turbo>; 1318 }; 1319 }; 1320 }; 1321 1322 mdss_dsi0: dsi@5e94000 { 1323 compatible = "qcom,sm6125-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1324 reg = <0x05e94000 0x400>; 1325 reg-names = "dsi_ctrl"; 1326 1327 interrupt-parent = <&mdss>; 1328 interrupts = <4>; 1329 1330 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1331 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1332 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1333 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1334 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1335 <&gcc GCC_DISP_HF_AXI_CLK>; 1336 clock-names = "byte", 1337 "byte_intf", 1338 "pixel", 1339 "core", 1340 "iface", 1341 "bus"; 1342 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1343 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1344 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1345 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1346 1347 operating-points-v2 = <&dsi_opp_table>; 1348 power-domains = <&rpmpd SM6125_VDDCX>; 1349 1350 phys = <&mdss_dsi0_phy>; 1351 phy-names = "dsi"; 1352 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 1356 status = "disabled"; 1357 1358 ports { 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 1362 port@0 { 1363 reg = <0>; 1364 mdss_dsi0_in: endpoint { 1365 remote-endpoint = <&dpu_intf1_out>; 1366 }; 1367 }; 1368 1369 port@1 { 1370 reg = <1>; 1371 mdss_dsi0_out: endpoint { 1372 }; 1373 }; 1374 }; 1375 1376 dsi_opp_table: opp-table { 1377 compatible = "operating-points-v2"; 1378 1379 opp-164000000 { 1380 opp-hz = /bits/ 64 <164000000>; 1381 required-opps = <&rpmpd_opp_low_svs>; 1382 }; 1383 1384 opp-187500000 { 1385 opp-hz = /bits/ 64 <187500000>; 1386 required-opps = <&rpmpd_opp_svs>; 1387 }; 1388 }; 1389 }; 1390 1391 mdss_dsi0_phy: phy@5e94400 { 1392 compatible = "qcom,sm6125-dsi-phy-14nm"; 1393 reg = <0x05e94400 0x100>, 1394 <0x05e94500 0x300>, 1395 <0x05e94800 0x188>; 1396 reg-names = "dsi_phy", 1397 "dsi_phy_lane", 1398 "dsi_pll"; 1399 1400 #clock-cells = <1>; 1401 #phy-cells = <0>; 1402 1403 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1404 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1405 clock-names = "iface", 1406 "ref"; 1407 1408 required-opps = <&rpmpd_opp_nom>; 1409 power-domains = <&rpmpd SM6125_VDDMX>; 1410 1411 status = "disabled"; 1412 }; 1413 }; 1414 1415 dispcc: clock-controller@5f00000 { 1416 compatible = "qcom,sm6125-dispcc"; 1417 reg = <0x05f00000 0x20000>; 1418 1419 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1420 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1421 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1422 <0>, 1423 <0>, 1424 <0>, 1425 <&gcc GCC_DISP_AHB_CLK>, 1426 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; 1427 clock-names = "bi_tcxo", 1428 "dsi0_phy_pll_out_byteclk", 1429 "dsi0_phy_pll_out_dsiclk", 1430 "dsi1_phy_pll_out_dsiclk", 1431 "dp_phy_pll_link_clk", 1432 "dp_phy_pll_vco_div_clk", 1433 "cfg_ahb_clk", 1434 "gcc_disp_gpll0_div_clk_src"; 1435 1436 required-opps = <&rpmpd_opp_ret>; 1437 power-domains = <&rpmpd SM6125_VDDCX>; 1438 1439 #clock-cells = <1>; 1440 #power-domain-cells = <1>; 1441 }; 1442 1443 apps_smmu: iommu@c600000 { 1444 compatible = "qcom,sm6125-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1445 reg = <0x0c600000 0x80000>; 1446 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 1447 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1448 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 1449 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 1450 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 1451 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 1452 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 1453 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 1454 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 1455 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1457 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1458 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1459 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1460 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1461 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1462 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1463 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1464 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1465 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1466 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1467 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1468 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1469 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1473 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1474 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1475 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1477 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1478 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1479 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1480 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1481 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1482 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1483 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1485 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1486 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 1487 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1488 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1489 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1490 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1491 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 1492 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 1493 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1494 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1496 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 1497 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 1498 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 1499 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 1500 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 1501 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 1502 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 1503 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 1504 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1505 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 1506 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 1507 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 1508 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1509 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 1510 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 1511 1512 #global-interrupts = <1>; 1513 #iommu-cells = <2>; 1514 }; 1515 1516 apcs_glb: mailbox@f111000 { 1517 compatible = "qcom,sm6125-apcs-hmss-global", 1518 "qcom,msm8994-apcs-kpss-global"; 1519 reg = <0x0f111000 0x1000>; 1520 1521 #mbox-cells = <1>; 1522 }; 1523 1524 timer@f120000 { 1525 compatible = "arm,armv7-timer-mem"; 1526 #address-cells = <1>; 1527 #size-cells = <1>; 1528 ranges; 1529 reg = <0x0f120000 0x1000>; 1530 clock-frequency = <19200000>; 1531 1532 frame@f121000 { 1533 frame-number = <0>; 1534 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1535 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1536 reg = <0x0f121000 0x1000>, 1537 <0x0f122000 0x1000>; 1538 }; 1539 1540 frame@f123000 { 1541 frame-number = <1>; 1542 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1543 reg = <0x0f123000 0x1000>; 1544 status = "disabled"; 1545 }; 1546 1547 frame@f124000 { 1548 frame-number = <2>; 1549 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1550 reg = <0x0f124000 0x1000>; 1551 status = "disabled"; 1552 }; 1553 1554 frame@f125000 { 1555 frame-number = <3>; 1556 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1557 reg = <0x0f125000 0x1000>; 1558 status = "disabled"; 1559 }; 1560 1561 frame@f126000 { 1562 frame-number = <4>; 1563 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1564 reg = <0x0f126000 0x1000>; 1565 status = "disabled"; 1566 }; 1567 1568 frame@f127000 { 1569 frame-number = <5>; 1570 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1571 reg = <0x0f127000 0x1000>; 1572 status = "disabled"; 1573 }; 1574 1575 frame@f128000 { 1576 frame-number = <6>; 1577 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1578 reg = <0x0f128000 0x1000>; 1579 status = "disabled"; 1580 }; 1581 }; 1582 1583 intc: interrupt-controller@f200000 { 1584 compatible = "arm,gic-v3"; 1585 reg = <0x0f200000 0x20000>, 1586 <0x0f300000 0x100000>; 1587 #interrupt-cells = <3>; 1588 interrupt-controller; 1589 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1590 }; 1591 }; 1592 1593 timer { 1594 compatible = "arm,armv8-timer"; 1595 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1596 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1597 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1598 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1599 clock-frequency = <19200000>; 1600 }; 1601};
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