sm6115.dtsi

   1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2/*
   3 * Copyright (c) 2021, Iskren Chernev <iskren.chernev@gmail.com>
   4 */
   5
   6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
   7#include <dt-bindings/clock/qcom,gcc-sm6115.h>
   8#include <dt-bindings/clock/qcom,sm6115-dispcc.h>
   9#include <dt-bindings/clock/qcom,sm6115-gpucc.h>
  10#include <dt-bindings/clock/qcom,rpmcc.h>
  11#include <dt-bindings/dma/qcom-gpi.h>
  12#include <dt-bindings/firmware/qcom,scm.h>
  13#include <dt-bindings/gpio/gpio.h>
  14#include <dt-bindings/interconnect/qcom,rpm-icc.h>
  15#include <dt-bindings/interconnect/qcom,sm6115.h>
  16#include <dt-bindings/interrupt-controller/arm-gic.h>
  17#include <dt-bindings/power/qcom-rpmpd.h>
  18#include <dt-bindings/soc/qcom,apr.h>
  19#include <dt-bindings/sound/qcom,q6asm.h>
  20#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
  21#include <dt-bindings/thermal/thermal.h>
  22
  23/ {
  24	interrupt-parent = <&intc>;
  25
  26	#address-cells = <2>;
  27	#size-cells = <2>;
  28
  29	chosen { };
  30
  31	clocks {
  32		xo_board: xo-board {
  33			compatible = "fixed-clock";
  34			#clock-cells = <0>;
  35		};
  36
  37		sleep_clk: sleep-clk {
  38			compatible = "fixed-clock";
  39			#clock-cells = <0>;
  40		};
  41	};
  42
  43	cpus {
  44		#address-cells = <2>;
  45		#size-cells = <0>;
  46
  47		cpu0: cpu@0 {
  48			device_type = "cpu";
  49			compatible = "qcom,kryo260";
  50			reg = <0x0 0x0>;
  51			clocks = <&cpufreq_hw 0>;
  52			capacity-dmips-mhz = <1024>;
  53			dynamic-power-coefficient = <100>;
  54			enable-method = "psci";
  55			next-level-cache = <&l2_0>;
  56			qcom,freq-domain = <&cpufreq_hw 0>;
  57			power-domains = <&cpu_pd0>;
  58			power-domain-names = "psci";
  59			l2_0: l2-cache {
  60				compatible = "cache";
  61				cache-level = <2>;
  62				cache-unified;
  63			};
  64		};
  65
  66		cpu1: cpu@1 {
  67			device_type = "cpu";
  68			compatible = "qcom,kryo260";
  69			reg = <0x0 0x1>;
  70			clocks = <&cpufreq_hw 0>;
  71			capacity-dmips-mhz = <1024>;
  72			dynamic-power-coefficient = <100>;
  73			enable-method = "psci";
  74			next-level-cache = <&l2_0>;
  75			qcom,freq-domain = <&cpufreq_hw 0>;
  76			power-domains = <&cpu_pd1>;
  77			power-domain-names = "psci";
  78		};
  79
  80		cpu2: cpu@2 {
  81			device_type = "cpu";
  82			compatible = "qcom,kryo260";
  83			reg = <0x0 0x2>;
  84			clocks = <&cpufreq_hw 0>;
  85			capacity-dmips-mhz = <1024>;
  86			dynamic-power-coefficient = <100>;
  87			enable-method = "psci";
  88			next-level-cache = <&l2_0>;
  89			qcom,freq-domain = <&cpufreq_hw 0>;
  90			power-domains = <&cpu_pd2>;
  91			power-domain-names = "psci";
  92		};
  93
  94		cpu3: cpu@3 {
  95			device_type = "cpu";
  96			compatible = "qcom,kryo260";
  97			reg = <0x0 0x3>;
  98			clocks = <&cpufreq_hw 0>;
  99			capacity-dmips-mhz = <1024>;
 100			dynamic-power-coefficient = <100>;
 101			enable-method = "psci";
 102			next-level-cache = <&l2_0>;
 103			qcom,freq-domain = <&cpufreq_hw 0>;
 104			power-domains = <&cpu_pd3>;
 105			power-domain-names = "psci";
 106		};
 107
 108		cpu4: cpu@100 {
 109			device_type = "cpu";
 110			compatible = "qcom,kryo260";
 111			reg = <0x0 0x100>;
 112			clocks = <&cpufreq_hw 1>;
 113			enable-method = "psci";
 114			capacity-dmips-mhz = <1638>;
 115			dynamic-power-coefficient = <282>;
 116			next-level-cache = <&l2_1>;
 117			qcom,freq-domain = <&cpufreq_hw 1>;
 118			power-domains = <&cpu_pd4>;
 119			power-domain-names = "psci";
 120			l2_1: l2-cache {
 121				compatible = "cache";
 122				cache-level = <2>;
 123				cache-unified;
 124			};
 125		};
 126
 127		cpu5: cpu@101 {
 128			device_type = "cpu";
 129			compatible = "qcom,kryo260";
 130			reg = <0x0 0x101>;
 131			clocks = <&cpufreq_hw 1>;
 132			capacity-dmips-mhz = <1638>;
 133			dynamic-power-coefficient = <282>;
 134			enable-method = "psci";
 135			next-level-cache = <&l2_1>;
 136			qcom,freq-domain = <&cpufreq_hw 1>;
 137			power-domains = <&cpu_pd5>;
 138			power-domain-names = "psci";
 139		};
 140
 141		cpu6: cpu@102 {
 142			device_type = "cpu";
 143			compatible = "qcom,kryo260";
 144			reg = <0x0 0x102>;
 145			clocks = <&cpufreq_hw 1>;
 146			capacity-dmips-mhz = <1638>;
 147			dynamic-power-coefficient = <282>;
 148			enable-method = "psci";
 149			next-level-cache = <&l2_1>;
 150			qcom,freq-domain = <&cpufreq_hw 1>;
 151			power-domains = <&cpu_pd6>;
 152			power-domain-names = "psci";
 153		};
 154
 155		cpu7: cpu@103 {
 156			device_type = "cpu";
 157			compatible = "qcom,kryo260";
 158			reg = <0x0 0x103>;
 159			clocks = <&cpufreq_hw 1>;
 160			capacity-dmips-mhz = <1638>;
 161			dynamic-power-coefficient = <282>;
 162			enable-method = "psci";
 163			next-level-cache = <&l2_1>;
 164			qcom,freq-domain = <&cpufreq_hw 1>;
 165			power-domains = <&cpu_pd7>;
 166			power-domain-names = "psci";
 167		};
 168
 169		cpu-map {
 170			cluster0 {
 171				core0 {
 172					cpu = <&cpu0>;
 173				};
 174
 175				core1 {
 176					cpu = <&cpu1>;
 177				};
 178
 179				core2 {
 180					cpu = <&cpu2>;
 181				};
 182
 183				core3 {
 184					cpu = <&cpu3>;
 185				};
 186			};
 187
 188			cluster1 {
 189				core0 {
 190					cpu = <&cpu4>;
 191				};
 192
 193				core1 {
 194					cpu = <&cpu5>;
 195				};
 196
 197				core2 {
 198					cpu = <&cpu6>;
 199				};
 200
 201				core3 {
 202					cpu = <&cpu7>;
 203				};
 204			};
 205		};
 206
 207		idle-states {
 208			entry-method = "psci";
 209
 210			little_cpu_sleep_0: cpu-sleep-0-0 {
 211				compatible = "arm,idle-state";
 212				idle-state-name = "silver-rail-power-collapse";
 213				arm,psci-suspend-param = <0x40000003>;
 214				entry-latency-us = <290>;
 215				exit-latency-us = <376>;
 216				min-residency-us = <1182>;
 217				local-timer-stop;
 218			};
 219
 220			big_cpu_sleep_0: cpu-sleep-1-0 {
 221				compatible = "arm,idle-state";
 222				idle-state-name = "gold-rail-power-collapse";
 223				arm,psci-suspend-param = <0x40000003>;
 224				entry-latency-us = <297>;
 225				exit-latency-us = <324>;
 226				min-residency-us = <1110>;
 227				local-timer-stop;
 228			};
 229		};
 230
 231		domain-idle-states {
 232			cluster_0_sleep_0: cluster-sleep-0-0 {
 233				/* GDHS */
 234				compatible = "domain-idle-state";
 235				arm,psci-suspend-param = <0x40000022>;
 236				entry-latency-us = <360>;
 237				exit-latency-us = <421>;
 238				min-residency-us = <782>;
 239			};
 240
 241			cluster_0_sleep_1: cluster-sleep-0-1 {
 242				/* Power Collapse */
 243				compatible = "domain-idle-state";
 244				arm,psci-suspend-param = <0x41000044>;
 245				entry-latency-us = <800>;
 246				exit-latency-us = <2118>;
 247				min-residency-us = <7376>;
 248			};
 249
 250			cluster_1_sleep_0: cluster-sleep-1-0 {
 251				/* GDHS */
 252				compatible = "domain-idle-state";
 253				arm,psci-suspend-param = <0x40000042>;
 254				entry-latency-us = <314>;
 255				exit-latency-us = <345>;
 256				min-residency-us = <660>;
 257			};
 258
 259			cluster_1_sleep_1: cluster-sleep-1-1 {
 260				/* Power Collapse */
 261				compatible = "domain-idle-state";
 262				arm,psci-suspend-param = <0x41000044>;
 263				entry-latency-us = <640>;
 264				exit-latency-us = <1654>;
 265				min-residency-us = <8094>;
 266			};
 267		};
 268	};
 269
 270	firmware {
 271		scm: scm {
 272			compatible = "qcom,scm-sm6115", "qcom,scm";
 273			#reset-cells = <1>;
 274			interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG
 275					 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
 276		};
 277	};
 278
 279	memory@80000000 {
 280		device_type = "memory";
 281		/* We expect the bootloader to fill in the size */
 282		reg = <0 0x80000000 0 0>;
 283	};
 284
 285	qup_opp_table: opp-table-qup {
 286		compatible = "operating-points-v2";
 287
 288		opp-75000000 {
 289			opp-hz = /bits/ 64 <75000000>;
 290			required-opps = <&rpmpd_opp_low_svs>;
 291		};
 292
 293		opp-100000000 {
 294			opp-hz = /bits/ 64 <100000000>;
 295			required-opps = <&rpmpd_opp_svs>;
 296		};
 297
 298		opp-128000000 {
 299			opp-hz = /bits/ 64 <128000000>;
 300			required-opps = <&rpmpd_opp_nom>;
 301		};
 302	};
 303
 304	pmu {
 305		compatible = "arm,armv8-pmuv3";
 306		interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>;
 307	};
 308
 309	psci {
 310		compatible = "arm,psci-1.0";
 311		method = "smc";
 312
 313		cpu_pd0: power-domain-cpu0 {
 314			#power-domain-cells = <0>;
 315			power-domains = <&cluster_0_pd>;
 316			domain-idle-states = <&little_cpu_sleep_0>;
 317		};
 318
 319		cpu_pd1: power-domain-cpu1 {
 320			#power-domain-cells = <0>;
 321			power-domains = <&cluster_0_pd>;
 322			domain-idle-states = <&little_cpu_sleep_0>;
 323		};
 324
 325		cpu_pd2: power-domain-cpu2 {
 326			#power-domain-cells = <0>;
 327			power-domains = <&cluster_0_pd>;
 328			domain-idle-states = <&little_cpu_sleep_0>;
 329		};
 330
 331		cpu_pd3: power-domain-cpu3 {
 332			#power-domain-cells = <0>;
 333			power-domains = <&cluster_0_pd>;
 334			domain-idle-states = <&little_cpu_sleep_0>;
 335		};
 336
 337		cpu_pd4: power-domain-cpu4 {
 338			#power-domain-cells = <0>;
 339			power-domains = <&cluster_1_pd>;
 340			domain-idle-states = <&big_cpu_sleep_0>;
 341		};
 342
 343		cpu_pd5: power-domain-cpu5 {
 344			#power-domain-cells = <0>;
 345			power-domains = <&cluster_1_pd>;
 346			domain-idle-states = <&big_cpu_sleep_0>;
 347		};
 348
 349		cpu_pd6: power-domain-cpu6 {
 350			#power-domain-cells = <0>;
 351			power-domains = <&cluster_1_pd>;
 352			domain-idle-states = <&big_cpu_sleep_0>;
 353		};
 354
 355		cpu_pd7: power-domain-cpu7 {
 356			#power-domain-cells = <0>;
 357			power-domains = <&cluster_1_pd>;
 358			domain-idle-states = <&big_cpu_sleep_0>;
 359		};
 360
 361		cluster_0_pd: power-domain-cpu-cluster0 {
 362			#power-domain-cells = <0>;
 363			domain-idle-states = <&cluster_0_sleep_0>, <&cluster_0_sleep_1>;
 364		};
 365
 366		cluster_1_pd: power-domain-cpu-cluster1 {
 367			#power-domain-cells = <0>;
 368			domain-idle-states = <&cluster_1_sleep_0>, <&cluster_1_sleep_1>;
 369		};
 370	};
 371
 372	rpm: remoteproc {
 373		compatible = "qcom,sm6115-rpm-proc", "qcom,rpm-proc";
 374
 375		glink-edge {
 376			compatible = "qcom,glink-rpm";
 377
 378			interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>;
 379			qcom,rpm-msg-ram = <&rpm_msg_ram>;
 380			mboxes = <&apcs_glb 0>;
 381
 382			rpm_requests: rpm-requests {
 383				compatible = "qcom,rpm-sm6115", "qcom,glink-smd-rpm";
 384				qcom,glink-channels = "rpm_requests";
 385
 386				rpmcc: clock-controller {
 387					compatible = "qcom,rpmcc-sm6115", "qcom,rpmcc";
 388					clocks = <&xo_board>;
 389					clock-names = "xo";
 390					#clock-cells = <1>;
 391				};
 392
 393				rpmpd: power-controller {
 394					compatible = "qcom,sm6115-rpmpd";
 395					#power-domain-cells = <1>;
 396					operating-points-v2 = <&rpmpd_opp_table>;
 397
 398					rpmpd_opp_table: opp-table {
 399						compatible = "operating-points-v2";
 400
 401						rpmpd_opp_min_svs: opp1 {
 402							opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
 403						};
 404
 405						rpmpd_opp_low_svs: opp2 {
 406							opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
 407						};
 408
 409						rpmpd_opp_svs: opp3 {
 410							opp-level = <RPM_SMD_LEVEL_SVS>;
 411						};
 412
 413						rpmpd_opp_svs_plus: opp4 {
 414							opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
 415						};
 416
 417						rpmpd_opp_nom: opp5 {
 418							opp-level = <RPM_SMD_LEVEL_NOM>;
 419						};
 420
 421						rpmpd_opp_nom_plus: opp6 {
 422							opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
 423						};
 424
 425						rpmpd_opp_turbo: opp7 {
 426							opp-level = <RPM_SMD_LEVEL_TURBO>;
 427						};
 428
 429						rpmpd_opp_turbo_plus: opp8 {
 430							opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
 431						};
 432					};
 433				};
 434			};
 435		};
 436	};
 437
 438	reserved_memory: reserved-memory {
 439		#address-cells = <2>;
 440		#size-cells = <2>;
 441		ranges;
 442
 443		hyp_mem: memory@45700000 {
 444			reg = <0x0 0x45700000 0x0 0x600000>;
 445			no-map;
 446		};
 447
 448		xbl_aop_mem: memory@45e00000 {
 449			reg = <0x0 0x45e00000 0x0 0x140000>;
 450			no-map;
 451		};
 452
 453		sec_apps_mem: memory@45fff000 {
 454			reg = <0x0 0x45fff000 0x0 0x1000>;
 455			no-map;
 456		};
 457
 458		smem_mem: memory@46000000 {
 459			compatible = "qcom,smem";
 460			reg = <0x0 0x46000000 0x0 0x200000>;
 461			no-map;
 462
 463			hwlocks = <&tcsr_mutex 3>;
 464			qcom,rpm-msg-ram = <&rpm_msg_ram>;
 465		};
 466
 467		cdsp_sec_mem: memory@46200000 {
 468			reg = <0x0 0x46200000 0x0 0x1e00000>;
 469			no-map;
 470		};
 471
 472		pil_modem_mem: memory@4ab00000 {
 473			reg = <0x0 0x4ab00000 0x0 0x6900000>;
 474			no-map;
 475		};
 476
 477		pil_video_mem: memory@51400000 {
 478			reg = <0x0 0x51400000 0x0 0x500000>;
 479			no-map;
 480		};
 481
 482		wlan_msa_mem: memory@51900000 {
 483			reg = <0x0 0x51900000 0x0 0x100000>;
 484			no-map;
 485		};
 486
 487		pil_cdsp_mem: memory@51a00000 {
 488			reg = <0x0 0x51a00000 0x0 0x1e00000>;
 489			no-map;
 490		};
 491
 492		pil_adsp_mem: memory@53800000 {
 493			reg = <0x0 0x53800000 0x0 0x2800000>;
 494			no-map;
 495		};
 496
 497		pil_ipa_fw_mem: memory@56100000 {
 498			reg = <0x0 0x56100000 0x0 0x10000>;
 499			no-map;
 500		};
 501
 502		pil_ipa_gsi_mem: memory@56110000 {
 503			reg = <0x0 0x56110000 0x0 0x5000>;
 504			no-map;
 505		};
 506
 507		pil_gpu_mem: memory@56115000 {
 508			reg = <0x0 0x56115000 0x0 0x2000>;
 509			no-map;
 510		};
 511
 512		cont_splash_memory: memory@5c000000 {
 513			reg = <0x0 0x5c000000 0x0 0x00f00000>;
 514			no-map;
 515		};
 516
 517		dfps_data_memory: memory@5cf00000 {
 518			reg = <0x0 0x5cf00000 0x0 0x0100000>;
 519			no-map;
 520		};
 521
 522		removed_mem: memory@60000000 {
 523			reg = <0x0 0x60000000 0x0 0x3900000>;
 524			no-map;
 525		};
 526
 527		rmtfs_mem: memory@89b01000 {
 528			compatible = "qcom,rmtfs-mem";
 529			reg = <0x0 0x89b01000 0x0 0x200000>;
 530			no-map;
 531
 532			qcom,client-id = <1>;
 533			qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>;
 534		};
 535	};
 536
 537	smp2p-adsp {
 538		compatible = "qcom,smp2p";
 539		qcom,smem = <443>, <429>;
 540
 541		interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>;
 542
 543		mboxes = <&apcs_glb 10>;
 544
 545		qcom,local-pid = <0>;
 546		qcom,remote-pid = <2>;
 547
 548		adsp_smp2p_out: master-kernel {
 549			qcom,entry-name = "master-kernel";
 550			#qcom,smem-state-cells = <1>;
 551		};
 552
 553		adsp_smp2p_in: slave-kernel {
 554			qcom,entry-name = "slave-kernel";
 555
 556			interrupt-controller;
 557			#interrupt-cells = <2>;
 558		};
 559	};
 560
 561	smp2p-cdsp {
 562		compatible = "qcom,smp2p";
 563		qcom,smem = <94>, <432>;
 564
 565		interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING>;
 566
 567		mboxes = <&apcs_glb 30>;
 568
 569		qcom,local-pid = <0>;
 570		qcom,remote-pid = <5>;
 571
 572		cdsp_smp2p_out: master-kernel {
 573			qcom,entry-name = "master-kernel";
 574			#qcom,smem-state-cells = <1>;
 575		};
 576
 577		cdsp_smp2p_in: slave-kernel {
 578			qcom,entry-name = "slave-kernel";
 579
 580			interrupt-controller;
 581			#interrupt-cells = <2>;
 582		};
 583	};
 584
 585	smp2p-mpss {
 586		compatible = "qcom,smp2p";
 587		qcom,smem = <435>, <428>;
 588
 589		interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>;
 590
 591		mboxes = <&apcs_glb 14>;
 592
 593		qcom,local-pid = <0>;
 594		qcom,remote-pid = <1>;
 595
 596		modem_smp2p_out: master-kernel {
 597			qcom,entry-name = "master-kernel";
 598			#qcom,smem-state-cells = <1>;
 599		};
 600
 601		modem_smp2p_in: slave-kernel {
 602			qcom,entry-name = "slave-kernel";
 603
 604			interrupt-controller;
 605			#interrupt-cells = <2>;
 606		};
 607	};
 608
 609	soc: soc@0 {
 610		compatible = "simple-bus";
 611		#address-cells = <2>;
 612		#size-cells = <2>;
 613		ranges = <0 0 0 0 0x10 0>;
 614		dma-ranges = <0 0 0 0 0x10 0>;
 615
 616		tcsr_mutex: hwlock@340000 {
 617			compatible = "qcom,tcsr-mutex";
 618			reg = <0x0 0x00340000 0x0 0x20000>;
 619			#hwlock-cells = <1>;
 620		};
 621
 622		tcsr_regs: syscon@3c0000 {
 623			compatible = "qcom,sm6115-tcsr", "syscon";
 624			reg = <0x0 0x003c0000 0x0 0x40000>;
 625		};
 626
 627		tlmm: pinctrl@500000 {
 628			compatible = "qcom,sm6115-tlmm";
 629			reg = <0x0 0x00500000 0x0 0x400000>,
 630			      <0x0 0x00900000 0x0 0x400000>,
 631			      <0x0 0x00d00000 0x0 0x400000>;
 632			reg-names = "west", "south", "east";
 633			interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 634			gpio-controller;
 635			gpio-ranges = <&tlmm 0 0 114>; /* GPIOs + ufs_reset */
 636			#gpio-cells = <2>;
 637			interrupt-controller;
 638			#interrupt-cells = <2>;
 639
 640			qup_i2c0_default: qup-i2c0-default-state {
 641				pins = "gpio0", "gpio1";
 642				function = "qup0";
 643				drive-strength = <2>;
 644				bias-pull-up;
 645			};
 646
 647			qup_i2c1_default: qup-i2c1-default-state {
 648				pins = "gpio4", "gpio5";
 649				function = "qup1";
 650				drive-strength = <2>;
 651				bias-pull-up;
 652			};
 653
 654			qup_i2c2_default: qup-i2c2-default-state {
 655				pins = "gpio6", "gpio7";
 656				function = "qup2";
 657				drive-strength = <2>;
 658				bias-pull-up;
 659			};
 660
 661			qup_i2c3_default: qup-i2c3-default-state {
 662				pins = "gpio8", "gpio9";
 663				function = "qup3";
 664				drive-strength = <2>;
 665				bias-pull-up;
 666			};
 667
 668			qup_i2c4_default: qup-i2c4-default-state {
 669				pins = "gpio12", "gpio13";
 670				function = "qup4";
 671				drive-strength = <2>;
 672				bias-pull-up;
 673			};
 674
 675			qup_i2c5_default: qup-i2c5-default-state {
 676				pins = "gpio14", "gpio15";
 677				function = "qup5";
 678				drive-strength = <2>;
 679				bias-pull-up;
 680			};
 681
 682			qup_spi0_default: qup-spi0-default-state {
 683				pins = "gpio0", "gpio1","gpio2", "gpio3";
 684				function = "qup0";
 685				drive-strength = <2>;
 686				bias-pull-up;
 687			};
 688
 689			qup_spi1_default: qup-spi1-default-state {
 690				pins = "gpio4", "gpio5", "gpio69", "gpio70";
 691				function = "qup1";
 692				drive-strength = <2>;
 693				bias-pull-up;
 694			};
 695
 696			qup_spi2_default: qup-spi2-default-state {
 697				pins = "gpio6", "gpio7", "gpio71", "gpio80";
 698				function = "qup2";
 699				drive-strength = <2>;
 700				bias-pull-up;
 701			};
 702
 703			qup_spi3_default: qup-spi3-default-state {
 704				pins = "gpio8", "gpio9", "gpio10", "gpio11";
 705				function = "qup3";
 706				drive-strength = <2>;
 707				bias-pull-up;
 708			};
 709
 710			qup_spi4_default: qup-spi4-default-state {
 711				pins = "gpio12", "gpio13", "gpio96", "gpio97";
 712				function = "qup4";
 713				drive-strength = <2>;
 714				bias-pull-up;
 715			};
 716
 717			qup_spi5_default: qup-spi5-default-state {
 718				pins = "gpio14", "gpio15", "gpio16", "gpio17";
 719				function = "qup5";
 720				drive-strength = <2>;
 721				bias-pull-up;
 722			};
 723
 724			qup_uart4_default: qup-uart4-default-state {
 725				pins = "gpio12", "gpio13";
 726				function = "qup4";
 727				drive-strength = <2>;
 728				bias-disable;
 729			};
 730
 731			sdc1_state_on: sdc1-on-state {
 732				clk-pins {
 733					pins = "sdc1_clk";
 734					bias-disable;
 735					drive-strength = <16>;
 736				};
 737
 738				cmd-pins {
 739					pins = "sdc1_cmd";
 740					bias-pull-up;
 741					drive-strength = <10>;
 742				};
 743
 744				data-pins {
 745					pins = "sdc1_data";
 746					bias-pull-up;
 747					drive-strength = <10>;
 748				};
 749
 750				rclk-pins {
 751					pins = "sdc1_rclk";
 752					bias-pull-down;
 753				};
 754			};
 755
 756			sdc1_state_off: sdc1-off-state {
 757				clk-pins {
 758					pins = "sdc1_clk";
 759					bias-disable;
 760					drive-strength = <2>;
 761				};
 762
 763				cmd-pins {
 764					pins = "sdc1_cmd";
 765					bias-pull-up;
 766					drive-strength = <2>;
 767				};
 768
 769				data-pins {
 770					pins = "sdc1_data";
 771					bias-pull-up;
 772					drive-strength = <2>;
 773				};
 774
 775				rclk-pins {
 776					pins = "sdc1_rclk";
 777					bias-pull-down;
 778				};
 779			};
 780
 781			sdc2_state_on: sdc2-on-state {
 782				clk-pins {
 783					pins = "sdc2_clk";
 784					bias-disable;
 785					drive-strength = <16>;
 786				};
 787
 788				cmd-pins {
 789					pins = "sdc2_cmd";
 790					bias-pull-up;
 791					drive-strength = <10>;
 792				};
 793
 794				data-pins {
 795					pins = "sdc2_data";
 796					bias-pull-up;
 797					drive-strength = <10>;
 798				};
 799			};
 800
 801			sdc2_state_off: sdc2-off-state {
 802				clk-pins {
 803					pins = "sdc2_clk";
 804					bias-disable;
 805					drive-strength = <2>;
 806				};
 807
 808				cmd-pins {
 809					pins = "sdc2_cmd";
 810					bias-pull-up;
 811					drive-strength = <2>;
 812				};
 813
 814				data-pins {
 815					pins = "sdc2_data";
 816					bias-pull-up;
 817					drive-strength = <2>;
 818				};
 819			};
 820		};
 821
 822		lpass_tlmm: pinctrl@a7c0000 {
 823			compatible = "qcom,sm6115-lpass-lpi-pinctrl";
 824			reg = <0x0 0x0a7c0000 0x0 0x20000>,
 825			      <0x0 0x0a950000 0x0 0x10000>;
 826
 827			clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
 828			clock-names = "audio";
 829
 830			gpio-controller;
 831			#gpio-cells = <2>;
 832			gpio-ranges = <&lpass_tlmm 0 0 19>;
 833
 834		};
 835
 836		gcc: clock-controller@1400000 {
 837			compatible = "qcom,gcc-sm6115";
 838			reg = <0x0 0x01400000 0x0 0x1f0000>;
 839			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
 840			clock-names = "bi_tcxo", "sleep_clk";
 841			#clock-cells = <1>;
 842			#reset-cells = <1>;
 843			#power-domain-cells = <1>;
 844		};
 845
 846		usb_hsphy: phy@1613000 {
 847			compatible = "qcom,sm6115-qusb2-phy";
 848			reg = <0x0 0x01613000 0x0 0x180>;
 849			#phy-cells = <0>;
 850
 851			clocks = <&gcc GCC_AHB2PHY_USB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
 852			clock-names = "cfg_ahb", "ref";
 853
 854			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
 855			nvmem-cells = <&qusb2_hstx_trim>;
 856
 857			status = "disabled";
 858		};
 859
 860		cryptobam: dma-controller@1b04000 {
 861			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
 862			reg = <0x0 0x01b04000 0x0 0x24000>;
 863			interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
 864			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
 865			clock-names = "bam_clk";
 866			#dma-cells = <1>;
 867			qcom,ee = <0>;
 868			qcom,controlled-remotely;
 869			iommus = <&apps_smmu 0x92 0>,
 870				 <&apps_smmu 0x94 0x11>,
 871				 <&apps_smmu 0x96 0x11>,
 872				 <&apps_smmu 0x98 0x1>,
 873				 <&apps_smmu 0x9F 0>;
 874		};
 875
 876		crypto: crypto@1b3a000 {
 877			compatible = "qcom,sm6115-qce", "qcom,ipq4019-qce", "qcom,qce";
 878			reg = <0x0 0x01b3a000 0x0 0x6000>;
 879			clocks = <&rpmcc RPM_SMD_CE1_CLK>;
 880			clock-names = "core";
 881
 882			dmas = <&cryptobam 6>, <&cryptobam 7>;
 883			dma-names = "rx", "tx";
 884			iommus = <&apps_smmu 0x92 0>,
 885				 <&apps_smmu 0x94 0x11>,
 886				 <&apps_smmu 0x96 0x11>,
 887				 <&apps_smmu 0x98 0x1>,
 888				 <&apps_smmu 0x9F 0>;
 889		};
 890
 891		usb_qmpphy: phy@1615000 {
 892			compatible = "qcom,sm6115-qmp-usb3-phy";
 893			reg = <0x0 0x01615000 0x0 0x1000>;
 894
 895			clocks = <&gcc GCC_AHB2PHY_USB_CLK>,
 896				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
 897				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
 898				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 899			clock-names = "cfg_ahb",
 900				      "ref",
 901				      "com_aux",
 902				      "pipe";
 903
 904			resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>,
 905				 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>;
 906			reset-names = "phy", "phy_phy";
 907
 908			#clock-cells = <0>;
 909			clock-output-names = "usb3_phy_pipe_clk_src";
 910
 911			#phy-cells = <0>;
 912			orientation-switch;
 913
 914			qcom,tcsr-reg = <&tcsr_regs 0xb244>;
 915
 916			status = "disabled";
 917
 918			ports {
 919				#address-cells = <1>;
 920				#size-cells = <0>;
 921
 922				port@0 {
 923					reg = <0>;
 924
 925					usb_qmpphy_out: endpoint {
 926					};
 927				};
 928
 929				port@1 {
 930					reg = <1>;
 931
 932					usb_qmpphy_usb_ss_in: endpoint {
 933						remote-endpoint = <&usb_dwc3_ss>;
 934					};
 935				};
 936			};
 937		};
 938
 939		system_noc: interconnect@1880000 {
 940			compatible = "qcom,sm6115-snoc";
 941			reg = <0x0 0x01880000 0x0 0x5f080>;
 942			clocks = <&gcc GCC_SYS_NOC_CPUSS_AHB_CLK>,
 943				 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
 944				 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
 945				 <&rpmcc RPM_SMD_IPA_CLK>;
 946			clock-names = "cpu_axi",
 947				      "ufs_axi",
 948				      "usb_axi",
 949				      "ipa";
 950			#interconnect-cells = <2>;
 951
 952			clk_virt: interconnect-clk {
 953				compatible = "qcom,sm6115-clk-virt";
 954				#interconnect-cells = <2>;
 955			};
 956
 957			mmrt_virt: interconnect-mmrt {
 958				compatible = "qcom,sm6115-mmrt-virt";
 959				#interconnect-cells = <2>;
 960			};
 961
 962			mmnrt_virt: interconnect-mmnrt {
 963				compatible = "qcom,sm6115-mmnrt-virt";
 964				#interconnect-cells = <2>;
 965			};
 966		};
 967
 968		config_noc: interconnect@1900000 {
 969			compatible = "qcom,sm6115-cnoc";
 970			reg = <0x0 0x01900000 0x0 0x6200>;
 971			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>;
 972			clock-names = "usb_axi";
 973			#interconnect-cells = <2>;
 974		};
 975
 976		qfprom@1b40000 {
 977			compatible = "qcom,sm6115-qfprom", "qcom,qfprom";
 978			reg = <0x0 0x01b40000 0x0 0x7000>;
 979			#address-cells = <1>;
 980			#size-cells = <1>;
 981
 982			qusb2_hstx_trim: hstx-trim@25b {
 983				reg = <0x25b 0x1>;
 984				bits = <1 4>;
 985			};
 986
 987			gpu_speed_bin: gpu-speed-bin@6006 {
 988				reg = <0x6006 0x2>;
 989				bits = <5 8>;
 990			};
 991		};
 992
 993		rng: rng@1b53000 {
 994			compatible = "qcom,prng-ee";
 995			reg = <0x0 0x01b53000 0x0 0x1000>;
 996			clocks = <&gcc GCC_PRNG_AHB_CLK>;
 997			clock-names = "core";
 998		};
 999
1000		pmu@1b8e300 {
1001			compatible = "qcom,sm6115-cpu-bwmon", "qcom,sdm845-bwmon";
1002			reg = <0x0 0x01b8e300 0x0 0x600>;
1003			interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>;
1004
1005			operating-points-v2 = <&cpu_bwmon_opp_table>;
1006			interconnects = <&bimc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
1007					 &bimc SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
1008
1009			cpu_bwmon_opp_table: opp-table {
1010				compatible = "operating-points-v2";
1011
1012				opp-0 {
1013					opp-peak-kBps = <(200 * 4 * 1000)>;
1014				};
1015
1016				opp-1 {
1017					opp-peak-kBps = <(300 * 4 * 1000)>;
1018				};
1019
1020				opp-2 {
1021					opp-peak-kBps = <(451 * 4 * 1000)>;
1022				};
1023
1024				opp-3 {
1025					opp-peak-kBps = <(547 * 4 * 1000)>;
1026				};
1027
1028				opp-4 {
1029					opp-peak-kBps = <(681 * 4 * 1000)>;
1030				};
1031
1032				opp-5 {
1033					opp-peak-kBps = <(768 * 4 * 1000)>;
1034				};
1035
1036				opp-6 {
1037					opp-peak-kBps = <(1017 * 4 * 1000)>;
1038				};
1039
1040				opp-7 {
1041					opp-peak-kBps = <(1353 * 4 * 1000)>;
1042				};
1043
1044				opp-8 {
1045					opp-peak-kBps = <(1555 * 4 * 1000)>;
1046				};
1047
1048				opp-9 {
1049					opp-peak-kBps = <(1804 * 4 * 1000)>;
1050				};
1051			};
1052		};
1053
1054		spmi_bus: spmi@1c40000 {
1055			compatible = "qcom,spmi-pmic-arb";
1056			reg = <0x0 0x01c40000 0x0 0x1100>,
1057			      <0x0 0x01e00000 0x0 0x2000000>,
1058			      <0x0 0x03e00000 0x0 0x100000>,
1059			      <0x0 0x03f00000 0x0 0xa0000>,
1060			      <0x0 0x01c0a000 0x0 0x26000>;
1061			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1062			interrupt-names = "periph_irq";
1063			interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
1064			qcom,ee = <0>;
1065			qcom,channel = <0>;
1066			#address-cells = <2>;
1067			#size-cells = <0>;
1068			interrupt-controller;
1069			#interrupt-cells = <4>;
1070		};
1071
1072		tsens0: thermal-sensor@4411000 {
1073			compatible = "qcom,sm6115-tsens", "qcom,tsens-v2";
1074			reg = <0x0 0x04411000 0x0 0x1ff>, /* TM */
1075			      <0x0 0x04410000 0x0 0x8>; /* SROT */
1076			#qcom,sensors = <16>;
1077			interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
1078				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
1079			interrupt-names = "uplow", "critical";
1080			#thermal-sensor-cells = <1>;
1081		};
1082
1083		bimc: interconnect@4480000 {
1084			compatible = "qcom,sm6115-bimc";
1085			reg = <0x0 0x04480000 0x0 0x80000>;
1086			#interconnect-cells = <2>;
1087		};
1088
1089		rpm_msg_ram: sram@45f0000 {
1090			compatible = "qcom,rpm-msg-ram";
1091			reg = <0x0 0x045f0000 0x0 0x7000>;
1092		};
1093
1094		sram@4690000 {
1095			compatible = "qcom,rpm-stats";
1096			reg = <0x0 0x04690000 0x0 0x10000>;
1097		};
1098
1099		sdhc_1: mmc@4744000 {
1100			compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1101			reg = <0x0 0x04744000 0x0 0x1000>,
1102			      <0x0 0x04745000 0x0 0x1000>,
1103			      <0x0 0x04748000 0x0 0x8000>;
1104			reg-names = "hc", "cqhci", "ice";
1105
1106			interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
1107				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
1108			interrupt-names = "hc_irq", "pwr_irq";
1109
1110			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
1111				 <&gcc GCC_SDCC1_APPS_CLK>,
1112				 <&rpmcc RPM_SMD_XO_CLK_SRC>,
1113				 <&gcc GCC_SDCC1_ICE_CORE_CLK>;
1114			clock-names = "iface", "core", "xo", "ice";
1115
1116			resets = <&gcc GCC_SDCC1_BCR>;
1117
1118			power-domains = <&rpmpd SM6115_VDDCX>;
1119			operating-points-v2 = <&sdhc1_opp_table>;
1120			iommus = <&apps_smmu 0x00c0 0x0>;
1121			interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG
1122					 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1123					<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1124					 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>;
1125			interconnect-names = "sdhc-ddr",
1126					     "cpu-sdhc";
1127
1128			bus-width = <8>;
1129			status = "disabled";
1130
1131			sdhc1_opp_table: opp-table {
1132				compatible = "operating-points-v2";
1133
1134				opp-100000000 {
1135					opp-hz = /bits/ 64 <100000000>;
1136					required-opps = <&rpmpd_opp_low_svs>;
1137					opp-peak-kBps = <250000 133320>;
1138					opp-avg-kBps = <102400 65000>;
1139				};
1140
1141				opp-192000000 {
1142					opp-hz = /bits/ 64 <192000000>;
1143					required-opps = <&rpmpd_opp_low_svs>;
1144					opp-peak-kBps = <800000 300000>;
1145					opp-avg-kBps = <204800 200000>;
1146				};
1147
1148				opp-384000000 {
1149					opp-hz = /bits/ 64 <384000000>;
1150					required-opps = <&rpmpd_opp_svs_plus>;
1151					opp-peak-kBps = <800000 300000>;
1152					opp-avg-kBps = <204800 200000>;
1153				};
1154			};
1155		};
1156
1157		sdhc_2: mmc@4784000 {
1158			compatible = "qcom,sm6115-sdhci", "qcom,sdhci-msm-v5";
1159			reg = <0x0 0x04784000 0x0 0x1000>;
1160			reg-names = "hc";
1161
1162			interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
1163				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1164			interrupt-names = "hc_irq", "pwr_irq";
1165
1166			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
1167				 <&gcc GCC_SDCC2_APPS_CLK>,
1168				 <&rpmcc RPM_SMD_XO_CLK_SRC>;
1169			clock-names = "iface", "core", "xo";
1170
1171			power-domains = <&rpmpd SM6115_VDDCX>;
1172			operating-points-v2 = <&sdhc2_opp_table>;
1173			iommus = <&apps_smmu 0x00a0 0x0>;
1174			resets = <&gcc GCC_SDCC2_BCR>;
1175			interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG
1176					 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1177					<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1178					 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>;
1179			interconnect-names = "sdhc-ddr",
1180					     "cpu-sdhc";
1181
1182			bus-width = <4>;
1183			qcom,dll-config = <0x0007642c>;
1184			qcom,ddr-config = <0x80040868>;
1185			status = "disabled";
1186
1187			sdhc2_opp_table: opp-table {
1188				compatible = "operating-points-v2";
1189
1190				opp-100000000 {
1191					opp-hz = /bits/ 64 <100000000>;
1192					required-opps = <&rpmpd_opp_low_svs>;
1193					opp-peak-kBps = <250000 133320>;
1194					opp-avg-kBps = <261438 150000>;
1195				};
1196
1197				opp-202000000 {
1198					opp-hz = /bits/ 64 <202000000>;
1199					required-opps = <&rpmpd_opp_nom>;
1200					opp-peak-kBps = <800000 300000>;
1201					opp-avg-kBps = <261438 300000>;
1202				};
1203			};
1204		};
1205
1206		ufs_mem_hc: ufshc@4804000 {
1207			compatible = "qcom,sm6115-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1208			reg = <0x0 0x04804000 0x0 0x3000>, <0x0 0x04810000 0x0 0x8000>;
1209			reg-names = "std", "ice";
1210			interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1211			phys = <&ufs_mem_phy>;
1212			phy-names = "ufsphy";
1213			lanes-per-direction = <1>;
1214			#reset-cells = <1>;
1215			resets = <&gcc GCC_UFS_PHY_BCR>;
1216			reset-names = "rst";
1217
1218			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1219			iommus = <&apps_smmu 0x100 0>;
1220
1221			clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1222				 <&gcc GCC_SYS_NOC_UFS_PHY_AXI_CLK>,
1223				 <&gcc GCC_UFS_PHY_AHB_CLK>,
1224				 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1225				 <&rpmcc RPM_SMD_XO_CLK_SRC>,
1226				 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1227				 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1228				 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
1229			clock-names = "core_clk",
1230				      "bus_aggr_clk",
1231				      "iface_clk",
1232				      "core_clk_unipro",
1233				      "ref_clk",
1234				      "tx_lane0_sync_clk",
1235				      "rx_lane0_sync_clk",
1236				      "ice_core_clk";
1237
1238			freq-table-hz = <50000000 200000000>,
1239					<0 0>,
1240					<0 0>,
1241					<37500000 150000000>,
1242					<0 0>,
1243					<0 0>,
1244					<0 0>,
1245					<75000000 300000000>;
1246
1247			status = "disabled";
1248		};
1249
1250		ufs_mem_phy: phy@4807000 {
1251			compatible = "qcom,sm6115-qmp-ufs-phy";
1252			reg = <0x0 0x04807000 0x0 0x1000>;
1253
1254			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1255				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1256				 <&gcc GCC_UFS_CLKREF_CLK>;
1257			clock-names = "ref",
1258				      "ref_aux",
1259				      "qref";
1260
1261			power-domains = <&gcc GCC_UFS_PHY_GDSC>;
1262
1263			resets = <&ufs_mem_hc 0>;
1264			reset-names = "ufsphy";
1265
1266			#phy-cells = <0>;
1267
1268			status = "disabled";
1269		};
1270
1271		gpi_dma0: dma-controller@4a00000 {
1272			compatible = "qcom,sm6115-gpi-dma", "qcom,sm6350-gpi-dma";
1273			reg = <0x0 0x04a00000 0x0 0x60000>;
1274			interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
1275				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
1276				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
1277				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
1278				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
1279				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
1280				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
1281				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
1282				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
1283				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
1284			dma-channels = <10>;
1285			dma-channel-mask = <0xf>;
1286			iommus = <&apps_smmu 0xf6 0x0>;
1287			#dma-cells = <3>;
1288			status = "disabled";
1289		};
1290
1291		qupv3_id_0: geniqup@4ac0000 {
1292			compatible = "qcom,geni-se-qup";
1293			reg = <0x0 0x04ac0000 0x0 0x2000>;
1294			clock-names = "m-ahb", "s-ahb";
1295			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
1296				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
1297			#address-cells = <2>;
1298			#size-cells = <2>;
1299			iommus = <&apps_smmu 0xe3 0x0>;
1300			ranges;
1301			status = "disabled";
1302
1303			i2c0: i2c@4a80000 {
1304				compatible = "qcom,geni-i2c";
1305				reg = <0x0 0x04a80000 0x0 0x4000>;
1306				clock-names = "se";
1307				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1308				pinctrl-names = "default";
1309				pinctrl-0 = <&qup_i2c0_default>;
1310				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1311				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
1312				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
1313				dma-names = "tx", "rx";
1314				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1315						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1316						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1317						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1318						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1319						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1320				interconnect-names = "qup-core",
1321						     "qup-config",
1322						     "qup-memory";
1323				#address-cells = <1>;
1324				#size-cells = <0>;
1325				status = "disabled";
1326			};
1327
1328			spi0: spi@4a80000 {
1329				compatible = "qcom,geni-spi";
1330				reg = <0x0 0x04a80000 0x0 0x4000>;
1331				clock-names = "se";
1332				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
1333				pinctrl-names = "default";
1334				pinctrl-0 = <&qup_spi0_default>;
1335				interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
1336				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
1337				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
1338				dma-names = "tx", "rx";
1339				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1340						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1341						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1342						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1343						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1344						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1345				interconnect-names = "qup-core",
1346						     "qup-config",
1347						     "qup-memory";
1348				#address-cells = <1>;
1349				#size-cells = <0>;
1350				status = "disabled";
1351			};
1352
1353			i2c1: i2c@4a84000 {
1354				compatible = "qcom,geni-i2c";
1355				reg = <0x0 0x04a84000 0x0 0x4000>;
1356				clock-names = "se";
1357				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1358				pinctrl-names = "default";
1359				pinctrl-0 = <&qup_i2c1_default>;
1360				interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1361				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
1362				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
1363				dma-names = "tx", "rx";
1364				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1365						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1366						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1367						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1368						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1369						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1370				interconnect-names = "qup-core",
1371						     "qup-config",
1372						     "qup-memory";
1373				#address-cells = <1>;
1374				#size-cells = <0>;
1375				status = "disabled";
1376			};
1377
1378			spi1: spi@4a84000 {
1379				compatible = "qcom,geni-spi";
1380				reg = <0x0 0x04a84000 0x0 0x4000>;
1381				clock-names = "se";
1382				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
1383				pinctrl-names = "default";
1384				pinctrl-0 = <&qup_spi1_default>;
1385				interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>;
1386				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
1387				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
1388				dma-names = "tx", "rx";
1389				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1390						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1391						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1392						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1393						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1394						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1395				interconnect-names = "qup-core",
1396						     "qup-config",
1397						     "qup-memory";
1398				#address-cells = <1>;
1399				#size-cells = <0>;
1400				status = "disabled";
1401			};
1402
1403			i2c2: i2c@4a88000 {
1404				compatible = "qcom,geni-i2c";
1405				reg = <0x0 0x04a88000 0x0 0x4000>;
1406				clock-names = "se";
1407				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1408				pinctrl-names = "default";
1409				pinctrl-0 = <&qup_i2c2_default>;
1410				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1411				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
1412				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
1413				dma-names = "tx", "rx";
1414				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1415						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1416						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1417						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1418						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1419						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1420				interconnect-names = "qup-core",
1421						     "qup-config",
1422						     "qup-memory";
1423				#address-cells = <1>;
1424				#size-cells = <0>;
1425				status = "disabled";
1426			};
1427
1428			spi2: spi@4a88000 {
1429				compatible = "qcom,geni-spi";
1430				reg = <0x0 0x04a88000 0x0 0x4000>;
1431				clock-names = "se";
1432				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
1433				pinctrl-names = "default";
1434				pinctrl-0 = <&qup_spi2_default>;
1435				interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>;
1436				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
1437				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
1438				dma-names = "tx", "rx";
1439				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1440						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1441						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1442						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1443						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1444						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1445				interconnect-names = "qup-core",
1446						     "qup-config",
1447						     "qup-memory";
1448				#address-cells = <1>;
1449				#size-cells = <0>;
1450				status = "disabled";
1451			};
1452
1453			i2c3: i2c@4a8c000 {
1454				compatible = "qcom,geni-i2c";
1455				reg = <0x0 0x04a8c000 0x0 0x4000>;
1456				clock-names = "se";
1457				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1458				pinctrl-names = "default";
1459				pinctrl-0 = <&qup_i2c3_default>;
1460				interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1461				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
1462				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
1463				dma-names = "tx", "rx";
1464				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1465						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1466						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1467						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1468						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1469						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1470				interconnect-names = "qup-core",
1471						     "qup-config",
1472						     "qup-memory";
1473				#address-cells = <1>;
1474				#size-cells = <0>;
1475				status = "disabled";
1476			};
1477
1478			spi3: spi@4a8c000 {
1479				compatible = "qcom,geni-spi";
1480				reg = <0x0 0x04a8c000 0x0 0x4000>;
1481				clock-names = "se";
1482				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1483				pinctrl-names = "default";
1484				pinctrl-0 = <&qup_spi3_default>;
1485				interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1486				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
1487				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
1488				dma-names = "tx", "rx";
1489				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1490						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1491						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1492						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1493						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1494						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1495				interconnect-names = "qup-core",
1496						     "qup-config",
1497						     "qup-memory";
1498				#address-cells = <1>;
1499				#size-cells = <0>;
1500				status = "disabled";
1501			};
1502
1503			uart3: serial@4a8c000 {
1504				compatible = "qcom,geni-uart";
1505				reg = <0x0 0x04a8c000 0x0 0x4000>;
1506				interrupts-extended = <&intc GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>;
1507				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1508				clock-names = "se";
1509				power-domains = <&rpmpd SM6115_VDDCX>;
1510				operating-points-v2 = <&qup_opp_table>;
1511				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1512						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1513						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1514						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
1515				interconnect-names = "qup-core",
1516						     "qup-config";
1517				status = "disabled";
1518			};
1519
1520			i2c4: i2c@4a90000 {
1521				compatible = "qcom,geni-i2c";
1522				reg = <0x0 0x04a90000 0x0 0x4000>;
1523				clock-names = "se";
1524				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1525				pinctrl-names = "default";
1526				pinctrl-0 = <&qup_i2c4_default>;
1527				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1528				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
1529				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
1530				dma-names = "tx", "rx";
1531				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1532						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1533						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1534						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1535						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1536						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1537				interconnect-names = "qup-core",
1538						     "qup-config",
1539						     "qup-memory";
1540				#address-cells = <1>;
1541				#size-cells = <0>;
1542				status = "disabled";
1543			};
1544
1545			spi4: spi@4a90000 {
1546				compatible = "qcom,geni-spi";
1547				reg = <0x0 0x04a90000 0x0 0x4000>;
1548				clock-names = "se";
1549				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1550				pinctrl-names = "default";
1551				pinctrl-0 = <&qup_spi4_default>;
1552				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1553				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
1554				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
1555				dma-names = "tx", "rx";
1556				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1557						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1558						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1559						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1560						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1561						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1562				interconnect-names = "qup-core",
1563						     "qup-config",
1564						     "qup-memory";
1565				#address-cells = <1>;
1566				#size-cells = <0>;
1567				status = "disabled";
1568			};
1569
1570			uart4: serial@4a90000 {
1571				compatible = "qcom,geni-debug-uart";
1572				reg = <0x0 0x04a90000 0x0 0x4000>;
1573				clock-names = "se";
1574				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1575				pinctrl-names = "default";
1576				pinctrl-0 = <&qup_uart4_default>;
1577				interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>;
1578				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1579						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1580						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1581						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
1582				interconnect-names = "qup-core",
1583						     "qup-config";
1584				status = "disabled";
1585			};
1586
1587			i2c5: i2c@4a94000 {
1588				compatible = "qcom,geni-i2c";
1589				reg = <0x0 0x04a94000 0x0 0x4000>;
1590				clock-names = "se";
1591				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1592				pinctrl-names = "default";
1593				pinctrl-0 = <&qup_i2c5_default>;
1594				interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1595				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
1596				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
1597				dma-names = "tx", "rx";
1598				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1599						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1600						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1601						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1602						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1603						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1604				interconnect-names = "qup-core",
1605						     "qup-config",
1606						     "qup-memory";
1607				#address-cells = <1>;
1608				#size-cells = <0>;
1609				status = "disabled";
1610			};
1611
1612			spi5: spi@4a94000 {
1613				compatible = "qcom,geni-spi";
1614				reg = <0x0 0x04a94000 0x0 0x4000>;
1615				clock-names = "se";
1616				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1617				pinctrl-names = "default";
1618				pinctrl-0 = <&qup_spi5_default>;
1619				interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
1620				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
1621				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
1622				dma-names = "tx", "rx";
1623				interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
1624						 &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
1625						<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1626						 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
1627						<&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
1628						 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
1629				interconnect-names = "qup-core",
1630						     "qup-config",
1631						     "qup-memory";
1632				#address-cells = <1>;
1633				#size-cells = <0>;
1634				status = "disabled";
1635			};
1636		};
1637
1638		usb: usb@4ef8800 {
1639			compatible = "qcom,sm6115-dwc3", "qcom,dwc3";
1640			reg = <0x0 0x04ef8800 0x0 0x400>;
1641			#address-cells = <2>;
1642			#size-cells = <2>;
1643			ranges;
1644
1645			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1646				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1647				 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>,
1648				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1649				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1650				 <&gcc GCC_USB3_PRIM_CLKREF_CLK>;
1651			clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", "xo";
1652
1653			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1654					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1655			assigned-clock-rates = <19200000>, <66666667>;
1656
1657			interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1658				     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>,
1659				     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
1660				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>;
1661			interrupt-names = "pwr_event",
1662					  "qusb2_phy",
1663					  "hs_phy_irq",
1664					  "ss_phy_irq";
1665
1666			resets = <&gcc GCC_USB30_PRIM_BCR>;
1667			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
1668			 /* TODO: USB<->IPA path */
1669			interconnects = <&system_noc MASTER_USB3 RPM_ALWAYS_TAG
1670					 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1671					<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1672					 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>;
1673			interconnect-names = "usb-ddr",
1674					     "apps-usb";
1675
1676			status = "disabled";
1677
1678			usb_dwc3: usb@4e00000 {
1679				compatible = "snps,dwc3";
1680				reg = <0x0 0x04e00000 0x0 0xcd00>;
1681				interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
1682				phys = <&usb_hsphy>, <&usb_qmpphy>;
1683				phy-names = "usb2-phy", "usb3-phy";
1684				iommus = <&apps_smmu 0x120 0x0>;
1685				snps,dis_u2_susphy_quirk;
1686				snps,dis_enblslpm_quirk;
1687				snps,has-lpm-erratum;
1688				snps,hird-threshold = /bits/ 8 <0x10>;
1689				snps,usb3_lpm_capable;
1690				snps,parkmode-disable-ss-quirk;
1691
1692				usb-role-switch;
1693
1694				ports {
1695					#address-cells = <1>;
1696					#size-cells = <0>;
1697
1698					port@0 {
1699						reg = <0>;
1700
1701						usb_dwc3_hs: endpoint {
1702						};
1703					};
1704
1705					port@1 {
1706						reg = <1>;
1707
1708						usb_dwc3_ss: endpoint {
1709							remote-endpoint = <&usb_qmpphy_usb_ss_in>;
1710						};
1711					};
1712				};
1713			};
1714		};
1715
1716		gpu: gpu@5900000 {
1717			compatible = "qcom,adreno-610.0", "qcom,adreno";
1718			reg = <0x0 0x05900000 0x0 0x40000>,
1719			      <0x0 0x0599e000 0x0 0x1000>,
1720			      <0x0 0x05961000 0x0 0x800>;
1721			reg-names = "kgsl_3d0_reg_memory",
1722				    "cx_mem",
1723				    "cx_dbgc";
1724
1725			/* There's no (real) GMU, so we have to handle quite a bunch of clocks! */
1726			clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>,
1727				 <&gpucc GPU_CC_AHB_CLK>,
1728				 <&gcc GCC_BIMC_GPU_AXI_CLK>,
1729				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1730				 <&gpucc GPU_CC_CX_GMU_CLK>,
1731				 <&gpucc GPU_CC_CXO_CLK>;
1732			clock-names = "core",
1733				      "iface",
1734				      "mem_iface",
1735				      "alt_mem_iface",
1736				      "gmu",
1737				      "xo";
1738
1739			interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
1740
1741			iommus = <&adreno_smmu 0 1>;
1742			operating-points-v2 = <&gpu_opp_table>;
1743			power-domains = <&rpmpd SM6115_VDDCX>;
1744			qcom,gmu = <&gmu_wrapper>;
1745
1746			nvmem-cells = <&gpu_speed_bin>;
1747			nvmem-cell-names = "speed_bin";
1748			#cooling-cells = <2>;
1749
1750			status = "disabled";
1751
1752			gpu_zap_shader: zap-shader {
1753				memory-region = <&pil_gpu_mem>;
1754			};
1755
1756			gpu_opp_table: opp-table {
1757				compatible = "operating-points-v2";
1758
1759				opp-320000000 {
1760					opp-hz = /bits/ 64 <320000000>;
1761					required-opps = <&rpmpd_opp_low_svs>;
1762					opp-supported-hw = <0x1f>;
1763				};
1764
1765				opp-465000000 {
1766					opp-hz = /bits/ 64 <465000000>;
1767					required-opps = <&rpmpd_opp_svs>;
1768					opp-supported-hw = <0x1f>;
1769				};
1770
1771				opp-600000000 {
1772					opp-hz = /bits/ 64 <600000000>;
1773					required-opps = <&rpmpd_opp_svs_plus>;
1774					opp-supported-hw = <0x1f>;
1775				};
1776
1777				opp-745000000 {
1778					opp-hz = /bits/ 64 <745000000>;
1779					required-opps = <&rpmpd_opp_nom>;
1780					opp-supported-hw = <0xf>;
1781				};
1782
1783				opp-820000000 {
1784					opp-hz = /bits/ 64 <820000000>;
1785					required-opps = <&rpmpd_opp_nom_plus>;
1786					opp-supported-hw = <0x7>;
1787				};
1788
1789				opp-900000000 {
1790					opp-hz = /bits/ 64 <900000000>;
1791					required-opps = <&rpmpd_opp_turbo>;
1792					opp-supported-hw = <0x7>;
1793				};
1794
1795				/* Speed bin 2 can reach 950 Mhz instead of 980 like the rest. */
1796				opp-950000000 {
1797					opp-hz = /bits/ 64 <950000000>;
1798					required-opps = <&rpmpd_opp_turbo_plus>;
1799					opp-supported-hw = <0x4>;
1800				};
1801
1802				opp-980000000 {
1803					opp-hz = /bits/ 64 <980000000>;
1804					required-opps = <&rpmpd_opp_turbo_plus>;
1805					opp-supported-hw = <0x3>;
1806				};
1807			};
1808		};
1809
1810		gmu_wrapper: gmu@596a000 {
1811			compatible = "qcom,adreno-gmu-wrapper";
1812			reg = <0x0 0x0596a000 0x0 0x30000>;
1813			reg-names = "gmu";
1814			power-domains = <&gpucc GPU_CX_GDSC>,
1815					<&gpucc GPU_GX_GDSC>;
1816			power-domain-names = "cx", "gx";
1817		};
1818
1819		gpucc: clock-controller@5990000 {
1820			compatible = "qcom,sm6115-gpucc";
1821			reg = <0x0 0x05990000 0x0 0x9000>;
1822			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
1823				 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1824				 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1825			#clock-cells = <1>;
1826			#reset-cells = <1>;
1827			#power-domain-cells = <1>;
1828		};
1829
1830		adreno_smmu: iommu@59a0000 {
1831			compatible = "qcom,sm6115-smmu-500", "qcom,adreno-smmu",
1832				     "qcom,smmu-500", "arm,mmu-500";
1833			reg = <0x0 0x059a0000 0x0 0x10000>;
1834			interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
1835				     <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
1836				     <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1837				     <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
1838				     <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
1839				     <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
1840				     <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
1841				     <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
1842				     <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
1843
1844			clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1845				 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
1846				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
1847			clock-names = "mem",
1848				      "hlos",
1849				      "iface";
1850			power-domains = <&gpucc GPU_CX_GDSC>;
1851
1852			#global-interrupts = <1>;
1853			#iommu-cells = <2>;
1854		};
1855
1856		mdss: display-subsystem@5e00000 {
1857			compatible = "qcom,sm6115-mdss";
1858			reg = <0x0 0x05e00000 0x0 0x1000>;
1859			reg-names = "mdss";
1860
1861			power-domains = <&dispcc MDSS_GDSC>;
1862
1863			clocks = <&gcc GCC_DISP_AHB_CLK>,
1864				 <&gcc GCC_DISP_HF_AXI_CLK>,
1865				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
1866
1867			interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
1868			interrupt-controller;
1869			#interrupt-cells = <1>;
1870
1871			iommus = <&apps_smmu 0x420 0x2>,
1872				 <&apps_smmu 0x421 0x0>;
1873
1874			interconnects = <&mmrt_virt MASTER_MDP_PORT0 RPM_ALWAYS_TAG
1875					 &bimc SLAVE_EBI_CH0 RPM_ALWAYS_TAG>,
1876					<&bimc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
1877					 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>;
1878			interconnect-names = "mdp0-mem",
1879					     "cpu-cfg";
1880
1881			#address-cells = <2>;
1882			#size-cells = <2>;
1883			ranges;
1884
1885			status = "disabled";
1886
1887			mdp: display-controller@5e01000 {
1888				compatible = "qcom,sm6115-dpu";
1889				reg = <0x0 0x05e01000 0x0 0x8f000>,
1890				      <0x0 0x05eb0000 0x0 0x3000>;
1891				reg-names = "mdp", "vbif";
1892
1893				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
1894					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1895					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
1896					 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
1897					 <&dispcc DISP_CC_MDSS_ROT_CLK>,
1898					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
1899				clock-names = "bus",
1900					      "iface",
1901					      "core",
1902					      "lut",
1903					      "rot",
1904					      "vsync";
1905
1906				operating-points-v2 = <&mdp_opp_table>;
1907				power-domains = <&rpmpd SM6115_VDDCX>;
1908
1909				interrupt-parent = <&mdss>;
1910				interrupts = <0>;
1911
1912				ports {
1913					#address-cells = <1>;
1914					#size-cells = <0>;
1915
1916					port@0 {
1917						reg = <0>;
1918						dpu_intf1_out: endpoint {
1919							remote-endpoint = <&mdss_dsi0_in>;
1920						};
1921					};
1922				};
1923
1924				mdp_opp_table: opp-table {
1925					compatible = "operating-points-v2";
1926
1927					opp-19200000 {
1928						opp-hz = /bits/ 64 <19200000>;
1929						required-opps = <&rpmpd_opp_min_svs>;
1930					};
1931
1932					opp-192000000 {
1933						opp-hz = /bits/ 64 <192000000>;
1934						required-opps = <&rpmpd_opp_low_svs>;
1935					};
1936
1937					opp-256000000 {
1938						opp-hz = /bits/ 64 <256000000>;
1939						required-opps = <&rpmpd_opp_svs>;
1940					};
1941
1942					opp-307200000 {
1943						opp-hz = /bits/ 64 <307200000>;
1944						required-opps = <&rpmpd_opp_svs_plus>;
1945					};
1946
1947					opp-384000000 {
1948						opp-hz = /bits/ 64 <384000000>;
1949						required-opps = <&rpmpd_opp_nom>;
1950					};
1951				};
1952			};
1953
1954			mdss_dsi0: dsi@5e94000 {
1955				compatible = "qcom,sm6115-dsi-ctrl", "qcom,mdss-dsi-ctrl";
1956				reg = <0x0 0x05e94000 0x0 0x400>;
1957				reg-names = "dsi_ctrl";
1958
1959				interrupt-parent = <&mdss>;
1960				interrupts = <4>;
1961
1962				clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
1963					 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
1964					 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
1965					 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
1966					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
1967					 <&gcc GCC_DISP_HF_AXI_CLK>;
1968				clock-names = "byte",
1969					      "byte_intf",
1970					      "pixel",
1971					      "core",
1972					      "iface",
1973					      "bus";
1974
1975				assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
1976						  <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
1977				assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
1978							 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>;
1979
1980				operating-points-v2 = <&dsi_opp_table>;
1981				power-domains = <&rpmpd SM6115_VDDCX>;
1982				phys = <&mdss_dsi0_phy>;
1983
1984				#address-cells = <1>;
1985				#size-cells = <0>;
1986
1987				status = "disabled";
1988
1989				ports {
1990					#address-cells = <1>;
1991					#size-cells = <0>;
1992
1993					port@0 {
1994						reg = <0>;
1995						mdss_dsi0_in: endpoint {
1996							remote-endpoint = <&dpu_intf1_out>;
1997						};
1998					};
1999
2000					port@1 {
2001						reg = <1>;
2002						mdss_dsi0_out: endpoint {
2003						};
2004					};
2005				};
2006
2007				dsi_opp_table: opp-table {
2008					compatible = "operating-points-v2";
2009
2010					opp-19200000 {
2011						opp-hz = /bits/ 64 <19200000>;
2012						required-opps = <&rpmpd_opp_min_svs>;
2013					};
2014
2015					opp-164000000 {
2016						opp-hz = /bits/ 64 <164000000>;
2017						required-opps = <&rpmpd_opp_low_svs>;
2018					};
2019
2020					opp-187500000 {
2021						opp-hz = /bits/ 64 <187500000>;
2022						required-opps = <&rpmpd_opp_svs>;
2023					};
2024				};
2025			};
2026
2027			mdss_dsi0_phy: phy@5e94400 {
2028				compatible = "qcom,dsi-phy-14nm-2290";
2029				reg = <0x0 0x05e94400 0x0 0x100>,
2030				      <0x0 0x05e94500 0x0 0x300>,
2031				      <0x0 0x05e94800 0x0 0x188>;
2032				reg-names = "dsi_phy",
2033					    "dsi_phy_lane",
2034					    "dsi_pll";
2035
2036				#clock-cells = <1>;
2037				#phy-cells = <0>;
2038
2039				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
2040					 <&rpmcc RPM_SMD_XO_CLK_SRC>;
2041				clock-names = "iface", "ref";
2042
2043				status = "disabled";
2044			};
2045		};
2046
2047		dispcc: clock-controller@5f00000 {
2048			compatible = "qcom,sm6115-dispcc";
2049			reg = <0x0 0x05f00000 0 0x20000>;
2050			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
2051				 <&sleep_clk>,
2052				 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
2053				 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
2054				 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
2055			#clock-cells = <1>;
2056			#reset-cells = <1>;
2057			#power-domain-cells = <1>;
2058		};
2059
2060		remoteproc_mpss: remoteproc@6080000 {
2061			compatible = "qcom,sm6115-mpss-pas";
2062			reg = <0x0 0x06080000 0x0 0x10000>;
2063
2064			interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>,
2065					      <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2066					      <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2067					      <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2068					      <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2069					      <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2070			interrupt-names = "wdog", "fatal", "ready", "handover",
2071					  "stop-ack", "shutdown-ack";
2072
2073			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2074			clock-names = "xo";
2075
2076			power-domains = <&rpmpd SM6115_VDDCX>;
2077
2078			memory-region = <&pil_modem_mem>;
2079
2080			qcom,smem-states = <&modem_smp2p_out 0>;
2081			qcom,smem-state-names = "stop";
2082
2083			status = "disabled";
2084
2085			glink-edge {
2086				interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>;
2087				label = "mpss";
2088				qcom,remote-pid = <1>;
2089				mboxes = <&apcs_glb 12>;
2090			};
2091		};
2092
2093		stm@8002000 {
2094			compatible = "arm,coresight-stm", "arm,primecell";
2095			reg = <0x0 0x08002000 0x0 0x1000>,
2096			      <0x0 0x0e280000 0x0 0x180000>;
2097			reg-names = "stm-base", "stm-stimulus-base";
2098
2099			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2100			clock-names = "apb_pclk";
2101
2102			status = "disabled";
2103
2104			out-ports {
2105				port {
2106					stm_out: endpoint {
2107						remote-endpoint = <&funnel_in0_in>;
2108					};
2109				};
2110			};
2111		};
2112
2113		cti0: cti@8010000 {
2114			compatible = "arm,coresight-cti", "arm,primecell";
2115			reg = <0x0 0x08010000 0x0 0x1000>;
2116
2117			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2118			clock-names = "apb_pclk";
2119
2120			status = "disabled";
2121		};
2122
2123		cti1: cti@8011000 {
2124			compatible = "arm,coresight-cti", "arm,primecell";
2125			reg = <0x0 0x08011000 0x0 0x1000>;
2126
2127			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2128			clock-names = "apb_pclk";
2129
2130			status = "disabled";
2131		};
2132
2133		cti2: cti@8012000 {
2134			compatible = "arm,coresight-cti", "arm,primecell";
2135			reg = <0x0 0x08012000 0x0 0x1000>;
2136
2137			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2138			clock-names = "apb_pclk";
2139
2140			status = "disabled";
2141		};
2142
2143		cti3: cti@8013000 {
2144			compatible = "arm,coresight-cti", "arm,primecell";
2145			reg = <0x0 0x08013000 0x0 0x1000>;
2146
2147			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2148			clock-names = "apb_pclk";
2149
2150			status = "disabled";
2151		};
2152
2153		cti4: cti@8014000 {
2154			compatible = "arm,coresight-cti", "arm,primecell";
2155			reg = <0x0 0x08014000 0x0 0x1000>;
2156
2157			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2158			clock-names = "apb_pclk";
2159
2160			status = "disabled";
2161		};
2162
2163		cti5: cti@8015000 {
2164			compatible = "arm,coresight-cti", "arm,primecell";
2165			reg = <0x0 0x08015000 0x0 0x1000>;
2166
2167			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2168			clock-names = "apb_pclk";
2169
2170			status = "disabled";
2171		};
2172
2173		cti6: cti@8016000 {
2174			compatible = "arm,coresight-cti", "arm,primecell";
2175			reg = <0x0 0x08016000 0x0 0x1000>;
2176
2177			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2178			clock-names = "apb_pclk";
2179
2180			status = "disabled";
2181		};
2182
2183		cti7: cti@8017000 {
2184			compatible = "arm,coresight-cti", "arm,primecell";
2185			reg = <0x0 0x08017000 0x0 0x1000>;
2186
2187			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2188			clock-names = "apb_pclk";
2189
2190			status = "disabled";
2191		};
2192
2193		cti8: cti@8018000 {
2194			compatible = "arm,coresight-cti", "arm,primecell";
2195			reg = <0x0 0x08018000 0x0 0x1000>;
2196
2197			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2198			clock-names = "apb_pclk";
2199
2200			status = "disabled";
2201		};
2202
2203		cti9: cti@8019000 {
2204			compatible = "arm,coresight-cti", "arm,primecell";
2205			reg = <0x0 0x08019000 0x0 0x1000>;
2206
2207			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2208			clock-names = "apb_pclk";
2209
2210			status = "disabled";
2211		};
2212
2213		cti10: cti@801a000 {
2214			compatible = "arm,coresight-cti", "arm,primecell";
2215			reg = <0x0 0x0801a000 0x0 0x1000>;
2216
2217			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2218			clock-names = "apb_pclk";
2219
2220			status = "disabled";
2221		};
2222
2223		cti11: cti@801b000 {
2224			compatible = "arm,coresight-cti", "arm,primecell";
2225			reg = <0x0 0x0801b000 0x0 0x1000>;
2226
2227			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2228			clock-names = "apb_pclk";
2229
2230			status = "disabled";
2231		};
2232
2233		cti12: cti@801c000 {
2234			compatible = "arm,coresight-cti", "arm,primecell";
2235			reg = <0x0 0x0801c000 0x0 0x1000>;
2236
2237			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2238			clock-names = "apb_pclk";
2239
2240			status = "disabled";
2241		};
2242
2243		cti13: cti@801d000 {
2244			compatible = "arm,coresight-cti", "arm,primecell";
2245			reg = <0x0 0x0801d000 0x0 0x1000>;
2246
2247			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2248			clock-names = "apb_pclk";
2249
2250			status = "disabled";
2251		};
2252
2253		cti14: cti@801e000 {
2254			compatible = "arm,coresight-cti", "arm,primecell";
2255			reg = <0x0 0x0801e000 0x0 0x1000>;
2256
2257			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2258			clock-names = "apb_pclk";
2259
2260			status = "disabled";
2261		};
2262
2263		cti15: cti@801f000 {
2264			compatible = "arm,coresight-cti", "arm,primecell";
2265			reg = <0x0 0x0801f000 0x0 0x1000>;
2266
2267			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2268			clock-names = "apb_pclk";
2269
2270			status = "disabled";
2271		};
2272
2273		replicator@8046000 {
2274			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2275			reg = <0x0 0x08046000 0x0 0x1000>;
2276
2277			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2278			clock-names = "apb_pclk";
2279
2280			status = "disabled";
2281
2282			out-ports {
2283				port {
2284					replicator_out: endpoint {
2285						remote-endpoint = <&etr_in>;
2286					};
2287				};
2288			};
2289
2290			in-ports {
2291				port {
2292					replicator_in: endpoint {
2293						remote-endpoint = <&etf_out>;
2294					};
2295				};
2296			};
2297		};
2298
2299		etf@8047000 {
2300			compatible = "arm,coresight-tmc", "arm,primecell";
2301			reg = <0x0 0x08047000 0x0 0x1000>;
2302
2303			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2304			clock-names = "apb_pclk";
2305
2306			status = "disabled";
2307
2308			in-ports {
2309				port {
2310					etf_in: endpoint {
2311						remote-endpoint = <&merge_funnel_out>;
2312					};
2313				};
2314			};
2315
2316			out-ports {
2317				port {
2318					etf_out: endpoint {
2319						remote-endpoint = <&replicator_in>;
2320					};
2321				};
2322			};
2323		};
2324
2325		etr@8048000 {
2326			compatible = "arm,coresight-tmc", "arm,primecell";
2327			reg = <0x0 0x08048000 0x0 0x1000>;
2328
2329			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2330			clock-names = "apb_pclk";
2331
2332			status = "disabled";
2333
2334			in-ports {
2335				port {
2336					etr_in: endpoint {
2337						remote-endpoint = <&replicator_out>;
2338					};
2339				};
2340			};
2341		};
2342
2343		funnel@8041000 {
2344			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2345			reg = <0x0 0x08041000 0x0 0x1000>;
2346
2347			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2348			clock-names = "apb_pclk";
2349
2350			status = "disabled";
2351
2352			out-ports {
2353				port {
2354					funnel_in0_out: endpoint {
2355						remote-endpoint = <&merge_funnel_in0>;
2356					};
2357				};
2358			};
2359
2360			in-ports {
2361				port {
2362					funnel_in0_in: endpoint {
2363						remote-endpoint = <&stm_out>;
2364					};
2365				};
2366			};
2367		};
2368
2369		funnel@8042000 {
2370			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2371			reg = <0x0 0x08042000 0x0 0x1000>;
2372
2373			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2374			clock-names = "apb_pclk";
2375
2376			status = "disabled";
2377
2378			out-ports {
2379				port {
2380					funnel_in1_out: endpoint {
2381						remote-endpoint = <&merge_funnel_in1>;
2382					};
2383				};
2384			};
2385
2386			in-ports {
2387				port {
2388					funnel_in1_in: endpoint {
2389						remote-endpoint = <&funnel_apss1_out>;
2390					};
2391				};
2392			};
2393		};
2394
2395		funnel@8045000 {
2396			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2397			reg = <0x0 0x08045000 0x0 0x1000>;
2398
2399			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2400			clock-names = "apb_pclk";
2401
2402			status = "disabled";
2403
2404			out-ports {
2405				port {
2406					merge_funnel_out: endpoint {
2407						remote-endpoint = <&etf_in>;
2408					};
2409				};
2410			};
2411
2412			in-ports {
2413				#address-cells = <1>;
2414				#size-cells = <0>;
2415
2416				port@0 {
2417					reg = <0>;
2418					merge_funnel_in0: endpoint {
2419						remote-endpoint = <&funnel_in0_out>;
2420					};
2421				};
2422
2423				port@1 {
2424					reg = <1>;
2425					merge_funnel_in1: endpoint {
2426						remote-endpoint = <&funnel_in1_out>;
2427					};
2428				};
2429			};
2430		};
2431
2432		etm@9040000 {
2433			compatible = "arm,coresight-etm4x", "arm,primecell";
2434			reg = <0x0 0x09040000 0x0 0x1000>;
2435
2436			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2437			clock-names = "apb_pclk";
2438			arm,coresight-loses-context-with-cpu;
2439
2440			cpu = <&cpu0>;
2441
2442			status = "disabled";
2443
2444			out-ports {
2445				port {
2446					etm0_out: endpoint {
2447						remote-endpoint = <&funnel_apss0_in0>;
2448					};
2449				};
2450			};
2451		};
2452
2453		etm@9140000 {
2454			compatible = "arm,coresight-etm4x", "arm,primecell";
2455			reg = <0x0 0x09140000 0x0 0x1000>;
2456
2457			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2458			clock-names = "apb_pclk";
2459			arm,coresight-loses-context-with-cpu;
2460
2461			cpu = <&cpu1>;
2462
2463			status = "disabled";
2464
2465			out-ports {
2466				port {
2467					etm1_out: endpoint {
2468						remote-endpoint = <&funnel_apss0_in1>;
2469					};
2470				};
2471			};
2472		};
2473
2474		etm@9240000 {
2475			compatible = "arm,coresight-etm4x", "arm,primecell";
2476			reg = <0x0 0x09240000 0x0 0x1000>;
2477
2478			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2479			clock-names = "apb_pclk";
2480			arm,coresight-loses-context-with-cpu;
2481
2482			cpu = <&cpu2>;
2483
2484			status = "disabled";
2485
2486			out-ports {
2487				port {
2488					etm2_out: endpoint {
2489						remote-endpoint = <&funnel_apss0_in2>;
2490					};
2491				};
2492			};
2493		};
2494
2495		etm@9340000 {
2496			compatible = "arm,coresight-etm4x", "arm,primecell";
2497			reg = <0x0 0x09340000 0x0 0x1000>;
2498
2499			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2500			clock-names = "apb_pclk";
2501			arm,coresight-loses-context-with-cpu;
2502
2503			cpu = <&cpu3>;
2504
2505			status = "disabled";
2506
2507			out-ports {
2508				port {
2509					etm3_out: endpoint {
2510						remote-endpoint = <&funnel_apss0_in3>;
2511					};
2512				};
2513			};
2514		};
2515
2516		etm@9440000 {
2517			compatible = "arm,coresight-etm4x", "arm,primecell";
2518			reg = <0x0 0x09440000 0x0 0x1000>;
2519
2520			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2521			clock-names = "apb_pclk";
2522			arm,coresight-loses-context-with-cpu;
2523
2524			cpu = <&cpu4>;
2525
2526			status = "disabled";
2527
2528			out-ports {
2529				port {
2530					etm4_out: endpoint {
2531						remote-endpoint = <&funnel_apss0_in4>;
2532					};
2533				};
2534			};
2535		};
2536
2537		etm@9540000 {
2538			compatible = "arm,coresight-etm4x", "arm,primecell";
2539			reg = <0x0 0x09540000 0x0 0x1000>;
2540
2541			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2542			clock-names = "apb_pclk";
2543			arm,coresight-loses-context-with-cpu;
2544
2545			cpu = <&cpu5>;
2546
2547			status = "disabled";
2548
2549			out-ports {
2550				port {
2551					etm5_out: endpoint {
2552						remote-endpoint = <&funnel_apss0_in5>;
2553					};
2554				};
2555			};
2556		};
2557
2558		etm@9640000 {
2559			compatible = "arm,coresight-etm4x", "arm,primecell";
2560			reg = <0x0 0x09640000 0x0 0x1000>;
2561
2562			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2563			clock-names = "apb_pclk";
2564			arm,coresight-loses-context-with-cpu;
2565
2566			cpu = <&cpu6>;
2567
2568			status = "disabled";
2569
2570			out-ports {
2571				port {
2572					etm6_out: endpoint {
2573						remote-endpoint = <&funnel_apss0_in6>;
2574					};
2575				};
2576			};
2577		};
2578
2579		etm@9740000 {
2580			compatible = "arm,coresight-etm4x", "arm,primecell";
2581			reg = <0x0 0x09740000 0x0 0x1000>;
2582
2583			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2584			clock-names = "apb_pclk";
2585			arm,coresight-loses-context-with-cpu;
2586
2587			cpu = <&cpu7>;
2588
2589			status = "disabled";
2590
2591			out-ports {
2592				port {
2593					etm7_out: endpoint {
2594						remote-endpoint = <&funnel_apss0_in7>;
2595					};
2596				};
2597			};
2598		};
2599
2600		funnel@9800000 {
2601			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2602			reg = <0x0 0x09800000 0x0 0x1000>;
2603
2604			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2605			clock-names = "apb_pclk";
2606
2607			status = "disabled";
2608
2609			out-ports {
2610				port {
2611					funnel_apss0_out: endpoint {
2612						remote-endpoint = <&funnel_apss1_in>;
2613					};
2614				};
2615			};
2616
2617			in-ports {
2618				#address-cells = <1>;
2619				#size-cells = <0>;
2620
2621				port@0 {
2622					reg = <0>;
2623					funnel_apss0_in0: endpoint {
2624						remote-endpoint = <&etm0_out>;
2625					};
2626				};
2627
2628				port@1 {
2629					reg = <1>;
2630					funnel_apss0_in1: endpoint {
2631						remote-endpoint = <&etm1_out>;
2632					};
2633				};
2634
2635				port@2 {
2636					reg = <2>;
2637					funnel_apss0_in2: endpoint {
2638						remote-endpoint = <&etm2_out>;
2639					};
2640				};
2641
2642				port@3 {
2643					reg = <3>;
2644					funnel_apss0_in3: endpoint {
2645						remote-endpoint = <&etm3_out>;
2646					};
2647				};
2648
2649				port@4 {
2650					reg = <4>;
2651					funnel_apss0_in4: endpoint {
2652						remote-endpoint = <&etm4_out>;
2653					};
2654				};
2655
2656				port@5 {
2657					reg = <5>;
2658					funnel_apss0_in5: endpoint {
2659						remote-endpoint = <&etm5_out>;
2660					};
2661				};
2662
2663				port@6 {
2664					reg = <6>;
2665					funnel_apss0_in6: endpoint {
2666						remote-endpoint = <&etm6_out>;
2667					};
2668				};
2669
2670				port@7 {
2671					reg = <7>;
2672					funnel_apss0_in7: endpoint {
2673						remote-endpoint = <&etm7_out>;
2674					};
2675				};
2676			};
2677		};
2678
2679		funnel@9810000 {
2680			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2681			reg = <0x0 0x09810000 0x0 0x1000>;
2682
2683			clocks = <&rpmcc RPM_SMD_QDSS_CLK>;
2684			clock-names = "apb_pclk";
2685
2686			status = "disabled";
2687
2688			out-ports {
2689				port {
2690					funnel_apss1_out: endpoint {
2691						remote-endpoint = <&funnel_in1_in>;
2692					};
2693				};
2694			};
2695
2696			in-ports {
2697				port {
2698					funnel_apss1_in: endpoint {
2699						remote-endpoint = <&funnel_apss0_out>;
2700					};
2701				};
2702			};
2703		};
2704
2705		remoteproc_adsp: remoteproc@a400000 {
2706			compatible = "qcom,sm6115-adsp-pas";
2707			reg = <0x0 0x0a400000 0x0 0x4040>;
2708
2709			interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>,
2710					      <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2711					      <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2712					      <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2713					      <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2714			interrupt-names = "wdog", "fatal", "ready",
2715					  "handover", "stop-ack";
2716
2717			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2718			clock-names = "xo";
2719
2720			power-domains = <&rpmpd SM6115_VDD_LPI_CX>,
2721					<&rpmpd SM6115_VDD_LPI_MX>;
2722
2723			memory-region = <&pil_adsp_mem>;
2724
2725			qcom,smem-states = <&adsp_smp2p_out 0>;
2726			qcom,smem-state-names = "stop";
2727
2728			status = "disabled";
2729
2730			glink-edge {
2731				interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>;
2732				label = "lpass";
2733				qcom,remote-pid = <2>;
2734				mboxes = <&apcs_glb 8>;
2735
2736				apr {
2737					compatible = "qcom,apr-v2";
2738					qcom,glink-channels = "apr_audio_svc";
2739					qcom,domain = <APR_DOMAIN_ADSP>;
2740					#address-cells = <1>;
2741					#size-cells = <0>;
2742
2743					service@3 {
2744						reg = <APR_SVC_ADSP_CORE>;
2745						compatible = "qcom,q6core";
2746						qcom,protection-domain = "avs/audio",
2747									 "msm/adsp/audio_pd";
2748					};
2749
2750					q6afe: service@4 {
2751						compatible = "qcom,q6afe";
2752						reg = <APR_SVC_AFE>;
2753						qcom,protection-domain = "avs/audio",
2754									 "msm/adsp/audio_pd";
2755						q6afedai: dais {
2756							compatible = "qcom,q6afe-dais";
2757							#address-cells = <1>;
2758							#size-cells = <0>;
2759							#sound-dai-cells = <1>;
2760						};
2761
2762						q6afecc: clock-controller {
2763							compatible = "qcom,q6afe-clocks";
2764							#clock-cells = <2>;
2765						};
2766					};
2767
2768					q6asm: service@7 {
2769						compatible = "qcom,q6asm";
2770						reg = <APR_SVC_ASM>;
2771						qcom,protection-domain = "avs/audio",
2772									 "msm/adsp/audio_pd";
2773						q6asmdai: dais {
2774							compatible = "qcom,q6asm-dais";
2775							#address-cells = <1>;
2776							#size-cells = <0>;
2777							#sound-dai-cells = <1>;
2778							iommus = <&apps_smmu 0x1c1 0x0>;
2779
2780							dai@0 {
2781								reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>;
2782							};
2783
2784							dai@1 {
2785								reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>;
2786							};
2787
2788							dai@2 {
2789								reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>;
2790							};
2791						};
2792					};
2793
2794					q6adm: service@8 {
2795						compatible = "qcom,q6adm";
2796						reg = <APR_SVC_ADM>;
2797						qcom,protection-domain = "avs/audio",
2798									 "msm/adsp/audio_pd";
2799						q6routing: routing {
2800							compatible = "qcom,q6adm-routing";
2801							#sound-dai-cells = <0>;
2802						};
2803					};
2804				};
2805
2806				fastrpc {
2807					compatible = "qcom,fastrpc";
2808					qcom,glink-channels = "fastrpcglink-apps-dsp";
2809					label = "adsp";
2810					qcom,non-secure-domain;
2811					#address-cells = <1>;
2812					#size-cells = <0>;
2813
2814					compute-cb@3 {
2815						compatible = "qcom,fastrpc-compute-cb";
2816						reg = <3>;
2817						iommus = <&apps_smmu 0x01c3 0x0>;
2818					};
2819
2820					compute-cb@4 {
2821						compatible = "qcom,fastrpc-compute-cb";
2822						reg = <4>;
2823						iommus = <&apps_smmu 0x01c4 0x0>;
2824					};
2825
2826					compute-cb@5 {
2827						compatible = "qcom,fastrpc-compute-cb";
2828						reg = <5>;
2829						iommus = <&apps_smmu 0x01c5 0x0>;
2830					};
2831
2832					compute-cb@6 {
2833						compatible = "qcom,fastrpc-compute-cb";
2834						reg = <6>;
2835						iommus = <&apps_smmu 0x01c6 0x0>;
2836					};
2837
2838					compute-cb@7 {
2839						compatible = "qcom,fastrpc-compute-cb";
2840						reg = <7>;
2841						iommus = <&apps_smmu 0x01c7 0x0>;
2842					};
2843				};
2844			};
2845		};
2846
2847		remoteproc_cdsp: remoteproc@b300000 {
2848			compatible = "qcom,sm6115-cdsp-pas";
2849			reg = <0x0 0x0b300000 0x0 0x4040>;
2850
2851			interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>,
2852					      <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2853					      <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2854					      <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2855					      <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
2856			interrupt-names = "wdog", "fatal", "ready",
2857					  "handover", "stop-ack";
2858
2859			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
2860			clock-names = "xo";
2861
2862			power-domains = <&rpmpd SM6115_VDDCX>;
2863
2864			memory-region = <&pil_cdsp_mem>;
2865
2866			qcom,smem-states = <&cdsp_smp2p_out 0>;
2867			qcom,smem-state-names = "stop";
2868
2869			status = "disabled";
2870
2871			glink-edge {
2872				interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING>;
2873				label = "cdsp";
2874				qcom,remote-pid = <5>;
2875				mboxes = <&apcs_glb 28>;
2876
2877				fastrpc {
2878					compatible = "qcom,fastrpc";
2879					qcom,glink-channels = "fastrpcglink-apps-dsp";
2880					label = "cdsp";
2881					qcom,non-secure-domain;
2882					#address-cells = <1>;
2883					#size-cells = <0>;
2884
2885					compute-cb@1 {
2886						compatible = "qcom,fastrpc-compute-cb";
2887						reg = <1>;
2888						iommus = <&apps_smmu 0x0c01 0x0>;
2889					};
2890
2891					compute-cb@2 {
2892						compatible = "qcom,fastrpc-compute-cb";
2893						reg = <2>;
2894						iommus = <&apps_smmu 0x0c02 0x0>;
2895					};
2896
2897					compute-cb@3 {
2898						compatible = "qcom,fastrpc-compute-cb";
2899						reg = <3>;
2900						iommus = <&apps_smmu 0x0c03 0x0>;
2901					};
2902
2903					compute-cb@4 {
2904						compatible = "qcom,fastrpc-compute-cb";
2905						reg = <4>;
2906						iommus = <&apps_smmu 0x0c04 0x0>;
2907					};
2908
2909					compute-cb@5 {
2910						compatible = "qcom,fastrpc-compute-cb";
2911						reg = <5>;
2912						iommus = <&apps_smmu 0x0c05 0x0>;
2913					};
2914
2915					compute-cb@6 {
2916						compatible = "qcom,fastrpc-compute-cb";
2917						reg = <6>;
2918						iommus = <&apps_smmu 0x0c06 0x0>;
2919					};
2920
2921					/* note: secure cb9 in downstream */
2922				};
2923			};
2924		};
2925
2926		apps_smmu: iommu@c600000 {
2927			compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500";
2928			reg = <0x0 0x0c600000 0x0 0x80000>;
2929			#iommu-cells = <2>;
2930			#global-interrupts = <1>;
2931
2932			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>,
2933				     <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
2934				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
2935				     <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
2936				     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
2937				     <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
2938				     <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
2939				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
2940				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
2941				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
2942				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
2943				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
2944				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
2945				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
2946				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
2947				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
2948				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
2949				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
2950				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
2951				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
2952				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
2953				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
2954				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
2955				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
2956				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
2957				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
2958				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
2959				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
2960				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
2961				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
2962				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
2963				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
2964				     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
2965				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
2966				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
2967				     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
2968				     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
2969				     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
2970				     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
2971				     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
2972				     <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
2973				     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
2974				     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
2975				     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
2976				     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2977				     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
2978				     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
2979				     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
2980				     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
2981				     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
2982				     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
2983				     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
2984				     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
2985				     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
2986				     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
2987				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
2988				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
2989				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
2990				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
2991				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
2992				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
2993				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
2994				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
2995				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
2996				     <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
2997		};
2998
2999		wifi: wifi@c800000 {
3000			compatible = "qcom,wcn3990-wifi";
3001			reg = <0x0 0x0c800000 0x0 0x800000>;
3002			reg-names = "membase";
3003			memory-region = <&wlan_msa_mem>;
3004			interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
3005				     <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
3006				     <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>,
3007				     <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>,
3008				     <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>,
3009				     <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>,
3010				     <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>,
3011				     <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>,
3012				     <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>,
3013				     <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>,
3014				     <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>,
3015				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
3016			iommus = <&apps_smmu 0x1a0 0x1>;
3017			qcom,msa-fixed-perm;
3018			status = "disabled";
3019		};
3020
3021		watchdog@f017000 {
3022			compatible = "qcom,apss-wdt-sm6115", "qcom,kpss-wdt";
3023			reg = <0x0 0x0f017000 0x0 0x1000>;
3024			clocks = <&sleep_clk>;
3025			interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>;
3026		};
3027
3028		apcs_glb: mailbox@f111000 {
3029			compatible = "qcom,sm6115-apcs-hmss-global",
3030				     "qcom,msm8994-apcs-kpss-global";
3031			reg = <0x0 0x0f111000 0x0 0x1000>;
3032
3033			#mbox-cells = <1>;
3034		};
3035
3036		timer@f120000 {
3037			compatible = "arm,armv7-timer-mem";
3038			reg = <0x0 0x0f120000 0x0 0x1000>;
3039			#address-cells = <2>;
3040			#size-cells = <1>;
3041			ranges = <0x0 0x0 0x0 0x0 0x20000000>;
3042			clock-frequency = <19200000>;
3043
3044			frame@f121000 {
3045				reg = <0x0 0x0f121000 0x1000>, <0x0 0x0f122000 0x1000>;
3046				frame-number = <0>;
3047				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3048					     <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
3049			};
3050
3051			frame@f123000 {
3052				reg = <0x0 0x0f123000 0x1000>;
3053				frame-number = <1>;
3054				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3055				status = "disabled";
3056			};
3057
3058			frame@f124000 {
3059				reg = <0x0 0x0f124000 0x1000>;
3060				frame-number = <2>;
3061				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3062				status = "disabled";
3063			};
3064
3065			frame@f125000 {
3066				reg = <0x0 0x0f125000 0x1000>;
3067				frame-number = <3>;
3068				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3069				status = "disabled";
3070			};
3071
3072			frame@f126000 {
3073				reg = <0x0 0x0f126000 0x1000>;
3074				frame-number = <4>;
3075				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3076				status = "disabled";
3077			};
3078
3079			frame@f127000 {
3080				reg = <0x0 0x0f127000 0x1000>;
3081				frame-number = <5>;
3082				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3083				status = "disabled";
3084			};
3085
3086			frame@f128000 {
3087				reg = <0x0 0x0f128000 0x1000>;
3088				frame-number = <6>;
3089				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3090				status = "disabled";
3091			};
3092		};
3093
3094		intc: interrupt-controller@f200000 {
3095			compatible = "arm,gic-v3";
3096			reg = <0x0 0x0f200000 0x0 0x10000>,
3097			      <0x0 0x0f300000 0x0 0x100000>;
3098			#interrupt-cells = <3>;
3099			interrupt-controller;
3100			interrupt-parent = <&intc>;
3101			#redistributor-regions = <1>;
3102			redistributor-stride = <0x0 0x20000>;
3103			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3104		};
3105
3106		cpufreq_hw: cpufreq@f521000 {
3107			compatible = "qcom,sm6115-cpufreq-hw", "qcom,cpufreq-hw";
3108			reg = <0x0 0x0f521000 0x0 0x1000>,
3109			      <0x0 0x0f523000 0x0 0x1000>;
3110
3111			reg-names = "freq-domain0", "freq-domain1";
3112			clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
3113			clock-names = "xo", "alternate";
3114
3115			#freq-domain-cells = <1>;
3116			#clock-cells = <1>;
3117		};
3118	};
3119
3120	thermal-zones {
3121		mapss-thermal {
3122			thermal-sensors = <&tsens0 0>;
3123
3124			trips {
3125				trip-point0 {
3126					temperature = <115000>;
3127					hysteresis = <5000>;
3128					type = "passive";
3129				};
3130
3131				trip-point1 {
3132					temperature = <125000>;
3133					hysteresis = <1000>;
3134					type = "passive";
3135				};
3136			};
3137		};
3138
3139		cdsp-hvx-thermal {
3140			thermal-sensors = <&tsens0 1>;
3141
3142			trips {
3143				trip-point0 {
3144					temperature = <115000>;
3145					hysteresis = <5000>;
3146					type = "passive";
3147				};
3148
3149				trip-point1 {
3150					temperature = <125000>;
3151					hysteresis = <1000>;
3152					type = "passive";
3153				};
3154			};
3155		};
3156
3157		wlan-thermal {
3158			thermal-sensors = <&tsens0 2>;
3159
3160			trips {
3161				trip-point0 {
3162					temperature = <115000>;
3163					hysteresis = <5000>;
3164					type = "passive";
3165				};
3166
3167				trip-point1 {
3168					temperature = <125000>;
3169					hysteresis = <1000>;
3170					type = "passive";
3171				};
3172			};
3173		};
3174
3175		camera-thermal {
3176			thermal-sensors = <&tsens0 3>;
3177
3178			trips {
3179				trip-point0 {
3180					temperature = <115000>;
3181					hysteresis = <5000>;
3182					type = "passive";
3183				};
3184
3185				trip-point1 {
3186					temperature = <125000>;
3187					hysteresis = <1000>;
3188					type = "passive";
3189				};
3190			};
3191		};
3192
3193		video-thermal {
3194			thermal-sensors = <&tsens0 4>;
3195
3196			trips {
3197				trip-point0 {
3198					temperature = <115000>;
3199					hysteresis = <5000>;
3200					type = "passive";
3201				};
3202
3203				trip-point1 {
3204					temperature = <125000>;
3205					hysteresis = <1000>;
3206					type = "passive";
3207				};
3208			};
3209		};
3210
3211		modem1-thermal {
3212			thermal-sensors = <&tsens0 5>;
3213
3214			trips {
3215				trip-point0 {
3216					temperature = <115000>;
3217					hysteresis = <5000>;
3218					type = "passive";
3219				};
3220
3221				trip-point1 {
3222					temperature = <125000>;
3223					hysteresis = <1000>;
3224					type = "passive";
3225				};
3226			};
3227		};
3228
3229		cpu4-thermal {
3230			thermal-sensors = <&tsens0 6>;
3231
3232			trips {
3233				cpu4_alert0: trip-point0 {
3234					temperature = <90000>;
3235					hysteresis = <2000>;
3236					type = "passive";
3237				};
3238
3239				cpu4_alert1: trip-point1 {
3240					temperature = <95000>;
3241					hysteresis = <2000>;
3242					type = "passive";
3243				};
3244
3245				cpu4_crit: cpu-crit {
3246					temperature = <110000>;
3247					hysteresis = <1000>;
3248					type = "critical";
3249				};
3250			};
3251		};
3252
3253		cpu5-thermal {
3254			thermal-sensors = <&tsens0 7>;
3255
3256			trips {
3257				cpu5_alert0: trip-point0 {
3258					temperature = <90000>;
3259					hysteresis = <2000>;
3260					type = "passive";
3261				};
3262
3263				cpu5_alert1: trip-point1 {
3264					temperature = <95000>;
3265					hysteresis = <2000>;
3266					type = "passive";
3267				};
3268
3269				cpu5_crit: cpu-crit {
3270					temperature = <110000>;
3271					hysteresis = <1000>;
3272					type = "critical";
3273				};
3274			};
3275		};
3276
3277		cpu6-thermal {
3278			thermal-sensors = <&tsens0 8>;
3279
3280			trips {
3281				cpu6_alert0: trip-point0 {
3282					temperature = <90000>;
3283					hysteresis = <2000>;
3284					type = "passive";
3285				};
3286
3287				cpu6_alert1: trip-point1 {
3288					temperature = <95000>;
3289					hysteresis = <2000>;
3290					type = "passive";
3291				};
3292
3293				cpu6_crit: cpu-crit {
3294					temperature = <110000>;
3295					hysteresis = <1000>;
3296					type = "critical";
3297				};
3298			};
3299		};
3300
3301		cpu7-thermal {
3302			thermal-sensors = <&tsens0 9>;
3303
3304			trips {
3305				cpu7_alert0: trip-point0 {
3306					temperature = <90000>;
3307					hysteresis = <2000>;
3308					type = "passive";
3309				};
3310
3311				cpu7_alert1: trip-point1 {
3312					temperature = <95000>;
3313					hysteresis = <2000>;
3314					type = "passive";
3315				};
3316
3317				cpu7_crit: cpu-crit {
3318					temperature = <110000>;
3319					hysteresis = <1000>;
3320					type = "critical";
3321				};
3322			};
3323		};
3324
3325		cpu45-thermal {
3326			thermal-sensors = <&tsens0 10>;
3327
3328			trips {
3329				cpu45_alert0: trip-point0 {
3330					temperature = <90000>;
3331					hysteresis = <2000>;
3332					type = "passive";
3333				};
3334
3335				cpu45_alert1: trip-point1 {
3336					temperature = <95000>;
3337					hysteresis = <2000>;
3338					type = "passive";
3339				};
3340
3341				cpu45_crit: cpu-crit {
3342					temperature = <110000>;
3343					hysteresis = <1000>;
3344					type = "critical";
3345				};
3346			};
3347		};
3348
3349		cpu67-thermal {
3350			thermal-sensors = <&tsens0 11>;
3351
3352			trips {
3353				cpu67_alert0: trip-point0 {
3354					temperature = <90000>;
3355					hysteresis = <2000>;
3356					type = "passive";
3357				};
3358
3359				cpu67_alert1: trip-point1 {
3360					temperature = <95000>;
3361					hysteresis = <2000>;
3362					type = "passive";
3363				};
3364
3365				cpu67_crit: cpu-crit {
3366					temperature = <110000>;
3367					hysteresis = <1000>;
3368					type = "critical";
3369				};
3370			};
3371		};
3372
3373		cpu0123-thermal {
3374			thermal-sensors = <&tsens0 12>;
3375
3376			trips {
3377				cpu0123_alert0: trip-point0 {
3378					temperature = <90000>;
3379					hysteresis = <2000>;
3380					type = "passive";
3381				};
3382
3383				cpu0123_alert1: trip-point1 {
3384					temperature = <95000>;
3385					hysteresis = <2000>;
3386					type = "passive";
3387				};
3388
3389				cpu0123_crit: cpu-crit {
3390					temperature = <110000>;
3391					hysteresis = <1000>;
3392					type = "critical";
3393				};
3394			};
3395		};
3396
3397		modem0-thermal {
3398			thermal-sensors = <&tsens0 13>;
3399
3400			trips {
3401				trip-point0 {
3402					temperature = <115000>;
3403					hysteresis = <5000>;
3404					type = "passive";
3405				};
3406
3407				trip-point1 {
3408					temperature = <125000>;
3409					hysteresis = <1000>;
3410					type = "passive";
3411				};
3412			};
3413		};
3414
3415		display-thermal {
3416			thermal-sensors = <&tsens0 14>;
3417
3418			trips {
3419				trip-point0 {
3420					temperature = <115000>;
3421					hysteresis = <5000>;
3422					type = "passive";
3423				};
3424
3425				trip-point1 {
3426					temperature = <125000>;
3427					hysteresis = <1000>;
3428					type = "passive";
3429				};
3430			};
3431		};
3432
3433		gpu-thermal {
3434			polling-delay-passive = <250>;
3435
3436			thermal-sensors = <&tsens0 15>;
3437
3438			cooling-maps {
3439				map0 {
3440					trip = <&gpu_alert0>;
3441					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3442				};
3443			};
3444
3445			trips {
3446				gpu_alert0: trip-point0 {
3447					temperature = <85000>;
3448					hysteresis = <1000>;
3449					type = "passive";
3450				};
3451
3452				trip-point1 {
3453					temperature = <110000>;
3454					hysteresis = <1000>;
3455					type = "critical";
3456				};
3457			};
3458		};
3459	};
3460
3461	timer {
3462		compatible = "arm,armv8-timer";
3463		interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3464			     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3465			     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
3466			     <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
3467	};
3468};