sdx75.dtsi

   1// SPDX-License-Identifier: BSD-3-Clause
   2/*
   3 * SDX75 SoC device tree source
   4 *
   5 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
   6 *
   7 */
   8
   9#include <dt-bindings/clock/qcom,rpmh.h>
  10#include <dt-bindings/clock/qcom,sdx75-gcc.h>
  11#include <dt-bindings/dma/qcom-gpi.h>
  12#include <dt-bindings/gpio/gpio.h>
  13#include <dt-bindings/interconnect/qcom,icc.h>
  14#include <dt-bindings/interconnect/qcom,sdx75.h>
  15#include <dt-bindings/interrupt-controller/arm-gic.h>
  16#include <dt-bindings/mailbox/qcom-ipcc.h>
  17#include <dt-bindings/power/qcom,rpmhpd.h>
  18#include <dt-bindings/power/qcom-rpmpd.h>
  19#include <dt-bindings/soc/qcom,rpmh-rsc.h>
  20
  21/ {
  22	#address-cells = <2>;
  23	#size-cells = <2>;
  24	interrupt-parent = <&intc>;
  25
  26	chosen: chosen { };
  27
  28	clocks {
  29		xo_board: xo-board {
  30			compatible = "fixed-clock";
  31			clock-frequency = <76800000>;
  32			#clock-cells = <0>;
  33		};
  34
  35		sleep_clk: sleep-clk {
  36			compatible = "fixed-clock";
  37			clock-frequency = <32764>;
  38			#clock-cells = <0>;
  39		};
  40	};
  41
  42	cpus {
  43		#address-cells = <2>;
  44		#size-cells = <0>;
  45
  46		cpu0: cpu@0 {
  47			device_type = "cpu";
  48			compatible = "arm,cortex-a55";
  49			reg = <0x0 0x0>;
  50			clocks = <&cpufreq_hw 0>;
  51			enable-method = "psci";
  52			power-domains = <&cpu_pd0>;
  53			power-domain-names = "psci";
  54			qcom,freq-domain = <&cpufreq_hw 0>;
  55			capacity-dmips-mhz = <1024>;
  56			dynamic-power-coefficient = <100>;
  57			next-level-cache = <&l2_0>;
  58
  59			l2_0: l2-cache {
  60				compatible = "cache";
  61				cache-level = <2>;
  62				cache-unified;
  63				next-level-cache = <&l3_0>;
  64				l3_0: l3-cache {
  65					compatible = "cache";
  66					cache-level = <3>;
  67					cache-unified;
  68				};
  69			};
  70		};
  71
  72		cpu1: cpu@100 {
  73			device_type = "cpu";
  74			compatible = "arm,cortex-a55";
  75			reg = <0x0 0x100>;
  76			clocks = <&cpufreq_hw 0>;
  77			enable-method = "psci";
  78			power-domains = <&cpu_pd1>;
  79			power-domain-names = "psci";
  80			qcom,freq-domain = <&cpufreq_hw 0>;
  81			capacity-dmips-mhz = <1024>;
  82			dynamic-power-coefficient = <100>;
  83			next-level-cache = <&l2_100>;
  84
  85			l2_100: l2-cache {
  86				compatible = "cache";
  87				cache-level = <2>;
  88				cache-unified;
  89				next-level-cache = <&l3_0>;
  90			};
  91		};
  92
  93		cpu2: cpu@200 {
  94			device_type = "cpu";
  95			compatible = "arm,cortex-a55";
  96			reg = <0x0 0x200>;
  97			clocks = <&cpufreq_hw 0>;
  98			enable-method = "psci";
  99			power-domains = <&cpu_pd2>;
 100			power-domain-names = "psci";
 101			qcom,freq-domain = <&cpufreq_hw 0>;
 102			capacity-dmips-mhz = <1024>;
 103			dynamic-power-coefficient = <100>;
 104			next-level-cache = <&l2_200>;
 105
 106			l2_200: l2-cache {
 107				compatible = "cache";
 108				cache-level = <2>;
 109				cache-unified;
 110				next-level-cache = <&l3_0>;
 111			};
 112		};
 113
 114		cpu3: cpu@300 {
 115			device_type = "cpu";
 116			compatible = "arm,cortex-a55";
 117			reg = <0x0 0x300>;
 118			clocks = <&cpufreq_hw 0>;
 119			enable-method = "psci";
 120			power-domains = <&cpu_pd3>;
 121			power-domain-names = "psci";
 122			qcom,freq-domain = <&cpufreq_hw 0>;
 123			capacity-dmips-mhz = <1024>;
 124			dynamic-power-coefficient = <100>;
 125			next-level-cache = <&l2_300>;
 126
 127			l2_300: l2-cache {
 128				compatible = "cache";
 129				cache-level = <2>;
 130				cache-unified;
 131				next-level-cache = <&l3_0>;
 132			};
 133		};
 134
 135		cpu-map {
 136			cluster0 {
 137				core0 {
 138					cpu = <&cpu0>;
 139				};
 140
 141				core1 {
 142					cpu = <&cpu1>;
 143				};
 144
 145				core2 {
 146					cpu = <&cpu2>;
 147				};
 148
 149				core3 {
 150					cpu = <&cpu3>;
 151				};
 152			};
 153		};
 154
 155		idle-states {
 156			entry-method = "psci";
 157
 158			cpu_off: cpu-sleep-0 {
 159				compatible = "arm,idle-state";
 160				entry-latency-us = <235>;
 161				exit-latency-us = <428>;
 162				min-residency-us = <1774>;
 163				arm,psci-suspend-param = <0x40000003>;
 164				local-timer-stop;
 165			};
 166
 167			cpu_rail_off: cpu-rail-sleep-1 {
 168				compatible = "arm,idle-state";
 169				entry-latency-us = <800>;
 170				exit-latency-us = <750>;
 171				min-residency-us = <4090>;
 172				arm,psci-suspend-param = <0x40000004>;
 173				local-timer-stop;
 174			};
 175
 176		};
 177
 178		domain-idle-states {
 179			cluster_sleep_0: cluster-sleep-0 {
 180				compatible = "domain-idle-state";
 181				arm,psci-suspend-param = <0x41000044>;
 182				entry-latency-us = <1050>;
 183				exit-latency-us = <2500>;
 184				min-residency-us = <5309>;
 185			};
 186
 187			cluster_sleep_1: cluster-sleep-1 {
 188				compatible = "domain-idle-state";
 189				arm,psci-suspend-param = <0x41001344>;
 190				entry-latency-us = <2761>;
 191				exit-latency-us = <3964>;
 192				min-residency-us = <8467>;
 193			};
 194
 195			cluster_sleep_2: cluster-sleep-2 {
 196				compatible = "domain-idle-state";
 197				arm,psci-suspend-param = <0x4100b344>;
 198				entry-latency-us = <2793>;
 199				exit-latency-us = <4023>;
 200				min-residency-us = <9826>;
 201			};
 202		};
 203	};
 204
 205	firmware {
 206		scm: scm {
 207			compatible = "qcom,scm-sdx75", "qcom,scm";
 208		};
 209	};
 210
 211	clk_virt: interconnect-0 {
 212		compatible = "qcom,sdx75-clk-virt";
 213		#interconnect-cells = <2>;
 214		qcom,bcm-voters = <&apps_bcm_voter>;
 215		clocks = <&rpmhcc RPMH_QPIC_CLK>;
 216	};
 217
 218	mc_virt: interconnect-1 {
 219		compatible = "qcom,sdx75-mc-virt";
 220		#interconnect-cells = <2>;
 221		qcom,bcm-voters = <&apps_bcm_voter>;
 222	};
 223
 224	memory@80000000 {
 225		device_type = "memory";
 226		reg = <0x0 0x80000000 0x0 0x0>;
 227	};
 228
 229	pmu {
 230		compatible = "arm,cortex-a55-pmu";
 231		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
 232	};
 233
 234	psci {
 235		compatible = "arm,psci-1.0";
 236		method = "smc";
 237
 238		cpu_pd0: power-domain-cpu0 {
 239			#power-domain-cells = <0>;
 240			power-domains = <&cluster_pd>;
 241			domain-idle-states = <&cpu_off &cpu_rail_off>;
 242		};
 243
 244		cpu_pd1: power-domain-cpu1 {
 245			#power-domain-cells = <0>;
 246			power-domains = <&cluster_pd>;
 247			domain-idle-states = <&cpu_off &cpu_rail_off>;
 248		};
 249
 250		cpu_pd2: power-domain-cpu2 {
 251			#power-domain-cells = <0>;
 252			power-domains = <&cluster_pd>;
 253			domain-idle-states = <&cpu_off &cpu_rail_off>;
 254		};
 255
 256		cpu_pd3: power-domain-cpu3 {
 257			#power-domain-cells = <0>;
 258			power-domains = <&cluster_pd>;
 259			domain-idle-states = <&cpu_off &cpu_rail_off>;
 260		};
 261
 262		cluster_pd: power-domain-cpu-cluster0 {
 263			#power-domain-cells = <0>;
 264			domain-idle-states = <&cluster_sleep_0 &cluster_sleep_1 &cluster_sleep_2>;
 265		};
 266	};
 267
 268	reserved-memory {
 269		#address-cells = <2>;
 270		#size-cells = <2>;
 271		ranges;
 272
 273		gunyah_hyp_mem: gunyah-hyp@80000000 {
 274			reg = <0x0 0x80000000 0x0 0x800000>;
 275			no-map;
 276		};
 277
 278		hyp_elf_package_mem: hyp-elf-package@80800000 {
 279			reg = <0x0 0x80800000 0x0 0x200000>;
 280			no-map;
 281		};
 282
 283		access_control_db_mem: access-control-db@81380000 {
 284			reg = <0x0 0x81380000 0x0 0x80000>;
 285			no-map;
 286		};
 287
 288		qteetz_mem: qteetz@814e0000 {
 289			reg = <0x0 0x814e0000 0x0 0x2a0000>;
 290			no-map;
 291		};
 292
 293		trusted_apps_mem: trusted-apps@81780000 {
 294			reg = <0x0 0x81780000 0x0 0xa00000>;
 295			no-map;
 296		};
 297
 298		xbl_ramdump_mem: xbl-ramdump@87a00000 {
 299			reg = <0x0 0x87a00000 0x0 0x1c0000>;
 300			no-map;
 301		};
 302
 303		cpucp_fw_mem: cpucp-fw@87c00000 {
 304			reg = <0x0 0x87c00000 0x0 0x100000>;
 305			no-map;
 306		};
 307
 308		xbl_dtlog_mem: xbl-dtlog@87d00000 {
 309			reg = <0x0 0x87d00000 0x0 0x40000>;
 310			no-map;
 311		};
 312
 313		xbl_sc_mem: xbl-sc@87d40000 {
 314			reg = <0x0 0x87d40000 0x0 0x40000>;
 315			no-map;
 316		};
 317
 318		modem_efs_shared_mem: modem-efs-shared@87d80000 {
 319			reg = <0x0 0x87d80000 0x0 0x10000>;
 320			no-map;
 321		};
 322
 323		aop_image_mem: aop-image@87e00000 {
 324			reg = <0x0 0x87e00000 0x0 0x20000>;
 325			no-map;
 326		};
 327
 328		smem_mem: smem@87e20000 {
 329			reg = <0x0 0x87e20000 0x0 0xc0000>;
 330			no-map;
 331		};
 332
 333		aop_cmd_db_mem: aop-cmd-db@87ee0000 {
 334			compatible = "qcom,cmd-db";
 335			reg = <0x0 0x87ee0000 0x0 0x20000>;
 336			no-map;
 337		};
 338
 339		aop_config_mem: aop-config@87f00000 {
 340			reg = <0x0 0x87f00000 0x0 0x20000>;
 341			no-map;
 342		};
 343
 344		ipa_fw_mem: ipa-fw@87f20000 {
 345			reg = <0x0 0x87f20000 0x0 0x10000>;
 346			no-map;
 347		};
 348
 349		secdata_mem: secdata@87f30000 {
 350			reg = <0x0 0x87f30000 0x0 0x1000>;
 351			no-map;
 352		};
 353
 354		tme_crashdump_mem: tme-crashdump@87f31000 {
 355			reg = <0x0 0x87f31000 0x0 0x40000>;
 356			no-map;
 357		};
 358
 359		tme_log_mem: tme-log@87f71000 {
 360			reg = <0x0 0x87f71000 0x0 0x4000>;
 361			no-map;
 362		};
 363
 364		uefi_log_mem: uefi-log@87f75000 {
 365			reg = <0x0 0x87f75000 0x0 0x10000>;
 366			no-map;
 367		};
 368
 369		qdss_mem: qdss@88500000 {
 370			reg = <0x0 0x88500000 0x0 0x300000>;
 371			no-map;
 372		};
 373
 374		qlink_logging_mem: qlink-logging@88800000 {
 375			reg = <0x0 0x88800000 0x0 0x300000>;
 376			no-map;
 377		};
 378
 379		audio_heap_mem: audio-heap@88b00000 {
 380			compatible = "shared-dma-pool";
 381			reg = <0x0 0x88b00000 0x0 0x400000>;
 382			no-map;
 383		};
 384
 385		mpss_dsm_mem_2: mpss-dsm-2@88f00000 {
 386			reg = <0x0 0x88f00000 0x0 0x2500000>;
 387			no-map;
 388		};
 389
 390		mpss_dsm_mem: mpss-dsm@8b400000 {
 391			reg = <0x0 0x8b400000 0x0 0x2b80000>;
 392			no-map;
 393		};
 394
 395		q6_mpss_dtb_mem: q6-mpss-dtb@8df80000 {
 396			reg = <0x0 0x8df80000 0x0 0x80000>;
 397			no-map;
 398		};
 399
 400		mpssadsp_mem: mpssadsp@8e000000 {
 401			reg = <0x0 0x8e000000 0x0 0xf100000>;
 402			no-map;
 403		};
 404
 405		gunyah_trace_buffer_mem: gunyah-trace-buffer@bdb00000 {
 406			reg = <0x0 0xbdb00000 0x0 0x2000000>;
 407			no-map;
 408		};
 409
 410		smmu_debug_buf_mem: smmu-debug-buf@bfb00000 {
 411			reg = <0x0 0xbfb00000 0x0 0x100000>;
 412			no-map;
 413		};
 414
 415		hyp_smmu_s2_pt_mem: hyp-smmu-s2-pt@bfc00000 {
 416			reg = <0x0 0xbfc00000 0x0 0x400000>;
 417			no-map;
 418		};
 419	};
 420
 421	smp2p-modem {
 422		compatible = "qcom,smp2p";
 423		qcom,smem = <435>, <428>;
 424		interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 425					     IPCC_MPROC_SIGNAL_SMP2P
 426					     IRQ_TYPE_EDGE_RISING>;
 427		mboxes = <&ipcc IPCC_CLIENT_MPSS
 428				IPCC_MPROC_SIGNAL_SMP2P>;
 429
 430		qcom,local-pid = <0>;
 431		qcom,remote-pid = <1>;
 432
 433		smp2p_modem_out: master-kernel {
 434			qcom,entry-name = "master-kernel";
 435			#qcom,smem-state-cells = <1>;
 436		};
 437
 438		smp2p_modem_in: slave-kernel {
 439			qcom,entry-name = "slave-kernel";
 440			interrupt-controller;
 441			#interrupt-cells = <2>;
 442		};
 443
 444		ipa_smp2p_out: ipa-ap-to-modem {
 445			qcom,entry-name = "ipa";
 446			#qcom,smem-state-cells = <1>;
 447		};
 448
 449		ipa_smp2p_in: ipa-modem-to-ap {
 450			qcom,entry-name = "ipa";
 451			interrupt-controller;
 452			#interrupt-cells = <2>;
 453		};
 454	};
 455
 456	smem: smem {
 457		compatible = "qcom,smem";
 458		memory-region = <&smem_mem>;
 459		hwlocks = <&tcsr_mutex 3>;
 460	};
 461
 462	soc: soc@0 {
 463		compatible = "simple-bus";
 464		#address-cells = <2>;
 465		#size-cells = <2>;
 466		ranges = <0 0 0 0 0x10 0>;
 467		dma-ranges = <0 0 0 0 0x10 0>;
 468
 469		gcc: clock-controller@80000 {
 470			compatible = "qcom,sdx75-gcc";
 471			reg = <0x0 0x0080000 0x0 0x1f7400>;
 472			clocks = <&rpmhcc RPMH_CXO_CLK>,
 473				 <&sleep_clk>,
 474				 <0>,
 475				 <0>,
 476				 <0>,
 477				 <0>,
 478				 <0>,
 479				 <0>,
 480				 <0>,
 481				 <0>,
 482				 <0>,
 483				 <0>,
 484				 <0>,
 485				 <0>,
 486				 <0>;
 487			#clock-cells = <1>;
 488			#reset-cells = <1>;
 489			#power-domain-cells = <1>;
 490		};
 491
 492		ipcc: mailbox@408000 {
 493			compatible = "qcom,sdx75-ipcc", "qcom,ipcc";
 494			reg = <0 0x00408000 0 0x1000>;
 495			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
 496			interrupt-controller;
 497			#interrupt-cells = <3>;
 498			#mbox-cells = <2>;
 499		};
 500
 501		gpi_dma: dma-controller@900000 {
 502			compatible = "qcom,sdx75-gpi-dma", "qcom,sm6350-gpi-dma";
 503			reg = <0x0 0x00900000 0x0 0x60000>;
 504			#dma-cells = <3>;
 505			interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
 506				     <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>,
 507				     <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>,
 508				     <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
 509				     <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>,
 510				     <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
 511				     <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>,
 512				     <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>,
 513				     <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>,
 514				     <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
 515				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
 516				     <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
 517			dma-channels = <12>;
 518			dma-channel-mask = <0x7f>;
 519			iommus = <&apps_smmu 0xf6 0x0>;
 520			status = "disabled";
 521		};
 522
 523		qupv3_id_0: geniqup@9c0000 {
 524			compatible = "qcom,geni-se-qup";
 525			reg = <0x0 0x009c0000 0x0 0x2000>;
 526			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 527				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 528			clock-names = "m-ahb",
 529				      "s-ahb";
 530			iommus = <&apps_smmu 0xe3 0x0>;
 531			interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 532					 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>;
 533			interconnect-names = "qup-core";
 534			#address-cells = <2>;
 535			#size-cells = <2>;
 536			ranges;
 537			status = "disabled";
 538
 539			i2c0: i2c@980000 {
 540				compatible = "qcom,geni-i2c";
 541				reg = <0x0 0x00980000 0x0 0x4000>;
 542				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 543				clock-names = "se";
 544				interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
 545				#address-cells = <1>;
 546				#size-cells = <0>;
 547				pinctrl-0 = <&qup_i2c0_data_clk>;
 548				pinctrl-names = "default";
 549				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 550						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 551						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 552						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 553						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 554						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 555				interconnect-names = "qup-core", "qup-config", "qup-memory";
 556				dmas = <&gpi_dma 0 0 QCOM_GPI_I2C>,
 557				       <&gpi_dma 1 0 QCOM_GPI_I2C>;
 558				dma-names = "tx", "rx";
 559				status = "disabled";
 560			};
 561
 562			spi0: spi@980000 {
 563				compatible = "qcom,geni-spi";
 564				reg = <0x0 0x00980000 0x0 0x4000>;
 565				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 566				clock-names = "se";
 567				interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>;
 568				#address-cells = <1>;
 569				#size-cells = <0>;
 570				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
 571				pinctrl-names = "default";
 572				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 573						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 574						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 575						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 576						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 577						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 578				interconnect-names = "qup-core", "qup-config", "qup-memory";
 579				dmas = <&gpi_dma 0 0 QCOM_GPI_SPI>,
 580				       <&gpi_dma 1 0 QCOM_GPI_SPI>;
 581				dma-names = "tx", "rx";
 582				status = "disabled";
 583			};
 584
 585			uart1: serial@984000 {
 586				compatible = "qcom,geni-debug-uart";
 587				reg = <0x0 0x00984000 0x0 0x4000>;
 588				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 589				clock-names = "se";
 590				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 591						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 592						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 593						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
 594				interconnect-names = "qup-core",
 595						     "qup-config";
 596				interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
 597				pinctrl-0 = <&qupv3_se1_2uart_active>;
 598				pinctrl-1 = <&qupv3_se1_2uart_sleep>;
 599				pinctrl-names = "default",
 600						"sleep";
 601				status = "disabled";
 602			};
 603
 604			i2c2: i2c@988000 {
 605				compatible = "qcom,geni-i2c";
 606				reg = <0x0 0x00988000 0x0 0x4000>;
 607				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 608				clock-names = "se";
 609				interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 610				#address-cells = <1>;
 611				#size-cells = <0>;
 612				pinctrl-0 = <&qup_i2c2_data_clk>;
 613				pinctrl-names = "default";
 614				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 615						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 616						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 617						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 618						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 619						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 620				interconnect-names = "qup-core", "qup-config", "qup-memory";
 621				dmas = <&gpi_dma 0 2 QCOM_GPI_I2C>,
 622				       <&gpi_dma 1 2 QCOM_GPI_I2C>;
 623				dma-names = "tx", "rx";
 624				status = "disabled";
 625			};
 626
 627			spi2: spi@988000 {
 628				compatible = "qcom,geni-spi";
 629				reg = <0x0 0x00988000 0x0 0x4000>;
 630				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 631				clock-names = "se";
 632				interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
 633				#address-cells = <1>;
 634				#size-cells = <0>;
 635				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
 636				pinctrl-names = "default";
 637				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 638						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 639						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 640						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 641						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 642						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 643				interconnect-names = "qup-core", "qup-config", "qup-memory";
 644				dmas = <&gpi_dma 0 2 QCOM_GPI_SPI>,
 645				       <&gpi_dma 1 2 QCOM_GPI_SPI>;
 646				dma-names = "tx", "rx";
 647				status = "disabled";
 648			};
 649
 650			i2c3: i2c@98c000 {
 651				compatible = "qcom,geni-i2c";
 652				reg = <0x0 0x0098c000 0x0 0x4000>;
 653				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 654				clock-names = "se";
 655				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 656				#address-cells = <1>;
 657				#size-cells = <0>;
 658				pinctrl-0 = <&qup_i2c3_data_clk>;
 659				pinctrl-names = "default";
 660				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 661						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 662						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 663						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 664						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 665						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 666				interconnect-names = "qup-core", "qup-config", "qup-memory";
 667				dmas = <&gpi_dma 0 3 QCOM_GPI_I2C>,
 668				       <&gpi_dma 1 3 QCOM_GPI_I2C>;
 669				dma-names = "tx", "rx";
 670				status = "disabled";
 671			};
 672
 673			spi3: spi@98c000 {
 674				compatible = "qcom,geni-spi";
 675				reg = <0x0 0x0098c000 0x0 0x4000>;
 676				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 677				clock-names = "se";
 678				interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
 679				#address-cells = <1>;
 680				#size-cells = <0>;
 681				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
 682				pinctrl-names = "default";
 683				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 684						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 685						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 686						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 687						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 688						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 689				interconnect-names = "qup-core", "qup-config", "qup-memory";
 690				dmas = <&gpi_dma 0 3 QCOM_GPI_SPI>,
 691				       <&gpi_dma 1 3 QCOM_GPI_SPI>;
 692				dma-names = "tx", "rx";
 693				status = "disabled";
 694			};
 695
 696			uart4: serial@990000 {
 697				compatible = "qcom,geni-uart";
 698				reg = <0x0 0x00990000 0x0 0x4000>;
 699				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 700				clock-names = "se";
 701				interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
 702				pinctrl-0 = <&qup_uart4_default>, <&qup_uart4_cts_rts>;
 703				pinctrl-names = "default";
 704				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 705						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 706						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 707						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>;
 708				interconnect-names = "qup-core", "qup-config";
 709				status = "disabled";
 710			};
 711
 712			i2c5: i2c@994000 {
 713				compatible = "qcom,geni-i2c";
 714				reg = <0x0 0x00994000 0x0 0x4000>;
 715				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 716				clock-names = "se";
 717				interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
 718				#address-cells = <1>;
 719				#size-cells = <0>;
 720				pinctrl-0 = <&qup_i2c5_data_clk>;
 721				pinctrl-names = "default";
 722				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 723						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 724						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 725						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 726						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 727						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 728				interconnect-names = "qup-core", "qup-config", "qup-memory";
 729				dmas = <&gpi_dma 0 5 QCOM_GPI_I2C>,
 730				       <&gpi_dma 1 5 QCOM_GPI_I2C>;
 731				dma-names = "tx", "rx";
 732				status = "disabled";
 733			};
 734
 735			i2c6: i2c@998000 {
 736				compatible = "qcom,geni-i2c";
 737				reg = <0x0 0x00998000 0x0 0x4000>;
 738				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 739				clock-names = "se";
 740				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
 741				#address-cells = <1>;
 742				#size-cells = <0>;
 743				pinctrl-0 = <&qup_i2c6_data_clk>;
 744				pinctrl-names = "default";
 745				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 746						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 747						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 748						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 749						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 750						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 751				interconnect-names = "qup-core", "qup-config", "qup-memory";
 752				dmas = <&gpi_dma 0 6 QCOM_GPI_I2C>,
 753				       <&gpi_dma 1 6 QCOM_GPI_I2C>;
 754				dma-names = "tx", "rx";
 755				status = "disabled";
 756			};
 757
 758			spi6: spi@998000 {
 759				compatible = "qcom,geni-spi";
 760				reg = <0x0 0x00998000 0x0 0x4000>;
 761				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
 762				clock-names = "se";
 763				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
 764				#address-cells = <1>;
 765				#size-cells = <0>;
 766				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
 767				pinctrl-names = "default";
 768				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 769						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 770						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 771						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 772						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 773						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 774				interconnect-names = "qup-core", "qup-config", "qup-memory";
 775				dmas = <&gpi_dma 0 6 QCOM_GPI_SPI>,
 776				       <&gpi_dma 1 6 QCOM_GPI_SPI>;
 777				dma-names = "tx", "rx";
 778				status = "disabled";
 779			};
 780
 781			i2c7: i2c@99c000 {
 782				compatible = "qcom,geni-i2c";
 783				reg = <0x0 0x0099c000 0x0 0x4000>;
 784				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 785				clock-names = "se";
 786				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 787				#address-cells = <1>;
 788				#size-cells = <0>;
 789				pinctrl-0 = <&qup_i2c7_data_clk>;
 790				pinctrl-names = "default";
 791				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 792						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 793						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 794						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 795						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 796						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 797				interconnect-names = "qup-core", "qup-config", "qup-memory";
 798				dmas = <&gpi_dma 0 7 QCOM_GPI_I2C>,
 799				       <&gpi_dma 1 7 QCOM_GPI_I2C>;
 800				dma-names = "tx", "rx";
 801				status = "disabled";
 802			};
 803
 804			spi7: spi@99c000 {
 805				compatible = "qcom,geni-spi";
 806				reg = <0x0 0x0099c000 0x0 0x4000>;
 807				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
 808				clock-names = "se";
 809				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
 810				#address-cells = <1>;
 811				#size-cells = <0>;
 812				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
 813				pinctrl-names = "default";
 814				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
 815						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
 816						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
 817						 &system_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
 818						<&system_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
 819						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 820				interconnect-names = "qup-core", "qup-config", "qup-memory";
 821				dmas = <&gpi_dma 0 7 QCOM_GPI_SPI>,
 822				       <&gpi_dma 1 7 QCOM_GPI_SPI>;
 823				dma-names = "tx", "rx";
 824				status = "disabled";
 825			};
 826		};
 827
 828		usb_hsphy: phy@ff4000 {
 829			compatible = "qcom,sdx75-snps-eusb2-phy", "qcom,sm8550-snps-eusb2-phy";
 830			reg = <0x0 0x00ff4000 0x0 0x154>;
 831			#phy-cells = <0>;
 832
 833			clocks = <&rpmhcc RPMH_CXO_CLK>;
 834			clock-names = "ref";
 835
 836			resets = <&gcc GCC_QUSB2PHY_BCR>;
 837
 838			status = "disabled";
 839		};
 840
 841		usb_qmpphy: phy@ff6000 {
 842			compatible = "qcom,sdx75-qmp-usb3-uni-phy";
 843			reg = <0x0 0x00ff6000 0x0 0x2000>;
 844
 845			clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
 846				 <&gcc GCC_USB2_CLKREF_EN>,
 847				 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 848				 <&gcc GCC_USB3_PHY_PIPE_CLK>;
 849			clock-names = "aux",
 850				      "ref",
 851				      "cfg_ahb",
 852				      "pipe";
 853
 854			power-domains = <&gcc GCC_USB3_PHY_GDSC>;
 855
 856			resets = <&gcc GCC_USB3_PHY_BCR>,
 857				 <&gcc GCC_USB3PHY_PHY_BCR>;
 858			reset-names = "phy",
 859				      "phy_phy";
 860
 861			#clock-cells = <0>;
 862			clock-output-names = "usb3_uni_phy_pipe_clk_src";
 863
 864			#phy-cells = <0>;
 865
 866			status = "disabled";
 867		};
 868
 869		system_noc: interconnect@1640000 {
 870			compatible = "qcom,sdx75-system-noc";
 871			reg = <0x0 0x01640000 0x0 0x4b400>;
 872			#interconnect-cells = <2>;
 873			qcom,bcm-voters = <&apps_bcm_voter>;
 874		};
 875
 876		pcie_anoc: interconnect@16c0000 {
 877			compatible = "qcom,sdx75-pcie-anoc";
 878			reg = <0x0 0x016c0000 0x0 0x14200>;
 879			#interconnect-cells = <2>;
 880			qcom,bcm-voters = <&apps_bcm_voter>;
 881		};
 882
 883		qpic_bam: dma-controller@1c9c000 {
 884			compatible = "qcom,bam-v1.7.0";
 885			reg = <0x0 0x01c9c000 0x0 0x1c000>;
 886			interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
 887			clocks = <&rpmhcc RPMH_QPIC_CLK>;
 888			clock-names = "bam_clk";
 889			#dma-cells = <1>;
 890			qcom,ee = <0>;
 891			qcom,controlled-remotely;
 892			iommus = <&apps_smmu 0x100 0x3>;
 893			dma-coherent;
 894			status = "disabled";
 895		};
 896
 897		qpic_nand: nand-controller@1cc8000 {
 898			compatible = "qcom,sdx75-nand", "qcom,sdx55-nand";
 899			reg = <0x0 0x01cc8000 0x0 0x10000>;
 900			#address-cells = <1>;
 901			#size-cells = <0>;
 902			clocks = <&rpmhcc RPMH_QPIC_CLK>,
 903				 <&sleep_clk>;
 904			clock-names = "core",
 905				      "aon";
 906			dmas = <&qpic_bam 0>,
 907			       <&qpic_bam 1>,
 908			       <&qpic_bam 2>;
 909			dma-names = "tx",
 910				    "rx",
 911				    "cmd";
 912			iommus = <&apps_smmu 0x100 0x3>;
 913			status = "disabled";
 914		};
 915
 916		tcsr_mutex: hwlock@1f40000 {
 917			compatible = "qcom,tcsr-mutex";
 918			reg = <0x0 0x01f40000 0x0 0x40000>;
 919			#hwlock-cells = <1>;
 920		};
 921
 922		tcsr: syscon@1fc0000 {
 923			compatible = "qcom,sdx75-tcsr", "syscon";
 924			reg = <0x0 0x01fc0000 0x0 0x30000>;
 925		};
 926
 927		remoteproc_mpss: remoteproc@4080000 {
 928			compatible = "qcom,sdx75-mpss-pas";
 929			reg = <0 0x04080000 0 0x10000>;
 930
 931			interrupts-extended = <&intc GIC_SPI 250 IRQ_TYPE_EDGE_RISING>,
 932					      <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>,
 933					      <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>,
 934					      <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>,
 935					      <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>,
 936					      <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>;
 937			interrupt-names = "wdog",
 938					  "fatal",
 939					  "ready",
 940					  "handover",
 941					  "stop-ack",
 942					  "shutdown-ack";
 943
 944			clocks = <&rpmhcc RPMH_CXO_CLK>;
 945			clock-names = "xo";
 946
 947			power-domains = <&rpmhpd RPMHPD_CX>,
 948					<&rpmhpd RPMHPD_MSS>;
 949			power-domain-names = "cx",
 950					     "mss";
 951
 952			memory-region = <&mpssadsp_mem>, <&q6_mpss_dtb_mem>,
 953					<&mpss_dsm_mem>, <&mpss_dsm_mem_2>,
 954					<&qlink_logging_mem>;
 955
 956			qcom,qmp = <&aoss_qmp>;
 957
 958			qcom,smem-states = <&smp2p_modem_out 0>;
 959			qcom,smem-state-names = "stop";
 960
 961			status = "disabled";
 962
 963			glink-edge {
 964				interrupts-extended = <&ipcc IPCC_CLIENT_MPSS
 965							     IPCC_MPROC_SIGNAL_PING
 966							     IRQ_TYPE_EDGE_RISING>;
 967				mboxes = <&ipcc IPCC_CLIENT_MPSS
 968						IPCC_MPROC_SIGNAL_PING>;
 969				label = "mpss";
 970				qcom,remote-pid = <1>;
 971			};
 972		};
 973
 974		sdhc: mmc@8804000 {
 975			compatible = "qcom,sdx75-sdhci", "qcom,sdhci-msm-v5";
 976			reg = <0x0 0x08804000 0x0 0x1000>;
 977
 978			interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
 979				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
 980			interrupt-names = "hc_irq",
 981					  "pwr_irq";
 982
 983			clocks = <&gcc GCC_SDCC1_AHB_CLK>,
 984				 <&gcc GCC_SDCC1_APPS_CLK>,
 985				 <&rpmhcc RPMH_CXO_CLK>;
 986			clock-names = "iface",
 987				      "core",
 988				      "xo";
 989			iommus = <&apps_smmu 0x00a0 0x0>;
 990			qcom,dll-config = <0x0007442c>;
 991			qcom,ddr-config = <0x80040868>;
 992			power-domains = <&rpmhpd RPMHPD_CX>;
 993			operating-points-v2 = <&sdhc1_opp_table>;
 994
 995			interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
 996					<&gem_noc MASTER_APPSS_PROC &system_noc SLAVE_SDCC_1>;
 997			interconnect-names = "sdhc-ddr",
 998					     "cpu-sdhc";
 999			bus-width = <4>;
1000			dma-coherent;
1001
1002			/* Forbid SDR104/SDR50 - broken hw! */
1003			sdhci-caps-mask = <0x3 0>;
1004
1005			status = "disabled";
1006
1007			sdhc1_opp_table: opp-table {
1008				compatible = "operating-points-v2";
1009
1010				opp-100000000 {
1011					opp-hz = /bits/ 64 <100000000>;
1012					required-opps = <&rpmhpd_opp_low_svs>;
1013				};
1014
1015				opp-384000000 {
1016					opp-hz = /bits/ 64 <384000000>;
1017					required-opps = <&rpmhpd_opp_nom>;
1018				};
1019			};
1020		};
1021
1022		usb: usb@a600000 {
1023			compatible = "qcom,sdx75-dwc3", "qcom,snps-dwc3";
1024			reg = <0x0 0x0a600000 0x0 0xfc100>;
1025
1026			clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
1027				 <&gcc GCC_USB30_MASTER_CLK>,
1028				 <&gcc GCC_USB30_MSTR_AXI_CLK>,
1029				 <&gcc GCC_USB30_SLEEP_CLK>,
1030				 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
1031			clock-names = "cfg_noc",
1032				      "core",
1033				      "iface",
1034				      "sleep",
1035				      "mock_utmi";
1036
1037			assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
1038					  <&gcc GCC_USB30_MASTER_CLK>;
1039			assigned-clock-rates = <19200000>, <200000000>;
1040
1041			interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
1042					      <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
1043					      <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
1044					      <&pdc 10 IRQ_TYPE_EDGE_RISING>,
1045					      <&pdc 9 IRQ_TYPE_EDGE_RISING>,
1046					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
1047			interrupt-names = "dwc_usb3",
1048					  "pwr_event",
1049					  "hs_phy_irq",
1050					  "dp_hs_phy_irq",
1051					  "dm_hs_phy_irq",
1052					  "ss_phy_irq";
1053
1054			iommus = <&apps_smmu 0x80 0x0>;
1055
1056			snps,dis_u2_susphy_quirk;
1057			snps,dis_enblslpm_quirk;
1058			snps,dis-u1-entry-quirk;
1059			snps,dis-u2-entry-quirk;
1060
1061			power-domains = <&gcc GCC_USB30_GDSC>;
1062
1063			resets = <&gcc GCC_USB30_BCR>;
1064
1065			phys = <&usb_hsphy>,
1066			       <&usb_qmpphy>;
1067			phy-names = "usb2-phy",
1068				    "usb3-phy";
1069
1070			interconnects = <&system_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS
1071					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
1072					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
1073					 &system_noc SLAVE_USB3 QCOM_ICC_TAG_ALWAYS>;
1074			interconnect-names = "usb-ddr",
1075					     "apps-usb";
1076
1077			usb-role-switch;
1078
1079			status = "disabled";
1080
1081			ports {
1082				#address-cells = <1>;
1083				#size-cells = <0>;
1084
1085				port@0 {
1086					reg = <0>;
1087
1088					usb_1_dwc3_hs: endpoint {
1089					};
1090				};
1091
1092				port@1 {
1093					reg = <1>;
1094
1095					usb_1_dwc3_ss: endpoint {
1096					};
1097				};
1098			};
1099		};
1100
1101		pdc: interrupt-controller@b220000 {
1102			compatible = "qcom,sdx75-pdc", "qcom,pdc";
1103			reg = <0x0 0xb220000 0x0 0x30000>,
1104			      <0x0 0x174000f0 0x0 0x64>;
1105			qcom,pdc-ranges = <0 147 52>,
1106					  <52 266 32>,
1107					  <84 500 59>;
1108			#interrupt-cells = <2>;
1109			interrupt-parent = <&intc>;
1110			interrupt-controller;
1111		};
1112
1113		aoss_qmp: power-management@c310000 {
1114			compatible = "qcom,sdx75-aoss-qmp", "qcom,aoss-qmp";
1115			reg = <0 0x0c310000 0 0x1000>;
1116			interrupt-parent = <&ipcc>;
1117			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
1118						     IRQ_TYPE_EDGE_RISING>;
1119			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
1120
1121			#clock-cells = <0>;
1122		};
1123
1124		spmi_bus: spmi@c400000 {
1125			compatible = "qcom,spmi-pmic-arb";
1126			reg = <0x0 0x0c400000 0x0 0x3000>,
1127			      <0x0 0x0c500000 0x0 0x400000>,
1128			      <0x0 0x0c440000 0x0 0x80000>,
1129			      <0x0 0x0c4c0000 0x0 0x10000>,
1130			      <0x0 0x0c42d000 0x0 0x4000>;
1131			reg-names = "core",
1132				    "chnls",
1133				    "obsrvr",
1134				    "intr",
1135				    "cnfg";
1136			interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
1137			interrupt-names = "periph_irq";
1138			qcom,ee = <0>;
1139			qcom,channel = <0>;
1140			qcom,bus-id = <0>;
1141			#address-cells = <2>;
1142			#size-cells = <0>;
1143			interrupt-controller;
1144			#interrupt-cells = <4>;
1145		};
1146
1147		tlmm: pinctrl@f000000 {
1148			compatible = "qcom,sdx75-tlmm";
1149			reg = <0x0 0x0f000000 0x0 0x400000>;
1150			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
1151			gpio-controller;
1152			#gpio-cells = <2>;
1153			gpio-ranges = <&tlmm 0 0 133>;
1154			interrupt-controller;
1155			#interrupt-cells = <2>;
1156			wakeup-parent = <&pdc>;
1157
1158			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
1159				/* SDA, SCL */
1160				pins = "gpio8", "gpio9";
1161				function = "qup_se0";
1162				drive-strength = <2>;
1163				bias-pull-up;
1164			};
1165
1166			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
1167				/* SDA, SCL */
1168				pins = "gpio14", "gpio15";
1169				function = "qup_se2";
1170				drive-strength = <2>;
1171				bias-pull-up;
1172			};
1173
1174			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
1175				/* SDA, SCL */
1176				pins = "gpio52", "gpio53";
1177				function = "qup_se3";
1178				drive-strength = <2>;
1179				bias-pull-up;
1180			};
1181
1182			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
1183				/* SDA, SCL */
1184				pins = "gpio110", "gpio111";
1185				function = "qup_se5";
1186				drive-strength = <2>;
1187				bias-pull-up;
1188			};
1189
1190			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
1191				/* SDA, SCL */
1192				pins = "gpio112", "gpio113";
1193				function = "qup_se6";
1194				drive-strength = <2>;
1195				bias-pull-up;
1196			};
1197
1198			qup_i2c7_data_clk: qup-i2c7-data-clk-state {
1199				/* SDA, SCL */
1200				pins = "gpio116", "gpio117";
1201				function = "qup_se7";
1202				drive-strength = <2>;
1203				bias-pull-up;
1204			};
1205
1206			qup_spi0_cs: qup-spi0-cs-state {
1207				pins = "gpio11";
1208				function = "qup_se0";
1209				drive-strength = <6>;
1210				bias-pull-down;
1211			};
1212
1213			qup_spi0_data_clk: qup-spi0-data-clk-state {
1214				/* MISO, MOSI, CLK */
1215				pins = "gpio8", "gpio9", "gpio10";
1216				function = "qup_se0";
1217				drive-strength = <6>;
1218				bias-pull-down;
1219			};
1220
1221			qup_spi2_cs: qup-spi2-cs-state {
1222				pins = "gpio17";
1223				function = "qup_se2";
1224				drive-strength = <6>;
1225				bias-pull-down;
1226			};
1227
1228			qup_spi2_data_clk: qup-spi2-data-clk-state {
1229				/* MISO, MOSI, CLK */
1230				pins = "gpio14", "gpio15", "gpio16";
1231				function = "qup_se2";
1232				drive-strength = <6>;
1233				bias-pull-down;
1234			};
1235
1236			qup_spi3_cs: qup-spi3-cs-state {
1237				pins = "gpio55";
1238				function = "qup_se3";
1239				drive-strength = <6>;
1240				bias-pull-down;
1241			};
1242
1243			qup_spi3_data_clk: qup-spi3-data-clk-state {
1244				/* MISO, MOSI, CLK */
1245				pins = "gpio52", "gpio53", "gpio54";
1246				function = "qup_se3";
1247				drive-strength = <6>;
1248				bias-pull-down;
1249			};
1250
1251			qup_spi6_cs: qup-spi6-cs-state {
1252				pins = "gpio115";
1253				function = "qup_se6";
1254				drive-strength = <6>;
1255				bias-pull-down;
1256			};
1257
1258			qup_spi6_data_clk: qup-spi6-data-clk-state {
1259				/* MISO, MOSI, CLK */
1260				pins = "gpio112", "gpio113", "gpio114";
1261				function = "qup_se6";
1262				drive-strength = <6>;
1263				bias-pull-down;
1264			};
1265
1266			qup_spi7_cs: qup-spi7-cs-state {
1267				pins = "gpio119";
1268				function = "qup_se7";
1269				drive-strength = <6>;
1270				bias-pull-down;
1271			};
1272
1273			qup_spi7_data_clk: qup-spi7-data-clk-state {
1274				/* MISO, MOSI, CLK */
1275				pins = "gpio116", "gpio117", "gpio118";
1276				function = "qup_se7";
1277				drive-strength = <6>;
1278				bias-pull-down;
1279			};
1280
1281			qup_uart4_cts_rts: qup-uart4-cts-rts-state {
1282				/* CTS, RTS */
1283				pins = "gpio52", "gpio53";
1284				function = "qup_se3";
1285				drive-strength = <2>;
1286				bias-pull-down;
1287			};
1288
1289			qup_uart4_default: qup-uart4-default-state {
1290				/* TX, RX */
1291				pins = "gpio54", "gpio55";
1292				function = "qup_se3";
1293				drive-strength = <2>;
1294				bias-pull-up;
1295			};
1296
1297			qupv3_se1_2uart_active: qupv3-se1-2uart-active-state {
1298				tx-pins {
1299					pins = "gpio12";
1300					function = "qup_se1_l2_mira";
1301					drive-strength = <2>;
1302					bias-disable;
1303				};
1304
1305				rx-pins {
1306					pins = "gpio13";
1307					function = "qup_se1_l3_mira";
1308					drive-strength = <2>;
1309					bias-disable;
1310				};
1311			};
1312
1313			qupv3_se1_2uart_sleep: qupv3-se1-2uart-sleep-state {
1314				pins = "gpio12", "gpio13";
1315				function = "gpio";
1316				drive-strength = <2>;
1317				bias-pull-down;
1318			};
1319
1320			sdc1_default: sdc1-default-state {
1321				clk-pins {
1322					pins = "sdc1_clk";
1323					drive-strength = <16>;
1324					bias-disable;
1325				};
1326
1327				cmd-pins {
1328					pins = "sdc1_cmd";
1329					drive-strength = <10>;
1330					bias-pull-up;
1331				};
1332
1333				data-pins {
1334					pins = "sdc1_data";
1335					drive-strength = <10>;
1336					bias-pull-up;
1337				};
1338			};
1339
1340			sdc1_sleep: sdc1-sleep-state {
1341				clk-pins {
1342					pins = "sdc1_clk";
1343					drive-strength = <2>;
1344					bias-disable;
1345				};
1346
1347				cmd-pins {
1348					pins = "sdc1_cmd";
1349					drive-strength = <2>;
1350					bias-pull-up;
1351				};
1352
1353				data-pins {
1354					pins = "sdc1_data";
1355					drive-strength = <2>;
1356					bias-pull-up;
1357				};
1358			};
1359		};
1360
1361		apps_smmu: iommu@15000000 {
1362			compatible = "qcom,sdx75-smmu-500", "qcom,smmu-500", "arm,mmu-500";
1363			reg = <0x0 0x15000000 0x0 0x40000>;
1364			#iommu-cells = <2>;
1365			#global-interrupts = <2>;
1366			dma-coherent;
1367			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
1368				     <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
1369				     <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
1370				     <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
1371				     <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
1372				     <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
1373				     <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
1374				     <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
1375				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1376				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
1377				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
1378				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
1379				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
1380				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1381				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1382				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
1383				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
1384				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
1385				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
1386				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
1387				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
1388				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
1389				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
1390				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
1391				     <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>,
1392				     <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>,
1393				     <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>,
1394				     <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>,
1395				     <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>,
1396				     <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
1397				     <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
1398				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
1399				     <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
1400		};
1401
1402		intc: interrupt-controller@17200000 {
1403			compatible = "arm,gic-v3";
1404			#interrupt-cells = <3>;
1405			interrupt-controller;
1406			#redistributor-regions = <1>;
1407			redistributor-stride = <0x0 0x20000>;
1408			reg = <0x0 0x17200000 0x0 0x10000>,
1409			      <0x0 0x17260000 0x0 0x80000>;
1410			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
1411		};
1412
1413		timer@17420000 {
1414			compatible = "arm,armv7-timer-mem";
1415			reg = <0x0 0x17420000 0x0 0x1000>;
1416			#address-cells = <1>;
1417			#size-cells = <1>;
1418			ranges = <0 0 0 0x20000000>;
1419
1420			frame@17421000 {
1421				reg = <0x17421000 0x1000>,
1422				      <0x17422000 0x1000>;
1423				frame-number = <0>;
1424				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
1425					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
1426			};
1427
1428			frame@17423000 {
1429				reg = <0x17423000 0x1000>;
1430				frame-number = <1>;
1431				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
1432				status = "disabled";
1433			};
1434
1435			frame@17425000 {
1436				reg = <0x17425000 0x1000>;
1437				frame-number = <2>;
1438				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
1439				status = "disabled";
1440			};
1441
1442			frame@17427000 {
1443				reg = <0x17427000 0x1000>;
1444				frame-number = <3>;
1445				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
1446				status = "disabled";
1447			};
1448
1449			frame@17429000 {
1450				reg = <0x17429000 0x1000>;
1451				frame-number = <4>;
1452				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
1453				status = "disabled";
1454			};
1455
1456			frame@1742b000 {
1457				reg = <0x1742b000 0x1000>;
1458				frame-number = <5>;
1459				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1460				status = "disabled";
1461			};
1462
1463			frame@1742d000 {
1464				reg = <0x1742d000 0x1000>;
1465				frame-number = <6>;
1466				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
1467				status = "disabled";
1468			};
1469		};
1470
1471		apps_rsc: rsc@17a00000 {
1472			label = "apps_rsc";
1473			compatible = "qcom,rpmh-rsc";
1474			reg = <0x0 0x17a00000 0x0 0x10000>,
1475			      <0x0 0x17a10000 0x0 0x10000>,
1476			      <0x0 0x17a20000 0x0 0x10000>;
1477			reg-names = "drv-0", "drv-1", "drv-2";
1478			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
1479				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
1480				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
1481
1482			power-domains = <&cluster_pd>;
1483			qcom,tcs-offset = <0xd00>;
1484			qcom,drv-id = <2>;
1485			qcom,tcs-config = <ACTIVE_TCS    3>,
1486					  <SLEEP_TCS     2>,
1487					  <WAKE_TCS      2>,
1488					  <CONTROL_TCS   0>;
1489
1490			apps_bcm_voter: bcm-voter {
1491				compatible = "qcom,bcm-voter";
1492			};
1493
1494			rpmhcc: clock-controller {
1495				compatible = "qcom,sdx75-rpmh-clk";
1496				clocks = <&xo_board>;
1497				clock-names = "xo";
1498				#clock-cells = <1>;
1499			};
1500
1501			rpmhpd: power-controller {
1502				compatible = "qcom,sdx75-rpmhpd";
1503				#power-domain-cells = <1>;
1504				operating-points-v2 = <&rpmhpd_opp_table>;
1505
1506				rpmhpd_opp_table: opp-table {
1507					compatible = "operating-points-v2";
1508
1509					rpmhpd_opp_ret: opp-16 {
1510						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
1511					};
1512
1513					rpmhpd_opp_min_svs: opp-48 {
1514						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
1515					};
1516
1517					rpmhpd_opp_low_svs: opp-64 {
1518						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
1519					};
1520
1521					rpmhpd_opp_svs: opp-128 {
1522						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
1523					};
1524
1525					rpmhpd_opp_svs_l1: opp-192 {
1526						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
1527					};
1528
1529					rpmhpd_opp_nom: opp-256 {
1530						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1531					};
1532
1533					rpmhpd_opp_nom_l1: opp-320 {
1534						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1535					};
1536
1537					rpmhpd_opp_nom_l2: opp-336 {
1538						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
1539					};
1540
1541					rpmhpd_opp_turbo: opp-384 {
1542						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1543					};
1544
1545					rpmhpd_opp_turbo_l1: opp-416 {
1546						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1547					};
1548				};
1549			};
1550		};
1551
1552		cpufreq_hw: cpufreq@17d91000 {
1553			compatible = "qcom,sdx75-cpufreq-epss", "qcom,cpufreq-epss";
1554			reg = <0x0 0x17d91000 0x0 0x1000>;
1555			reg-names = "freq-domain0";
1556			clocks = <&rpmhcc RPMH_CXO_CLK>,
1557				 <&gcc GPLL0>;
1558			clock-names = "xo",
1559				      "alternate";
1560			interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
1561			interrupt-names = "dcvsh-irq-0";
1562			#freq-domain-cells = <1>;
1563			#clock-cells = <1>;
1564		};
1565
1566		dc_noc: interconnect@190e0000 {
1567			compatible = "qcom,sdx75-dc-noc";
1568			reg = <0x0 0x190e0000 0x0 0x8200>;
1569			#interconnect-cells = <2>;
1570			qcom,bcm-voters = <&apps_bcm_voter>;
1571		};
1572
1573		gem_noc: interconnect@19100000 {
1574			compatible = "qcom,sdx75-gem-noc";
1575			reg = <0x0 0x19100000 0x0 0x34080>;
1576			#interconnect-cells = <2>;
1577			qcom,bcm-voters = <&apps_bcm_voter>;
1578		};
1579	};
1580
1581	timer {
1582		compatible = "arm,armv8-timer";
1583		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1584			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1585			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
1586			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
1587	};
1588};