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sdm670.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/sdm670.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM670 SoC device tree source, adapted from SDM845 SoC device tree 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 * Copyright (c) 2022, Richard Acayan. All rights reserved. 7 */ 8 9#include <dt-bindings/clock/qcom,camcc-sdm845.h> 10#include <dt-bindings/clock/qcom,dispcc-sdm845.h> 11#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 12#include <dt-bindings/clock/qcom,gcc-sdm845.h> 13#include <dt-bindings/clock/qcom,gpucc-sdm845.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/dma/qcom-gpi.h> 16#include <dt-bindings/gpio/gpio.h> 17#include <dt-bindings/interconnect/qcom,osm-l3.h> 18#include <dt-bindings/interconnect/qcom,sdm670-rpmh.h> 19#include <dt-bindings/interrupt-controller/arm-gic.h> 20#include <dt-bindings/phy/phy-qcom-qusb2.h> 21#include <dt-bindings/power/qcom-rpmpd.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 aliases { }; 31 32 chosen { }; 33 34 clocks { 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 }; 40 41 xo_board: xo-board { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <38400000>; 45 }; 46 }; 47 48 cpus { 49 #address-cells = <2>; 50 #size-cells = <0>; 51 52 cpu0: cpu@0 { 53 device_type = "cpu"; 54 compatible = "qcom,kryo360"; 55 reg = <0x0 0x0>; 56 enable-method = "psci"; 57 capacity-dmips-mhz = <610>; 58 dynamic-power-coefficient = <203>; 59 qcom,freq-domain = <&cpufreq_hw 0>; 60 operating-points-v2 = <&cpu0_opp_table>; 61 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 62 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 63 power-domains = <&cpu_pd0>; 64 power-domain-names = "psci"; 65 next-level-cache = <&l2_0>; 66 l2_0: l2-cache { 67 compatible = "cache"; 68 next-level-cache = <&l3_0>; 69 cache-level = <2>; 70 cache-unified; 71 l3_0: l3-cache { 72 compatible = "cache"; 73 cache-level = <3>; 74 cache-unified; 75 }; 76 }; 77 }; 78 79 cpu1: cpu@100 { 80 device_type = "cpu"; 81 compatible = "qcom,kryo360"; 82 reg = <0x0 0x100>; 83 enable-method = "psci"; 84 capacity-dmips-mhz = <610>; 85 dynamic-power-coefficient = <203>; 86 qcom,freq-domain = <&cpufreq_hw 0>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 89 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 90 power-domains = <&cpu_pd1>; 91 power-domain-names = "psci"; 92 next-level-cache = <&l2_100>; 93 l2_100: l2-cache { 94 compatible = "cache"; 95 cache-level = <2>; 96 cache-unified; 97 next-level-cache = <&l3_0>; 98 }; 99 }; 100 101 cpu2: cpu@200 { 102 device_type = "cpu"; 103 compatible = "qcom,kryo360"; 104 reg = <0x0 0x200>; 105 enable-method = "psci"; 106 capacity-dmips-mhz = <610>; 107 dynamic-power-coefficient = <203>; 108 qcom,freq-domain = <&cpufreq_hw 0>; 109 operating-points-v2 = <&cpu0_opp_table>; 110 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 111 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 112 power-domains = <&cpu_pd2>; 113 power-domain-names = "psci"; 114 next-level-cache = <&l2_200>; 115 l2_200: l2-cache { 116 compatible = "cache"; 117 cache-level = <2>; 118 cache-unified; 119 next-level-cache = <&l3_0>; 120 }; 121 }; 122 123 cpu3: cpu@300 { 124 device_type = "cpu"; 125 compatible = "qcom,kryo360"; 126 reg = <0x0 0x300>; 127 enable-method = "psci"; 128 capacity-dmips-mhz = <610>; 129 dynamic-power-coefficient = <203>; 130 qcom,freq-domain = <&cpufreq_hw 0>; 131 operating-points-v2 = <&cpu0_opp_table>; 132 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 133 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 134 power-domains = <&cpu_pd3>; 135 power-domain-names = "psci"; 136 next-level-cache = <&l2_300>; 137 l2_300: l2-cache { 138 compatible = "cache"; 139 cache-level = <2>; 140 cache-unified; 141 next-level-cache = <&l3_0>; 142 }; 143 }; 144 145 cpu4: cpu@400 { 146 device_type = "cpu"; 147 compatible = "qcom,kryo360"; 148 reg = <0x0 0x400>; 149 enable-method = "psci"; 150 capacity-dmips-mhz = <610>; 151 dynamic-power-coefficient = <203>; 152 qcom,freq-domain = <&cpufreq_hw 0>; 153 operating-points-v2 = <&cpu0_opp_table>; 154 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 155 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 156 power-domains = <&cpu_pd4>; 157 power-domain-names = "psci"; 158 next-level-cache = <&l2_400>; 159 l2_400: l2-cache { 160 compatible = "cache"; 161 cache-level = <2>; 162 cache-unified; 163 next-level-cache = <&l3_0>; 164 }; 165 }; 166 167 cpu5: cpu@500 { 168 device_type = "cpu"; 169 compatible = "qcom,kryo360"; 170 reg = <0x0 0x500>; 171 enable-method = "psci"; 172 capacity-dmips-mhz = <610>; 173 dynamic-power-coefficient = <203>; 174 qcom,freq-domain = <&cpufreq_hw 0>; 175 operating-points-v2 = <&cpu0_opp_table>; 176 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 177 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 178 power-domains = <&cpu_pd5>; 179 power-domain-names = "psci"; 180 next-level-cache = <&l2_500>; 181 l2_500: l2-cache { 182 compatible = "cache"; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&l3_0>; 186 }; 187 }; 188 189 cpu6: cpu@600 { 190 device_type = "cpu"; 191 compatible = "qcom,kryo360"; 192 reg = <0x0 0x600>; 193 enable-method = "psci"; 194 capacity-dmips-mhz = <1024>; 195 dynamic-power-coefficient = <393>; 196 qcom,freq-domain = <&cpufreq_hw 1>; 197 operating-points-v2 = <&cpu6_opp_table>; 198 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 199 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 200 power-domains = <&cpu_pd6>; 201 power-domain-names = "psci"; 202 next-level-cache = <&l2_600>; 203 l2_600: l2-cache { 204 compatible = "cache"; 205 cache-level = <2>; 206 cache-unified; 207 next-level-cache = <&l3_0>; 208 }; 209 }; 210 211 cpu7: cpu@700 { 212 device_type = "cpu"; 213 compatible = "qcom,kryo360"; 214 reg = <0x0 0x700>; 215 enable-method = "psci"; 216 capacity-dmips-mhz = <1024>; 217 dynamic-power-coefficient = <393>; 218 qcom,freq-domain = <&cpufreq_hw 1>; 219 operating-points-v2 = <&cpu6_opp_table>; 220 interconnects = <&gladiator_noc MASTER_AMPSS_M0 3 &mem_noc SLAVE_EBI_CH0 3>, 221 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>; 222 power-domains = <&cpu_pd7>; 223 power-domain-names = "psci"; 224 next-level-cache = <&l2_700>; 225 l2_700: l2-cache { 226 compatible = "cache"; 227 cache-level = <2>; 228 cache-unified; 229 next-level-cache = <&l3_0>; 230 }; 231 }; 232 233 cpu-map { 234 cluster0 { 235 core0 { 236 cpu = <&cpu0>; 237 }; 238 239 core1 { 240 cpu = <&cpu1>; 241 }; 242 243 core2 { 244 cpu = <&cpu2>; 245 }; 246 247 core3 { 248 cpu = <&cpu3>; 249 }; 250 251 core4 { 252 cpu = <&cpu4>; 253 }; 254 255 core5 { 256 cpu = <&cpu5>; 257 }; 258 259 core6 { 260 cpu = <&cpu6>; 261 }; 262 263 core7 { 264 cpu = <&cpu7>; 265 }; 266 }; 267 }; 268 269 idle-states { 270 entry-method = "psci"; 271 272 little_cpu_sleep_0: cpu-sleep-0-0 { 273 compatible = "arm,idle-state"; 274 idle-state-name = "little-rail-power-collapse"; 275 arm,psci-suspend-param = <0x40000004>; 276 entry-latency-us = <702>; 277 exit-latency-us = <915>; 278 min-residency-us = <1617>; 279 local-timer-stop; 280 }; 281 282 big_cpu_sleep_0: cpu-sleep-1-0 { 283 compatible = "arm,idle-state"; 284 idle-state-name = "big-rail-power-collapse"; 285 arm,psci-suspend-param = <0x40000004>; 286 entry-latency-us = <526>; 287 exit-latency-us = <1854>; 288 min-residency-us = <2380>; 289 local-timer-stop; 290 }; 291 }; 292 293 domain-idle-states { 294 cluster_sleep_0: cluster-sleep-0 { 295 compatible = "domain-idle-state"; 296 arm,psci-suspend-param = <0x4100c244>; 297 entry-latency-us = <3263>; 298 exit-latency-us = <6562>; 299 min-residency-us = <9825>; 300 }; 301 }; 302 }; 303 304 firmware { 305 scm { 306 compatible = "qcom,scm-sdm670", "qcom,scm"; 307 }; 308 }; 309 310 memory@80000000 { 311 device_type = "memory"; 312 /* We expect the bootloader to fill in the size */ 313 reg = <0x0 0x80000000 0x0 0x0>; 314 }; 315 316 cpu0_opp_table: opp-table-cpu0 { 317 compatible = "operating-points-v2"; 318 opp-shared; 319 320 cpu0_opp1: opp-300000000 { 321 opp-hz = /bits/ 64 <300000000>; 322 opp-peak-kBps = <400000 4800000>; 323 }; 324 325 cpu0_opp2: opp-576000000 { 326 opp-hz = /bits/ 64 <576000000>; 327 opp-peak-kBps = <400000 4800000>; 328 }; 329 330 cpu0_opp3: opp-748800000 { 331 opp-hz = /bits/ 64 <748800000>; 332 opp-peak-kBps = <1200000 4800000>; 333 }; 334 335 cpu0_opp4: opp-998400000 { 336 opp-hz = /bits/ 64 <998400000>; 337 opp-peak-kBps = <1804000 8908800>; 338 }; 339 340 cpu0_opp5: opp-1209600000 { 341 opp-hz = /bits/ 64 <1209600000>; 342 opp-peak-kBps = <2188000 8908800>; 343 }; 344 345 cpu0_opp6: opp-1324800000 { 346 opp-hz = /bits/ 64 <1324800000>; 347 opp-peak-kBps = <2188000 13516800>; 348 }; 349 350 cpu0_opp7: opp-1516800000 { 351 opp-hz = /bits/ 64 <1516800000>; 352 opp-peak-kBps = <3072000 15052800>; 353 }; 354 355 cpu0_opp8: opp-1612800000 { 356 opp-hz = /bits/ 64 <1612800000>; 357 opp-peak-kBps = <3072000 22118400>; 358 }; 359 360 cpu0_opp9: opp-1708800000 { 361 opp-hz = /bits/ 64 <1708800000>; 362 opp-peak-kBps = <4068000 23040000>; 363 }; 364 }; 365 366 cpu6_opp_table: opp-table-cpu6 { 367 compatible = "operating-points-v2"; 368 opp-shared; 369 370 cpu6_opp1: opp-300000000 { 371 opp-hz = /bits/ 64 <300000000>; 372 opp-peak-kBps = <400000 4800000>; 373 }; 374 375 cpu6_opp2: opp-652800000 { 376 opp-hz = /bits/ 64 <652800000>; 377 opp-peak-kBps = <400000 4800000>; 378 }; 379 380 cpu6_opp3: opp-825600000 { 381 opp-hz = /bits/ 64 <825600000>; 382 opp-peak-kBps = <1200000 4800000>; 383 }; 384 385 cpu6_opp4: opp-979200000 { 386 opp-hz = /bits/ 64 <979200000>; 387 opp-peak-kBps = <1200000 4800000>; 388 }; 389 390 cpu6_opp5: opp-1132800000 { 391 opp-hz = /bits/ 64 <1132800000>; 392 opp-peak-kBps = <2188000 8908800>; 393 }; 394 395 cpu6_opp6: opp-1363200000 { 396 opp-hz = /bits/ 64 <1363200000>; 397 opp-peak-kBps = <4068000 12902400>; 398 }; 399 400 cpu6_opp7: opp-1536000000 { 401 opp-hz = /bits/ 64 <1536000000>; 402 opp-peak-kBps = <4068000 12902400>; 403 }; 404 405 cpu6_opp8: opp-1747200000 { 406 opp-hz = /bits/ 64 <1747200000>; 407 opp-peak-kBps = <4068000 15052800>; 408 }; 409 410 cpu6_opp9: opp-1843200000 { 411 opp-hz = /bits/ 64 <1843200000>; 412 opp-peak-kBps = <4068000 15052800>; 413 }; 414 415 cpu6_opp10: opp-1996800000 { 416 opp-hz = /bits/ 64 <1996800000>; 417 opp-peak-kBps = <6220000 19046400>; 418 }; 419 }; 420 421 dsi_opp_table: opp-table-dsi { 422 compatible = "operating-points-v2"; 423 424 opp-19200000 { 425 opp-hz = /bits/ 64 <19200000>; 426 required-opps = <&rpmhpd_opp_min_svs>; 427 }; 428 429 opp-180000000 { 430 opp-hz = /bits/ 64 <180000000>; 431 required-opps = <&rpmhpd_opp_low_svs>; 432 }; 433 434 opp-275000000 { 435 opp-hz = /bits/ 64 <275000000>; 436 required-opps = <&rpmhpd_opp_svs>; 437 }; 438 439 opp-358000000 { 440 opp-hz = /bits/ 64 <358000000>; 441 required-opps = <&rpmhpd_opp_svs_l1>; 442 }; 443 }; 444 445 psci { 446 compatible = "arm,psci-1.0"; 447 method = "smc"; 448 449 cpu_pd0: power-domain-cpu0 { 450 #power-domain-cells = <0>; 451 power-domains = <&cluster_pd>; 452 domain-idle-states = <&little_cpu_sleep_0>; 453 }; 454 455 cpu_pd1: power-domain-cpu1 { 456 #power-domain-cells = <0>; 457 power-domains = <&cluster_pd>; 458 domain-idle-states = <&little_cpu_sleep_0>; 459 }; 460 461 cpu_pd2: power-domain-cpu2 { 462 #power-domain-cells = <0>; 463 power-domains = <&cluster_pd>; 464 domain-idle-states = <&little_cpu_sleep_0>; 465 }; 466 467 cpu_pd3: power-domain-cpu3 { 468 #power-domain-cells = <0>; 469 power-domains = <&cluster_pd>; 470 domain-idle-states = <&little_cpu_sleep_0>; 471 }; 472 473 cpu_pd4: power-domain-cpu4 { 474 #power-domain-cells = <0>; 475 power-domains = <&cluster_pd>; 476 domain-idle-states = <&little_cpu_sleep_0>; 477 }; 478 479 cpu_pd5: power-domain-cpu5 { 480 #power-domain-cells = <0>; 481 power-domains = <&cluster_pd>; 482 domain-idle-states = <&little_cpu_sleep_0>; 483 }; 484 485 cpu_pd6: power-domain-cpu6 { 486 #power-domain-cells = <0>; 487 power-domains = <&cluster_pd>; 488 domain-idle-states = <&big_cpu_sleep_0>; 489 }; 490 491 cpu_pd7: power-domain-cpu7 { 492 #power-domain-cells = <0>; 493 power-domains = <&cluster_pd>; 494 domain-idle-states = <&big_cpu_sleep_0>; 495 }; 496 497 cluster_pd: power-domain-cluster { 498 #power-domain-cells = <0>; 499 domain-idle-states = <&cluster_sleep_0>; 500 }; 501 }; 502 503 reserved-memory { 504 #address-cells = <2>; 505 #size-cells = <2>; 506 ranges; 507 508 hyp_mem: hyp-mem@85700000 { 509 reg = <0 0x85700000 0 0x600000>; 510 no-map; 511 }; 512 513 xbl_mem: xbl-mem@85e00000 { 514 reg = <0 0x85e00000 0 0x100000>; 515 no-map; 516 }; 517 518 aop_mem: aop-mem@85fc0000 { 519 reg = <0 0x85fc0000 0 0x20000>; 520 no-map; 521 }; 522 523 aop_cmd_db_mem: aop-cmd-db-mem@85fe0000 { 524 compatible = "qcom,cmd-db"; 525 reg = <0 0x85fe0000 0 0x20000>; 526 no-map; 527 }; 528 529 smem@86000000 { 530 compatible = "qcom,smem"; 531 reg = <0 0x86000000 0 0x200000>; 532 no-map; 533 hwlocks = <&tcsr_mutex 3>; 534 }; 535 536 tz_mem: tz@86200000 { 537 reg = <0 0x86200000 0 0x2d00000>; 538 no-map; 539 }; 540 541 camera_mem: camera-mem@8ab00000 { 542 reg = <0 0x8ab00000 0 0x500000>; 543 no-map; 544 }; 545 546 mpss_region: mpss@8b000000 { 547 reg = <0 0x8b000000 0 0x7e00000>; 548 no-map; 549 }; 550 551 venus_mem: venus@92e00000 { 552 reg = <0 0x92e00000 0 0x500000>; 553 no-map; 554 }; 555 556 wlan_msa_mem: wlan-msa@93300000 { 557 reg = <0 0x93300000 0 0x100000>; 558 no-map; 559 }; 560 561 cdsp_mem: cdsp@93400000 { 562 reg = <0 0x93400000 0 0x800000>; 563 no-map; 564 }; 565 566 mba_region: mba@93c00000 { 567 reg = <0 0x93c00000 0 0x200000>; 568 no-map; 569 }; 570 571 adsp_mem: adsp@93e00000 { 572 reg = <0 0x93e00000 0 0x1e00000>; 573 no-map; 574 }; 575 576 ipa_fw_mem: ipa-fw@95c00000 { 577 reg = <0 0x95c00000 0 0x10000>; 578 no-map; 579 }; 580 581 ipa_gsi_mem: ipa-gsi@95c10000 { 582 reg = <0 0x95c10000 0 0x5000>; 583 no-map; 584 }; 585 586 gpu_mem: gpu@95c15000 { 587 reg = <0 0x95c15000 0 0x2000>; 588 no-map; 589 }; 590 591 spss_mem: spss@97b00000 { 592 reg = <0 0x97b00000 0 0x100000>; 593 no-map; 594 }; 595 596 qseecom_mem: qseecom@9e400000 { 597 reg = <0 0x9e400000 0 0x1400000>; 598 no-map; 599 }; 600 }; 601 602 timer { 603 compatible = "arm,armv8-timer"; 604 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 605 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 606 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 607 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 608 }; 609 610 soc: soc@0 { 611 #address-cells = <2>; 612 #size-cells = <2>; 613 ranges = <0 0 0 0 0x10 0>; 614 dma-ranges = <0 0 0 0 0x10 0>; 615 compatible = "simple-bus"; 616 617 gcc: clock-controller@100000 { 618 compatible = "qcom,gcc-sdm670"; 619 reg = <0 0x00100000 0 0x1f0000>; 620 clocks = <&rpmhcc RPMH_CXO_CLK>, 621 <&rpmhcc RPMH_CXO_CLK_A>, 622 <&sleep_clk>; 623 clock-names = "bi_tcxo", 624 "bi_tcxo_ao", 625 "sleep_clk"; 626 #clock-cells = <1>; 627 #reset-cells = <1>; 628 #power-domain-cells = <1>; 629 }; 630 631 qfprom: qfprom@784000 { 632 compatible = "qcom,sdm670-qfprom", "qcom,qfprom"; 633 reg = <0 0x00784000 0 0x1000>; 634 #address-cells = <1>; 635 #size-cells = <1>; 636 637 gpu_speed_bin: gpu_speed_bin@1a2 { 638 reg = <0x1a2 0x2>; 639 bits = <5 8>; 640 }; 641 642 qusb2_hstx_trim: hstx-trim@1eb { 643 reg = <0x1eb 0x1>; 644 bits = <1 4>; 645 }; 646 }; 647 648 sdhc_1: mmc@7c4000 { 649 compatible = "qcom,sdm670-sdhci", "qcom,sdhci-msm-v5"; 650 reg = <0 0x007c4000 0 0x1000>, 651 <0 0x007c5000 0 0x1000>, 652 <0 0x007c8000 0 0x8000>; 653 reg-names = "hc", "cqhci", "ice"; 654 655 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>; 657 interrupt-names = "hc_irq", "pwr_irq"; 658 659 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 660 <&gcc GCC_SDCC1_APPS_CLK>, 661 <&rpmhcc RPMH_CXO_CLK>, 662 <&gcc GCC_SDCC1_ICE_CORE_CLK>, 663 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>; 664 clock-names = "iface", "core", "xo", "ice", "bus"; 665 interconnects = <&aggre1_noc MASTER_EMMC 0 &aggre1_noc SLAVE_A1NOC_SNOC 0>, 666 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_EMMC_CFG 0>; 667 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 668 operating-points-v2 = <&sdhc1_opp_table>; 669 670 iommus = <&apps_smmu 0x140 0xf>; 671 672 pinctrl-names = "default", "sleep"; 673 pinctrl-0 = <&sdc1_state_on>; 674 pinctrl-1 = <&sdc1_state_off>; 675 power-domains = <&rpmhpd SDM670_CX>; 676 677 bus-width = <8>; 678 non-removable; 679 680 status = "disabled"; 681 682 sdhc1_opp_table: opp-table { 683 compatible = "operating-points-v2"; 684 685 opp-20000000 { 686 opp-hz = /bits/ 64 <20000000>; 687 required-opps = <&rpmhpd_opp_min_svs>; 688 opp-peak-kBps = <80000 80000>; 689 opp-avg-kBps = <52286 80000>; 690 }; 691 692 opp-50000000 { 693 opp-hz = /bits/ 64 <50000000>; 694 required-opps = <&rpmhpd_opp_low_svs>; 695 opp-peak-kBps = <200000 100000>; 696 opp-avg-kBps = <130718 100000>; 697 }; 698 699 opp-100000000 { 700 opp-hz = /bits/ 64 <100000000>; 701 required-opps = <&rpmhpd_opp_svs>; 702 opp-peak-kBps = <200000 130000>; 703 opp-avg-kBps = <130718 130000>; 704 }; 705 706 opp-384000000 { 707 opp-hz = /bits/ 64 <384000000>; 708 required-opps = <&rpmhpd_opp_nom>; 709 opp-peak-kBps = <4096000 4096000>; 710 opp-avg-kBps = <1338562 1338562>; 711 }; 712 }; 713 }; 714 715 gpi_dma0: dma-controller@800000 { 716 #dma-cells = <3>; 717 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 718 reg = <0 0x00800000 0 0x60000>; 719 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 732 dma-channels = <13>; 733 dma-channel-mask = <0xfa>; 734 iommus = <&apps_smmu 0x16 0x0>; 735 status = "disabled"; 736 }; 737 738 qupv3_id_0: geniqup@8c0000 { 739 compatible = "qcom,geni-se-qup"; 740 reg = <0 0x008c0000 0 0x6000>; 741 clock-names = "m-ahb", "s-ahb"; 742 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 743 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 744 iommus = <&apps_smmu 0x3 0x0>; 745 #address-cells = <2>; 746 #size-cells = <2>; 747 ranges; 748 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>; 749 interconnect-names = "qup-core"; 750 status = "disabled"; 751 752 i2c0: i2c@880000 { 753 compatible = "qcom,geni-i2c"; 754 reg = <0 0x00880000 0 0x4000>; 755 clock-names = "se"; 756 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&qup_i2c0_default>; 759 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 760 #address-cells = <1>; 761 #size-cells = <0>; 762 power-domains = <&rpmhpd SDM670_CX>; 763 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 764 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 765 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 766 interconnect-names = "qup-core", "qup-config", "qup-memory"; 767 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 768 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 769 dma-names = "tx", "rx"; 770 status = "disabled"; 771 }; 772 773 i2c1: i2c@884000 { 774 compatible = "qcom,geni-i2c"; 775 reg = <0 0x00884000 0 0x4000>; 776 clock-names = "se"; 777 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 778 pinctrl-names = "default"; 779 pinctrl-0 = <&qup_i2c1_default>; 780 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 781 #address-cells = <1>; 782 #size-cells = <0>; 783 power-domains = <&rpmhpd SDM670_CX>; 784 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 785 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 786 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 787 interconnect-names = "qup-core", "qup-config", "qup-memory"; 788 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 789 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 790 dma-names = "tx", "rx"; 791 status = "disabled"; 792 }; 793 794 i2c2: i2c@888000 { 795 compatible = "qcom,geni-i2c"; 796 reg = <0 0x00888000 0 0x4000>; 797 clock-names = "se"; 798 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 799 pinctrl-names = "default"; 800 pinctrl-0 = <&qup_i2c2_default>; 801 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 802 #address-cells = <1>; 803 #size-cells = <0>; 804 power-domains = <&rpmhpd SDM670_CX>; 805 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 806 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 807 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 808 interconnect-names = "qup-core", "qup-config", "qup-memory"; 809 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 810 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 811 dma-names = "tx", "rx"; 812 status = "disabled"; 813 }; 814 815 i2c3: i2c@88c000 { 816 compatible = "qcom,geni-i2c"; 817 reg = <0 0x0088c000 0 0x4000>; 818 clock-names = "se"; 819 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 820 pinctrl-names = "default"; 821 pinctrl-0 = <&qup_i2c3_default>; 822 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 823 #address-cells = <1>; 824 #size-cells = <0>; 825 power-domains = <&rpmhpd SDM670_CX>; 826 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 827 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 828 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 829 interconnect-names = "qup-core", "qup-config", "qup-memory"; 830 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 831 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 832 dma-names = "tx", "rx"; 833 status = "disabled"; 834 }; 835 836 i2c4: i2c@890000 { 837 compatible = "qcom,geni-i2c"; 838 reg = <0 0x00890000 0 0x4000>; 839 clock-names = "se"; 840 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 841 pinctrl-names = "default"; 842 pinctrl-0 = <&qup_i2c4_default>; 843 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 power-domains = <&rpmhpd SDM670_CX>; 847 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 848 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 849 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 850 interconnect-names = "qup-core", "qup-config", "qup-memory"; 851 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 852 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 853 dma-names = "tx", "rx"; 854 status = "disabled"; 855 }; 856 857 i2c5: i2c@894000 { 858 compatible = "qcom,geni-i2c"; 859 reg = <0 0x00894000 0 0x4000>; 860 clock-names = "se"; 861 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&qup_i2c5_default>; 864 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 865 #address-cells = <1>; 866 #size-cells = <0>; 867 power-domains = <&rpmhpd SDM670_CX>; 868 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 869 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 870 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 871 interconnect-names = "qup-core", "qup-config", "qup-memory"; 872 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 873 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 874 dma-names = "tx", "rx"; 875 status = "disabled"; 876 }; 877 878 i2c6: i2c@898000 { 879 compatible = "qcom,geni-i2c"; 880 reg = <0 0x00898000 0 0x4000>; 881 clock-names = "se"; 882 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 883 pinctrl-names = "default"; 884 pinctrl-0 = <&qup_i2c6_default>; 885 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 886 #address-cells = <1>; 887 #size-cells = <0>; 888 power-domains = <&rpmhpd SDM670_CX>; 889 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 890 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 891 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 892 interconnect-names = "qup-core", "qup-config", "qup-memory"; 893 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 894 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 895 dma-names = "tx", "rx"; 896 status = "disabled"; 897 }; 898 899 i2c7: i2c@89c000 { 900 compatible = "qcom,geni-i2c"; 901 reg = <0 0x0089c000 0 0x4000>; 902 clock-names = "se"; 903 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 904 pinctrl-names = "default"; 905 pinctrl-0 = <&qup_i2c7_default>; 906 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 907 #address-cells = <1>; 908 #size-cells = <0>; 909 power-domains = <&rpmhpd SDM670_CX>; 910 interconnects = <&aggre1_noc MASTER_BLSP_1 0 &config_noc SLAVE_BLSP_1 0>, 911 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_1 0>, 912 <&aggre1_noc MASTER_BLSP_1 0 &mem_noc SLAVE_EBI_CH0 0>; 913 interconnect-names = "qup-core", "qup-config", "qup-memory"; 914 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 915 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 916 dma-names = "tx", "rx"; 917 status = "disabled"; 918 }; 919 }; 920 921 gpi_dma1: dma-controller@a00000 { 922 #dma-cells = <3>; 923 compatible = "qcom,sdm670-gpi-dma", "qcom,sdm845-gpi-dma"; 924 reg = <0 0x00a00000 0 0x60000>; 925 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 926 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 927 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 928 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 929 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 930 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 931 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 932 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 933 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 934 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 935 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 936 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 937 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 938 dma-channels = <13>; 939 dma-channel-mask = <0xfa>; 940 iommus = <&apps_smmu 0x6d6 0x0>; 941 status = "disabled"; 942 }; 943 944 qupv3_id_1: geniqup@ac0000 { 945 compatible = "qcom,geni-se-qup"; 946 reg = <0 0x00ac0000 0 0x6000>; 947 clock-names = "m-ahb", "s-ahb"; 948 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 949 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 950 iommus = <&apps_smmu 0x6c3 0x0>; 951 #address-cells = <2>; 952 #size-cells = <2>; 953 ranges; 954 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>; 955 interconnect-names = "qup-core"; 956 status = "disabled"; 957 958 i2c8: i2c@a80000 { 959 compatible = "qcom,geni-i2c"; 960 reg = <0 0x00a80000 0 0x4000>; 961 clock-names = "se"; 962 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&qup_i2c8_default>; 965 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 966 #address-cells = <1>; 967 #size-cells = <0>; 968 power-domains = <&rpmhpd SDM670_CX>; 969 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 970 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 971 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 972 interconnect-names = "qup-core", "qup-config", "qup-memory"; 973 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 974 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 975 dma-names = "tx", "rx"; 976 status = "disabled"; 977 }; 978 979 i2c9: i2c@a84000 { 980 compatible = "qcom,geni-i2c"; 981 reg = <0 0x00a84000 0 0x4000>; 982 clock-names = "se"; 983 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 984 pinctrl-names = "default"; 985 pinctrl-0 = <&qup_i2c9_default>; 986 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 987 #address-cells = <1>; 988 #size-cells = <0>; 989 power-domains = <&rpmhpd SDM670_CX>; 990 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 991 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 992 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 993 interconnect-names = "qup-core", "qup-config", "qup-memory"; 994 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 995 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 996 dma-names = "tx", "rx"; 997 status = "disabled"; 998 }; 999 1000 i2c10: i2c@a88000 { 1001 compatible = "qcom,geni-i2c"; 1002 reg = <0 0x00a88000 0 0x4000>; 1003 clock-names = "se"; 1004 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1005 pinctrl-names = "default"; 1006 pinctrl-0 = <&qup_i2c10_default>; 1007 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1008 #address-cells = <1>; 1009 #size-cells = <0>; 1010 power-domains = <&rpmhpd SDM670_CX>; 1011 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1012 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1013 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1014 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1015 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1016 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1017 dma-names = "tx", "rx"; 1018 status = "disabled"; 1019 }; 1020 1021 i2c11: i2c@a8c000 { 1022 compatible = "qcom,geni-i2c"; 1023 reg = <0 0x00a8c000 0 0x4000>; 1024 clock-names = "se"; 1025 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1026 pinctrl-names = "default"; 1027 pinctrl-0 = <&qup_i2c11_default>; 1028 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1029 #address-cells = <1>; 1030 #size-cells = <0>; 1031 power-domains = <&rpmhpd SDM670_CX>; 1032 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1033 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1034 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1035 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1036 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1037 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1038 dma-names = "tx", "rx"; 1039 status = "disabled"; 1040 }; 1041 1042 i2c12: i2c@a90000 { 1043 compatible = "qcom,geni-i2c"; 1044 reg = <0 0x00a90000 0 0x4000>; 1045 clock-names = "se"; 1046 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1047 pinctrl-names = "default"; 1048 pinctrl-0 = <&qup_i2c12_default>; 1049 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 power-domains = <&rpmhpd SDM670_CX>; 1053 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1054 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1055 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1056 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1057 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1058 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1059 dma-names = "tx", "rx"; 1060 status = "disabled"; 1061 }; 1062 1063 i2c13: i2c@a94000 { 1064 compatible = "qcom,geni-i2c"; 1065 reg = <0 0x00a94000 0 0x4000>; 1066 clock-names = "se"; 1067 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1068 pinctrl-names = "default"; 1069 pinctrl-0 = <&qup_i2c13_default>; 1070 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 power-domains = <&rpmhpd SDM670_CX>; 1074 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1075 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1076 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1077 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1078 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1079 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1080 dma-names = "tx", "rx"; 1081 status = "disabled"; 1082 }; 1083 1084 i2c14: i2c@a98000 { 1085 compatible = "qcom,geni-i2c"; 1086 reg = <0 0x00a98000 0 0x4000>; 1087 clock-names = "se"; 1088 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1089 pinctrl-names = "default"; 1090 pinctrl-0 = <&qup_i2c14_default>; 1091 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 1092 #address-cells = <1>; 1093 #size-cells = <0>; 1094 power-domains = <&rpmhpd SDM670_CX>; 1095 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1096 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1097 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1098 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1099 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1100 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1101 dma-names = "tx", "rx"; 1102 status = "disabled"; 1103 }; 1104 1105 i2c15: i2c@a9c000 { 1106 compatible = "qcom,geni-i2c"; 1107 reg = <0 0x00a9c000 0 0x4000>; 1108 clock-names = "se"; 1109 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1110 pinctrl-names = "default"; 1111 pinctrl-0 = <&qup_i2c15_default>; 1112 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 power-domains = <&rpmhpd SDM670_CX>; 1116 interconnects = <&aggre2_noc MASTER_BLSP_2 0 &config_noc SLAVE_BLSP_2 0>, 1117 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_BLSP_2 0>, 1118 <&aggre2_noc MASTER_BLSP_2 0 &mem_noc SLAVE_EBI_CH0 0>; 1119 interconnect-names = "qup-core", "qup-config", "qup-memory"; 1120 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 1121 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 1122 dma-names = "tx", "rx"; 1123 status = "disabled"; 1124 }; 1125 }; 1126 1127 refgen: regulator@ff1000 { 1128 compatible = "qcom,sdm670-refgen-regulator", 1129 "qcom,sdm845-refgen-regulator"; 1130 reg = <0x0 0x00ff1000 0x0 0x60>; 1131 }; 1132 1133 mem_noc: interconnect@1380000 { 1134 compatible = "qcom,sdm670-mem-noc"; 1135 reg = <0 0x01380000 0 0x27200>; 1136 #interconnect-cells = <2>; 1137 qcom,bcm-voters = <&apps_bcm_voter>; 1138 }; 1139 1140 dc_noc: interconnect@14e0000 { 1141 compatible = "qcom,sdm670-dc-noc"; 1142 reg = <0 0x014e0000 0 0x400>; 1143 #interconnect-cells = <2>; 1144 qcom,bcm-voters = <&apps_bcm_voter>; 1145 }; 1146 1147 config_noc: interconnect@1500000 { 1148 compatible = "qcom,sdm670-config-noc"; 1149 reg = <0 0x01500000 0 0x5080>; 1150 #interconnect-cells = <2>; 1151 qcom,bcm-voters = <&apps_bcm_voter>; 1152 }; 1153 1154 system_noc: interconnect@1620000 { 1155 compatible = "qcom,sdm670-system-noc"; 1156 reg = <0 0x01620000 0 0x18080>; 1157 #interconnect-cells = <2>; 1158 qcom,bcm-voters = <&apps_bcm_voter>; 1159 }; 1160 1161 aggre1_noc: interconnect@16e0000 { 1162 compatible = "qcom,sdm670-aggre1-noc"; 1163 reg = <0 0x016e0000 0 0x15080>; 1164 #interconnect-cells = <2>; 1165 qcom,bcm-voters = <&apps_bcm_voter>; 1166 }; 1167 1168 aggre2_noc: interconnect@1700000 { 1169 compatible = "qcom,sdm670-aggre2-noc"; 1170 reg = <0 0x01700000 0 0x1f300>; 1171 #interconnect-cells = <2>; 1172 qcom,bcm-voters = <&apps_bcm_voter>; 1173 }; 1174 1175 mmss_noc: interconnect@1740000 { 1176 compatible = "qcom,sdm670-mmss-noc"; 1177 reg = <0 0x01740000 0 0x1c100>; 1178 #interconnect-cells = <2>; 1179 qcom,bcm-voters = <&apps_bcm_voter>; 1180 }; 1181 1182 tcsr_mutex: hwlock@1f40000 { 1183 compatible = "qcom,tcsr-mutex"; 1184 reg = <0 0x01f40000 0 0x20000>; 1185 #hwlock-cells = <1>; 1186 }; 1187 1188 tlmm: pinctrl@3400000 { 1189 compatible = "qcom,sdm670-tlmm"; 1190 reg = <0 0x03400000 0 0xc00000>; 1191 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1192 gpio-controller; 1193 #gpio-cells = <2>; 1194 interrupt-controller; 1195 #interrupt-cells = <2>; 1196 gpio-ranges = <&tlmm 0 0 151>; 1197 wakeup-parent = <&pdc>; 1198 1199 cci0_default: cci0-default-state { 1200 pins = "gpio17", "gpio18"; 1201 function = "cci_i2c"; 1202 drive-strength = <2>; 1203 bias-pull-up; 1204 }; 1205 1206 cci0_sleep: cci0-sleep-state { 1207 pins = "gpio17", "gpio18"; 1208 function = "cci_i2c"; 1209 drive-strength = <2>; 1210 bias-pull-down; 1211 }; 1212 1213 cci1_default: cci1-default-state { 1214 pins = "gpio19", "gpio20"; 1215 function = "cci_i2c"; 1216 drive-strength = <2>; 1217 bias-pull-up; 1218 }; 1219 1220 cci1_sleep: cci1-sleep-state { 1221 pins = "gpio19", "gpio20"; 1222 function = "cci_i2c"; 1223 drive-strength = <2>; 1224 bias-pull-down; 1225 }; 1226 1227 qup_i2c0_default: qup-i2c0-default-state { 1228 pins = "gpio0", "gpio1"; 1229 function = "qup0"; 1230 }; 1231 1232 qup_i2c1_default: qup-i2c1-default-state { 1233 pins = "gpio17", "gpio18"; 1234 function = "qup1"; 1235 }; 1236 1237 qup_i2c2_default: qup-i2c2-default-state { 1238 pins = "gpio27", "gpio28"; 1239 function = "qup2"; 1240 }; 1241 1242 qup_i2c3_default: qup-i2c3-default-state { 1243 pins = "gpio41", "gpio42"; 1244 function = "qup3"; 1245 }; 1246 1247 qup_i2c4_default: qup-i2c4-default-state { 1248 pins = "gpio89", "gpio90"; 1249 function = "qup4"; 1250 }; 1251 1252 qup_i2c5_default: qup-i2c5-default-state { 1253 pins = "gpio85", "gpio86"; 1254 function = "qup5"; 1255 }; 1256 1257 qup_i2c6_default: qup-i2c6-default-state { 1258 pins = "gpio45", "gpio46"; 1259 function = "qup6"; 1260 }; 1261 1262 qup_i2c7_default: qup-i2c7-default-state { 1263 pins = "gpio93", "gpio94"; 1264 function = "qup7"; 1265 }; 1266 1267 qup_i2c8_default: qup-i2c8-default-state { 1268 pins = "gpio65", "gpio66"; 1269 function = "qup8"; 1270 }; 1271 1272 qup_i2c9_default: qup-i2c9-default-state { 1273 pins = "gpio6", "gpio7"; 1274 function = "qup9"; 1275 }; 1276 1277 qup_i2c10_default: qup-i2c10-default-state { 1278 pins = "gpio55", "gpio56"; 1279 function = "qup10"; 1280 }; 1281 1282 qup_i2c11_default: qup-i2c11-default-state { 1283 pins = "gpio31", "gpio32"; 1284 function = "qup11"; 1285 }; 1286 1287 qup_i2c12_default: qup-i2c12-default-state { 1288 pins = "gpio49", "gpio50"; 1289 function = "qup12"; 1290 }; 1291 1292 qup_i2c13_default: qup-i2c13-default-state { 1293 pins = "gpio105", "gpio106"; 1294 function = "qup13"; 1295 }; 1296 1297 qup_i2c14_default: qup-i2c14-default-state { 1298 pins = "gpio33", "gpio34"; 1299 function = "qup14"; 1300 }; 1301 1302 qup_i2c15_default: qup-i2c15-default-state { 1303 pins = "gpio81", "gpio82"; 1304 function = "qup15"; 1305 }; 1306 1307 sdc1_state_on: sdc1-on-state { 1308 clk-pins { 1309 pins = "sdc1_clk"; 1310 bias-disable; 1311 drive-strength = <16>; 1312 }; 1313 1314 cmd-pins { 1315 pins = "sdc1_cmd"; 1316 bias-pull-up; 1317 drive-strength = <10>; 1318 }; 1319 1320 data-pins { 1321 pins = "sdc1_data"; 1322 bias-pull-up; 1323 drive-strength = <10>; 1324 }; 1325 1326 rclk-pins { 1327 pins = "sdc1_rclk"; 1328 bias-pull-down; 1329 }; 1330 }; 1331 1332 sdc1_state_off: sdc1-off-state { 1333 clk-pins { 1334 pins = "sdc1_clk"; 1335 bias-disable; 1336 drive-strength = <2>; 1337 }; 1338 1339 cmd-pins { 1340 pins = "sdc1_cmd"; 1341 bias-pull-up; 1342 drive-strength = <2>; 1343 }; 1344 1345 data-pins { 1346 pins = "sdc1_data"; 1347 bias-pull-up; 1348 drive-strength = <2>; 1349 }; 1350 1351 rclk-pins { 1352 pins = "sdc1_rclk"; 1353 bias-pull-down; 1354 }; 1355 }; 1356 }; 1357 1358 gpu: gpu@5000000 { 1359 compatible = "qcom,adreno-615.0", "qcom,adreno"; 1360 1361 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x10>; 1362 reg-names = "kgsl_3d0_reg_memory", "cx_mem"; 1363 1364 /* 1365 * Look ma, no clocks! The GPU clocks and power are 1366 * controlled entirely by the GMU 1367 */ 1368 1369 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1370 1371 iommus = <&adreno_smmu 0>; 1372 1373 operating-points-v2 = <&gpu_opp_table>; 1374 1375 qcom,gmu = <&gmu>; 1376 1377 interconnects = <&mem_noc MASTER_GRAPHICS_3D 0 &mem_noc SLAVE_EBI_CH0 0>; 1378 interconnect-names = "gfx-mem"; 1379 1380 nvmem-cells = <&gpu_speed_bin>; 1381 nvmem-cell-names = "speed_bin"; 1382 1383 status = "disabled"; 1384 1385 gpu_zap_shader: zap-shader { 1386 memory-region = <&gpu_mem>; 1387 }; 1388 1389 gpu_opp_table: opp-table { 1390 compatible = "operating-points-v2"; 1391 1392 opp-780000000 { 1393 opp-hz = /bits/ 64 <780000000>; 1394 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1395 opp-peak-kBps = <7216000>; 1396 opp-supported-hw = <0x8>; 1397 }; 1398 1399 opp-750000000 { 1400 opp-hz = /bits/ 64 <750000000>; 1401 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1402 opp-peak-kBps = <7216000>; 1403 opp-supported-hw = <0x8>; 1404 }; 1405 1406 opp-700000000 { 1407 opp-hz = /bits/ 64 <700000000>; 1408 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1409 opp-peak-kBps = <7216000>; 1410 opp-supported-hw = <0x4>; 1411 }; 1412 1413 opp-650000000 { 1414 opp-hz = /bits/ 64 <650000000>; 1415 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1416 opp-peak-kBps = <7216000>; 1417 opp-supported-hw = <0xc>; 1418 }; 1419 1420 opp-565000000 { 1421 opp-hz = /bits/ 64 <565000000>; 1422 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1423 opp-peak-kBps = <7216000>; 1424 opp-supported-hw = <0xc>; 1425 }; 1426 1427 opp-504000000 { 1428 opp-hz = /bits/ 64 <504000000>; 1429 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1430 opp-peak-kBps = <7216000>; 1431 opp-supported-hw = <0x2>; 1432 }; 1433 1434 opp-430000000 { 1435 opp-hz = /bits/ 64 <430000000>; 1436 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1437 opp-peak-kBps = <7216000>; 1438 opp-supported-hw = <0xf>; 1439 }; 1440 1441 opp-355000000 { 1442 opp-hz = /bits/ 64 <355000000>; 1443 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1444 opp-peak-kBps = <6220000>; 1445 opp-supported-hw = <0xf>; 1446 }; 1447 1448 opp-267000000 { 1449 opp-hz = /bits/ 64 <267000000>; 1450 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1451 opp-peak-kBps = <4068000>; 1452 opp-supported-hw = <0xf>; 1453 }; 1454 1455 opp-180000000 { 1456 opp-hz = /bits/ 64 <180000000>; 1457 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1458 opp-peak-kBps = <1804000>; 1459 opp-supported-hw = <0xf>; 1460 }; 1461 }; 1462 }; 1463 1464 adreno_smmu: iommu@5040000 { 1465 compatible = "qcom,sdm670-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2"; 1466 reg = <0 0x05040000 0 0x10000>; 1467 #iommu-cells = <1>; 1468 #global-interrupts = <2>; 1469 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>, 1470 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 1471 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 1472 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 1473 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 1474 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 1475 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 1476 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>, 1477 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>, 1478 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>; 1479 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1480 <&gcc GCC_GPU_CFG_AHB_CLK>; 1481 clock-names = "bus", "iface"; 1482 1483 power-domains = <&gpucc GPU_CX_GDSC>; 1484 }; 1485 1486 gmu: gmu@506a000 { 1487 compatible = "qcom,adreno-gmu-615.0", "qcom,adreno-gmu"; 1488 1489 reg = <0 0x0506a000 0 0x30000>, 1490 <0 0x0b280000 0 0x10000>, 1491 <0 0x0b480000 0 0x10000>; 1492 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq"; 1493 1494 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 1495 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 1496 interrupt-names = "hfi", "gmu"; 1497 1498 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 1499 <&gpucc GPU_CC_CXO_CLK>, 1500 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 1501 <&gcc GCC_GPU_MEMNOC_GFX_CLK>; 1502 clock-names = "gmu", "cxo", "axi", "memnoc"; 1503 1504 power-domains = <&gpucc GPU_CX_GDSC>, 1505 <&gpucc GPU_GX_GDSC>; 1506 power-domain-names = "cx", "gx"; 1507 1508 iommus = <&adreno_smmu 5>; 1509 1510 operating-points-v2 = <&gmu_opp_table>; 1511 1512 gmu_opp_table: opp-table { 1513 compatible = "operating-points-v2"; 1514 1515 opp-200000000 { 1516 opp-hz = /bits/ 64 <200000000>; 1517 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1518 }; 1519 }; 1520 }; 1521 1522 gpucc: clock-controller@5090000 { 1523 compatible = "qcom,sdm845-gpucc"; 1524 reg = <0 0x05090000 0 0x9000>; 1525 #clock-cells = <1>; 1526 #reset-cells = <1>; 1527 #power-domain-cells = <1>; 1528 clocks = <&rpmhcc RPMH_CXO_CLK>, 1529 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1530 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1531 clock-names = "bi_tcxo", 1532 "gcc_gpu_gpll0_clk_src", 1533 "gcc_gpu_gpll0_div_clk_src"; 1534 }; 1535 1536 usb_1_hsphy: phy@88e2000 { 1537 compatible = "qcom,sdm670-qusb2-phy", "qcom,qusb2-v2-phy"; 1538 reg = <0 0x088e2000 0 0x400>; 1539 #phy-cells = <0>; 1540 1541 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 1542 <&rpmhcc RPMH_CXO_CLK>; 1543 clock-names = "cfg_ahb", "ref"; 1544 1545 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 1546 1547 nvmem-cells = <&qusb2_hstx_trim>; 1548 1549 status = "disabled"; 1550 }; 1551 1552 usb_1: usb@a6f8800 { 1553 compatible = "qcom,sdm670-dwc3", "qcom,dwc3"; 1554 reg = <0 0x0a6f8800 0 0x400>; 1555 #address-cells = <2>; 1556 #size-cells = <2>; 1557 ranges; 1558 dma-ranges; 1559 1560 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1561 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1562 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1563 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1564 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 1565 clock-names = "cfg_noc", 1566 "core", 1567 "iface", 1568 "sleep", 1569 "mock_utmi"; 1570 1571 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1572 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1573 assigned-clock-rates = <19200000>, <150000000>; 1574 1575 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 1576 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 1577 <&pdc 9 IRQ_TYPE_EDGE_BOTH>, 1578 <&pdc 8 IRQ_TYPE_EDGE_BOTH>, 1579 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>; 1580 interrupt-names = "pwr_event", 1581 "hs_phy_irq", 1582 "dp_hs_phy_irq", 1583 "dm_hs_phy_irq", 1584 "ss_phy_irq"; 1585 1586 power-domains = <&gcc USB30_PRIM_GDSC>; 1587 1588 resets = <&gcc GCC_USB30_PRIM_BCR>; 1589 1590 interconnects = <&aggre2_noc MASTER_USB3 0 &mem_noc SLAVE_EBI_CH0 0>, 1591 <&gladiator_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_USB3 0>; 1592 interconnect-names = "usb-ddr", "apps-usb"; 1593 1594 status = "disabled"; 1595 1596 usb_1_dwc3: usb@a600000 { 1597 compatible = "snps,dwc3"; 1598 reg = <0 0x0a600000 0 0xcd00>; 1599 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 1600 iommus = <&apps_smmu 0x740 0>; 1601 snps,dis_u2_susphy_quirk; 1602 snps,dis_enblslpm_quirk; 1603 phys = <&usb_1_hsphy>; 1604 phy-names = "usb2-phy"; 1605 }; 1606 }; 1607 1608 pdc: interrupt-controller@b220000 { 1609 compatible = "qcom,sdm670-pdc", "qcom,pdc"; 1610 reg = <0 0x0b220000 0 0x30000>; 1611 qcom,pdc-ranges = <0 480 40>, <41 521 7>, <49 529 4>, 1612 <54 534 24>, <79 559 15>, <94 609 15>, 1613 <115 630 7>; 1614 #interrupt-cells = <2>; 1615 interrupt-parent = <&intc>; 1616 interrupt-controller; 1617 }; 1618 1619 spmi_bus: spmi@c440000 { 1620 compatible = "qcom,spmi-pmic-arb"; 1621 reg = <0 0x0c440000 0 0x1100>, 1622 <0 0x0c600000 0 0x2000000>, 1623 <0 0x0e600000 0 0x100000>, 1624 <0 0x0e700000 0 0xa0000>, 1625 <0 0x0c40a000 0 0x26000>; 1626 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1627 interrupt-names = "periph_irq"; 1628 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 1629 qcom,ee = <0>; 1630 qcom,channel = <0>; 1631 #address-cells = <2>; 1632 #size-cells = <0>; 1633 interrupt-controller; 1634 #interrupt-cells = <4>; 1635 }; 1636 1637 cci: cci@ac4a000 { 1638 compatible = "qcom,sdm670-cci", "qcom,msm8996-cci"; 1639 #address-cells = <1>; 1640 #size-cells = <0>; 1641 1642 reg = <0 0x0ac4a000 0 0x4000>; 1643 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 1644 power-domains = <&camcc TITAN_TOP_GDSC>; 1645 1646 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 1647 <&camcc CAM_CC_SOC_AHB_CLK>, 1648 <&camcc CAM_CC_CPAS_AHB_CLK>, 1649 <&camcc CAM_CC_CCI_CLK>; 1650 clock-names = "camnoc_axi", 1651 "soc_ahb", 1652 "cpas_ahb", 1653 "cci"; 1654 1655 pinctrl-names = "default", "sleep"; 1656 pinctrl-0 = <&cci0_default &cci1_default>; 1657 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 1658 1659 status = "disabled"; 1660 1661 cci_i2c0: i2c-bus@0 { 1662 reg = <0>; 1663 clock-frequency = <1000000>; 1664 #address-cells = <1>; 1665 #size-cells = <0>; 1666 }; 1667 1668 cci_i2c1: i2c-bus@1 { 1669 reg = <1>; 1670 clock-frequency = <1000000>; 1671 #address-cells = <1>; 1672 #size-cells = <0>; 1673 }; 1674 }; 1675 1676 camss: isp@acb3000 { 1677 compatible = "qcom,sdm670-camss"; 1678 reg = <0 0x0acb3000 0 0x1000>, 1679 <0 0x0acba000 0 0x1000>, 1680 <0 0x0acc8000 0 0x1000>, 1681 <0 0x0ac65000 0 0x1000>, 1682 <0 0x0ac66000 0 0x1000>, 1683 <0 0x0ac67000 0 0x1000>, 1684 <0 0x0acaf000 0 0x4000>, 1685 <0 0x0acb6000 0 0x4000>, 1686 <0 0x0acc4000 0 0x4000>; 1687 reg-names = "csid0", 1688 "csid1", 1689 "csid2", 1690 "csiphy0", 1691 "csiphy1", 1692 "csiphy2", 1693 "vfe0", 1694 "vfe1", 1695 "vfe_lite"; 1696 1697 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 1698 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 1699 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 1700 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 1701 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 1702 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 1703 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 1704 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 1705 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>; 1706 interrupt-names = "csid0", 1707 "csid1", 1708 "csid2", 1709 "csiphy0", 1710 "csiphy1", 1711 "csiphy2", 1712 "vfe0", 1713 "vfe1", 1714 "vfe_lite"; 1715 1716 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 1717 <&camcc CAM_CC_CPAS_AHB_CLK>, 1718 <&camcc CAM_CC_IFE_0_CSID_CLK>, 1719 <&camcc CAM_CC_IFE_1_CSID_CLK>, 1720 <&camcc CAM_CC_IFE_LITE_CSID_CLK>, 1721 <&camcc CAM_CC_CSIPHY0_CLK>, 1722 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 1723 <&camcc CAM_CC_CSIPHY1_CLK>, 1724 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 1725 <&camcc CAM_CC_CSIPHY2_CLK>, 1726 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 1727 <&gcc GCC_CAMERA_AHB_CLK>, 1728 <&gcc GCC_CAMERA_AXI_CLK>, 1729 <&camcc CAM_CC_SOC_AHB_CLK>, 1730 <&camcc CAM_CC_IFE_0_CLK>, 1731 <&camcc CAM_CC_IFE_0_AXI_CLK>, 1732 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 1733 <&camcc CAM_CC_IFE_1_CLK>, 1734 <&camcc CAM_CC_IFE_1_AXI_CLK>, 1735 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 1736 <&camcc CAM_CC_IFE_LITE_CLK>, 1737 <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>; 1738 clock-names = "camnoc_axi", 1739 "cpas_ahb", 1740 "csi0", 1741 "csi1", 1742 "csi2", 1743 "csiphy0", 1744 "csiphy0_timer", 1745 "csiphy1", 1746 "csiphy1_timer", 1747 "csiphy2", 1748 "csiphy2_timer", 1749 "gcc_camera_ahb", 1750 "gcc_camera_axi", 1751 "soc_ahb", 1752 "vfe0", 1753 "vfe0_axi", 1754 "vfe0_cphy_rx", 1755 "vfe1", 1756 "vfe1_axi", 1757 "vfe1_cphy_rx", 1758 "vfe_lite", 1759 "vfe_lite_cphy_rx"; 1760 1761 iommus = <&apps_smmu 0x808 0x0>, 1762 <&apps_smmu 0x810 0x8>, 1763 <&apps_smmu 0xc08 0x0>, 1764 <&apps_smmu 0xc10 0x8>; 1765 1766 power-domains = <&camcc IFE_0_GDSC>, 1767 <&camcc IFE_1_GDSC>, 1768 <&camcc TITAN_TOP_GDSC>; 1769 power-domain-names = "ife0", 1770 "ife1", 1771 "top"; 1772 1773 status = "disabled"; 1774 1775 ports { 1776 #address-cells = <1>; 1777 #size-cells = <0>; 1778 1779 port@0 { 1780 reg = <0>; 1781 1782 camss_endpoint0: endpoint { 1783 status = "disabled"; 1784 }; 1785 }; 1786 1787 port@1 { 1788 reg = <1>; 1789 1790 camss_endpoint1: endpoint { 1791 status = "disabled"; 1792 }; 1793 }; 1794 1795 port@2 { 1796 reg = <2>; 1797 1798 camss_endpoint2: endpoint { 1799 status = "disabled"; 1800 }; 1801 }; 1802 }; 1803 }; 1804 1805 camcc: clock-controller@ad00000 { 1806 compatible = "qcom,sdm670-camcc", "qcom,sdm845-camcc"; 1807 reg = <0 0x0ad00000 0 0x10000>; 1808 clocks = <&rpmhcc RPMH_CXO_CLK>; 1809 clock-names = "bi_tcxo"; 1810 #clock-cells = <1>; 1811 #reset-cells = <1>; 1812 #power-domain-cells = <1>; 1813 }; 1814 1815 mdss: display-subsystem@ae00000 { 1816 compatible = "qcom,sdm670-mdss"; 1817 reg = <0 0x0ae00000 0 0x1000>; 1818 reg-names = "mdss"; 1819 1820 power-domains = <&dispcc MDSS_GDSC>; 1821 1822 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1823 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1824 clock-names = "iface", "core"; 1825 1826 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1827 interrupt-controller; 1828 #interrupt-cells = <1>; 1829 1830 interconnects = <&mmss_noc MASTER_MDP_PORT0 0 &mem_noc SLAVE_EBI_CH0 0>, 1831 <&mmss_noc MASTER_MDP_PORT1 0 &mem_noc SLAVE_EBI_CH0 0>; 1832 interconnect-names = "mdp0-mem", "mdp1-mem"; 1833 1834 iommus = <&apps_smmu 0x880 0x8>, 1835 <&apps_smmu 0xc80 0x8>; 1836 1837 #address-cells = <2>; 1838 #size-cells = <2>; 1839 ranges; 1840 1841 status = "disabled"; 1842 1843 mdss_mdp: display-controller@ae01000 { 1844 compatible = "qcom,sdm670-dpu"; 1845 reg = <0 0x0ae01000 0 0x8f000>, 1846 <0 0x0aeb0000 0 0x3000>; 1847 reg-names = "mdp", "vbif"; 1848 1849 clocks = <&gcc GCC_DISP_AXI_CLK>, 1850 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1851 <&dispcc DISP_CC_MDSS_AXI_CLK>, 1852 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1853 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1854 clock-names = "gcc-bus", "iface", "bus", "core", "vsync"; 1855 1856 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1857 assigned-clock-rates = <19200000>; 1858 operating-points-v2 = <&mdp_opp_table>; 1859 power-domains = <&rpmhpd SDM670_CX>; 1860 1861 interrupt-parent = <&mdss>; 1862 interrupts = <0>; 1863 1864 ports { 1865 #address-cells = <1>; 1866 #size-cells = <0>; 1867 1868 port@0 { 1869 reg = <0>; 1870 dpu_intf0_out: endpoint { 1871 remote-endpoint = <&mdss_dsi0_in>; 1872 }; 1873 }; 1874 1875 port@1 { 1876 reg = <1>; 1877 dpu_intf1_out: endpoint { 1878 remote-endpoint = <&mdss_dsi1_in>; 1879 }; 1880 }; 1881 }; 1882 1883 mdp_opp_table: opp-table { 1884 compatible = "operating-points-v2"; 1885 1886 opp-19200000 { 1887 opp-hz = /bits/ 64 <19200000>; 1888 required-opps = <&rpmhpd_opp_min_svs>; 1889 }; 1890 1891 opp-171428571 { 1892 opp-hz = /bits/ 64 <171428571>; 1893 required-opps = <&rpmhpd_opp_low_svs>; 1894 }; 1895 1896 opp-358000000 { 1897 opp-hz = /bits/ 64 <358000000>; 1898 required-opps = <&rpmhpd_opp_svs_l1>; 1899 }; 1900 1901 opp-430000000 { 1902 opp-hz = /bits/ 64 <430000000>; 1903 required-opps = <&rpmhpd_opp_nom>; 1904 }; 1905 }; 1906 }; 1907 1908 mdss_dsi0: dsi@ae94000 { 1909 compatible = "qcom,sdm670-dsi-ctrl", 1910 "qcom,mdss-dsi-ctrl"; 1911 reg = <0 0x0ae94000 0 0x400>; 1912 reg-names = "dsi_ctrl"; 1913 1914 interrupt-parent = <&mdss>; 1915 interrupts = <4>; 1916 1917 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1918 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1919 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1920 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1921 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1922 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1923 clock-names = "byte", 1924 "byte_intf", 1925 "pixel", 1926 "core", 1927 "iface", 1928 "bus"; 1929 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 1930 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 1931 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1932 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1933 1934 operating-points-v2 = <&dsi_opp_table>; 1935 power-domains = <&rpmhpd SDM670_CX>; 1936 1937 phys = <&mdss_dsi0_phy>; 1938 1939 refgen-supply = <&refgen>; 1940 1941 #address-cells = <1>; 1942 #size-cells = <0>; 1943 1944 status = "disabled"; 1945 1946 ports { 1947 #address-cells = <1>; 1948 #size-cells = <0>; 1949 1950 port@0 { 1951 reg = <0>; 1952 mdss_dsi0_in: endpoint { 1953 remote-endpoint = <&dpu_intf0_out>; 1954 }; 1955 }; 1956 1957 port@1 { 1958 reg = <1>; 1959 mdss_dsi0_out: endpoint { 1960 }; 1961 }; 1962 }; 1963 }; 1964 1965 mdss_dsi0_phy: phy@ae94400 { 1966 compatible = "qcom,dsi-phy-10nm"; 1967 reg = <0 0x0ae94400 0 0x200>, 1968 <0 0x0ae94600 0 0x280>, 1969 <0 0x0ae94a00 0 0x1e0>; 1970 reg-names = "dsi_phy", 1971 "dsi_phy_lane", 1972 "dsi_pll"; 1973 1974 #clock-cells = <1>; 1975 #phy-cells = <0>; 1976 1977 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 1978 <&rpmhcc RPMH_CXO_CLK>; 1979 clock-names = "iface", "ref"; 1980 1981 status = "disabled"; 1982 }; 1983 1984 mdss_dsi1: dsi@ae96000 { 1985 compatible = "qcom,sdm670-dsi-ctrl", 1986 "qcom,mdss-dsi-ctrl"; 1987 reg = <0 0x0ae96000 0 0x400>; 1988 reg-names = "dsi_ctrl"; 1989 1990 interrupt-parent = <&mdss>; 1991 interrupts = <5>; 1992 1993 clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, 1994 <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, 1995 <&dispcc DISP_CC_MDSS_PCLK1_CLK>, 1996 <&dispcc DISP_CC_MDSS_ESC1_CLK>, 1997 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1998 <&dispcc DISP_CC_MDSS_AXI_CLK>; 1999 clock-names = "byte", 2000 "byte_intf", 2001 "pixel", 2002 "core", 2003 "iface", 2004 "bus"; 2005 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, 2006 <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; 2007 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2008 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 2009 2010 operating-points-v2 = <&dsi_opp_table>; 2011 power-domains = <&rpmhpd SDM670_CX>; 2012 2013 phys = <&mdss_dsi1_phy>; 2014 2015 refgen-supply = <&refgen>; 2016 2017 #address-cells = <1>; 2018 #size-cells = <0>; 2019 2020 status = "disabled"; 2021 2022 ports { 2023 #address-cells = <1>; 2024 #size-cells = <0>; 2025 2026 port@0 { 2027 reg = <0>; 2028 mdss_dsi1_in: endpoint { 2029 remote-endpoint = <&dpu_intf1_out>; 2030 }; 2031 }; 2032 2033 port@1 { 2034 reg = <1>; 2035 mdss_dsi1_out: endpoint { 2036 }; 2037 }; 2038 }; 2039 }; 2040 2041 mdss_dsi1_phy: phy@ae96400 { 2042 compatible = "qcom,dsi-phy-10nm"; 2043 reg = <0 0x0ae96400 0 0x200>, 2044 <0 0x0ae96600 0 0x280>, 2045 <0 0x0ae96a00 0 0x10e>; 2046 reg-names = "dsi_phy", 2047 "dsi_phy_lane", 2048 "dsi_pll"; 2049 2050 #clock-cells = <1>; 2051 #phy-cells = <0>; 2052 2053 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2054 <&rpmhcc RPMH_CXO_CLK>; 2055 clock-names = "iface", "ref"; 2056 2057 status = "disabled"; 2058 }; 2059 }; 2060 2061 dispcc: clock-controller@af00000 { 2062 compatible = "qcom,sdm845-dispcc"; 2063 reg = <0 0x0af00000 0 0x10000>; 2064 clocks = <&rpmhcc RPMH_CXO_CLK>, 2065 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2066 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 2067 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2068 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2069 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2070 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 2071 <0>, 2072 <0>; 2073 clock-names = "bi_tcxo", 2074 "gcc_disp_gpll0_clk_src", 2075 "gcc_disp_gpll0_div_clk_src", 2076 "dsi0_phy_pll_out_byteclk", 2077 "dsi0_phy_pll_out_dsiclk", 2078 "dsi1_phy_pll_out_byteclk", 2079 "dsi1_phy_pll_out_dsiclk", 2080 "dp_link_clk_divsel_ten", 2081 "dp_vco_divided_clk_src_mux"; 2082 #clock-cells = <1>; 2083 #reset-cells = <1>; 2084 #power-domain-cells = <1>; 2085 }; 2086 2087 apps_smmu: iommu@15000000 { 2088 compatible = "qcom,sdm670-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2089 reg = <0 0x15000000 0 0x80000>; 2090 #iommu-cells = <2>; 2091 #global-interrupts = <1>; 2092 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 2093 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2094 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2095 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2096 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2097 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2098 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2099 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2100 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2101 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2102 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2103 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2104 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2105 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2106 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2107 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2108 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2109 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2110 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2111 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2115 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 2117 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 2118 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 2119 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 2120 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 2121 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 2122 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 2123 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 2124 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 2125 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 2126 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 2127 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 2128 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 2129 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 2130 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 2131 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 2132 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 2133 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 2134 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 2135 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 2136 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 2137 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 2138 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 2139 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 2140 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 2141 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 2142 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 2143 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 2144 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 2145 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 2146 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 2147 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 2148 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 2149 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 2150 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 2151 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 2152 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 2153 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 2154 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 2155 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 2156 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 2157 dma-coherent; 2158 }; 2159 2160 gladiator_noc: interconnect@17900000 { 2161 compatible = "qcom,sdm670-gladiator-noc"; 2162 reg = <0 0x17900000 0 0xd080>; 2163 #interconnect-cells = <2>; 2164 qcom,bcm-voters = <&apps_bcm_voter>; 2165 }; 2166 2167 apps_rsc: rsc@179c0000 { 2168 compatible = "qcom,rpmh-rsc"; 2169 reg = <0 0x179c0000 0 0x10000>, 2170 <0 0x179d0000 0 0x10000>, 2171 <0 0x179e0000 0 0x10000>; 2172 reg-names = "drv-0", "drv-1", "drv-2"; 2173 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 2174 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 2175 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 2176 label = "apps_rsc"; 2177 qcom,tcs-offset = <0xd00>; 2178 qcom,drv-id = <2>; 2179 qcom,tcs-config = <ACTIVE_TCS 2>, 2180 <SLEEP_TCS 3>, 2181 <WAKE_TCS 3>, 2182 <CONTROL_TCS 1>; 2183 power-domains = <&cluster_pd>; 2184 2185 apps_bcm_voter: bcm-voter { 2186 compatible = "qcom,bcm-voter"; 2187 }; 2188 2189 rpmhcc: clock-controller { 2190 compatible = "qcom,sdm670-rpmh-clk"; 2191 #clock-cells = <1>; 2192 clock-names = "xo"; 2193 clocks = <&xo_board>; 2194 }; 2195 2196 rpmhpd: power-controller { 2197 compatible = "qcom,sdm670-rpmhpd"; 2198 #power-domain-cells = <1>; 2199 operating-points-v2 = <&rpmhpd_opp_table>; 2200 2201 rpmhpd_opp_table: opp-table { 2202 compatible = "operating-points-v2"; 2203 2204 rpmhpd_opp_ret: opp1 { 2205 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 2206 }; 2207 2208 rpmhpd_opp_min_svs: opp2 { 2209 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 2210 }; 2211 2212 rpmhpd_opp_low_svs: opp3 { 2213 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 2214 }; 2215 2216 rpmhpd_opp_svs: opp4 { 2217 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 2218 }; 2219 2220 rpmhpd_opp_svs_l1: opp5 { 2221 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 2222 }; 2223 2224 rpmhpd_opp_nom: opp6 { 2225 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 2226 }; 2227 2228 rpmhpd_opp_nom_l1: opp7 { 2229 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 2230 }; 2231 2232 rpmhpd_opp_nom_l2: opp8 { 2233 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 2234 }; 2235 2236 rpmhpd_opp_turbo: opp9 { 2237 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 2238 }; 2239 2240 rpmhpd_opp_turbo_l1: opp10 { 2241 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 2242 }; 2243 }; 2244 }; 2245 }; 2246 2247 intc: interrupt-controller@17a00000 { 2248 compatible = "arm,gic-v3"; 2249 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 2250 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 2251 interrupt-controller; 2252 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2253 #interrupt-cells = <3>; 2254 }; 2255 2256 osm_l3: interconnect@17d41000 { 2257 compatible = "qcom,sdm670-osm-l3", "qcom,osm-l3"; 2258 reg = <0 0x17d41000 0 0x1400>; 2259 2260 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2261 clock-names = "xo", "alternate"; 2262 2263 #interconnect-cells = <1>; 2264 }; 2265 2266 cpufreq_hw: cpufreq@17d43000 { 2267 compatible = "qcom,sdm670-cpufreq-hw", "qcom,cpufreq-hw"; 2268 reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>; 2269 reg-names = "freq-domain0", "freq-domain1"; 2270 2271 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>; 2272 clock-names = "xo", "alternate"; 2273 2274 #freq-domain-cells = <1>; 2275 }; 2276 }; 2277};
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