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qcs404.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/qcs404.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2018, Linaro Limited 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-qcs404.h> 8#include <dt-bindings/clock/qcom,turingcc-qcs404.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 chosen { }; 20 21 clocks { 22 xo_board: xo-board { 23 compatible = "fixed-clock"; 24 #clock-cells = <0>; 25 clock-frequency = <19200000>; 26 }; 27 28 sleep_clk: sleep-clk { 29 compatible = "fixed-clock"; 30 #clock-cells = <0>; 31 clock-frequency = <32764>; 32 }; 33 }; 34 35 cpus { 36 #address-cells = <1>; 37 #size-cells = <0>; 38 39 cpu0: cpu@100 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a53"; 42 reg = <0x100>; 43 enable-method = "psci"; 44 cpu-idle-states = <&cpu_sleep_0>; 45 next-level-cache = <&l2_0>; 46 #cooling-cells = <2>; 47 clocks = <&apcs_glb>; 48 operating-points-v2 = <&cpu_opp_table>; 49 power-domains = <&cpr>; 50 power-domain-names = "cpr"; 51 }; 52 53 cpu1: cpu@101 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a53"; 56 reg = <0x101>; 57 enable-method = "psci"; 58 cpu-idle-states = <&cpu_sleep_0>; 59 next-level-cache = <&l2_0>; 60 #cooling-cells = <2>; 61 clocks = <&apcs_glb>; 62 operating-points-v2 = <&cpu_opp_table>; 63 power-domains = <&cpr>; 64 power-domain-names = "cpr"; 65 }; 66 67 cpu2: cpu@102 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x102>; 71 enable-method = "psci"; 72 cpu-idle-states = <&cpu_sleep_0>; 73 next-level-cache = <&l2_0>; 74 #cooling-cells = <2>; 75 clocks = <&apcs_glb>; 76 operating-points-v2 = <&cpu_opp_table>; 77 power-domains = <&cpr>; 78 power-domain-names = "cpr"; 79 }; 80 81 cpu3: cpu@103 { 82 device_type = "cpu"; 83 compatible = "arm,cortex-a53"; 84 reg = <0x103>; 85 enable-method = "psci"; 86 cpu-idle-states = <&cpu_sleep_0>; 87 next-level-cache = <&l2_0>; 88 #cooling-cells = <2>; 89 clocks = <&apcs_glb>; 90 operating-points-v2 = <&cpu_opp_table>; 91 power-domains = <&cpr>; 92 power-domain-names = "cpr"; 93 }; 94 95 l2_0: l2-cache { 96 compatible = "cache"; 97 cache-level = <2>; 98 cache-unified; 99 }; 100 101 idle-states { 102 entry-method = "psci"; 103 104 cpu_sleep_0: cpu-sleep-0 { 105 compatible = "arm,idle-state"; 106 idle-state-name = "standalone-power-collapse"; 107 arm,psci-suspend-param = <0x40000003>; 108 entry-latency-us = <125>; 109 exit-latency-us = <180>; 110 min-residency-us = <595>; 111 local-timer-stop; 112 }; 113 }; 114 }; 115 116 cpu_opp_table: opp-table-cpu { 117 compatible = "operating-points-v2-kryo-cpu"; 118 opp-shared; 119 120 opp-1094400000 { 121 opp-hz = /bits/ 64 <1094400000>; 122 required-opps = <&cpr_opp1>; 123 }; 124 opp-1248000000 { 125 opp-hz = /bits/ 64 <1248000000>; 126 required-opps = <&cpr_opp2>; 127 }; 128 opp-1401600000 { 129 opp-hz = /bits/ 64 <1401600000>; 130 required-opps = <&cpr_opp3>; 131 }; 132 }; 133 134 cpr_opp_table: opp-table-cpr { 135 compatible = "operating-points-v2-qcom-level"; 136 137 cpr_opp1: opp1 { 138 opp-level = <1>; 139 qcom,opp-fuse-level = <1>; 140 }; 141 cpr_opp2: opp2 { 142 opp-level = <2>; 143 qcom,opp-fuse-level = <2>; 144 }; 145 cpr_opp3: opp3 { 146 opp-level = <3>; 147 qcom,opp-fuse-level = <3>; 148 }; 149 }; 150 151 firmware { 152 scm: scm { 153 compatible = "qcom,scm-qcs404", "qcom,scm"; 154 #reset-cells = <1>; 155 }; 156 }; 157 158 memory@80000000 { 159 device_type = "memory"; 160 /* We expect the bootloader to fill in the size */ 161 reg = <0 0x80000000 0 0>; 162 }; 163 164 psci { 165 compatible = "arm,psci-1.0"; 166 method = "smc"; 167 }; 168 169 rpm: remoteproc { 170 compatible = "qcom,qcs404-rpm-proc", "qcom,rpm-proc"; 171 172 glink-edge { 173 compatible = "qcom,glink-rpm"; 174 175 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 176 qcom,rpm-msg-ram = <&rpm_msg_ram>; 177 mboxes = <&apcs_glb 0>; 178 179 rpm_requests: rpm-requests { 180 compatible = "qcom,rpm-qcs404", "qcom,glink-smd-rpm"; 181 qcom,glink-channels = "rpm_requests"; 182 183 rpmcc: clock-controller { 184 compatible = "qcom,rpmcc-qcs404", "qcom,rpmcc"; 185 #clock-cells = <1>; 186 clocks = <&xo_board>; 187 clock-names = "xo"; 188 }; 189 190 rpmpd: power-controller { 191 compatible = "qcom,qcs404-rpmpd"; 192 #power-domain-cells = <1>; 193 operating-points-v2 = <&rpmpd_opp_table>; 194 195 rpmpd_opp_table: opp-table { 196 compatible = "operating-points-v2"; 197 198 rpmpd_opp_ret: opp1 { 199 opp-level = <16>; 200 }; 201 202 rpmpd_opp_ret_plus: opp2 { 203 opp-level = <32>; 204 }; 205 206 rpmpd_opp_min_svs: opp3 { 207 opp-level = <48>; 208 }; 209 210 rpmpd_opp_low_svs: opp4 { 211 opp-level = <64>; 212 }; 213 214 rpmpd_opp_svs: opp5 { 215 opp-level = <128>; 216 }; 217 218 rpmpd_opp_svs_plus: opp6 { 219 opp-level = <192>; 220 }; 221 222 rpmpd_opp_nom: opp7 { 223 opp-level = <256>; 224 }; 225 226 rpmpd_opp_nom_plus: opp8 { 227 opp-level = <320>; 228 }; 229 230 rpmpd_opp_turbo: opp9 { 231 opp-level = <384>; 232 }; 233 234 rpmpd_opp_turbo_no_cpr: opp10 { 235 opp-level = <416>; 236 }; 237 238 rpmpd_opp_turbo_plus: opp11 { 239 opp-level = <512>; 240 }; 241 }; 242 }; 243 }; 244 }; 245 }; 246 247 reserved-memory { 248 #address-cells = <2>; 249 #size-cells = <2>; 250 ranges; 251 252 tz_apps_mem: memory@85900000 { 253 reg = <0 0x85900000 0 0x500000>; 254 no-map; 255 }; 256 257 xbl_mem: memory@85e00000 { 258 reg = <0 0x85e00000 0 0x100000>; 259 no-map; 260 }; 261 262 smem_region: memory@85f00000 { 263 reg = <0 0x85f00000 0 0x200000>; 264 no-map; 265 }; 266 267 tz_mem: memory@86100000 { 268 reg = <0 0x86100000 0 0x300000>; 269 no-map; 270 }; 271 272 wlan_fw_mem: memory@86400000 { 273 reg = <0 0x86400000 0 0x1100000>; 274 no-map; 275 }; 276 277 adsp_fw_mem: memory@87500000 { 278 reg = <0 0x87500000 0 0x1a00000>; 279 no-map; 280 }; 281 282 cdsp_fw_mem: memory@88f00000 { 283 reg = <0 0x88f00000 0 0x600000>; 284 no-map; 285 }; 286 287 wlan_msa_mem: memory@89500000 { 288 reg = <0 0x89500000 0 0x100000>; 289 no-map; 290 }; 291 292 uefi_mem: memory@9f800000 { 293 reg = <0 0x9f800000 0 0x800000>; 294 no-map; 295 }; 296 }; 297 298 smem { 299 compatible = "qcom,smem"; 300 301 memory-region = <&smem_region>; 302 qcom,rpm-msg-ram = <&rpm_msg_ram>; 303 304 hwlocks = <&tcsr_mutex 3>; 305 }; 306 307 soc: soc@0 { 308 #address-cells = <1>; 309 #size-cells = <1>; 310 ranges = <0 0 0 0xffffffff>; 311 compatible = "simple-bus"; 312 313 turingcc: clock-controller@800000 { 314 compatible = "qcom,qcs404-turingcc"; 315 reg = <0x00800000 0x30000>; 316 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>; 317 318 #clock-cells = <1>; 319 #reset-cells = <1>; 320 321 status = "disabled"; 322 }; 323 324 rpm_msg_ram: sram@60000 { 325 compatible = "qcom,rpm-msg-ram"; 326 reg = <0x00060000 0x6000>; 327 }; 328 329 usb3_phy: phy@78000 { 330 compatible = "qcom,usb-ss-28nm-phy"; 331 reg = <0x00078000 0x400>; 332 #phy-cells = <0>; 333 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 334 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 335 <&gcc GCC_USB3_PHY_PIPE_CLK>; 336 clock-names = "ref", "ahb", "pipe"; 337 resets = <&gcc GCC_USB3_PHY_BCR>, 338 <&gcc GCC_USB3PHY_PHY_BCR>; 339 reset-names = "com", "phy"; 340 status = "disabled"; 341 }; 342 343 usb2_phy_prim: phy@7a000 { 344 compatible = "qcom,usb-hs-28nm-femtophy"; 345 reg = <0x0007a000 0x200>; 346 #phy-cells = <0>; 347 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 348 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 349 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 350 clock-names = "ref", "ahb", "sleep"; 351 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>, 352 <&gcc GCC_USB2A_PHY_BCR>; 353 reset-names = "phy", "por"; 354 status = "disabled"; 355 }; 356 357 usb2_phy_sec: phy@7c000 { 358 compatible = "qcom,usb-hs-28nm-femtophy"; 359 reg = <0x0007c000 0x200>; 360 #phy-cells = <0>; 361 clocks = <&rpmcc RPM_SMD_LN_BB_CLK>, 362 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 363 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 364 clock-names = "ref", "ahb", "sleep"; 365 resets = <&gcc GCC_QUSB2_PHY_BCR>, 366 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 367 reset-names = "phy", "por"; 368 status = "disabled"; 369 }; 370 371 qfprom: qfprom@a4000 { 372 compatible = "qcom,qcs404-qfprom", "qcom,qfprom"; 373 reg = <0x000a4000 0x1000>; 374 #address-cells = <1>; 375 #size-cells = <1>; 376 cpr_efuse_speedbin: speedbin@13c { 377 reg = <0x13c 0x4>; 378 bits = <2 3>; 379 }; 380 381 tsens_s0_p1: s0-p1@1f8 { 382 reg = <0x1f8 0x1>; 383 bits = <0 6>; 384 }; 385 386 tsens_s0_p2: s0-p2@1f8 { 387 reg = <0x1f8 0x2>; 388 bits = <6 6>; 389 }; 390 391 tsens_s1_p1: s1-p1@1f9 { 392 reg = <0x1f9 0x2>; 393 bits = <4 6>; 394 }; 395 396 tsens_s1_p2: s1-p2@1fa { 397 reg = <0x1fa 0x1>; 398 bits = <2 6>; 399 }; 400 401 tsens_s2_p1: s2-p1@1fb { 402 reg = <0x1fb 0x1>; 403 bits = <0 6>; 404 }; 405 406 tsens_s2_p2: s2-p2@1fb { 407 reg = <0x1fb 0x2>; 408 bits = <6 6>; 409 }; 410 411 tsens_s3_p1: s3-p1@1fc { 412 reg = <0x1fc 0x2>; 413 bits = <4 6>; 414 }; 415 416 tsens_s3_p2: s3-p2@1fd { 417 reg = <0x1fd 0x1>; 418 bits = <2 6>; 419 }; 420 421 tsens_s4_p1: s4-p1@1fe { 422 reg = <0x1fe 0x1>; 423 bits = <0 6>; 424 }; 425 426 tsens_s4_p2: s4-p2@1fe { 427 reg = <0x1fe 0x2>; 428 bits = <6 6>; 429 }; 430 431 tsens_s5_p1: s5-p1@200 { 432 reg = <0x200 0x1>; 433 bits = <0 6>; 434 }; 435 436 tsens_s5_p2: s5-p2@200 { 437 reg = <0x200 0x2>; 438 bits = <6 6>; 439 }; 440 441 tsens_s6_p1: s6-p1@201 { 442 reg = <0x201 0x2>; 443 bits = <4 6>; 444 }; 445 446 tsens_s6_p2: s6-p2@202 { 447 reg = <0x202 0x1>; 448 bits = <2 6>; 449 }; 450 451 tsens_s7_p1: s7-p1@203 { 452 reg = <0x203 0x1>; 453 bits = <0 6>; 454 }; 455 456 tsens_s7_p2: s7-p2@203 { 457 reg = <0x203 0x2>; 458 bits = <6 6>; 459 }; 460 461 tsens_s8_p1: s8-p1@204 { 462 reg = <0x204 0x2>; 463 bits = <4 6>; 464 }; 465 466 tsens_s8_p2: s8-p2@205 { 467 reg = <0x205 0x1>; 468 bits = <2 6>; 469 }; 470 471 tsens_s9_p1: s9-p1@206 { 472 reg = <0x206 0x1>; 473 bits = <0 6>; 474 }; 475 476 tsens_s9_p2: s9-p2@206 { 477 reg = <0x206 0x2>; 478 bits = <6 6>; 479 }; 480 481 tsens_mode: mode@208 { 482 reg = <0x208 1>; 483 bits = <0 3>; 484 }; 485 486 tsens_base1: base1@208 { 487 reg = <0x208 2>; 488 bits = <3 8>; 489 }; 490 491 tsens_base2: base2@208 { 492 reg = <0x209 2>; 493 bits = <3 8>; 494 }; 495 496 cpr_efuse_quot_offset1: qoffset1@231 { 497 reg = <0x231 0x4>; 498 bits = <4 7>; 499 }; 500 cpr_efuse_quot_offset2: qoffset2@232 { 501 reg = <0x232 0x4>; 502 bits = <3 7>; 503 }; 504 cpr_efuse_quot_offset3: qoffset3@233 { 505 reg = <0x233 0x4>; 506 bits = <2 7>; 507 }; 508 cpr_efuse_init_voltage1: ivoltage1@229 { 509 reg = <0x229 0x4>; 510 bits = <4 6>; 511 }; 512 cpr_efuse_init_voltage2: ivoltage2@22a { 513 reg = <0x22a 0x4>; 514 bits = <2 6>; 515 }; 516 cpr_efuse_init_voltage3: ivoltage3@22b { 517 reg = <0x22b 0x4>; 518 bits = <0 6>; 519 }; 520 cpr_efuse_quot1: quot1@22b { 521 reg = <0x22b 0x4>; 522 bits = <6 12>; 523 }; 524 cpr_efuse_quot2: quot2@22d { 525 reg = <0x22d 0x4>; 526 bits = <2 12>; 527 }; 528 cpr_efuse_quot3: quot3@230 { 529 reg = <0x230 0x4>; 530 bits = <0 12>; 531 }; 532 cpr_efuse_ring1: ring1@228 { 533 reg = <0x228 0x4>; 534 bits = <0 3>; 535 }; 536 cpr_efuse_ring2: ring2@228 { 537 reg = <0x228 0x4>; 538 bits = <4 3>; 539 }; 540 cpr_efuse_ring3: ring3@229 { 541 reg = <0x229 0x4>; 542 bits = <0 3>; 543 }; 544 cpr_efuse_revision: revision@218 { 545 reg = <0x218 0x4>; 546 bits = <3 3>; 547 }; 548 }; 549 550 rng: rng@e3000 { 551 compatible = "qcom,prng-ee"; 552 reg = <0x000e3000 0x1000>; 553 clocks = <&gcc GCC_PRNG_AHB_CLK>; 554 clock-names = "core"; 555 }; 556 557 bimc: interconnect@400000 { 558 reg = <0x00400000 0x80000>; 559 compatible = "qcom,qcs404-bimc"; 560 #interconnect-cells = <1>; 561 }; 562 563 tsens: thermal-sensor@4a9000 { 564 compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; 565 reg = <0x004a9000 0x1000>, /* TM */ 566 <0x004a8000 0x1000>; /* SROT */ 567 nvmem-cells = <&tsens_mode>, 568 <&tsens_base1>, <&tsens_base2>, 569 <&tsens_s0_p1>, <&tsens_s0_p2>, 570 <&tsens_s1_p1>, <&tsens_s1_p2>, 571 <&tsens_s2_p1>, <&tsens_s2_p2>, 572 <&tsens_s3_p1>, <&tsens_s3_p2>, 573 <&tsens_s4_p1>, <&tsens_s4_p2>, 574 <&tsens_s5_p1>, <&tsens_s5_p2>, 575 <&tsens_s6_p1>, <&tsens_s6_p2>, 576 <&tsens_s7_p1>, <&tsens_s7_p2>, 577 <&tsens_s8_p1>, <&tsens_s8_p2>, 578 <&tsens_s9_p1>, <&tsens_s9_p2>; 579 nvmem-cell-names = "mode", 580 "base1", "base2", 581 "s0_p1", "s0_p2", 582 "s1_p1", "s1_p2", 583 "s2_p1", "s2_p2", 584 "s3_p1", "s3_p2", 585 "s4_p1", "s4_p2", 586 "s5_p1", "s5_p2", 587 "s6_p1", "s6_p2", 588 "s7_p1", "s7_p2", 589 "s8_p1", "s8_p2", 590 "s9_p1", "s9_p2"; 591 #qcom,sensors = <10>; 592 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 593 interrupt-names = "uplow"; 594 #thermal-sensor-cells = <1>; 595 }; 596 597 pcnoc: interconnect@500000 { 598 reg = <0x00500000 0x15080>; 599 compatible = "qcom,qcs404-pcnoc"; 600 #interconnect-cells = <1>; 601 }; 602 603 snoc: interconnect@580000 { 604 reg = <0x00580000 0x23080>; 605 compatible = "qcom,qcs404-snoc"; 606 #interconnect-cells = <1>; 607 }; 608 609 remoteproc_cdsp: remoteproc@b00000 { 610 compatible = "qcom,qcs404-cdsp-pas"; 611 reg = <0x00b00000 0x4040>; 612 613 interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>, 614 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 615 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 616 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 617 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 618 interrupt-names = "wdog", "fatal", "ready", 619 "handover", "stop-ack"; 620 621 clocks = <&xo_board>; 622 clock-names = "xo"; 623 624 /* 625 * If the node was using the PIL binding, then include properties: 626 * clocks = <&xo_board>, 627 * <&gcc GCC_CDSP_CFG_AHB_CLK>, 628 * <&gcc GCC_CDSP_TBU_CLK>, 629 * <&gcc GCC_BIMC_CDSP_CLK>, 630 * <&turingcc TURING_WRAPPER_AON_CLK>, 631 * <&turingcc TURING_Q6SS_AHBS_AON_CLK>, 632 * <&turingcc TURING_Q6SS_AHBM_AON_CLK>, 633 * <&turingcc TURING_Q6SS_Q6_AXIM_CLK>; 634 * clock-names = "xo", 635 * "sway", 636 * "tbu", 637 * "bimc", 638 * "ahb_aon", 639 * "q6ss_slave", 640 * "q6ss_master", 641 * "q6_axim"; 642 * resets = <&gcc GCC_CDSP_RESTART>; 643 * reset-names = "restart"; 644 * qcom,halt-regs = <&tcsr 0x19004>; 645 */ 646 647 memory-region = <&cdsp_fw_mem>; 648 649 qcom,smem-states = <&cdsp_smp2p_out 0>; 650 qcom,smem-state-names = "stop"; 651 652 status = "disabled"; 653 654 glink-edge { 655 interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>; 656 657 qcom,remote-pid = <5>; 658 mboxes = <&apcs_glb 12>; 659 660 label = "cdsp"; 661 }; 662 }; 663 664 usb3: usb@7678800 { 665 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 666 reg = <0x07678800 0x400>; 667 #address-cells = <1>; 668 #size-cells = <1>; 669 ranges; 670 clocks = <&gcc GCC_USB30_MASTER_CLK>, 671 <&gcc GCC_SYS_NOC_USB3_CLK>, 672 <&gcc GCC_USB30_SLEEP_CLK>, 673 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 674 clock-names = "core", "iface", "sleep", "mock_utmi"; 675 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 676 <&gcc GCC_USB30_MASTER_CLK>; 677 assigned-clock-rates = <19200000>, <200000000>; 678 679 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>; 682 interrupt-names = "pwr_event", 683 "hs_phy_irq", 684 "qusb2_phy"; 685 686 status = "disabled"; 687 688 usb3_dwc3: usb@7580000 { 689 compatible = "snps,dwc3"; 690 reg = <0x07580000 0xcd00>; 691 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 692 phys = <&usb2_phy_prim>, <&usb3_phy>; 693 phy-names = "usb2-phy", "usb3-phy"; 694 snps,has-lpm-erratum; 695 snps,hird-threshold = /bits/ 8 <0x10>; 696 snps,usb3_lpm_capable; 697 snps,dis-u1-entry-quirk; 698 snps,dis-u2-entry-quirk; 699 dr_mode = "otg"; 700 }; 701 }; 702 703 usb2: usb@79b8800 { 704 compatible = "qcom,qcs404-dwc3", "qcom,dwc3"; 705 reg = <0x079b8800 0x400>; 706 #address-cells = <1>; 707 #size-cells = <1>; 708 ranges; 709 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>, 710 <&gcc GCC_PCNOC_USB2_CLK>, 711 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>, 712 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 713 clock-names = "core", "iface", "sleep", "mock_utmi"; 714 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 715 <&gcc GCC_USB_HS_SYSTEM_CLK>; 716 assigned-clock-rates = <19200000>, <133333333>; 717 718 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 721 interrupt-names = "pwr_event", 722 "hs_phy_irq", 723 "qusb2_phy"; 724 725 status = "disabled"; 726 727 usb@78c0000 { 728 compatible = "snps,dwc3"; 729 reg = <0x078c0000 0xcc00>; 730 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 731 phys = <&usb2_phy_sec>; 732 phy-names = "usb2-phy"; 733 snps,has-lpm-erratum; 734 snps,hird-threshold = /bits/ 8 <0x10>; 735 snps,usb3_lpm_capable; 736 snps,dis-u1-entry-quirk; 737 snps,dis-u2-entry-quirk; 738 dr_mode = "peripheral"; 739 }; 740 }; 741 742 tlmm: pinctrl@1000000 { 743 compatible = "qcom,qcs404-pinctrl"; 744 reg = <0x01000000 0x200000>, 745 <0x01300000 0x200000>, 746 <0x07b00000 0x200000>; 747 reg-names = "south", "north", "east"; 748 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 749 gpio-ranges = <&tlmm 0 0 120>; 750 gpio-controller; 751 #gpio-cells = <2>; 752 interrupt-controller; 753 #interrupt-cells = <2>; 754 755 blsp1_i2c0_default: blsp1-i2c0-default-state { 756 pins = "gpio32", "gpio33"; 757 function = "blsp_i2c0"; 758 }; 759 760 blsp1_i2c1_default: blsp1-i2c1-default-state { 761 pins = "gpio24", "gpio25"; 762 function = "blsp_i2c1"; 763 }; 764 765 blsp1_i2c2_default: blsp1-i2c2-default-state { 766 sda-pins { 767 pins = "gpio19"; 768 function = "blsp_i2c_sda_a2"; 769 }; 770 771 scl-pins { 772 pins = "gpio20"; 773 function = "blsp_i2c_scl_a2"; 774 }; 775 }; 776 777 blsp1_i2c3_default: blsp1-i2c3-default-state { 778 pins = "gpio84", "gpio85"; 779 function = "blsp_i2c3"; 780 }; 781 782 blsp1_i2c4_default: blsp1-i2c4-default-state { 783 pins = "gpio117", "gpio118"; 784 function = "blsp_i2c4"; 785 }; 786 787 blsp1_uart0_default: blsp1-uart0-default-state { 788 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 789 function = "blsp_uart0"; 790 }; 791 792 blsp1_uart1_default: blsp1-uart1-default-state { 793 pins = "gpio22", "gpio23"; 794 function = "blsp_uart1"; 795 }; 796 797 blsp1_uart2_default: blsp1-uart2-default-state { 798 rx-pins { 799 pins = "gpio18"; 800 function = "blsp_uart_rx_a2"; 801 }; 802 803 tx-pins { 804 pins = "gpio17"; 805 function = "blsp_uart_tx_a2"; 806 }; 807 }; 808 809 blsp1_uart3_default: blsp1-uart3-default-state { 810 cts-pins { 811 pins = "gpio84"; 812 function = "blsp_uart3"; 813 }; 814 815 rts-tx-pins { 816 pins = "gpio85", "gpio82"; 817 function = "blsp_uart3"; 818 }; 819 820 rx-pins { 821 pins = "gpio83"; 822 function = "blsp_uart3"; 823 }; 824 }; 825 826 blsp2_i2c0_default: blsp2-i2c0-default-state { 827 pins = "gpio28", "gpio29"; 828 function = "blsp_i2c5"; 829 }; 830 831 blsp1_spi0_default: blsp1-spi0-default-state { 832 pins = "gpio30", "gpio31", "gpio32", "gpio33"; 833 function = "blsp_spi0"; 834 }; 835 836 blsp1_spi1_default: blsp1-spi1-default-state { 837 mosi-pins { 838 pins = "gpio22"; 839 function = "blsp_spi_mosi_a1"; 840 }; 841 842 miso-pins { 843 pins = "gpio23"; 844 function = "blsp_spi_miso_a1"; 845 }; 846 847 cs-n-pins { 848 pins = "gpio24"; 849 function = "blsp_spi_cs_n_a1"; 850 }; 851 852 clk-pins { 853 pins = "gpio25"; 854 function = "blsp_spi_clk_a1"; 855 }; 856 }; 857 858 blsp1_spi2_default: blsp1-spi2-default-state { 859 pins = "gpio17", "gpio18", "gpio19", "gpio20"; 860 function = "blsp_spi2"; 861 }; 862 863 blsp1_spi3_default: blsp1-spi3-default-state { 864 pins = "gpio82", "gpio83", "gpio84", "gpio85"; 865 function = "blsp_spi3"; 866 }; 867 868 blsp1_spi4_default: blsp1-spi4-default-state { 869 pins = "gpio37", "gpio38", "gpio117", "gpio118"; 870 function = "blsp_spi4"; 871 }; 872 873 blsp2_spi0_default: blsp2-spi0-default-state { 874 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 875 function = "blsp_spi5"; 876 }; 877 878 blsp2_uart0_default: blsp2-uart0-default-state { 879 pins = "gpio26", "gpio27", "gpio28", "gpio29"; 880 function = "blsp_uart5"; 881 }; 882 }; 883 884 gcc: clock-controller@1800000 { 885 compatible = "qcom,gcc-qcs404"; 886 reg = <0x01800000 0x80000>; 887 #clock-cells = <1>; 888 #reset-cells = <1>; 889 #power-domain-cells = <1>; 890 891 clocks = <&xo_board>, 892 <&sleep_clk>, 893 <&pcie_phy>, 894 <0>, 895 <0>, 896 <0>; 897 898 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>; 899 assigned-clock-rates = <19200000>; 900 }; 901 902 tcsr_mutex: hwlock@1905000 { 903 compatible = "qcom,tcsr-mutex"; 904 reg = <0x01905000 0x20000>; 905 #hwlock-cells = <1>; 906 }; 907 908 tcsr: syscon@1937000 { 909 compatible = "qcom,qcs404-tcsr", "syscon"; 910 reg = <0x01937000 0x25000>; 911 }; 912 913 sram@290000 { 914 compatible = "qcom,rpm-stats"; 915 reg = <0x00290000 0x10000>; 916 }; 917 918 spmi_bus: spmi@200f000 { 919 compatible = "qcom,spmi-pmic-arb"; 920 reg = <0x0200f000 0x001000>, 921 <0x02400000 0x800000>, 922 <0x02c00000 0x800000>, 923 <0x03800000 0x200000>, 924 <0x0200a000 0x002100>; 925 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 926 interrupt-names = "periph_irq"; 927 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 928 qcom,ee = <0>; 929 qcom,channel = <0>; 930 #address-cells = <2>; 931 #size-cells = <0>; 932 interrupt-controller; 933 #interrupt-cells = <4>; 934 }; 935 936 remoteproc_wcss: remoteproc@7400000 { 937 compatible = "qcom,qcs404-wcss-pas"; 938 reg = <0x07400000 0x4040>; 939 940 interrupts-extended = <&intc GIC_SPI 153 IRQ_TYPE_EDGE_RISING>, 941 <&wcss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 942 <&wcss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 943 <&wcss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 944 <&wcss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 945 interrupt-names = "wdog", "fatal", "ready", 946 "handover", "stop-ack"; 947 948 clocks = <&xo_board>; 949 clock-names = "xo"; 950 951 memory-region = <&wlan_fw_mem>; 952 953 qcom,smem-states = <&wcss_smp2p_out 0>; 954 qcom,smem-state-names = "stop"; 955 956 status = "disabled"; 957 958 glink-edge { 959 interrupts = <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>; 960 961 qcom,remote-pid = <1>; 962 mboxes = <&apcs_glb 16>; 963 964 label = "wcss"; 965 }; 966 }; 967 968 pcie_phy: phy@7786000 { 969 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; 970 reg = <0x07786000 0xb8>; 971 972 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; 973 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, 974 <&gcc GCC_PCIE_0_PIPE_ARES>; 975 reset-names = "phy", "pipe"; 976 977 clock-output-names = "pcie_0_pipe_clk"; 978 #clock-cells = <0>; 979 #phy-cells = <0>; 980 981 status = "disabled"; 982 }; 983 984 sdcc1: mmc@7804000 { 985 compatible = "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"; 986 reg = <0x07804000 0x1000>, <0x7805000 0x1000>; 987 reg-names = "hc", "cqhci"; 988 989 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 990 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 991 interrupt-names = "hc_irq", "pwr_irq"; 992 993 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 994 <&gcc GCC_SDCC1_APPS_CLK>, 995 <&xo_board>; 996 clock-names = "iface", "core", "xo"; 997 998 status = "disabled"; 999 }; 1000 1001 blsp1_dma: dma-controller@7884000 { 1002 compatible = "qcom,bam-v1.7.0"; 1003 reg = <0x07884000 0x25000>; 1004 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1006 clock-names = "bam_clk"; 1007 #dma-cells = <1>; 1008 qcom,ee = <0>; 1009 status = "okay"; 1010 }; 1011 1012 blsp1_uart0: serial@78af000 { 1013 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1014 reg = <0x078af000 0x200>; 1015 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1017 clock-names = "core", "iface"; 1018 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1019 dma-names = "tx", "rx"; 1020 pinctrl-names = "default"; 1021 pinctrl-0 = <&blsp1_uart0_default>; 1022 status = "disabled"; 1023 }; 1024 1025 blsp1_uart1: serial@78b0000 { 1026 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1027 reg = <0x078b0000 0x200>; 1028 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1029 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1030 clock-names = "core", "iface"; 1031 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1032 dma-names = "tx", "rx"; 1033 pinctrl-names = "default"; 1034 pinctrl-0 = <&blsp1_uart1_default>; 1035 status = "disabled"; 1036 }; 1037 1038 blsp1_uart2: serial@78b1000 { 1039 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1040 reg = <0x078b1000 0x200>; 1041 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1043 clock-names = "core", "iface"; 1044 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1045 dma-names = "tx", "rx"; 1046 pinctrl-names = "default"; 1047 pinctrl-0 = <&blsp1_uart2_default>; 1048 status = "okay"; 1049 }; 1050 1051 ethernet: ethernet@7a80000 { 1052 compatible = "qcom,qcs404-ethqos"; 1053 reg = <0x07a80000 0x10000>, 1054 <0x07a96000 0x100>; 1055 reg-names = "stmmaceth", "rgmii"; 1056 clock-names = "stmmaceth", "pclk", "ptp_ref", "rgmii"; 1057 clocks = <&gcc GCC_ETH_AXI_CLK>, 1058 <&gcc GCC_ETH_SLAVE_AHB_CLK>, 1059 <&gcc GCC_ETH_PTP_CLK>, 1060 <&gcc GCC_ETH_RGMII_CLK>; 1061 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1063 interrupt-names = "macirq", "eth_lpi"; 1064 1065 snps,tso; 1066 rx-fifo-depth = <4096>; 1067 tx-fifo-depth = <4096>; 1068 1069 status = "disabled"; 1070 }; 1071 1072 wifi: wifi@a000000 { 1073 compatible = "qcom,wcn3990-wifi"; 1074 reg = <0xa000000 0x800000>; 1075 reg-names = "membase"; 1076 memory-region = <&wlan_msa_mem>; 1077 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 1089 status = "disabled"; 1090 }; 1091 1092 blsp1_uart3: serial@78b2000 { 1093 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1094 reg = <0x078b2000 0x200>; 1095 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1096 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1097 clock-names = "core", "iface"; 1098 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1099 dma-names = "tx", "rx"; 1100 pinctrl-names = "default"; 1101 pinctrl-0 = <&blsp1_uart3_default>; 1102 status = "disabled"; 1103 }; 1104 1105 blsp1_i2c0: i2c@78b5000 { 1106 compatible = "qcom,i2c-qup-v2.2.1"; 1107 reg = <0x078b5000 0x600>; 1108 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1109 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>, 1110 <&gcc GCC_BLSP1_AHB_CLK>; 1111 clock-names = "core", "iface"; 1112 pinctrl-names = "default"; 1113 pinctrl-0 = <&blsp1_i2c0_default>; 1114 #address-cells = <1>; 1115 #size-cells = <0>; 1116 status = "disabled"; 1117 }; 1118 1119 blsp1_spi0: spi@78b5000 { 1120 compatible = "qcom,spi-qup-v2.2.1"; 1121 reg = <0x078b5000 0x600>; 1122 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1123 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>, 1124 <&gcc GCC_BLSP1_AHB_CLK>; 1125 clock-names = "core", "iface"; 1126 pinctrl-names = "default"; 1127 pinctrl-0 = <&blsp1_spi0_default>; 1128 #address-cells = <1>; 1129 #size-cells = <0>; 1130 status = "disabled"; 1131 }; 1132 1133 blsp1_i2c1: i2c@78b6000 { 1134 compatible = "qcom,i2c-qup-v2.2.1"; 1135 reg = <0x078b6000 0x600>; 1136 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1138 <&gcc GCC_BLSP1_AHB_CLK>; 1139 clock-names = "core", "iface"; 1140 pinctrl-names = "default"; 1141 pinctrl-0 = <&blsp1_i2c1_default>; 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 status = "disabled"; 1145 }; 1146 1147 blsp1_spi1: spi@78b6000 { 1148 compatible = "qcom,spi-qup-v2.2.1"; 1149 reg = <0x078b6000 0x600>; 1150 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1151 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1152 <&gcc GCC_BLSP1_AHB_CLK>; 1153 clock-names = "core", "iface"; 1154 pinctrl-names = "default"; 1155 pinctrl-0 = <&blsp1_spi1_default>; 1156 #address-cells = <1>; 1157 #size-cells = <0>; 1158 status = "disabled"; 1159 }; 1160 1161 blsp1_i2c2: i2c@78b7000 { 1162 compatible = "qcom,i2c-qup-v2.2.1"; 1163 reg = <0x078b7000 0x600>; 1164 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1165 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1166 <&gcc GCC_BLSP1_AHB_CLK>; 1167 clock-names = "core", "iface"; 1168 pinctrl-names = "default"; 1169 pinctrl-0 = <&blsp1_i2c2_default>; 1170 #address-cells = <1>; 1171 #size-cells = <0>; 1172 status = "disabled"; 1173 }; 1174 1175 blsp1_spi2: spi@78b7000 { 1176 compatible = "qcom,spi-qup-v2.2.1"; 1177 reg = <0x078b7000 0x600>; 1178 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1179 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1180 <&gcc GCC_BLSP1_AHB_CLK>; 1181 clock-names = "core", "iface"; 1182 pinctrl-names = "default"; 1183 pinctrl-0 = <&blsp1_spi2_default>; 1184 #address-cells = <1>; 1185 #size-cells = <0>; 1186 status = "disabled"; 1187 }; 1188 1189 blsp1_i2c3: i2c@78b8000 { 1190 compatible = "qcom,i2c-qup-v2.2.1"; 1191 reg = <0x078b8000 0x600>; 1192 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1194 <&gcc GCC_BLSP1_AHB_CLK>; 1195 clock-names = "core", "iface"; 1196 pinctrl-names = "default"; 1197 pinctrl-0 = <&blsp1_i2c3_default>; 1198 #address-cells = <1>; 1199 #size-cells = <0>; 1200 status = "disabled"; 1201 }; 1202 1203 blsp1_spi3: spi@78b8000 { 1204 compatible = "qcom,spi-qup-v2.2.1"; 1205 reg = <0x078b8000 0x600>; 1206 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1208 <&gcc GCC_BLSP1_AHB_CLK>; 1209 clock-names = "core", "iface"; 1210 pinctrl-names = "default"; 1211 pinctrl-0 = <&blsp1_spi3_default>; 1212 #address-cells = <1>; 1213 #size-cells = <0>; 1214 status = "disabled"; 1215 }; 1216 1217 blsp1_i2c4: i2c@78b9000 { 1218 compatible = "qcom,i2c-qup-v2.2.1"; 1219 reg = <0x078b9000 0x600>; 1220 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1221 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1222 <&gcc GCC_BLSP1_AHB_CLK>; 1223 clock-names = "core", "iface"; 1224 pinctrl-names = "default"; 1225 pinctrl-0 = <&blsp1_i2c4_default>; 1226 #address-cells = <1>; 1227 #size-cells = <0>; 1228 status = "disabled"; 1229 }; 1230 1231 blsp1_spi4: spi@78b9000 { 1232 compatible = "qcom,spi-qup-v2.2.1"; 1233 reg = <0x078b9000 0x600>; 1234 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1236 <&gcc GCC_BLSP1_AHB_CLK>; 1237 clock-names = "core", "iface"; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&blsp1_spi4_default>; 1240 #address-cells = <1>; 1241 #size-cells = <0>; 1242 status = "disabled"; 1243 }; 1244 1245 blsp2_dma: dma-controller@7ac4000 { 1246 compatible = "qcom,bam-v1.7.0"; 1247 reg = <0x07ac4000 0x17000>; 1248 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1249 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1250 clock-names = "bam_clk"; 1251 #dma-cells = <1>; 1252 qcom,ee = <0>; 1253 status = "disabled"; 1254 }; 1255 1256 blsp2_uart0: serial@7aef000 { 1257 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1258 reg = <0x07aef000 0x200>; 1259 interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>; 1260 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; 1261 clock-names = "core", "iface"; 1262 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1263 dma-names = "tx", "rx"; 1264 pinctrl-names = "default"; 1265 pinctrl-0 = <&blsp2_uart0_default>; 1266 status = "disabled"; 1267 }; 1268 1269 blsp2_i2c0: i2c@7af5000 { 1270 compatible = "qcom,i2c-qup-v2.2.1"; 1271 reg = <0x07af5000 0x600>; 1272 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1273 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>, 1274 <&gcc GCC_BLSP2_AHB_CLK>; 1275 clock-names = "core", "iface"; 1276 pinctrl-names = "default"; 1277 pinctrl-0 = <&blsp2_i2c0_default>; 1278 #address-cells = <1>; 1279 #size-cells = <0>; 1280 status = "disabled"; 1281 }; 1282 1283 blsp2_spi0: spi@7af5000 { 1284 compatible = "qcom,spi-qup-v2.2.1"; 1285 reg = <0x07af5000 0x600>; 1286 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>, 1288 <&gcc GCC_BLSP2_AHB_CLK>; 1289 clock-names = "core", "iface"; 1290 pinctrl-names = "default"; 1291 pinctrl-0 = <&blsp2_spi0_default>; 1292 #address-cells = <1>; 1293 #size-cells = <0>; 1294 status = "disabled"; 1295 }; 1296 1297 sram@8600000 { 1298 compatible = "qcom,qcs404-imem", "syscon", "simple-mfd"; 1299 reg = <0x08600000 0x1000>; 1300 1301 #address-cells = <1>; 1302 #size-cells = <1>; 1303 1304 ranges = <0 0x08600000 0x1000>; 1305 1306 pil-reloc@94c { 1307 compatible = "qcom,pil-reloc-info"; 1308 reg = <0x94c 0xc8>; 1309 }; 1310 }; 1311 1312 intc: interrupt-controller@b000000 { 1313 compatible = "qcom,msm-qgic2"; 1314 interrupt-controller; 1315 #address-cells = <0>; 1316 #interrupt-cells = <3>; 1317 reg = <0x0b000000 0x1000>, 1318 <0x0b002000 0x1000>; 1319 }; 1320 1321 apcs_glb: mailbox@b011000 { 1322 compatible = "qcom,qcs404-apcs-apps-global", 1323 "qcom,msm8916-apcs-kpss-global", "syscon"; 1324 reg = <0x0b011000 0x1000>; 1325 #mbox-cells = <1>; 1326 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>; 1327 clock-names = "pll", "aux"; 1328 #clock-cells = <0>; 1329 }; 1330 1331 apcs_hfpll: clock-controller@b016000 { 1332 compatible = "qcom,qcs404-hfpll"; 1333 reg = <0x0b016000 0x30>; 1334 #clock-cells = <0>; 1335 clock-output-names = "apcs_hfpll"; 1336 clocks = <&xo_board>; 1337 clock-names = "xo"; 1338 }; 1339 1340 watchdog@b017000 { 1341 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1342 reg = <0x0b017000 0x1000>; 1343 clocks = <&sleep_clk>; 1344 }; 1345 1346 cpr: power-controller@b018000 { 1347 compatible = "qcom,qcs404-cpr", "qcom,cpr"; 1348 reg = <0x0b018000 0x1000>; 1349 interrupts = <0 15 IRQ_TYPE_EDGE_RISING>; 1350 clocks = <&xo_board>; 1351 clock-names = "ref"; 1352 vdd-apc-supply = <&pms405_s3>; 1353 #power-domain-cells = <0>; 1354 operating-points-v2 = <&cpr_opp_table>; 1355 acc-syscon = <&tcsr>; 1356 1357 nvmem-cells = <&cpr_efuse_quot_offset1>, 1358 <&cpr_efuse_quot_offset2>, 1359 <&cpr_efuse_quot_offset3>, 1360 <&cpr_efuse_init_voltage1>, 1361 <&cpr_efuse_init_voltage2>, 1362 <&cpr_efuse_init_voltage3>, 1363 <&cpr_efuse_quot1>, 1364 <&cpr_efuse_quot2>, 1365 <&cpr_efuse_quot3>, 1366 <&cpr_efuse_ring1>, 1367 <&cpr_efuse_ring2>, 1368 <&cpr_efuse_ring3>, 1369 <&cpr_efuse_revision>; 1370 nvmem-cell-names = "cpr_quotient_offset1", 1371 "cpr_quotient_offset2", 1372 "cpr_quotient_offset3", 1373 "cpr_init_voltage1", 1374 "cpr_init_voltage2", 1375 "cpr_init_voltage3", 1376 "cpr_quotient1", 1377 "cpr_quotient2", 1378 "cpr_quotient3", 1379 "cpr_ring_osc1", 1380 "cpr_ring_osc2", 1381 "cpr_ring_osc3", 1382 "cpr_fuse_revision"; 1383 }; 1384 1385 timer@b120000 { 1386 #address-cells = <1>; 1387 #size-cells = <1>; 1388 ranges; 1389 compatible = "arm,armv7-timer-mem"; 1390 reg = <0x0b120000 0x1000>; 1391 clock-frequency = <19200000>; 1392 1393 frame@b121000 { 1394 frame-number = <0>; 1395 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1396 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1397 reg = <0x0b121000 0x1000>, 1398 <0x0b122000 0x1000>; 1399 }; 1400 1401 frame@b123000 { 1402 frame-number = <1>; 1403 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1404 reg = <0x0b123000 0x1000>; 1405 status = "disabled"; 1406 }; 1407 1408 frame@b124000 { 1409 frame-number = <2>; 1410 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1411 reg = <0x0b124000 0x1000>; 1412 status = "disabled"; 1413 }; 1414 1415 frame@b125000 { 1416 frame-number = <3>; 1417 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1418 reg = <0x0b125000 0x1000>; 1419 status = "disabled"; 1420 }; 1421 1422 frame@b126000 { 1423 frame-number = <4>; 1424 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1425 reg = <0x0b126000 0x1000>; 1426 status = "disabled"; 1427 }; 1428 1429 frame@b127000 { 1430 frame-number = <5>; 1431 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1432 reg = <0xb127000 0x1000>; 1433 status = "disabled"; 1434 }; 1435 1436 frame@b128000 { 1437 frame-number = <6>; 1438 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1439 reg = <0x0b128000 0x1000>; 1440 status = "disabled"; 1441 }; 1442 }; 1443 1444 remoteproc_adsp: remoteproc@c700000 { 1445 compatible = "qcom,qcs404-adsp-pas"; 1446 reg = <0x0c700000 0x4040>; 1447 1448 interrupts-extended = <&intc GIC_SPI 293 IRQ_TYPE_EDGE_RISING>, 1449 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1450 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1451 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1452 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1453 interrupt-names = "wdog", "fatal", "ready", 1454 "handover", "stop-ack"; 1455 1456 clocks = <&xo_board>; 1457 clock-names = "xo"; 1458 1459 memory-region = <&adsp_fw_mem>; 1460 1461 qcom,smem-states = <&adsp_smp2p_out 0>; 1462 qcom,smem-state-names = "stop"; 1463 1464 status = "disabled"; 1465 1466 glink-edge { 1467 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 1468 1469 qcom,remote-pid = <2>; 1470 mboxes = <&apcs_glb 8>; 1471 1472 label = "adsp"; 1473 }; 1474 }; 1475 1476 pcie: pcie@10000000 { 1477 compatible = "qcom,pcie-qcs404"; 1478 reg = <0x10000000 0xf1d>, 1479 <0x10000f20 0xa8>, 1480 <0x07780000 0x2000>, 1481 <0x10001000 0x2000>; 1482 reg-names = "dbi", "elbi", "parf", "config"; 1483 device_type = "pci"; 1484 linux,pci-domain = <0>; 1485 bus-range = <0x00 0xff>; 1486 num-lanes = <1>; 1487 #address-cells = <3>; 1488 #size-cells = <2>; 1489 1490 ranges = <0x81000000 0x0 0x00000000 0x10003000 0x0 0x00010000>, /* I/O */ 1491 <0x82000000 0x0 0x10013000 0x10013000 0x0 0x007ed000>; /* memory */ 1492 1493 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1494 interrupt-names = "msi"; 1495 #interrupt-cells = <1>; 1496 interrupt-map-mask = <0 0 0 0x7>; 1497 interrupt-map = <0 0 0 1 &intc GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 1498 <0 0 0 2 &intc GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 1499 <0 0 0 3 &intc GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 1500 <0 0 0 4 &intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 1501 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 1502 <&gcc GCC_PCIE_0_AUX_CLK>, 1503 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 1504 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 1505 clock-names = "iface", "aux", "master_bus", "slave_bus"; 1506 1507 resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>, 1508 <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>, 1509 <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>, 1510 <&gcc GCC_PCIE_0_CORE_STICKY_ARES>, 1511 <&gcc GCC_PCIE_0_BCR>, 1512 <&gcc GCC_PCIE_0_AHB_ARES>; 1513 reset-names = "axi_m", 1514 "axi_s", 1515 "axi_m_sticky", 1516 "pipe_sticky", 1517 "pwr", 1518 "ahb"; 1519 1520 phys = <&pcie_phy>; 1521 phy-names = "pciephy"; 1522 1523 status = "disabled"; 1524 1525 pcie@0 { 1526 device_type = "pci"; 1527 reg = <0x0 0x0 0x0 0x0 0x0>; 1528 bus-range = <0x01 0xff>; 1529 1530 #address-cells = <3>; 1531 #size-cells = <2>; 1532 ranges; 1533 }; 1534 }; 1535 }; 1536 1537 timer { 1538 compatible = "arm,armv8-timer"; 1539 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1540 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1541 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1542 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1543 }; 1544 1545 smp2p-adsp { 1546 compatible = "qcom,smp2p"; 1547 qcom,smem = <443>, <429>; 1548 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 1549 mboxes = <&apcs_glb 10>; 1550 qcom,local-pid = <0>; 1551 qcom,remote-pid = <2>; 1552 1553 adsp_smp2p_out: master-kernel { 1554 qcom,entry-name = "master-kernel"; 1555 #qcom,smem-state-cells = <1>; 1556 }; 1557 1558 adsp_smp2p_in: slave-kernel { 1559 qcom,entry-name = "slave-kernel"; 1560 interrupt-controller; 1561 #interrupt-cells = <2>; 1562 }; 1563 }; 1564 1565 smp2p-cdsp { 1566 compatible = "qcom,smp2p"; 1567 qcom,smem = <94>, <432>; 1568 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 1569 mboxes = <&apcs_glb 14>; 1570 qcom,local-pid = <0>; 1571 qcom,remote-pid = <5>; 1572 1573 cdsp_smp2p_out: master-kernel { 1574 qcom,entry-name = "master-kernel"; 1575 #qcom,smem-state-cells = <1>; 1576 }; 1577 1578 cdsp_smp2p_in: slave-kernel { 1579 qcom,entry-name = "slave-kernel"; 1580 interrupt-controller; 1581 #interrupt-cells = <2>; 1582 }; 1583 }; 1584 1585 smp2p-wcss { 1586 compatible = "qcom,smp2p"; 1587 qcom,smem = <435>, <428>; 1588 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 1589 mboxes = <&apcs_glb 18>; 1590 qcom,local-pid = <0>; 1591 qcom,remote-pid = <1>; 1592 1593 wcss_smp2p_out: master-kernel { 1594 qcom,entry-name = "master-kernel"; 1595 #qcom,smem-state-cells = <1>; 1596 }; 1597 1598 wcss_smp2p_in: slave-kernel { 1599 qcom,entry-name = "slave-kernel"; 1600 interrupt-controller; 1601 #interrupt-cells = <2>; 1602 }; 1603 }; 1604 1605 thermal-zones { 1606 aoss-thermal { 1607 polling-delay-passive = <250>; 1608 1609 thermal-sensors = <&tsens 0>; 1610 1611 trips { 1612 aoss_alert0: trip-point0 { 1613 temperature = <105000>; 1614 hysteresis = <2000>; 1615 type = "hot"; 1616 }; 1617 }; 1618 }; 1619 1620 q6-hvx-thermal { 1621 polling-delay-passive = <250>; 1622 1623 thermal-sensors = <&tsens 1>; 1624 1625 trips { 1626 q6_hvx_alert0: trip-point0 { 1627 temperature = <105000>; 1628 hysteresis = <2000>; 1629 type = "hot"; 1630 }; 1631 }; 1632 }; 1633 1634 lpass-thermal { 1635 polling-delay-passive = <250>; 1636 1637 thermal-sensors = <&tsens 2>; 1638 1639 trips { 1640 lpass_alert0: trip-point0 { 1641 temperature = <105000>; 1642 hysteresis = <2000>; 1643 type = "hot"; 1644 }; 1645 }; 1646 }; 1647 1648 wlan-thermal { 1649 polling-delay-passive = <250>; 1650 1651 thermal-sensors = <&tsens 3>; 1652 1653 trips { 1654 wlan_alert0: trip-point0 { 1655 temperature = <105000>; 1656 hysteresis = <2000>; 1657 type = "hot"; 1658 }; 1659 }; 1660 }; 1661 1662 cluster-thermal { 1663 polling-delay-passive = <250>; 1664 1665 thermal-sensors = <&tsens 4>; 1666 1667 trips { 1668 cluster_alert0: trip-point0 { 1669 temperature = <95000>; 1670 hysteresis = <2000>; 1671 type = "hot"; 1672 }; 1673 cluster_alert1: trip-point1 { 1674 temperature = <105000>; 1675 hysteresis = <2000>; 1676 type = "passive"; 1677 }; 1678 cluster_crit: cluster-crit { 1679 temperature = <120000>; 1680 hysteresis = <2000>; 1681 type = "critical"; 1682 }; 1683 }; 1684 cooling-maps { 1685 map0 { 1686 trip = <&cluster_alert1>; 1687 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1688 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1689 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1690 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1691 }; 1692 }; 1693 }; 1694 1695 cpu0-thermal { 1696 polling-delay-passive = <250>; 1697 1698 thermal-sensors = <&tsens 5>; 1699 1700 trips { 1701 cpu0_alert0: trip-point0 { 1702 temperature = <95000>; 1703 hysteresis = <2000>; 1704 type = "hot"; 1705 }; 1706 cpu0_alert1: trip-point1 { 1707 temperature = <105000>; 1708 hysteresis = <2000>; 1709 type = "passive"; 1710 }; 1711 cpu0_crit: cpu-crit { 1712 temperature = <120000>; 1713 hysteresis = <2000>; 1714 type = "critical"; 1715 }; 1716 }; 1717 cooling-maps { 1718 map0 { 1719 trip = <&cpu0_alert1>; 1720 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1721 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1722 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1723 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1724 }; 1725 }; 1726 }; 1727 1728 cpu1-thermal { 1729 polling-delay-passive = <250>; 1730 1731 thermal-sensors = <&tsens 6>; 1732 1733 trips { 1734 cpu1_alert0: trip-point0 { 1735 temperature = <95000>; 1736 hysteresis = <2000>; 1737 type = "hot"; 1738 }; 1739 cpu1_alert1: trip-point1 { 1740 temperature = <105000>; 1741 hysteresis = <2000>; 1742 type = "passive"; 1743 }; 1744 cpu1_crit: cpu-crit { 1745 temperature = <120000>; 1746 hysteresis = <2000>; 1747 type = "critical"; 1748 }; 1749 }; 1750 cooling-maps { 1751 map0 { 1752 trip = <&cpu1_alert1>; 1753 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1754 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1755 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1756 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1757 }; 1758 }; 1759 }; 1760 1761 cpu2-thermal { 1762 polling-delay-passive = <250>; 1763 1764 thermal-sensors = <&tsens 7>; 1765 1766 trips { 1767 cpu2_alert0: trip-point0 { 1768 temperature = <95000>; 1769 hysteresis = <2000>; 1770 type = "hot"; 1771 }; 1772 cpu2_alert1: trip-point1 { 1773 temperature = <105000>; 1774 hysteresis = <2000>; 1775 type = "passive"; 1776 }; 1777 cpu2_crit: cpu-crit { 1778 temperature = <120000>; 1779 hysteresis = <2000>; 1780 type = "critical"; 1781 }; 1782 }; 1783 cooling-maps { 1784 map0 { 1785 trip = <&cpu2_alert1>; 1786 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1787 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1788 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1789 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1790 }; 1791 }; 1792 }; 1793 1794 cpu3-thermal { 1795 polling-delay-passive = <250>; 1796 1797 thermal-sensors = <&tsens 8>; 1798 1799 trips { 1800 cpu3_alert0: trip-point0 { 1801 temperature = <95000>; 1802 hysteresis = <2000>; 1803 type = "hot"; 1804 }; 1805 cpu3_alert1: trip-point1 { 1806 temperature = <105000>; 1807 hysteresis = <2000>; 1808 type = "passive"; 1809 }; 1810 cpu3_crit: cpu-crit { 1811 temperature = <120000>; 1812 hysteresis = <2000>; 1813 type = "critical"; 1814 }; 1815 }; 1816 cooling-maps { 1817 map0 { 1818 trip = <&cpu3_alert1>; 1819 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1820 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1821 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1822 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1823 }; 1824 }; 1825 }; 1826 1827 gpu-thermal { 1828 polling-delay-passive = <250>; 1829 1830 thermal-sensors = <&tsens 9>; 1831 1832 trips { 1833 gpu_alert0: trip-point0 { 1834 temperature = <95000>; 1835 hysteresis = <2000>; 1836 type = "hot"; 1837 }; 1838 }; 1839 }; 1840 }; 1841};
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