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msm8998.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/msm8998.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2016, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 6#include <dt-bindings/clock/qcom,gcc-msm8998.h> 7#include <dt-bindings/clock/qcom,gpucc-msm8998.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8998.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/firmware/qcom,scm.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/gpio/gpio.h> 13 14/ { 15 interrupt-parent = <&intc>; 16 17 qcom,msm-id = <292 0x0>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 chosen { }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* We expect the bootloader to fill in the reg */ 27 reg = <0x0 0x80000000 0x0 0x0>; 28 }; 29 30 reserved-memory { 31 #address-cells = <2>; 32 #size-cells = <2>; 33 ranges; 34 35 hyp_mem: memory@85800000 { 36 reg = <0x0 0x85800000 0x0 0x600000>; 37 no-map; 38 }; 39 40 xbl_mem: memory@85e00000 { 41 reg = <0x0 0x85e00000 0x0 0x100000>; 42 no-map; 43 }; 44 45 smem_mem: smem-mem@86000000 { 46 reg = <0x0 0x86000000 0x0 0x200000>; 47 no-map; 48 }; 49 50 tz_mem: memory@86200000 { 51 reg = <0x0 0x86200000 0x0 0x2d00000>; 52 no-map; 53 }; 54 55 rmtfs_mem: memory@88f00000 { 56 compatible = "qcom,rmtfs-mem"; 57 reg = <0x0 0x88f00000 0x0 0x200000>; 58 no-map; 59 60 qcom,client-id = <1>; 61 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 62 }; 63 64 spss_mem: memory@8ab00000 { 65 reg = <0x0 0x8ab00000 0x0 0x700000>; 66 no-map; 67 }; 68 69 adsp_mem: memory@8b200000 { 70 reg = <0x0 0x8b200000 0x0 0x1a00000>; 71 no-map; 72 }; 73 74 mpss_mem: memory@8cc00000 { 75 reg = <0x0 0x8cc00000 0x0 0x7000000>; 76 no-map; 77 }; 78 79 venus_mem: memory@93c00000 { 80 reg = <0x0 0x93c00000 0x0 0x500000>; 81 no-map; 82 }; 83 84 mba_mem: memory@94100000 { 85 reg = <0x0 0x94100000 0x0 0x200000>; 86 no-map; 87 }; 88 89 slpi_mem: memory@94300000 { 90 reg = <0x0 0x94300000 0x0 0xf00000>; 91 no-map; 92 }; 93 94 ipa_fw_mem: memory@95200000 { 95 reg = <0x0 0x95200000 0x0 0x10000>; 96 no-map; 97 }; 98 99 ipa_gsi_mem: memory@95210000 { 100 reg = <0x0 0x95210000 0x0 0x5000>; 101 no-map; 102 }; 103 104 gpu_mem: memory@95600000 { 105 reg = <0x0 0x95600000 0x0 0x100000>; 106 no-map; 107 }; 108 109 wlan_msa_mem: memory@95700000 { 110 reg = <0x0 0x95700000 0x0 0x100000>; 111 no-map; 112 }; 113 114 mdata_mem: mpss-metadata { 115 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>; 116 size = <0x0 0x4000>; 117 no-map; 118 }; 119 }; 120 121 clocks { 122 xo: xo-board { 123 compatible = "fixed-clock"; 124 #clock-cells = <0>; 125 clock-frequency = <19200000>; 126 clock-output-names = "xo_board"; 127 }; 128 129 sleep_clk: sleep-clk { 130 compatible = "fixed-clock"; 131 #clock-cells = <0>; 132 clock-frequency = <32764>; 133 }; 134 }; 135 136 cpus { 137 #address-cells = <2>; 138 #size-cells = <0>; 139 140 cpu0: cpu@0 { 141 device_type = "cpu"; 142 compatible = "qcom,kryo280"; 143 reg = <0x0 0x0>; 144 enable-method = "psci"; 145 capacity-dmips-mhz = <1024>; 146 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 147 next-level-cache = <&l2_0>; 148 l2_0: l2-cache { 149 compatible = "cache"; 150 cache-level = <2>; 151 cache-unified; 152 }; 153 }; 154 155 cpu1: cpu@1 { 156 device_type = "cpu"; 157 compatible = "qcom,kryo280"; 158 reg = <0x0 0x1>; 159 enable-method = "psci"; 160 capacity-dmips-mhz = <1024>; 161 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 162 next-level-cache = <&l2_0>; 163 }; 164 165 cpu2: cpu@2 { 166 device_type = "cpu"; 167 compatible = "qcom,kryo280"; 168 reg = <0x0 0x2>; 169 enable-method = "psci"; 170 capacity-dmips-mhz = <1024>; 171 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 172 next-level-cache = <&l2_0>; 173 }; 174 175 cpu3: cpu@3 { 176 device_type = "cpu"; 177 compatible = "qcom,kryo280"; 178 reg = <0x0 0x3>; 179 enable-method = "psci"; 180 capacity-dmips-mhz = <1024>; 181 cpu-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 182 next-level-cache = <&l2_0>; 183 }; 184 185 cpu4: cpu@100 { 186 device_type = "cpu"; 187 compatible = "qcom,kryo280"; 188 reg = <0x0 0x100>; 189 enable-method = "psci"; 190 capacity-dmips-mhz = <1536>; 191 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 192 next-level-cache = <&l2_1>; 193 l2_1: l2-cache { 194 compatible = "cache"; 195 cache-level = <2>; 196 cache-unified; 197 }; 198 }; 199 200 cpu5: cpu@101 { 201 device_type = "cpu"; 202 compatible = "qcom,kryo280"; 203 reg = <0x0 0x101>; 204 enable-method = "psci"; 205 capacity-dmips-mhz = <1536>; 206 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 207 next-level-cache = <&l2_1>; 208 }; 209 210 cpu6: cpu@102 { 211 device_type = "cpu"; 212 compatible = "qcom,kryo280"; 213 reg = <0x0 0x102>; 214 enable-method = "psci"; 215 capacity-dmips-mhz = <1536>; 216 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 217 next-level-cache = <&l2_1>; 218 }; 219 220 cpu7: cpu@103 { 221 device_type = "cpu"; 222 compatible = "qcom,kryo280"; 223 reg = <0x0 0x103>; 224 enable-method = "psci"; 225 capacity-dmips-mhz = <1536>; 226 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 227 next-level-cache = <&l2_1>; 228 }; 229 230 cpu-map { 231 cluster0 { 232 core0 { 233 cpu = <&cpu0>; 234 }; 235 236 core1 { 237 cpu = <&cpu1>; 238 }; 239 240 core2 { 241 cpu = <&cpu2>; 242 }; 243 244 core3 { 245 cpu = <&cpu3>; 246 }; 247 }; 248 249 cluster1 { 250 core0 { 251 cpu = <&cpu4>; 252 }; 253 254 core1 { 255 cpu = <&cpu5>; 256 }; 257 258 core2 { 259 cpu = <&cpu6>; 260 }; 261 262 core3 { 263 cpu = <&cpu7>; 264 }; 265 }; 266 }; 267 268 idle-states { 269 entry-method = "psci"; 270 271 little_cpu_sleep_0: cpu-sleep-0-0 { 272 compatible = "arm,idle-state"; 273 idle-state-name = "little-retention"; 274 /* CPU Retention (C2D), L2 Active */ 275 arm,psci-suspend-param = <0x00000002>; 276 entry-latency-us = <81>; 277 exit-latency-us = <86>; 278 min-residency-us = <504>; 279 }; 280 281 little_cpu_sleep_1: cpu-sleep-0-1 { 282 compatible = "arm,idle-state"; 283 idle-state-name = "little-power-collapse"; 284 /* CPU + L2 Power Collapse (C3, D4) */ 285 arm,psci-suspend-param = <0x40000003>; 286 entry-latency-us = <814>; 287 exit-latency-us = <4562>; 288 min-residency-us = <9183>; 289 local-timer-stop; 290 }; 291 292 big_cpu_sleep_0: cpu-sleep-1-0 { 293 compatible = "arm,idle-state"; 294 idle-state-name = "big-retention"; 295 /* CPU Retention (C2D), L2 Active */ 296 arm,psci-suspend-param = <0x00000002>; 297 entry-latency-us = <79>; 298 exit-latency-us = <82>; 299 min-residency-us = <1302>; 300 }; 301 302 big_cpu_sleep_1: cpu-sleep-1-1 { 303 compatible = "arm,idle-state"; 304 idle-state-name = "big-power-collapse"; 305 /* CPU + L2 Power Collapse (C3, D4) */ 306 arm,psci-suspend-param = <0x40000003>; 307 entry-latency-us = <724>; 308 exit-latency-us = <2027>; 309 min-residency-us = <9419>; 310 local-timer-stop; 311 }; 312 }; 313 }; 314 315 firmware { 316 scm { 317 compatible = "qcom,scm-msm8998", "qcom,scm"; 318 }; 319 }; 320 321 dsi_opp_table: opp-table-dsi { 322 compatible = "operating-points-v2"; 323 324 opp-131250000 { 325 opp-hz = /bits/ 64 <131250000>; 326 required-opps = <&rpmpd_opp_low_svs>; 327 }; 328 329 opp-210000000 { 330 opp-hz = /bits/ 64 <210000000>; 331 required-opps = <&rpmpd_opp_svs>; 332 }; 333 334 opp-312500000 { 335 opp-hz = /bits/ 64 <312500000>; 336 required-opps = <&rpmpd_opp_nom>; 337 }; 338 }; 339 340 psci { 341 compatible = "arm,psci-1.0"; 342 method = "smc"; 343 }; 344 345 rpm: remoteproc { 346 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc"; 347 348 glink-edge { 349 compatible = "qcom,glink-rpm"; 350 351 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 352 qcom,rpm-msg-ram = <&rpm_msg_ram>; 353 mboxes = <&apcs_glb 0>; 354 355 rpm_requests: rpm-requests { 356 compatible = "qcom,rpm-msm8998", "qcom,glink-smd-rpm"; 357 qcom,glink-channels = "rpm_requests"; 358 359 rpmcc: clock-controller { 360 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc"; 361 clocks = <&xo>; 362 clock-names = "xo"; 363 #clock-cells = <1>; 364 }; 365 366 rpmpd: power-controller { 367 compatible = "qcom,msm8998-rpmpd"; 368 #power-domain-cells = <1>; 369 operating-points-v2 = <&rpmpd_opp_table>; 370 371 rpmpd_opp_table: opp-table { 372 compatible = "operating-points-v2"; 373 374 rpmpd_opp_ret: opp1 { 375 opp-level = <RPM_SMD_LEVEL_RETENTION>; 376 }; 377 378 rpmpd_opp_ret_plus: opp2 { 379 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 380 }; 381 382 rpmpd_opp_min_svs: opp3 { 383 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 384 }; 385 386 rpmpd_opp_low_svs: opp4 { 387 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 388 }; 389 390 rpmpd_opp_svs: opp5 { 391 opp-level = <RPM_SMD_LEVEL_SVS>; 392 }; 393 394 rpmpd_opp_svs_plus: opp6 { 395 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 396 }; 397 398 rpmpd_opp_nom: opp7 { 399 opp-level = <RPM_SMD_LEVEL_NOM>; 400 }; 401 402 rpmpd_opp_nom_plus: opp8 { 403 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 404 }; 405 406 rpmpd_opp_turbo: opp9 { 407 opp-level = <RPM_SMD_LEVEL_TURBO>; 408 }; 409 410 rpmpd_opp_turbo_plus: opp10 { 411 opp-level = <RPM_SMD_LEVEL_BINNING>; 412 }; 413 }; 414 }; 415 }; 416 }; 417 }; 418 419 smem { 420 compatible = "qcom,smem"; 421 memory-region = <&smem_mem>; 422 hwlocks = <&tcsr_mutex 3>; 423 }; 424 425 smp2p-lpass { 426 compatible = "qcom,smp2p"; 427 qcom,smem = <443>, <429>; 428 429 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 430 431 mboxes = <&apcs_glb 10>; 432 433 qcom,local-pid = <0>; 434 qcom,remote-pid = <2>; 435 436 adsp_smp2p_out: master-kernel { 437 qcom,entry-name = "master-kernel"; 438 #qcom,smem-state-cells = <1>; 439 }; 440 441 adsp_smp2p_in: slave-kernel { 442 qcom,entry-name = "slave-kernel"; 443 444 interrupt-controller; 445 #interrupt-cells = <2>; 446 }; 447 }; 448 449 smp2p-mpss { 450 compatible = "qcom,smp2p"; 451 qcom,smem = <435>, <428>; 452 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>; 453 mboxes = <&apcs_glb 14>; 454 qcom,local-pid = <0>; 455 qcom,remote-pid = <1>; 456 457 modem_smp2p_out: master-kernel { 458 qcom,entry-name = "master-kernel"; 459 #qcom,smem-state-cells = <1>; 460 }; 461 462 modem_smp2p_in: slave-kernel { 463 qcom,entry-name = "slave-kernel"; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 }; 467 }; 468 469 smp2p-slpi { 470 compatible = "qcom,smp2p"; 471 qcom,smem = <481>, <430>; 472 interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>; 473 mboxes = <&apcs_glb 26>; 474 qcom,local-pid = <0>; 475 qcom,remote-pid = <3>; 476 477 slpi_smp2p_out: master-kernel { 478 qcom,entry-name = "master-kernel"; 479 #qcom,smem-state-cells = <1>; 480 }; 481 482 slpi_smp2p_in: slave-kernel { 483 qcom,entry-name = "slave-kernel"; 484 interrupt-controller; 485 #interrupt-cells = <2>; 486 }; 487 }; 488 489 thermal-zones { 490 cpu0-thermal { 491 polling-delay-passive = <250>; 492 493 thermal-sensors = <&tsens0 1>; 494 495 trips { 496 cpu0_alert0: trip-point0 { 497 temperature = <75000>; 498 hysteresis = <2000>; 499 type = "passive"; 500 }; 501 502 cpu0_crit: cpu-crit { 503 temperature = <110000>; 504 hysteresis = <2000>; 505 type = "critical"; 506 }; 507 }; 508 }; 509 510 cpu1-thermal { 511 polling-delay-passive = <250>; 512 513 thermal-sensors = <&tsens0 2>; 514 515 trips { 516 cpu1_alert0: trip-point0 { 517 temperature = <75000>; 518 hysteresis = <2000>; 519 type = "passive"; 520 }; 521 522 cpu1_crit: cpu-crit { 523 temperature = <110000>; 524 hysteresis = <2000>; 525 type = "critical"; 526 }; 527 }; 528 }; 529 530 cpu2-thermal { 531 polling-delay-passive = <250>; 532 533 thermal-sensors = <&tsens0 3>; 534 535 trips { 536 cpu2_alert0: trip-point0 { 537 temperature = <75000>; 538 hysteresis = <2000>; 539 type = "passive"; 540 }; 541 542 cpu2_crit: cpu-crit { 543 temperature = <110000>; 544 hysteresis = <2000>; 545 type = "critical"; 546 }; 547 }; 548 }; 549 550 cpu3-thermal { 551 polling-delay-passive = <250>; 552 553 thermal-sensors = <&tsens0 4>; 554 555 trips { 556 cpu3_alert0: trip-point0 { 557 temperature = <75000>; 558 hysteresis = <2000>; 559 type = "passive"; 560 }; 561 562 cpu3_crit: cpu-crit { 563 temperature = <110000>; 564 hysteresis = <2000>; 565 type = "critical"; 566 }; 567 }; 568 }; 569 570 cpu4-thermal { 571 polling-delay-passive = <250>; 572 573 thermal-sensors = <&tsens0 7>; 574 575 trips { 576 cpu4_alert0: trip-point0 { 577 temperature = <75000>; 578 hysteresis = <2000>; 579 type = "passive"; 580 }; 581 582 cpu4_crit: cpu-crit { 583 temperature = <110000>; 584 hysteresis = <2000>; 585 type = "critical"; 586 }; 587 }; 588 }; 589 590 cpu5-thermal { 591 polling-delay-passive = <250>; 592 593 thermal-sensors = <&tsens0 8>; 594 595 trips { 596 cpu5_alert0: trip-point0 { 597 temperature = <75000>; 598 hysteresis = <2000>; 599 type = "passive"; 600 }; 601 602 cpu5_crit: cpu-crit { 603 temperature = <110000>; 604 hysteresis = <2000>; 605 type = "critical"; 606 }; 607 }; 608 }; 609 610 cpu6-thermal { 611 polling-delay-passive = <250>; 612 613 thermal-sensors = <&tsens0 9>; 614 615 trips { 616 cpu6_alert0: trip-point0 { 617 temperature = <75000>; 618 hysteresis = <2000>; 619 type = "passive"; 620 }; 621 622 cpu6_crit: cpu-crit { 623 temperature = <110000>; 624 hysteresis = <2000>; 625 type = "critical"; 626 }; 627 }; 628 }; 629 630 cpu7-thermal { 631 polling-delay-passive = <250>; 632 633 thermal-sensors = <&tsens0 10>; 634 635 trips { 636 cpu7_alert0: trip-point0 { 637 temperature = <75000>; 638 hysteresis = <2000>; 639 type = "passive"; 640 }; 641 642 cpu7_crit: cpu-crit { 643 temperature = <110000>; 644 hysteresis = <2000>; 645 type = "critical"; 646 }; 647 }; 648 }; 649 650 gpu-bottom-thermal { 651 polling-delay-passive = <250>; 652 653 thermal-sensors = <&tsens0 12>; 654 655 trips { 656 gpu1_alert0: trip-point0 { 657 temperature = <90000>; 658 hysteresis = <2000>; 659 type = "hot"; 660 }; 661 }; 662 }; 663 664 gpu-top-thermal { 665 polling-delay-passive = <250>; 666 667 thermal-sensors = <&tsens0 13>; 668 669 trips { 670 gpu2_alert0: trip-point0 { 671 temperature = <90000>; 672 hysteresis = <2000>; 673 type = "hot"; 674 }; 675 }; 676 }; 677 678 clust0-mhm-thermal { 679 polling-delay-passive = <250>; 680 681 thermal-sensors = <&tsens0 5>; 682 683 trips { 684 cluster0_mhm_alert0: trip-point0 { 685 temperature = <90000>; 686 hysteresis = <2000>; 687 type = "hot"; 688 }; 689 }; 690 }; 691 692 clust1-mhm-thermal { 693 polling-delay-passive = <250>; 694 695 thermal-sensors = <&tsens0 6>; 696 697 trips { 698 cluster1_mhm_alert0: trip-point0 { 699 temperature = <90000>; 700 hysteresis = <2000>; 701 type = "hot"; 702 }; 703 }; 704 }; 705 706 cluster1-l2-thermal { 707 polling-delay-passive = <250>; 708 709 thermal-sensors = <&tsens0 11>; 710 711 trips { 712 cluster1_l2_alert0: trip-point0 { 713 temperature = <90000>; 714 hysteresis = <2000>; 715 type = "hot"; 716 }; 717 }; 718 }; 719 720 modem-thermal { 721 polling-delay-passive = <250>; 722 723 thermal-sensors = <&tsens1 1>; 724 725 trips { 726 modem_alert0: trip-point0 { 727 temperature = <90000>; 728 hysteresis = <2000>; 729 type = "hot"; 730 }; 731 }; 732 }; 733 734 mem-thermal { 735 polling-delay-passive = <250>; 736 737 thermal-sensors = <&tsens1 2>; 738 739 trips { 740 mem_alert0: trip-point0 { 741 temperature = <90000>; 742 hysteresis = <2000>; 743 type = "hot"; 744 }; 745 }; 746 }; 747 748 wlan-thermal { 749 polling-delay-passive = <250>; 750 751 thermal-sensors = <&tsens1 3>; 752 753 trips { 754 wlan_alert0: trip-point0 { 755 temperature = <90000>; 756 hysteresis = <2000>; 757 type = "hot"; 758 }; 759 }; 760 }; 761 762 q6-dsp-thermal { 763 polling-delay-passive = <250>; 764 765 thermal-sensors = <&tsens1 4>; 766 767 trips { 768 q6_dsp_alert0: trip-point0 { 769 temperature = <90000>; 770 hysteresis = <2000>; 771 type = "hot"; 772 }; 773 }; 774 }; 775 776 camera-thermal { 777 polling-delay-passive = <250>; 778 779 thermal-sensors = <&tsens1 5>; 780 781 trips { 782 camera_alert0: trip-point0 { 783 temperature = <90000>; 784 hysteresis = <2000>; 785 type = "hot"; 786 }; 787 }; 788 }; 789 790 multimedia-thermal { 791 polling-delay-passive = <250>; 792 793 thermal-sensors = <&tsens1 6>; 794 795 trips { 796 multimedia_alert0: trip-point0 { 797 temperature = <90000>; 798 hysteresis = <2000>; 799 type = "hot"; 800 }; 801 }; 802 }; 803 }; 804 805 timer { 806 compatible = "arm,armv8-timer"; 807 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 808 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 809 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 810 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 811 }; 812 813 soc: soc@0 { 814 #address-cells = <1>; 815 #size-cells = <1>; 816 ranges = <0 0 0 0xffffffff>; 817 compatible = "simple-bus"; 818 819 gcc: clock-controller@100000 { 820 compatible = "qcom,gcc-msm8998"; 821 #clock-cells = <1>; 822 #reset-cells = <1>; 823 #power-domain-cells = <1>; 824 reg = <0x00100000 0xb0000>; 825 826 clock-names = "xo", "sleep_clk"; 827 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 828 829 /* 830 * The hypervisor typically configures the memory region where these clocks 831 * reside as read-only for the HLOS. If the HLOS tried to enable or disable 832 * these clocks on a device with such configuration (e.g. because they are 833 * enabled but unused during boot-up), the device will most likely decide 834 * to reboot. 835 * In light of that, we are conservative here and we list all such clocks 836 * as protected. The board dts (or a user-supplied dts) can override the 837 * list of protected clocks if it differs from the norm, and it is in fact 838 * desired for the HLOS to manage these clocks 839 */ 840 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>, 841 <SSC_XO>, 842 <SSC_CNOC_AHBS_CLK>; 843 }; 844 845 rpm_msg_ram: sram@778000 { 846 compatible = "qcom,rpm-msg-ram"; 847 reg = <0x00778000 0x7000>; 848 }; 849 850 qfprom: qfprom@784000 { 851 compatible = "qcom,msm8998-qfprom", "qcom,qfprom"; 852 reg = <0x00784000 0x621c>; 853 #address-cells = <1>; 854 #size-cells = <1>; 855 856 qusb2_hstx_trim: hstx-trim@23a { 857 reg = <0x23a 0x1>; 858 bits = <0 4>; 859 }; 860 }; 861 862 tsens0: thermal@10ab000 { 863 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 864 reg = <0x010ab000 0x1000>, /* TM */ 865 <0x010aa000 0x1000>; /* SROT */ 866 #qcom,sensors = <14>; 867 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 868 <GIC_SPI 445 IRQ_TYPE_LEVEL_HIGH>; 869 interrupt-names = "uplow", "critical"; 870 #thermal-sensor-cells = <1>; 871 }; 872 873 tsens1: thermal@10ae000 { 874 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2"; 875 reg = <0x010ae000 0x1000>, /* TM */ 876 <0x010ad000 0x1000>; /* SROT */ 877 #qcom,sensors = <8>; 878 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 879 <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>; 880 interrupt-names = "uplow", "critical"; 881 #thermal-sensor-cells = <1>; 882 }; 883 884 anoc1_smmu: iommu@1680000 { 885 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 886 reg = <0x01680000 0x10000>; 887 #iommu-cells = <1>; 888 889 #global-interrupts = <0>; 890 interrupts = 891 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>, 892 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>, 893 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>, 894 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>, 895 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>, 896 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>; 897 }; 898 899 anoc2_smmu: iommu@16c0000 { 900 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 901 reg = <0x016c0000 0x40000>; 902 #iommu-cells = <1>; 903 904 #global-interrupts = <0>; 905 interrupts = 906 <GIC_SPI 373 IRQ_TYPE_EDGE_RISING>, 907 <GIC_SPI 374 IRQ_TYPE_EDGE_RISING>, 908 <GIC_SPI 375 IRQ_TYPE_EDGE_RISING>, 909 <GIC_SPI 376 IRQ_TYPE_EDGE_RISING>, 910 <GIC_SPI 377 IRQ_TYPE_EDGE_RISING>, 911 <GIC_SPI 378 IRQ_TYPE_EDGE_RISING>, 912 <GIC_SPI 462 IRQ_TYPE_EDGE_RISING>, 913 <GIC_SPI 463 IRQ_TYPE_EDGE_RISING>, 914 <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 915 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>; 916 }; 917 918 pcie0: pcie@1c00000 { 919 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996"; 920 reg = <0x01c00000 0x2000>, 921 <0x1b000000 0xf1d>, 922 <0x1b000f20 0xa8>, 923 <0x1b100000 0x100000>; 924 reg-names = "parf", "dbi", "elbi", "config"; 925 device_type = "pci"; 926 linux,pci-domain = <0>; 927 bus-range = <0x00 0xff>; 928 #address-cells = <3>; 929 #size-cells = <2>; 930 num-lanes = <1>; 931 phys = <&pcie_phy>; 932 phy-names = "pciephy"; 933 status = "disabled"; 934 935 ranges = <0x01000000 0x0 0x00000000 0x1b200000 0x0 0x100000>, 936 <0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>; 937 938 #interrupt-cells = <1>; 939 interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 941 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 942 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 943 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 944 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 945 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 946 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 947 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 948 interrupt-names = "msi0", 949 "msi1", 950 "msi2", 951 "msi3", 952 "msi4", 953 "msi5", 954 "msi6", 955 "msi7", 956 "global"; 957 interrupt-map-mask = <0 0 0 0x7>; 958 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>, 959 <0 0 0 2 &intc 0 0 136 IRQ_TYPE_LEVEL_HIGH>, 960 <0 0 0 3 &intc 0 0 138 IRQ_TYPE_LEVEL_HIGH>, 961 <0 0 0 4 &intc 0 0 139 IRQ_TYPE_LEVEL_HIGH>; 962 963 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 964 <&gcc GCC_PCIE_0_AUX_CLK>, 965 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 966 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 967 <&gcc GCC_PCIE_0_SLV_AXI_CLK>; 968 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave"; 969 970 power-domains = <&gcc PCIE_0_GDSC>; 971 iommu-map = <0x100 &anoc1_smmu 0x1480 1>; 972 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; 973 974 pcie@0 { 975 device_type = "pci"; 976 reg = <0x0 0x0 0x0 0x0 0x0>; 977 bus-range = <0x01 0xff>; 978 979 #address-cells = <3>; 980 #size-cells = <2>; 981 ranges; 982 }; 983 }; 984 985 pcie_phy: phy@1c06000 { 986 compatible = "qcom,msm8998-qmp-pcie-phy"; 987 reg = <0x01c06000 0x1000>; 988 status = "disabled"; 989 990 clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>, 991 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 992 <&gcc GCC_PCIE_CLKREF_CLK>, 993 <&gcc GCC_PCIE_0_PIPE_CLK>; 994 clock-names = "aux", 995 "cfg_ahb", 996 "ref", 997 "pipe"; 998 999 clock-output-names = "pcie_0_pipe_clk_src"; 1000 #clock-cells = <0>; 1001 1002 #phy-cells = <0>; 1003 1004 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>; 1005 reset-names = "phy", "common"; 1006 1007 vdda-phy-supply = <&vreg_l1a_0p875>; 1008 vdda-pll-supply = <&vreg_l2a_1p2>; 1009 }; 1010 1011 ufshc: ufshc@1da4000 { 1012 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 1013 reg = <0x01da4000 0x2500>; 1014 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 1015 phys = <&ufsphy>; 1016 phy-names = "ufsphy"; 1017 lanes-per-direction = <2>; 1018 power-domains = <&gcc UFS_GDSC>; 1019 status = "disabled"; 1020 #reset-cells = <1>; 1021 1022 clock-names = 1023 "core_clk", 1024 "bus_aggr_clk", 1025 "iface_clk", 1026 "core_clk_unipro", 1027 "ref_clk", 1028 "tx_lane0_sync_clk", 1029 "rx_lane0_sync_clk", 1030 "rx_lane1_sync_clk"; 1031 clocks = 1032 <&gcc GCC_UFS_AXI_CLK>, 1033 <&gcc GCC_AGGRE1_UFS_AXI_CLK>, 1034 <&gcc GCC_UFS_AHB_CLK>, 1035 <&gcc GCC_UFS_UNIPRO_CORE_CLK>, 1036 <&rpmcc RPM_SMD_LN_BB_CLK1>, 1037 <&gcc GCC_UFS_TX_SYMBOL_0_CLK>, 1038 <&gcc GCC_UFS_RX_SYMBOL_0_CLK>, 1039 <&gcc GCC_UFS_RX_SYMBOL_1_CLK>; 1040 freq-table-hz = 1041 <50000000 200000000>, 1042 <0 0>, 1043 <0 0>, 1044 <37500000 150000000>, 1045 <0 0>, 1046 <0 0>, 1047 <0 0>, 1048 <0 0>; 1049 1050 resets = <&gcc GCC_UFS_BCR>; 1051 reset-names = "rst"; 1052 }; 1053 1054 ufsphy: phy@1da7000 { 1055 compatible = "qcom,msm8998-qmp-ufs-phy"; 1056 reg = <0x01da7000 0x1000>; 1057 1058 clocks = <&rpmcc RPM_SMD_LN_BB_CLK1>, 1059 <&gcc GCC_UFS_PHY_AUX_CLK>, 1060 <&gcc GCC_UFS_CLKREF_CLK>; 1061 clock-names = "ref", 1062 "ref_aux", 1063 "qref"; 1064 1065 reset-names = "ufsphy"; 1066 resets = <&ufshc 0>; 1067 1068 #phy-cells = <0>; 1069 status = "disabled"; 1070 }; 1071 1072 tcsr_mutex: hwlock@1f40000 { 1073 compatible = "qcom,tcsr-mutex"; 1074 reg = <0x01f40000 0x20000>; 1075 #hwlock-cells = <1>; 1076 }; 1077 1078 tcsr_regs_1: syscon@1f60000 { 1079 compatible = "qcom,msm8998-tcsr", "syscon"; 1080 reg = <0x01f60000 0x20000>; 1081 }; 1082 1083 tcsr_regs_2: syscon@1fc0000 { 1084 compatible = "qcom,msm8998-tcsr", "syscon"; 1085 reg = <0x01fc0000 0x26000>; 1086 }; 1087 1088 tlmm: pinctrl@3400000 { 1089 compatible = "qcom,msm8998-pinctrl"; 1090 reg = <0x03400000 0xc00000>; 1091 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1092 gpio-ranges = <&tlmm 0 0 150>; 1093 gpio-controller; 1094 #gpio-cells = <2>; 1095 interrupt-controller; 1096 #interrupt-cells = <2>; 1097 1098 sdc2_on: sdc2-on-state { 1099 clk-pins { 1100 pins = "sdc2_clk"; 1101 drive-strength = <16>; 1102 bias-disable; 1103 }; 1104 1105 cmd-pins { 1106 pins = "sdc2_cmd"; 1107 drive-strength = <10>; 1108 bias-pull-up; 1109 }; 1110 1111 data-pins { 1112 pins = "sdc2_data"; 1113 drive-strength = <10>; 1114 bias-pull-up; 1115 }; 1116 }; 1117 1118 sdc2_off: sdc2-off-state { 1119 clk-pins { 1120 pins = "sdc2_clk"; 1121 drive-strength = <2>; 1122 bias-disable; 1123 }; 1124 1125 cmd-pins { 1126 pins = "sdc2_cmd"; 1127 drive-strength = <2>; 1128 bias-pull-up; 1129 }; 1130 1131 data-pins { 1132 pins = "sdc2_data"; 1133 drive-strength = <2>; 1134 bias-pull-up; 1135 }; 1136 }; 1137 1138 sdc2_cd: sdc2-cd-state { 1139 pins = "gpio95"; 1140 function = "gpio"; 1141 bias-pull-up; 1142 drive-strength = <2>; 1143 }; 1144 1145 blsp1_uart3_on: blsp1-uart3-on-state { 1146 tx-pins { 1147 pins = "gpio45"; 1148 function = "blsp_uart3_a"; 1149 drive-strength = <2>; 1150 bias-disable; 1151 }; 1152 1153 rx-pins { 1154 pins = "gpio46"; 1155 function = "blsp_uart3_a"; 1156 drive-strength = <2>; 1157 bias-disable; 1158 }; 1159 1160 cts-pins { 1161 pins = "gpio47"; 1162 function = "blsp_uart3_a"; 1163 drive-strength = <2>; 1164 bias-disable; 1165 }; 1166 1167 rfr-pins { 1168 pins = "gpio48"; 1169 function = "blsp_uart3_a"; 1170 drive-strength = <2>; 1171 bias-disable; 1172 }; 1173 }; 1174 1175 blsp1_i2c1_default: blsp1-i2c1-default-state { 1176 pins = "gpio2", "gpio3"; 1177 function = "blsp_i2c1"; 1178 drive-strength = <2>; 1179 bias-disable; 1180 }; 1181 1182 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state { 1183 pins = "gpio2", "gpio3"; 1184 function = "blsp_i2c1"; 1185 drive-strength = <2>; 1186 bias-pull-up; 1187 }; 1188 1189 blsp1_i2c2_default: blsp1-i2c2-default-state { 1190 pins = "gpio32", "gpio33"; 1191 function = "blsp_i2c2"; 1192 drive-strength = <2>; 1193 bias-disable; 1194 }; 1195 1196 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state { 1197 pins = "gpio32", "gpio33"; 1198 function = "blsp_i2c2"; 1199 drive-strength = <2>; 1200 bias-pull-up; 1201 }; 1202 1203 blsp1_i2c3_default: blsp1-i2c3-default-state { 1204 pins = "gpio47", "gpio48"; 1205 function = "blsp_i2c3"; 1206 drive-strength = <2>; 1207 bias-disable; 1208 }; 1209 1210 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 1211 pins = "gpio47", "gpio48"; 1212 function = "blsp_i2c3"; 1213 drive-strength = <2>; 1214 bias-pull-up; 1215 }; 1216 1217 blsp1_i2c4_default: blsp1-i2c4-default-state { 1218 pins = "gpio10", "gpio11"; 1219 function = "blsp_i2c4"; 1220 drive-strength = <2>; 1221 bias-disable; 1222 }; 1223 1224 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 1225 pins = "gpio10", "gpio11"; 1226 function = "blsp_i2c4"; 1227 drive-strength = <2>; 1228 bias-pull-up; 1229 }; 1230 1231 blsp1_i2c5_default: blsp1-i2c5-default-state { 1232 pins = "gpio87", "gpio88"; 1233 function = "blsp_i2c5"; 1234 drive-strength = <2>; 1235 bias-disable; 1236 }; 1237 1238 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state { 1239 pins = "gpio87", "gpio88"; 1240 function = "blsp_i2c5"; 1241 drive-strength = <2>; 1242 bias-pull-up; 1243 }; 1244 1245 blsp1_i2c6_default: blsp1-i2c6-default-state { 1246 pins = "gpio43", "gpio44"; 1247 function = "blsp_i2c6"; 1248 drive-strength = <2>; 1249 bias-disable; 1250 }; 1251 1252 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state { 1253 pins = "gpio43", "gpio44"; 1254 function = "blsp_i2c6"; 1255 drive-strength = <2>; 1256 bias-pull-up; 1257 }; 1258 1259 blsp1_spi_b_default: blsp1-spi-b-default-state { 1260 pins = "gpio23", "gpio28"; 1261 function = "blsp1_spi_b"; 1262 drive-strength = <6>; 1263 bias-disable; 1264 }; 1265 1266 blsp1_spi1_default: blsp1-spi1-default-state { 1267 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 1268 function = "blsp_spi1"; 1269 drive-strength = <6>; 1270 bias-disable; 1271 }; 1272 1273 blsp1_spi2_default: blsp1-spi2-default-state { 1274 pins = "gpio31", "gpio34", "gpio32", "gpio33"; 1275 function = "blsp_spi2"; 1276 drive-strength = <6>; 1277 bias-disable; 1278 }; 1279 1280 blsp1_spi3_default: blsp1-spi3-default-state { 1281 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 1282 function = "blsp_spi2"; 1283 drive-strength = <6>; 1284 bias-disable; 1285 }; 1286 1287 blsp1_spi4_default: blsp1-spi4-default-state { 1288 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 1289 function = "blsp_spi4"; 1290 drive-strength = <6>; 1291 bias-disable; 1292 }; 1293 1294 blsp1_spi5_default: blsp1-spi5-default-state { 1295 pins = "gpio85", "gpio86", "gpio87", "gpio88"; 1296 function = "blsp_spi5"; 1297 drive-strength = <6>; 1298 bias-disable; 1299 }; 1300 1301 blsp1_spi6_default: blsp1-spi6-default-state { 1302 pins = "gpio41", "gpio42", "gpio43", "gpio44"; 1303 function = "blsp_spi6"; 1304 drive-strength = <6>; 1305 bias-disable; 1306 }; 1307 1308 1309 /* 6 interfaces per QUP, BLSP2 indexes are numbered (n)+6 */ 1310 blsp2_i2c1_default: blsp2-i2c1-default-state { 1311 pins = "gpio55", "gpio56"; 1312 function = "blsp_i2c7"; 1313 drive-strength = <2>; 1314 bias-disable; 1315 }; 1316 1317 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 1318 pins = "gpio55", "gpio56"; 1319 function = "blsp_i2c7"; 1320 drive-strength = <2>; 1321 bias-pull-up; 1322 }; 1323 1324 blsp2_i2c2_default: blsp2-i2c2-default-state { 1325 pins = "gpio6", "gpio7"; 1326 function = "blsp_i2c8"; 1327 drive-strength = <2>; 1328 bias-disable; 1329 }; 1330 1331 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state { 1332 pins = "gpio6", "gpio7"; 1333 function = "blsp_i2c8"; 1334 drive-strength = <2>; 1335 bias-pull-up; 1336 }; 1337 1338 blsp2_i2c3_default: blsp2-i2c3-default-state { 1339 pins = "gpio51", "gpio52"; 1340 function = "blsp_i2c9"; 1341 drive-strength = <2>; 1342 bias-disable; 1343 }; 1344 1345 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state { 1346 pins = "gpio51", "gpio52"; 1347 function = "blsp_i2c9"; 1348 drive-strength = <2>; 1349 bias-pull-up; 1350 }; 1351 1352 blsp2_i2c4_default: blsp2-i2c4-default-state { 1353 pins = "gpio67", "gpio68"; 1354 function = "blsp_i2c10"; 1355 drive-strength = <2>; 1356 bias-disable; 1357 }; 1358 1359 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state { 1360 pins = "gpio67", "gpio68"; 1361 function = "blsp_i2c10"; 1362 drive-strength = <2>; 1363 bias-pull-up; 1364 }; 1365 1366 blsp2_i2c5_default: blsp2-i2c5-default-state { 1367 pins = "gpio60", "gpio61"; 1368 function = "blsp_i2c11"; 1369 drive-strength = <2>; 1370 bias-disable; 1371 }; 1372 1373 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state { 1374 pins = "gpio60", "gpio61"; 1375 function = "blsp_i2c11"; 1376 drive-strength = <2>; 1377 bias-pull-up; 1378 }; 1379 1380 blsp2_i2c6_default: blsp2-i2c6-default-state { 1381 pins = "gpio83", "gpio84"; 1382 function = "blsp_i2c12"; 1383 drive-strength = <2>; 1384 bias-disable; 1385 }; 1386 1387 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { 1388 pins = "gpio83", "gpio84"; 1389 function = "blsp_i2c12"; 1390 drive-strength = <2>; 1391 bias-pull-up; 1392 }; 1393 1394 blsp2_spi1_default: blsp2-spi1-default-state { 1395 pins = "gpio53", "gpio54", "gpio55", "gpio56"; 1396 function = "blsp_spi7"; 1397 drive-strength = <6>; 1398 bias-disable; 1399 }; 1400 1401 blsp2_spi2_default: blsp2-spi2-default-state { 1402 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 1403 function = "blsp_spi8"; 1404 drive-strength = <6>; 1405 bias-disable; 1406 }; 1407 1408 blsp2_spi3_default: blsp2-spi3-default-state { 1409 pins = "gpio49", "gpio50", "gpio51", "gpio52"; 1410 function = "blsp_spi9"; 1411 drive-strength = <6>; 1412 bias-disable; 1413 }; 1414 1415 blsp2_spi4_default: blsp2-spi4-default-state { 1416 pins = "gpio65", "gpio66", "gpio67", "gpio68"; 1417 function = "blsp_spi10"; 1418 drive-strength = <6>; 1419 bias-disable; 1420 }; 1421 1422 blsp2_spi5_default: blsp2-spi5-default-state { 1423 pins = "gpio58", "gpio59", "gpio60", "gpio61"; 1424 function = "blsp_spi11"; 1425 drive-strength = <6>; 1426 bias-disable; 1427 }; 1428 1429 blsp2_spi6_default: blsp2-spi6-default-state { 1430 pins = "gpio81", "gpio82", "gpio83", "gpio84"; 1431 function = "blsp_spi12"; 1432 drive-strength = <6>; 1433 bias-disable; 1434 }; 1435 1436 hdmi_cec_default: hdmi-cec-default-state { 1437 pins = "gpio31"; 1438 function = "hdmi_cec"; 1439 drive-strength = <2>; 1440 bias-pull-up; 1441 }; 1442 1443 hdmi_ddc_default: hdmi-ddc-default-state { 1444 pins = "gpio32", "gpio33"; 1445 function = "hdmi_ddc"; 1446 drive-strength = <2>; 1447 bias-pull-up; 1448 }; 1449 1450 hdmi_hpd_default: hdmi-hpd-default-state { 1451 pins = "gpio34"; 1452 function = "hdmi_hot"; 1453 drive-strength = <16>; 1454 bias-pull-down; 1455 }; 1456 1457 hdmi_hpd_sleep: hdmi-hpd-sleep-state { 1458 pins = "gpio34"; 1459 function = "hdmi_hot"; 1460 drive-strength = <2>; 1461 bias-pull-down; 1462 }; 1463 }; 1464 1465 remoteproc_mss: remoteproc@4080000 { 1466 compatible = "qcom,msm8998-mss-pil"; 1467 reg = <0x04080000 0x100>, <0x04180000 0x20>; 1468 reg-names = "qdsp6", "rmb"; 1469 1470 interrupts-extended = 1471 <&intc GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 1472 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1473 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1474 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1475 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 1476 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 1477 interrupt-names = "wdog", "fatal", "ready", 1478 "handover", "stop-ack", 1479 "shutdown-ack"; 1480 1481 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1482 <&gcc GCC_BIMC_MSS_Q6_AXI_CLK>, 1483 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1484 <&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>, 1485 <&gcc GCC_MSS_SNOC_AXI_CLK>, 1486 <&gcc GCC_MSS_MNOC_BIMC_AXI_CLK>, 1487 <&rpmcc RPM_SMD_QDSS_CLK>, 1488 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1489 clock-names = "iface", "bus", "mem", "gpll0_mss", 1490 "snoc_axi", "mnoc_axi", "qdss", "xo"; 1491 1492 qcom,smem-states = <&modem_smp2p_out 0>; 1493 qcom,smem-state-names = "stop"; 1494 1495 resets = <&gcc GCC_MSS_RESTART>; 1496 reset-names = "mss_restart"; 1497 1498 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>; 1499 1500 power-domains = <&rpmpd MSM8998_VDDCX>, 1501 <&rpmpd MSM8998_VDDMX>; 1502 power-domain-names = "cx", "mx"; 1503 1504 status = "disabled"; 1505 1506 mba { 1507 memory-region = <&mba_mem>; 1508 }; 1509 1510 mpss { 1511 memory-region = <&mpss_mem>; 1512 }; 1513 1514 metadata { 1515 memory-region = <&mdata_mem>; 1516 }; 1517 1518 glink-edge { 1519 interrupts = <GIC_SPI 452 IRQ_TYPE_EDGE_RISING>; 1520 label = "modem"; 1521 qcom,remote-pid = <1>; 1522 mboxes = <&apcs_glb 15>; 1523 }; 1524 }; 1525 1526 adreno_gpu: gpu@5000000 { 1527 compatible = "qcom,adreno-540.1", "qcom,adreno"; 1528 reg = <0x05000000 0x40000>; 1529 reg-names = "kgsl_3d0_reg_memory"; 1530 1531 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1532 <&gpucc RBBMTIMER_CLK>, 1533 <&gcc GCC_BIMC_GFX_CLK>, 1534 <&gcc GCC_GPU_BIMC_GFX_CLK>, 1535 <&gpucc RBCPR_CLK>, 1536 <&gpucc GFX3D_CLK>; 1537 clock-names = "iface", 1538 "rbbmtimer", 1539 "mem", 1540 "mem_iface", 1541 "rbcpr", 1542 "core"; 1543 1544 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1545 iommus = <&adreno_smmu 0>; 1546 operating-points-v2 = <&gpu_opp_table>; 1547 power-domains = <&rpmpd MSM8998_VDDMX>; 1548 status = "disabled"; 1549 1550 gpu_opp_table: opp-table { 1551 compatible = "operating-points-v2"; 1552 opp-710000097 { 1553 opp-hz = /bits/ 64 <710000097>; 1554 opp-level = <RPM_SMD_LEVEL_TURBO>; 1555 opp-supported-hw = <0xff>; 1556 }; 1557 1558 opp-670000048 { 1559 opp-hz = /bits/ 64 <670000048>; 1560 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 1561 opp-supported-hw = <0xff>; 1562 }; 1563 1564 opp-596000097 { 1565 opp-hz = /bits/ 64 <596000097>; 1566 opp-level = <RPM_SMD_LEVEL_NOM>; 1567 opp-supported-hw = <0xff>; 1568 }; 1569 1570 opp-515000097 { 1571 opp-hz = /bits/ 64 <515000097>; 1572 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 1573 opp-supported-hw = <0xff>; 1574 }; 1575 1576 opp-414000000 { 1577 opp-hz = /bits/ 64 <414000000>; 1578 opp-level = <RPM_SMD_LEVEL_SVS>; 1579 opp-supported-hw = <0xff>; 1580 }; 1581 1582 opp-342000000 { 1583 opp-hz = /bits/ 64 <342000000>; 1584 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 1585 opp-supported-hw = <0xff>; 1586 }; 1587 1588 opp-257000000 { 1589 opp-hz = /bits/ 64 <257000000>; 1590 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 1591 opp-supported-hw = <0xff>; 1592 }; 1593 }; 1594 }; 1595 1596 adreno_smmu: iommu@5040000 { 1597 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1598 reg = <0x05040000 0x10000>; 1599 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1600 <&gcc GCC_BIMC_GFX_CLK>, 1601 <&gcc GCC_GPU_BIMC_GFX_CLK>; 1602 clock-names = "iface", "mem", "mem_iface"; 1603 1604 #global-interrupts = <0>; 1605 #iommu-cells = <1>; 1606 interrupts = 1607 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1610 /* 1611 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the 1612 * GPU-CX for SMMU but we need both of them up for Adreno. 1613 * Contemporarily, we also need to manage the VDDMX rpmpd 1614 * domain in the Adreno driver. 1615 * Enable GPU CX/GX GDSCs here so that we can manage the 1616 * SoC VDDMX RPM Power Domain in the Adreno driver. 1617 */ 1618 power-domains = <&gpucc GPU_GX_GDSC>; 1619 }; 1620 1621 gpucc: clock-controller@5065000 { 1622 compatible = "qcom,msm8998-gpucc"; 1623 #clock-cells = <1>; 1624 #reset-cells = <1>; 1625 #power-domain-cells = <1>; 1626 reg = <0x05065000 0x9000>; 1627 1628 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1629 <&gcc GCC_GPU_GPLL0_CLK>; 1630 clock-names = "xo", 1631 "gpll0"; 1632 }; 1633 1634 lpass_q6_smmu: iommu@5100000 { 1635 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 1636 reg = <0x05100000 0x40000>; 1637 clocks = <&gcc HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>; 1638 clock-names = "bus"; 1639 1640 #global-interrupts = <0>; 1641 #iommu-cells = <1>; 1642 interrupts = 1643 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1644 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 1645 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 1646 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1647 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1648 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1649 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1650 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1651 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1652 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1653 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1654 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1655 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 1656 1657 power-domains = <&gcc LPASS_ADSP_GDSC>; 1658 status = "disabled"; 1659 }; 1660 1661 remoteproc_slpi: remoteproc@5800000 { 1662 compatible = "qcom,msm8998-slpi-pas"; 1663 reg = <0x05800000 0x4040>; 1664 1665 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>, 1666 <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1667 <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1668 <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1669 <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1670 interrupt-names = "wdog", "fatal", "ready", 1671 "handover", "stop-ack"; 1672 1673 px-supply = <&vreg_lvs2a_1p8>; 1674 1675 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 1676 clock-names = "xo"; 1677 1678 memory-region = <&slpi_mem>; 1679 1680 qcom,smem-states = <&slpi_smp2p_out 0>; 1681 qcom,smem-state-names = "stop"; 1682 1683 power-domains = <&rpmpd MSM8998_SSCCX>; 1684 power-domain-names = "ssc_cx"; 1685 1686 status = "disabled"; 1687 1688 glink-edge { 1689 interrupts = <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>; 1690 label = "dsps"; 1691 qcom,remote-pid = <3>; 1692 mboxes = <&apcs_glb 27>; 1693 }; 1694 }; 1695 1696 stm: stm@6002000 { 1697 compatible = "arm,coresight-stm", "arm,primecell"; 1698 reg = <0x06002000 0x1000>, 1699 <0x16280000 0x180000>; 1700 reg-names = "stm-base", "stm-stimulus-base"; 1701 status = "disabled"; 1702 1703 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1704 clock-names = "apb_pclk", "atclk"; 1705 1706 out-ports { 1707 port { 1708 stm_out: endpoint { 1709 remote-endpoint = <&funnel0_in7>; 1710 }; 1711 }; 1712 }; 1713 }; 1714 1715 funnel1: funnel@6041000 { 1716 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1717 reg = <0x06041000 0x1000>; 1718 status = "disabled"; 1719 1720 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1721 clock-names = "apb_pclk", "atclk"; 1722 1723 out-ports { 1724 port { 1725 funnel0_out: endpoint { 1726 remote-endpoint = 1727 <&merge_funnel_in0>; 1728 }; 1729 }; 1730 }; 1731 1732 in-ports { 1733 #address-cells = <1>; 1734 #size-cells = <0>; 1735 1736 port@7 { 1737 reg = <7>; 1738 funnel0_in7: endpoint { 1739 remote-endpoint = <&stm_out>; 1740 }; 1741 }; 1742 }; 1743 }; 1744 1745 funnel2: funnel@6042000 { 1746 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1747 reg = <0x06042000 0x1000>; 1748 status = "disabled"; 1749 1750 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1751 clock-names = "apb_pclk", "atclk"; 1752 1753 out-ports { 1754 port { 1755 funnel1_out: endpoint { 1756 remote-endpoint = 1757 <&merge_funnel_in1>; 1758 }; 1759 }; 1760 }; 1761 1762 in-ports { 1763 #address-cells = <1>; 1764 #size-cells = <0>; 1765 1766 port@6 { 1767 reg = <6>; 1768 funnel1_in6: endpoint { 1769 remote-endpoint = 1770 <&apss_merge_funnel_out>; 1771 }; 1772 }; 1773 }; 1774 }; 1775 1776 funnel3: funnel@6045000 { 1777 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 1778 reg = <0x06045000 0x1000>; 1779 status = "disabled"; 1780 1781 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1782 clock-names = "apb_pclk", "atclk"; 1783 1784 out-ports { 1785 port { 1786 merge_funnel_out: endpoint { 1787 remote-endpoint = 1788 <&etf_in>; 1789 }; 1790 }; 1791 }; 1792 1793 in-ports { 1794 #address-cells = <1>; 1795 #size-cells = <0>; 1796 1797 port@0 { 1798 reg = <0>; 1799 merge_funnel_in0: endpoint { 1800 remote-endpoint = 1801 <&funnel0_out>; 1802 }; 1803 }; 1804 1805 port@1 { 1806 reg = <1>; 1807 merge_funnel_in1: endpoint { 1808 remote-endpoint = 1809 <&funnel1_out>; 1810 }; 1811 }; 1812 }; 1813 }; 1814 1815 replicator1: replicator@6046000 { 1816 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 1817 reg = <0x06046000 0x1000>; 1818 status = "disabled"; 1819 1820 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1821 clock-names = "apb_pclk", "atclk"; 1822 1823 out-ports { 1824 port { 1825 replicator_out: endpoint { 1826 remote-endpoint = <&etr_in>; 1827 }; 1828 }; 1829 }; 1830 1831 in-ports { 1832 port { 1833 replicator_in: endpoint { 1834 remote-endpoint = <&etf_out>; 1835 }; 1836 }; 1837 }; 1838 }; 1839 1840 etf: etf@6047000 { 1841 compatible = "arm,coresight-tmc", "arm,primecell"; 1842 reg = <0x06047000 0x1000>; 1843 status = "disabled"; 1844 1845 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1846 clock-names = "apb_pclk", "atclk"; 1847 1848 out-ports { 1849 port { 1850 etf_out: endpoint { 1851 remote-endpoint = 1852 <&replicator_in>; 1853 }; 1854 }; 1855 }; 1856 1857 in-ports { 1858 port { 1859 etf_in: endpoint { 1860 remote-endpoint = 1861 <&merge_funnel_out>; 1862 }; 1863 }; 1864 }; 1865 }; 1866 1867 etr: etr@6048000 { 1868 compatible = "arm,coresight-tmc", "arm,primecell"; 1869 reg = <0x06048000 0x1000>; 1870 status = "disabled"; 1871 1872 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1873 clock-names = "apb_pclk", "atclk"; 1874 arm,scatter-gather; 1875 1876 in-ports { 1877 port { 1878 etr_in: endpoint { 1879 remote-endpoint = 1880 <&replicator_out>; 1881 }; 1882 }; 1883 }; 1884 }; 1885 1886 etm1: etm@7840000 { 1887 compatible = "arm,coresight-etm4x", "arm,primecell"; 1888 reg = <0x07840000 0x1000>; 1889 status = "disabled"; 1890 1891 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1892 clock-names = "apb_pclk", "atclk"; 1893 1894 cpu = <&cpu0>; 1895 1896 out-ports { 1897 port { 1898 etm0_out: endpoint { 1899 remote-endpoint = 1900 <&apss_funnel_in0>; 1901 }; 1902 }; 1903 }; 1904 }; 1905 1906 etm2: etm@7940000 { 1907 compatible = "arm,coresight-etm4x", "arm,primecell"; 1908 reg = <0x07940000 0x1000>; 1909 status = "disabled"; 1910 1911 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1912 clock-names = "apb_pclk", "atclk"; 1913 1914 cpu = <&cpu1>; 1915 1916 out-ports { 1917 port { 1918 etm1_out: endpoint { 1919 remote-endpoint = 1920 <&apss_funnel_in1>; 1921 }; 1922 }; 1923 }; 1924 }; 1925 1926 etm3: etm@7a40000 { 1927 compatible = "arm,coresight-etm4x", "arm,primecell"; 1928 reg = <0x07a40000 0x1000>; 1929 status = "disabled"; 1930 1931 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1932 clock-names = "apb_pclk", "atclk"; 1933 1934 cpu = <&cpu2>; 1935 1936 out-ports { 1937 port { 1938 etm2_out: endpoint { 1939 remote-endpoint = 1940 <&apss_funnel_in2>; 1941 }; 1942 }; 1943 }; 1944 }; 1945 1946 etm4: etm@7b40000 { 1947 compatible = "arm,coresight-etm4x", "arm,primecell"; 1948 reg = <0x07b40000 0x1000>; 1949 status = "disabled"; 1950 1951 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1952 clock-names = "apb_pclk", "atclk"; 1953 1954 cpu = <&cpu3>; 1955 1956 out-ports { 1957 port { 1958 etm3_out: endpoint { 1959 remote-endpoint = 1960 <&apss_funnel_in3>; 1961 }; 1962 }; 1963 }; 1964 }; 1965 1966 funnel4: funnel@7b60000 { /* APSS Funnel */ 1967 compatible = "arm,coresight-etm4x", "arm,primecell"; 1968 reg = <0x07b60000 0x1000>; 1969 status = "disabled"; 1970 1971 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 1972 clock-names = "apb_pclk", "atclk"; 1973 1974 out-ports { 1975 port { 1976 apss_funnel_out: endpoint { 1977 remote-endpoint = 1978 <&apss_merge_funnel_in>; 1979 }; 1980 }; 1981 }; 1982 1983 in-ports { 1984 #address-cells = <1>; 1985 #size-cells = <0>; 1986 1987 port@0 { 1988 reg = <0>; 1989 apss_funnel_in0: endpoint { 1990 remote-endpoint = 1991 <&etm0_out>; 1992 }; 1993 }; 1994 1995 port@1 { 1996 reg = <1>; 1997 apss_funnel_in1: endpoint { 1998 remote-endpoint = 1999 <&etm1_out>; 2000 }; 2001 }; 2002 2003 port@2 { 2004 reg = <2>; 2005 apss_funnel_in2: endpoint { 2006 remote-endpoint = 2007 <&etm2_out>; 2008 }; 2009 }; 2010 2011 port@3 { 2012 reg = <3>; 2013 apss_funnel_in3: endpoint { 2014 remote-endpoint = 2015 <&etm3_out>; 2016 }; 2017 }; 2018 2019 port@4 { 2020 reg = <4>; 2021 apss_funnel_in4: endpoint { 2022 remote-endpoint = 2023 <&etm4_out>; 2024 }; 2025 }; 2026 2027 port@5 { 2028 reg = <5>; 2029 apss_funnel_in5: endpoint { 2030 remote-endpoint = 2031 <&etm5_out>; 2032 }; 2033 }; 2034 2035 port@6 { 2036 reg = <6>; 2037 apss_funnel_in6: endpoint { 2038 remote-endpoint = 2039 <&etm6_out>; 2040 }; 2041 }; 2042 2043 port@7 { 2044 reg = <7>; 2045 apss_funnel_in7: endpoint { 2046 remote-endpoint = 2047 <&etm7_out>; 2048 }; 2049 }; 2050 }; 2051 }; 2052 2053 funnel5: funnel@7b70000 { 2054 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2055 reg = <0x07b70000 0x1000>; 2056 status = "disabled"; 2057 2058 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2059 clock-names = "apb_pclk", "atclk"; 2060 2061 out-ports { 2062 port { 2063 apss_merge_funnel_out: endpoint { 2064 remote-endpoint = 2065 <&funnel1_in6>; 2066 }; 2067 }; 2068 }; 2069 2070 in-ports { 2071 port { 2072 apss_merge_funnel_in: endpoint { 2073 remote-endpoint = 2074 <&apss_funnel_out>; 2075 }; 2076 }; 2077 }; 2078 }; 2079 2080 etm5: etm@7c40000 { 2081 compatible = "arm,coresight-etm4x", "arm,primecell"; 2082 reg = <0x07c40000 0x1000>; 2083 status = "disabled"; 2084 2085 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2086 clock-names = "apb_pclk", "atclk"; 2087 2088 cpu = <&cpu4>; 2089 2090 out-ports { 2091 port { 2092 etm4_out: endpoint { 2093 remote-endpoint = <&apss_funnel_in4>; 2094 }; 2095 }; 2096 }; 2097 }; 2098 2099 etm6: etm@7d40000 { 2100 compatible = "arm,coresight-etm4x", "arm,primecell"; 2101 reg = <0x07d40000 0x1000>; 2102 status = "disabled"; 2103 2104 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2105 clock-names = "apb_pclk", "atclk"; 2106 2107 cpu = <&cpu5>; 2108 2109 out-ports { 2110 port { 2111 etm5_out: endpoint { 2112 remote-endpoint = <&apss_funnel_in5>; 2113 }; 2114 }; 2115 }; 2116 }; 2117 2118 etm7: etm@7e40000 { 2119 compatible = "arm,coresight-etm4x", "arm,primecell"; 2120 reg = <0x07e40000 0x1000>; 2121 status = "disabled"; 2122 2123 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2124 clock-names = "apb_pclk", "atclk"; 2125 2126 cpu = <&cpu6>; 2127 2128 out-ports { 2129 port { 2130 etm6_out: endpoint { 2131 remote-endpoint = <&apss_funnel_in6>; 2132 }; 2133 }; 2134 }; 2135 }; 2136 2137 etm8: etm@7f40000 { 2138 compatible = "arm,coresight-etm4x", "arm,primecell"; 2139 reg = <0x07f40000 0x1000>; 2140 status = "disabled"; 2141 2142 clocks = <&rpmcc RPM_SMD_QDSS_CLK>, <&rpmcc RPM_SMD_QDSS_A_CLK>; 2143 clock-names = "apb_pclk", "atclk"; 2144 2145 cpu = <&cpu7>; 2146 2147 out-ports { 2148 port { 2149 etm7_out: endpoint { 2150 remote-endpoint = <&apss_funnel_in7>; 2151 }; 2152 }; 2153 }; 2154 }; 2155 2156 sram@290000 { 2157 compatible = "qcom,rpm-stats"; 2158 reg = <0x00290000 0x10000>; 2159 }; 2160 2161 spmi_bus: spmi@800f000 { 2162 compatible = "qcom,spmi-pmic-arb"; 2163 reg = <0x0800f000 0x1000>, 2164 <0x08400000 0x1000000>, 2165 <0x09400000 0x1000000>, 2166 <0x0a400000 0x220000>, 2167 <0x0800a000 0x3000>; 2168 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 2169 interrupt-names = "periph_irq"; 2170 interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>; 2171 qcom,ee = <0>; 2172 qcom,channel = <0>; 2173 #address-cells = <2>; 2174 #size-cells = <0>; 2175 interrupt-controller; 2176 #interrupt-cells = <4>; 2177 }; 2178 2179 usb3: usb@a8f8800 { 2180 compatible = "qcom,msm8998-dwc3", "qcom,dwc3"; 2181 reg = <0x0a8f8800 0x400>; 2182 status = "disabled"; 2183 #address-cells = <1>; 2184 #size-cells = <1>; 2185 ranges; 2186 2187 clocks = <&gcc GCC_CFG_NOC_USB3_AXI_CLK>, 2188 <&gcc GCC_USB30_MASTER_CLK>, 2189 <&gcc GCC_AGGRE1_USB3_AXI_CLK>, 2190 <&gcc GCC_USB30_SLEEP_CLK>, 2191 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 2192 clock-names = "cfg_noc", 2193 "core", 2194 "iface", 2195 "sleep", 2196 "mock_utmi"; 2197 2198 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 2199 <&gcc GCC_USB30_MASTER_CLK>; 2200 assigned-clock-rates = <19200000>, <120000000>; 2201 2202 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 2203 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 2204 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 2205 interrupt-names = "pwr_event", 2206 "qusb2_phy", 2207 "ss_phy_irq"; 2208 2209 power-domains = <&gcc USB_30_GDSC>; 2210 2211 resets = <&gcc GCC_USB_30_BCR>; 2212 2213 usb3_dwc3: usb@a800000 { 2214 compatible = "snps,dwc3"; 2215 reg = <0x0a800000 0xcd00>; 2216 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 2217 snps,dis_u2_susphy_quirk; 2218 snps,dis_enblslpm_quirk; 2219 snps,parkmode-disable-ss-quirk; 2220 phys = <&qusb2phy>, <&usb3phy>; 2221 phy-names = "usb2-phy", "usb3-phy"; 2222 snps,has-lpm-erratum; 2223 snps,hird-threshold = /bits/ 8 <0x10>; 2224 }; 2225 }; 2226 2227 usb3phy: phy@c010000 { 2228 compatible = "qcom,msm8998-qmp-usb3-phy"; 2229 reg = <0x0c010000 0x1000>; 2230 2231 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>, 2232 <&gcc GCC_USB3_CLKREF_CLK>, 2233 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2234 <&gcc GCC_USB3_PHY_PIPE_CLK>; 2235 clock-names = "aux", 2236 "ref", 2237 "cfg_ahb", 2238 "pipe"; 2239 clock-output-names = "usb3_phy_pipe_clk_src"; 2240 #clock-cells = <0>; 2241 #phy-cells = <0>; 2242 2243 resets = <&gcc GCC_USB3_PHY_BCR>, 2244 <&gcc GCC_USB3PHY_PHY_BCR>; 2245 reset-names = "phy", 2246 "phy_phy"; 2247 2248 qcom,tcsr-reg = <&tcsr_regs_2 0xb244>; 2249 2250 status = "disabled"; 2251 }; 2252 2253 qusb2phy: phy@c012000 { 2254 compatible = "qcom,msm8998-qusb2-phy"; 2255 reg = <0x0c012000 0x2a8>; 2256 status = "disabled"; 2257 #phy-cells = <0>; 2258 2259 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>, 2260 <&gcc GCC_RX1_USB2_CLKREF_CLK>; 2261 clock-names = "cfg_ahb", "ref"; 2262 2263 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 2264 2265 nvmem-cells = <&qusb2_hstx_trim>; 2266 }; 2267 2268 sdhc2: mmc@c0a4900 { 2269 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4"; 2270 reg = <0x0c0a4900 0x314>, <0x0c0a4000 0x800>; 2271 reg-names = "hc", "core"; 2272 2273 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2274 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 2275 interrupt-names = "hc_irq", "pwr_irq"; 2276 2277 clock-names = "iface", "core", "xo"; 2278 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 2279 <&gcc GCC_SDCC2_APPS_CLK>, 2280 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2281 bus-width = <4>; 2282 status = "disabled"; 2283 }; 2284 2285 blsp1_dma: dma-controller@c144000 { 2286 compatible = "qcom,bam-v1.7.0"; 2287 reg = <0x0c144000 0x25000>; 2288 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 2289 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 2290 clock-names = "bam_clk"; 2291 #dma-cells = <1>; 2292 qcom,ee = <0>; 2293 qcom,controlled-remotely; 2294 num-channels = <18>; 2295 qcom,num-ees = <4>; 2296 }; 2297 2298 blsp1_uart3: serial@c171000 { 2299 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2300 reg = <0x0c171000 0x1000>; 2301 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 2302 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 2303 <&gcc GCC_BLSP1_AHB_CLK>; 2304 clock-names = "core", "iface"; 2305 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 2306 dma-names = "tx", "rx"; 2307 pinctrl-names = "default"; 2308 pinctrl-0 = <&blsp1_uart3_on>; 2309 status = "disabled"; 2310 }; 2311 2312 blsp1_i2c1: i2c@c175000 { 2313 compatible = "qcom,i2c-qup-v2.2.1"; 2314 reg = <0x0c175000 0x600>; 2315 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2316 2317 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 2318 <&gcc GCC_BLSP1_AHB_CLK>; 2319 clock-names = "core", "iface"; 2320 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2321 dma-names = "tx", "rx"; 2322 pinctrl-names = "default", "sleep"; 2323 pinctrl-0 = <&blsp1_i2c1_default>; 2324 pinctrl-1 = <&blsp1_i2c1_sleep>; 2325 clock-frequency = <400000>; 2326 2327 status = "disabled"; 2328 #address-cells = <1>; 2329 #size-cells = <0>; 2330 }; 2331 2332 blsp1_i2c2: i2c@c176000 { 2333 compatible = "qcom,i2c-qup-v2.2.1"; 2334 reg = <0x0c176000 0x600>; 2335 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2336 2337 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 2338 <&gcc GCC_BLSP1_AHB_CLK>; 2339 clock-names = "core", "iface"; 2340 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2341 dma-names = "tx", "rx"; 2342 pinctrl-names = "default", "sleep"; 2343 pinctrl-0 = <&blsp1_i2c2_default>; 2344 pinctrl-1 = <&blsp1_i2c2_sleep>; 2345 clock-frequency = <400000>; 2346 2347 status = "disabled"; 2348 #address-cells = <1>; 2349 #size-cells = <0>; 2350 }; 2351 2352 blsp1_i2c3: i2c@c177000 { 2353 compatible = "qcom,i2c-qup-v2.2.1"; 2354 reg = <0x0c177000 0x600>; 2355 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2356 2357 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 2358 <&gcc GCC_BLSP1_AHB_CLK>; 2359 clock-names = "core", "iface"; 2360 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2361 dma-names = "tx", "rx"; 2362 pinctrl-names = "default", "sleep"; 2363 pinctrl-0 = <&blsp1_i2c3_default>; 2364 pinctrl-1 = <&blsp1_i2c3_sleep>; 2365 clock-frequency = <400000>; 2366 2367 status = "disabled"; 2368 #address-cells = <1>; 2369 #size-cells = <0>; 2370 }; 2371 2372 blsp1_i2c4: i2c@c178000 { 2373 compatible = "qcom,i2c-qup-v2.2.1"; 2374 reg = <0x0c178000 0x600>; 2375 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2376 2377 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 2378 <&gcc GCC_BLSP1_AHB_CLK>; 2379 clock-names = "core", "iface"; 2380 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2381 dma-names = "tx", "rx"; 2382 pinctrl-names = "default", "sleep"; 2383 pinctrl-0 = <&blsp1_i2c4_default>; 2384 pinctrl-1 = <&blsp1_i2c4_sleep>; 2385 clock-frequency = <400000>; 2386 2387 status = "disabled"; 2388 #address-cells = <1>; 2389 #size-cells = <0>; 2390 }; 2391 2392 blsp1_i2c5: i2c@c179000 { 2393 compatible = "qcom,i2c-qup-v2.2.1"; 2394 reg = <0x0c179000 0x600>; 2395 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2396 2397 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 2398 <&gcc GCC_BLSP1_AHB_CLK>; 2399 clock-names = "core", "iface"; 2400 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2401 dma-names = "tx", "rx"; 2402 pinctrl-names = "default", "sleep"; 2403 pinctrl-0 = <&blsp1_i2c5_default>; 2404 pinctrl-1 = <&blsp1_i2c5_sleep>; 2405 clock-frequency = <400000>; 2406 2407 status = "disabled"; 2408 #address-cells = <1>; 2409 #size-cells = <0>; 2410 }; 2411 2412 blsp1_i2c6: i2c@c17a000 { 2413 compatible = "qcom,i2c-qup-v2.2.1"; 2414 reg = <0x0c17a000 0x600>; 2415 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2416 2417 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 2418 <&gcc GCC_BLSP1_AHB_CLK>; 2419 clock-names = "core", "iface"; 2420 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2421 dma-names = "tx", "rx"; 2422 pinctrl-names = "default", "sleep"; 2423 pinctrl-0 = <&blsp1_i2c6_default>; 2424 pinctrl-1 = <&blsp1_i2c6_sleep>; 2425 clock-frequency = <400000>; 2426 2427 status = "disabled"; 2428 #address-cells = <1>; 2429 #size-cells = <0>; 2430 }; 2431 2432 blsp1_spi1: spi@c175000 { 2433 compatible = "qcom,spi-qup-v2.2.1"; 2434 reg = <0x0c175000 0x600>; 2435 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 2436 2437 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 2438 <&gcc GCC_BLSP1_AHB_CLK>; 2439 clock-names = "core", "iface"; 2440 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 2441 dma-names = "tx", "rx"; 2442 pinctrl-names = "default"; 2443 pinctrl-0 = <&blsp1_spi1_default>; 2444 2445 status = "disabled"; 2446 #address-cells = <1>; 2447 #size-cells = <0>; 2448 }; 2449 2450 blsp1_spi2: spi@c176000 { 2451 compatible = "qcom,spi-qup-v2.2.1"; 2452 reg = <0x0c176000 0x600>; 2453 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 2454 2455 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 2456 <&gcc GCC_BLSP1_AHB_CLK>; 2457 clock-names = "core", "iface"; 2458 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 2459 dma-names = "tx", "rx"; 2460 pinctrl-names = "default"; 2461 pinctrl-0 = <&blsp1_spi2_default>; 2462 2463 status = "disabled"; 2464 #address-cells = <1>; 2465 #size-cells = <0>; 2466 }; 2467 2468 blsp1_spi3: spi@c177000 { 2469 compatible = "qcom,spi-qup-v2.2.1"; 2470 reg = <0x0c177000 0x600>; 2471 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 2472 2473 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 2474 <&gcc GCC_BLSP1_AHB_CLK>; 2475 clock-names = "core", "iface"; 2476 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 2477 dma-names = "tx", "rx"; 2478 pinctrl-names = "default"; 2479 pinctrl-0 = <&blsp1_spi3_default>; 2480 2481 status = "disabled"; 2482 #address-cells = <1>; 2483 #size-cells = <0>; 2484 }; 2485 2486 blsp1_spi4: spi@c178000 { 2487 compatible = "qcom,spi-qup-v2.2.1"; 2488 reg = <0x0c178000 0x600>; 2489 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2490 2491 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 2492 <&gcc GCC_BLSP1_AHB_CLK>; 2493 clock-names = "core", "iface"; 2494 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 2495 dma-names = "tx", "rx"; 2496 pinctrl-names = "default"; 2497 pinctrl-0 = <&blsp1_spi4_default>; 2498 2499 status = "disabled"; 2500 #address-cells = <1>; 2501 #size-cells = <0>; 2502 }; 2503 2504 blsp1_spi5: spi@c179000 { 2505 compatible = "qcom,spi-qup-v2.2.1"; 2506 reg = <0x0c179000 0x600>; 2507 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 2508 2509 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 2510 <&gcc GCC_BLSP1_AHB_CLK>; 2511 clock-names = "core", "iface"; 2512 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 2513 dma-names = "tx", "rx"; 2514 pinctrl-names = "default"; 2515 pinctrl-0 = <&blsp1_spi5_default>; 2516 2517 status = "disabled"; 2518 #address-cells = <1>; 2519 #size-cells = <0>; 2520 }; 2521 2522 blsp1_spi6: spi@c17a000 { 2523 compatible = "qcom,spi-qup-v2.2.1"; 2524 reg = <0x0c17a000 0x600>; 2525 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2526 2527 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2528 <&gcc GCC_BLSP1_AHB_CLK>; 2529 clock-names = "core", "iface"; 2530 dmas = <&blsp1_dma 16>, <&blsp1_dma 17>; 2531 dma-names = "tx", "rx"; 2532 pinctrl-names = "default"; 2533 pinctrl-0 = <&blsp1_spi6_default>; 2534 2535 status = "disabled"; 2536 #address-cells = <1>; 2537 #size-cells = <0>; 2538 }; 2539 2540 blsp2_dma: dma-controller@c184000 { 2541 compatible = "qcom,bam-v1.7.0"; 2542 reg = <0x0c184000 0x25000>; 2543 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 2544 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 2545 clock-names = "bam_clk"; 2546 #dma-cells = <1>; 2547 qcom,ee = <0>; 2548 qcom,controlled-remotely; 2549 num-channels = <18>; 2550 qcom,num-ees = <4>; 2551 }; 2552 2553 blsp2_uart1: serial@c1b0000 { 2554 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 2555 reg = <0x0c1b0000 0x1000>; 2556 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 2557 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 2558 <&gcc GCC_BLSP2_AHB_CLK>; 2559 clock-names = "core", "iface"; 2560 status = "disabled"; 2561 }; 2562 2563 blsp2_i2c1: i2c@c1b5000 { 2564 compatible = "qcom,i2c-qup-v2.2.1"; 2565 reg = <0x0c1b5000 0x600>; 2566 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2567 2568 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 2569 <&gcc GCC_BLSP2_AHB_CLK>; 2570 clock-names = "core", "iface"; 2571 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2572 dma-names = "tx", "rx"; 2573 pinctrl-names = "default", "sleep"; 2574 pinctrl-0 = <&blsp2_i2c1_default>; 2575 pinctrl-1 = <&blsp2_i2c1_sleep>; 2576 clock-frequency = <400000>; 2577 2578 status = "disabled"; 2579 #address-cells = <1>; 2580 #size-cells = <0>; 2581 }; 2582 2583 blsp2_i2c2: i2c@c1b6000 { 2584 compatible = "qcom,i2c-qup-v2.2.1"; 2585 reg = <0x0c1b6000 0x600>; 2586 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2587 2588 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 2589 <&gcc GCC_BLSP2_AHB_CLK>; 2590 clock-names = "core", "iface"; 2591 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2592 dma-names = "tx", "rx"; 2593 pinctrl-names = "default", "sleep"; 2594 pinctrl-0 = <&blsp2_i2c2_default>; 2595 pinctrl-1 = <&blsp2_i2c2_sleep>; 2596 clock-frequency = <400000>; 2597 2598 status = "disabled"; 2599 #address-cells = <1>; 2600 #size-cells = <0>; 2601 }; 2602 2603 blsp2_i2c3: i2c@c1b7000 { 2604 compatible = "qcom,i2c-qup-v2.2.1"; 2605 reg = <0x0c1b7000 0x600>; 2606 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2607 2608 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 2609 <&gcc GCC_BLSP2_AHB_CLK>; 2610 clock-names = "core", "iface"; 2611 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2612 dma-names = "tx", "rx"; 2613 pinctrl-names = "default", "sleep"; 2614 pinctrl-0 = <&blsp2_i2c3_default>; 2615 pinctrl-1 = <&blsp2_i2c3_sleep>; 2616 clock-frequency = <400000>; 2617 2618 status = "disabled"; 2619 #address-cells = <1>; 2620 #size-cells = <0>; 2621 }; 2622 2623 blsp2_i2c4: i2c@c1b8000 { 2624 compatible = "qcom,i2c-qup-v2.2.1"; 2625 reg = <0x0c1b8000 0x600>; 2626 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2627 2628 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 2629 <&gcc GCC_BLSP2_AHB_CLK>; 2630 clock-names = "core", "iface"; 2631 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2632 dma-names = "tx", "rx"; 2633 pinctrl-names = "default", "sleep"; 2634 pinctrl-0 = <&blsp2_i2c4_default>; 2635 pinctrl-1 = <&blsp2_i2c4_sleep>; 2636 clock-frequency = <400000>; 2637 2638 status = "disabled"; 2639 #address-cells = <1>; 2640 #size-cells = <0>; 2641 }; 2642 2643 blsp2_i2c5: i2c@c1b9000 { 2644 compatible = "qcom,i2c-qup-v2.2.1"; 2645 reg = <0x0c1b9000 0x600>; 2646 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2647 2648 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 2649 <&gcc GCC_BLSP2_AHB_CLK>; 2650 clock-names = "core", "iface"; 2651 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2652 dma-names = "tx", "rx"; 2653 pinctrl-names = "default", "sleep"; 2654 pinctrl-0 = <&blsp2_i2c5_default>; 2655 pinctrl-1 = <&blsp2_i2c5_sleep>; 2656 clock-frequency = <400000>; 2657 2658 status = "disabled"; 2659 #address-cells = <1>; 2660 #size-cells = <0>; 2661 }; 2662 2663 blsp2_i2c6: i2c@c1ba000 { 2664 compatible = "qcom,i2c-qup-v2.2.1"; 2665 reg = <0x0c1ba000 0x600>; 2666 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2667 2668 clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, 2669 <&gcc GCC_BLSP2_AHB_CLK>; 2670 clock-names = "core", "iface"; 2671 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2672 dma-names = "tx", "rx"; 2673 pinctrl-names = "default", "sleep"; 2674 pinctrl-0 = <&blsp2_i2c6_default>; 2675 pinctrl-1 = <&blsp2_i2c6_sleep>; 2676 clock-frequency = <400000>; 2677 2678 status = "disabled"; 2679 #address-cells = <1>; 2680 #size-cells = <0>; 2681 }; 2682 2683 blsp2_spi1: spi@c1b5000 { 2684 compatible = "qcom,spi-qup-v2.2.1"; 2685 reg = <0x0c1b5000 0x600>; 2686 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 2687 2688 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, 2689 <&gcc GCC_BLSP2_AHB_CLK>; 2690 clock-names = "core", "iface"; 2691 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 2692 dma-names = "tx", "rx"; 2693 pinctrl-names = "default"; 2694 pinctrl-0 = <&blsp2_spi1_default>; 2695 2696 status = "disabled"; 2697 #address-cells = <1>; 2698 #size-cells = <0>; 2699 }; 2700 2701 blsp2_spi2: spi@c1b6000 { 2702 compatible = "qcom,spi-qup-v2.2.1"; 2703 reg = <0x0c1b6000 0x600>; 2704 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 2705 2706 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 2707 <&gcc GCC_BLSP2_AHB_CLK>; 2708 clock-names = "core", "iface"; 2709 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 2710 dma-names = "tx", "rx"; 2711 pinctrl-names = "default"; 2712 pinctrl-0 = <&blsp2_spi2_default>; 2713 2714 status = "disabled"; 2715 #address-cells = <1>; 2716 #size-cells = <0>; 2717 }; 2718 2719 blsp2_spi3: spi@c1b7000 { 2720 compatible = "qcom,spi-qup-v2.2.1"; 2721 reg = <0x0c1b7000 0x600>; 2722 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 2723 2724 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, 2725 <&gcc GCC_BLSP2_AHB_CLK>; 2726 clock-names = "core", "iface"; 2727 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 2728 dma-names = "tx", "rx"; 2729 pinctrl-names = "default"; 2730 pinctrl-0 = <&blsp2_spi3_default>; 2731 2732 status = "disabled"; 2733 #address-cells = <1>; 2734 #size-cells = <0>; 2735 }; 2736 2737 blsp2_spi4: spi@c1b8000 { 2738 compatible = "qcom,spi-qup-v2.2.1"; 2739 reg = <0x0c1b8000 0x600>; 2740 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 2741 2742 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 2743 <&gcc GCC_BLSP2_AHB_CLK>; 2744 clock-names = "core", "iface"; 2745 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 2746 dma-names = "tx", "rx"; 2747 pinctrl-names = "default"; 2748 pinctrl-0 = <&blsp2_spi4_default>; 2749 2750 status = "disabled"; 2751 #address-cells = <1>; 2752 #size-cells = <0>; 2753 }; 2754 2755 blsp2_spi5: spi@c1b9000 { 2756 compatible = "qcom,spi-qup-v2.2.1"; 2757 reg = <0x0c1b9000 0x600>; 2758 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 2759 2760 clocks = <&gcc GCC_BLSP2_QUP5_SPI_APPS_CLK>, 2761 <&gcc GCC_BLSP2_AHB_CLK>; 2762 clock-names = "core", "iface"; 2763 dmas = <&blsp2_dma 14>, <&blsp2_dma 15>; 2764 dma-names = "tx", "rx"; 2765 pinctrl-names = "default"; 2766 pinctrl-0 = <&blsp2_spi5_default>; 2767 2768 status = "disabled"; 2769 #address-cells = <1>; 2770 #size-cells = <0>; 2771 }; 2772 2773 blsp2_spi6: spi@c1ba000 { 2774 compatible = "qcom,spi-qup-v2.2.1"; 2775 reg = <0x0c1ba000 0x600>; 2776 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 2777 2778 clocks = <&gcc GCC_BLSP2_QUP6_SPI_APPS_CLK>, 2779 <&gcc GCC_BLSP2_AHB_CLK>; 2780 clock-names = "core", "iface"; 2781 dmas = <&blsp2_dma 16>, <&blsp2_dma 17>; 2782 dma-names = "tx", "rx"; 2783 pinctrl-names = "default"; 2784 pinctrl-0 = <&blsp2_spi6_default>; 2785 2786 status = "disabled"; 2787 #address-cells = <1>; 2788 #size-cells = <0>; 2789 }; 2790 2791 mmcc: clock-controller@c8c0000 { 2792 compatible = "qcom,mmcc-msm8998"; 2793 #clock-cells = <1>; 2794 #reset-cells = <1>; 2795 #power-domain-cells = <1>; 2796 reg = <0xc8c0000 0x40000>; 2797 2798 clock-names = "xo", 2799 "gpll0", 2800 "dsi0dsi", 2801 "dsi0byte", 2802 "dsi1dsi", 2803 "dsi1byte", 2804 "hdmipll", 2805 "dplink", 2806 "dpvco", 2807 "gpll0_div"; 2808 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2809 <&gcc GCC_MMSS_GPLL0_CLK>, 2810 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 2811 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2812 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 2813 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 2814 <&mdss_hdmi_phy>, 2815 <0>, 2816 <0>, 2817 <&gcc GCC_MMSS_GPLL0_DIV_CLK>; 2818 }; 2819 2820 mdss: display-subsystem@c900000 { 2821 compatible = "qcom,msm8998-mdss"; 2822 reg = <0x0c900000 0x1000>; 2823 reg-names = "mdss"; 2824 2825 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 2826 interrupt-controller; 2827 #interrupt-cells = <1>; 2828 2829 clocks = <&mmcc MDSS_AHB_CLK>, 2830 <&mmcc MDSS_AXI_CLK>, 2831 <&mmcc MDSS_MDP_CLK>; 2832 clock-names = "iface", 2833 "bus", 2834 "core"; 2835 2836 power-domains = <&mmcc MDSS_GDSC>; 2837 iommus = <&mmss_smmu 0>; 2838 2839 #address-cells = <1>; 2840 #size-cells = <1>; 2841 ranges; 2842 2843 status = "disabled"; 2844 2845 mdss_mdp: display-controller@c901000 { 2846 compatible = "qcom,msm8998-dpu"; 2847 reg = <0x0c901000 0x8f000>, 2848 <0x0c9a8e00 0xf0>, 2849 <0x0c9b0000 0x3000>, 2850 <0x0c9b8000 0x3000>; 2851 reg-names = "mdp", 2852 "regdma", 2853 "vbif", 2854 "vbif_nrt"; 2855 2856 interrupt-parent = <&mdss>; 2857 interrupts = <0>; 2858 2859 clocks = <&mmcc MDSS_AHB_CLK>, 2860 <&mmcc MDSS_AXI_CLK>, 2861 <&mmcc MNOC_AHB_CLK>, 2862 <&mmcc MDSS_MDP_CLK>, 2863 <&mmcc MDSS_VSYNC_CLK>; 2864 clock-names = "iface", 2865 "bus", 2866 "mnoc", 2867 "core", 2868 "vsync"; 2869 2870 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>; 2871 assigned-clock-rates = <19200000>; 2872 2873 operating-points-v2 = <&mdp_opp_table>; 2874 power-domains = <&rpmpd MSM8998_VDDMX>; 2875 2876 mdp_opp_table: opp-table { 2877 compatible = "operating-points-v2"; 2878 2879 opp-171430000 { 2880 opp-hz = /bits/ 64 <171430000>; 2881 required-opps = <&rpmpd_opp_low_svs>; 2882 }; 2883 2884 opp-275000000 { 2885 opp-hz = /bits/ 64 <275000000>; 2886 required-opps = <&rpmpd_opp_svs>; 2887 }; 2888 2889 opp-330000000 { 2890 opp-hz = /bits/ 64 <330000000>; 2891 required-opps = <&rpmpd_opp_nom>; 2892 }; 2893 2894 opp-412500000 { 2895 opp-hz = /bits/ 64 <412500000>; 2896 required-opps = <&rpmpd_opp_turbo>; 2897 }; 2898 }; 2899 2900 ports { 2901 #address-cells = <1>; 2902 #size-cells = <0>; 2903 2904 port@0 { 2905 reg = <0>; 2906 2907 dpu_intf1_out: endpoint { 2908 remote-endpoint = <&mdss_dsi0_in>; 2909 }; 2910 }; 2911 2912 port@1 { 2913 reg = <1>; 2914 2915 dpu_intf2_out: endpoint { 2916 remote-endpoint = <&mdss_dsi1_in>; 2917 }; 2918 }; 2919 2920 port@2 { 2921 reg = <2>; 2922 2923 dpu_intf3_out: endpoint { 2924 remote-endpoint = <&hdmi_in>; 2925 }; 2926 }; 2927 }; 2928 }; 2929 2930 mdss_dsi0: dsi@c994000 { 2931 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 2932 reg = <0x0c994000 0x400>; 2933 reg-names = "dsi_ctrl"; 2934 2935 interrupt-parent = <&mdss>; 2936 interrupts = <4>; 2937 2938 clocks = <&mmcc MDSS_BYTE0_CLK>, 2939 <&mmcc MDSS_BYTE0_INTF_CLK>, 2940 <&mmcc MDSS_PCLK0_CLK>, 2941 <&mmcc MDSS_ESC0_CLK>, 2942 <&mmcc MDSS_AHB_CLK>, 2943 <&mmcc MDSS_AXI_CLK>; 2944 clock-names = "byte", 2945 "byte_intf", 2946 "pixel", 2947 "core", 2948 "iface", 2949 "bus"; 2950 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, 2951 <&mmcc PCLK0_CLK_SRC>; 2952 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2953 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2954 2955 operating-points-v2 = <&dsi_opp_table>; 2956 power-domains = <&rpmpd MSM8998_VDDCX>; 2957 2958 phys = <&mdss_dsi0_phy>; 2959 phy-names = "dsi"; 2960 2961 #address-cells = <1>; 2962 #size-cells = <0>; 2963 2964 status = "disabled"; 2965 2966 ports { 2967 #address-cells = <1>; 2968 #size-cells = <0>; 2969 2970 port@0 { 2971 reg = <0>; 2972 2973 mdss_dsi0_in: endpoint { 2974 remote-endpoint = <&dpu_intf1_out>; 2975 }; 2976 }; 2977 2978 port@1 { 2979 reg = <1>; 2980 2981 mdss_dsi0_out: endpoint { 2982 }; 2983 }; 2984 }; 2985 }; 2986 2987 mdss_dsi0_phy: phy@c994400 { 2988 compatible = "qcom,dsi-phy-10nm-8998"; 2989 reg = <0x0c994400 0x200>, 2990 <0x0c994600 0x280>, 2991 <0x0c994a00 0x1e0>; 2992 reg-names = "dsi_phy", 2993 "dsi_phy_lane", 2994 "dsi_pll"; 2995 2996 clocks = <&mmcc MDSS_AHB_CLK>, 2997 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2998 clock-names = "iface", "ref"; 2999 3000 #clock-cells = <1>; 3001 #phy-cells = <0>; 3002 3003 status = "disabled"; 3004 }; 3005 3006 mdss_dsi1: dsi@c996000 { 3007 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3008 reg = <0x0c996000 0x400>; 3009 reg-names = "dsi_ctrl"; 3010 3011 interrupt-parent = <&mdss>; 3012 interrupts = <5>; 3013 3014 clocks = <&mmcc MDSS_BYTE1_CLK>, 3015 <&mmcc MDSS_BYTE1_INTF_CLK>, 3016 <&mmcc MDSS_PCLK1_CLK>, 3017 <&mmcc MDSS_ESC1_CLK>, 3018 <&mmcc MDSS_AHB_CLK>, 3019 <&mmcc MDSS_AXI_CLK>; 3020 clock-names = "byte", 3021 "byte_intf", 3022 "pixel", 3023 "core", 3024 "iface", 3025 "bus"; 3026 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, 3027 <&mmcc PCLK1_CLK_SRC>; 3028 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 3029 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 3030 3031 operating-points-v2 = <&dsi_opp_table>; 3032 power-domains = <&rpmpd MSM8998_VDDCX>; 3033 3034 phys = <&mdss_dsi1_phy>; 3035 phy-names = "dsi"; 3036 3037 #address-cells = <1>; 3038 #size-cells = <0>; 3039 3040 status = "disabled"; 3041 3042 ports { 3043 #address-cells = <1>; 3044 #size-cells = <0>; 3045 3046 port@0 { 3047 reg = <0>; 3048 3049 mdss_dsi1_in: endpoint { 3050 remote-endpoint = <&dpu_intf2_out>; 3051 }; 3052 }; 3053 3054 port@1 { 3055 reg = <1>; 3056 3057 mdss_dsi1_out: endpoint { 3058 }; 3059 }; 3060 }; 3061 }; 3062 3063 mdss_dsi1_phy: phy@c996400 { 3064 compatible = "qcom,dsi-phy-10nm-8998"; 3065 reg = <0x0c996400 0x200>, 3066 <0x0c996600 0x280>, 3067 <0x0c996a00 0x10e>; 3068 reg-names = "dsi_phy", 3069 "dsi_phy_lane", 3070 "dsi_pll"; 3071 3072 clocks = <&mmcc MDSS_AHB_CLK>, 3073 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3074 clock-names = "iface", 3075 "ref"; 3076 3077 #clock-cells = <1>; 3078 #phy-cells = <0>; 3079 3080 status = "disabled"; 3081 }; 3082 3083 mdss_hdmi: hdmi-tx@c9a0000 { 3084 compatible = "qcom,hdmi-tx-8998"; 3085 reg = <0x0c9a0000 0x50c>, 3086 <0x00780000 0x6220>, 3087 <0x0c9e0000 0x2c>; 3088 reg-names = "core_physical", 3089 "qfprom_physical", 3090 "hdcp_physical"; 3091 3092 interrupt-parent = <&mdss>; 3093 interrupts = <8>; 3094 3095 clocks = <&mmcc MDSS_MDP_CLK>, 3096 <&mmcc MDSS_AHB_CLK>, 3097 <&mmcc MDSS_HDMI_CLK>, 3098 <&mmcc MDSS_HDMI_DP_AHB_CLK>, 3099 <&mmcc MDSS_EXTPCLK_CLK>, 3100 <&mmcc MDSS_AXI_CLK>, 3101 <&mmcc MNOC_AHB_CLK>, 3102 <&mmcc MISC_AHB_CLK>; 3103 clock-names = 3104 "mdp_core", 3105 "iface", 3106 "core", 3107 "alt_iface", 3108 "extp", 3109 "bus", 3110 "mnoc", 3111 "iface_mmss"; 3112 3113 phys = <&mdss_hdmi_phy>; 3114 #sound-dai-cells = <1>; 3115 3116 pinctrl-0 = <&hdmi_hpd_default>, 3117 <&hdmi_ddc_default>, 3118 <&hdmi_cec_default>; 3119 pinctrl-1 = <&hdmi_hpd_sleep>, 3120 <&hdmi_ddc_default>, 3121 <&hdmi_cec_default>; 3122 pinctrl-names = "default", "sleep"; 3123 3124 status = "disabled"; 3125 3126 ports { 3127 #address-cells = <1>; 3128 #size-cells = <0>; 3129 3130 port@0 { 3131 reg = <0>; 3132 hdmi_in: endpoint { 3133 remote-endpoint = <&dpu_intf3_out>; 3134 }; 3135 }; 3136 3137 port@1 { 3138 reg = <1>; 3139 hdmi_out: endpoint { 3140 }; 3141 }; 3142 }; 3143 }; 3144 3145 mdss_hdmi_phy: hdmi-phy@c9a0600 { 3146 compatible = "qcom,hdmi-phy-8998"; 3147 reg = <0x0c9a0600 0x18b>, 3148 <0x0c9a0a00 0x38>, 3149 <0x0c9a0c00 0x38>, 3150 <0x0c9a0e00 0x38>, 3151 <0x0c9a1000 0x38>, 3152 <0x0c9a1200 0x0e8>; 3153 reg-names = "hdmi_pll", 3154 "hdmi_tx_l0", 3155 "hdmi_tx_l1", 3156 "hdmi_tx_l2", 3157 "hdmi_tx_l3", 3158 "hdmi_phy"; 3159 3160 #clock-cells = <0>; 3161 #phy-cells = <0>; 3162 3163 clocks = <&mmcc MDSS_AHB_CLK>, 3164 <&gcc GCC_HDMI_CLKREF_CLK>, 3165 <&rpmcc RPM_SMD_XO_CLK_SRC>; 3166 clock-names = "iface", 3167 "ref", 3168 "xo"; 3169 3170 status = "disabled"; 3171 }; 3172 }; 3173 3174 venus: video-codec@cc00000 { 3175 compatible = "qcom,msm8998-venus"; 3176 reg = <0x0cc00000 0xff000>; 3177 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 3178 power-domains = <&mmcc VIDEO_TOP_GDSC>; 3179 clocks = <&mmcc VIDEO_CORE_CLK>, 3180 <&mmcc VIDEO_AHB_CLK>, 3181 <&mmcc VIDEO_AXI_CLK>, 3182 <&mmcc VIDEO_MAXI_CLK>; 3183 clock-names = "core", "iface", "bus", "mbus"; 3184 iommus = <&mmss_smmu 0x400>, 3185 <&mmss_smmu 0x401>, 3186 <&mmss_smmu 0x40a>, 3187 <&mmss_smmu 0x407>, 3188 <&mmss_smmu 0x40e>, 3189 <&mmss_smmu 0x40f>, 3190 <&mmss_smmu 0x408>, 3191 <&mmss_smmu 0x409>, 3192 <&mmss_smmu 0x40b>, 3193 <&mmss_smmu 0x40c>, 3194 <&mmss_smmu 0x40d>, 3195 <&mmss_smmu 0x410>, 3196 <&mmss_smmu 0x421>, 3197 <&mmss_smmu 0x428>, 3198 <&mmss_smmu 0x429>, 3199 <&mmss_smmu 0x42b>, 3200 <&mmss_smmu 0x42c>, 3201 <&mmss_smmu 0x42d>, 3202 <&mmss_smmu 0x411>, 3203 <&mmss_smmu 0x431>; 3204 memory-region = <&venus_mem>; 3205 status = "disabled"; 3206 3207 video-decoder { 3208 compatible = "venus-decoder"; 3209 clocks = <&mmcc VIDEO_SUBCORE0_CLK>; 3210 clock-names = "core"; 3211 power-domains = <&mmcc VIDEO_SUBCORE0_GDSC>; 3212 }; 3213 3214 video-encoder { 3215 compatible = "venus-encoder"; 3216 clocks = <&mmcc VIDEO_SUBCORE1_CLK>; 3217 clock-names = "core"; 3218 power-domains = <&mmcc VIDEO_SUBCORE1_GDSC>; 3219 }; 3220 }; 3221 3222 mmss_smmu: iommu@cd00000 { 3223 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2"; 3224 reg = <0x0cd00000 0x40000>; 3225 #iommu-cells = <1>; 3226 3227 clocks = <&mmcc MNOC_AHB_CLK>, 3228 <&mmcc BIMC_SMMU_AHB_CLK>, 3229 <&mmcc BIMC_SMMU_AXI_CLK>; 3230 clock-names = "iface-mm", 3231 "iface-smmu", 3232 "bus-smmu"; 3233 3234 #global-interrupts = <0>; 3235 interrupts = 3236 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 3237 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 3238 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 3239 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 3240 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 3241 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 3242 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 3243 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 3244 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 3245 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 3246 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 3247 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 3248 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 3249 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 3250 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 3251 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 3252 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 3253 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 3254 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 3255 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 3256 3257 power-domains = <&mmcc BIMC_SMMU_GDSC>; 3258 }; 3259 3260 remoteproc_adsp: remoteproc@17300000 { 3261 compatible = "qcom,msm8998-adsp-pas"; 3262 reg = <0x17300000 0x4040>; 3263 3264 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, 3265 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3266 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3267 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3268 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 3269 interrupt-names = "wdog", "fatal", "ready", 3270 "handover", "stop-ack"; 3271 3272 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 3273 clock-names = "xo"; 3274 3275 memory-region = <&adsp_mem>; 3276 3277 qcom,smem-states = <&adsp_smp2p_out 0>; 3278 qcom,smem-state-names = "stop"; 3279 3280 power-domains = <&rpmpd MSM8998_VDDCX>; 3281 power-domain-names = "cx"; 3282 3283 status = "disabled"; 3284 3285 glink-edge { 3286 interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>; 3287 label = "lpass"; 3288 qcom,remote-pid = <2>; 3289 mboxes = <&apcs_glb 9>; 3290 }; 3291 }; 3292 3293 apcs_glb: mailbox@17911000 { 3294 compatible = "qcom,msm8998-apcs-hmss-global", 3295 "qcom,msm8994-apcs-kpss-global"; 3296 reg = <0x17911000 0x1000>; 3297 3298 #mbox-cells = <1>; 3299 }; 3300 3301 timer@17920000 { 3302 #address-cells = <1>; 3303 #size-cells = <1>; 3304 ranges; 3305 compatible = "arm,armv7-timer-mem"; 3306 reg = <0x17920000 0x1000>; 3307 3308 frame@17921000 { 3309 frame-number = <0>; 3310 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 3311 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 3312 reg = <0x17921000 0x1000>, 3313 <0x17922000 0x1000>; 3314 }; 3315 3316 frame@17923000 { 3317 frame-number = <1>; 3318 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 3319 reg = <0x17923000 0x1000>; 3320 status = "disabled"; 3321 }; 3322 3323 frame@17924000 { 3324 frame-number = <2>; 3325 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 3326 reg = <0x17924000 0x1000>; 3327 status = "disabled"; 3328 }; 3329 3330 frame@17925000 { 3331 frame-number = <3>; 3332 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 3333 reg = <0x17925000 0x1000>; 3334 status = "disabled"; 3335 }; 3336 3337 frame@17926000 { 3338 frame-number = <4>; 3339 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 3340 reg = <0x17926000 0x1000>; 3341 status = "disabled"; 3342 }; 3343 3344 frame@17927000 { 3345 frame-number = <5>; 3346 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 3347 reg = <0x17927000 0x1000>; 3348 status = "disabled"; 3349 }; 3350 3351 frame@17928000 { 3352 frame-number = <6>; 3353 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 3354 reg = <0x17928000 0x1000>; 3355 status = "disabled"; 3356 }; 3357 }; 3358 3359 intc: interrupt-controller@17a00000 { 3360 compatible = "arm,gic-v3"; 3361 reg = <0x17a00000 0x10000>, /* GICD */ 3362 <0x17b00000 0x100000>; /* GICR * 8 */ 3363 #interrupt-cells = <3>; 3364 #address-cells = <1>; 3365 #size-cells = <1>; 3366 ranges; 3367 interrupt-controller; 3368 #redistributor-regions = <1>; 3369 redistributor-stride = <0x0 0x20000>; 3370 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 3371 }; 3372 3373 wifi: wifi@18800000 { 3374 compatible = "qcom,wcn3990-wifi"; 3375 status = "disabled"; 3376 reg = <0x18800000 0x800000>; 3377 reg-names = "membase"; 3378 memory-region = <&wlan_msa_mem>; 3379 clocks = <&rpmcc RPM_SMD_RF_CLK2_PIN>; 3380 clock-names = "cxo_ref_clk_pin"; 3381 interrupts = 3382 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 3383 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 3384 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>, 3385 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, 3386 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, 3387 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 3388 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 3389 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 3390 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 3391 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 3392 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 3393 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>; 3394 iommus = <&anoc2_smmu 0x1900>, 3395 <&anoc2_smmu 0x1901>; 3396 qcom,snoc-host-cap-8bit-quirk; 3397 qcom,no-msa-ready-indicator; 3398 }; 3399 }; 3400};
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