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msm8994.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/msm8994.dtsi
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2016, The Linux Foundation. All rights reserved. 4 */ 5 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/clock/qcom,gcc-msm8994.h> 8#include <dt-bindings/clock/qcom,mmcc-msm8994.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 mmc1 = &sdhc1; 21 mmc2 = &sdhc2; 22 }; 23 24 chosen { }; 25 26 clocks { 27 xo_board: xo-board { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <19200000>; 31 clock-output-names = "xo_board"; 32 }; 33 34 sleep_clk: sleep-clk { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <32764>; 38 clock-output-names = "sleep_clk"; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <2>; 44 #size-cells = <0>; 45 46 cpu0: cpu@0 { 47 device_type = "cpu"; 48 compatible = "arm,cortex-a53"; 49 reg = <0x0 0x0>; 50 enable-method = "psci"; 51 next-level-cache = <&l2_0>; 52 l2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 cache-unified; 56 }; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 reg = <0x0 0x1>; 63 enable-method = "psci"; 64 next-level-cache = <&l2_0>; 65 }; 66 67 cpu2: cpu@2 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a53"; 70 reg = <0x0 0x2>; 71 enable-method = "psci"; 72 next-level-cache = <&l2_0>; 73 }; 74 75 cpu3: cpu@3 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a53"; 78 reg = <0x0 0x3>; 79 enable-method = "psci"; 80 next-level-cache = <&l2_0>; 81 }; 82 83 cpu4: cpu@100 { 84 device_type = "cpu"; 85 compatible = "arm,cortex-a57"; 86 reg = <0x0 0x100>; 87 enable-method = "psci"; 88 next-level-cache = <&l2_1>; 89 l2_1: l2-cache { 90 compatible = "cache"; 91 cache-level = <2>; 92 cache-unified; 93 }; 94 }; 95 96 cpu5: cpu@101 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a57"; 99 reg = <0x0 0x101>; 100 enable-method = "psci"; 101 next-level-cache = <&l2_1>; 102 }; 103 104 cpu6: cpu@102 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a57"; 107 reg = <0x0 0x102>; 108 enable-method = "psci"; 109 next-level-cache = <&l2_1>; 110 }; 111 112 cpu7: cpu@103 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a57"; 115 reg = <0x0 0x103>; 116 enable-method = "psci"; 117 next-level-cache = <&l2_1>; 118 }; 119 120 cpu-map { 121 cluster0 { 122 core0 { 123 cpu = <&cpu0>; 124 }; 125 126 core1 { 127 cpu = <&cpu1>; 128 }; 129 130 core2 { 131 cpu = <&cpu2>; 132 }; 133 134 core3 { 135 cpu = <&cpu3>; 136 }; 137 }; 138 139 cluster1 { 140 core0 { 141 cpu = <&cpu4>; 142 }; 143 144 core1 { 145 cpu = <&cpu5>; 146 }; 147 148 cpu6_map: core2 { 149 cpu = <&cpu6>; 150 }; 151 152 cpu7_map: core3 { 153 cpu = <&cpu7>; 154 }; 155 }; 156 }; 157 }; 158 159 firmware { 160 scm { 161 compatible = "qcom,scm-msm8994", "qcom,scm"; 162 }; 163 }; 164 165 memory@80000000 { 166 device_type = "memory"; 167 /* We expect the bootloader to fill in the reg */ 168 reg = <0 0x80000000 0 0>; 169 }; 170 171 pmu { 172 compatible = "arm,cortex-a53-pmu"; 173 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4)| IRQ_TYPE_LEVEL_HIGH)>; 174 }; 175 176 psci { 177 compatible = "arm,psci-0.2"; 178 method = "hvc"; 179 }; 180 181 rpm: remoteproc { 182 compatible = "qcom,msm8994-rpm-proc", "qcom,rpm-proc"; 183 184 smd-edge { 185 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 186 mboxes = <&apcs 0>; 187 qcom,smd-edge = <15>; 188 qcom,remote-pid = <6>; 189 190 rpm_requests: rpm-requests { 191 compatible = "qcom,rpm-msm8994", "qcom,smd-rpm"; 192 qcom,smd-channels = "rpm_requests"; 193 194 rpmcc: clock-controller { 195 compatible = "qcom,rpmcc-msm8994", "qcom,rpmcc"; 196 #clock-cells = <1>; 197 }; 198 199 rpmpd: power-controller { 200 compatible = "qcom,msm8994-rpmpd"; 201 #power-domain-cells = <1>; 202 operating-points-v2 = <&rpmpd_opp_table>; 203 204 rpmpd_opp_table: opp-table { 205 compatible = "operating-points-v2"; 206 207 rpmpd_opp_ret: opp1 { 208 opp-level = <1>; 209 }; 210 rpmpd_opp_svs_krait: opp2 { 211 opp-level = <2>; 212 }; 213 rpmpd_opp_svs_soc: opp3 { 214 opp-level = <3>; 215 }; 216 rpmpd_opp_nom: opp4 { 217 opp-level = <4>; 218 }; 219 rpmpd_opp_turbo: opp5 { 220 opp-level = <5>; 221 }; 222 rpmpd_opp_super_turbo: opp6 { 223 opp-level = <6>; 224 }; 225 }; 226 }; 227 }; 228 }; 229 }; 230 231 reserved-memory { 232 #address-cells = <2>; 233 #size-cells = <2>; 234 ranges; 235 236 dfps_data_mem: dfps-data@3400000 { 237 reg = <0 0x03400000 0 0x1000>; 238 no-map; 239 }; 240 241 cont_splash_mem: memory@3401000 { 242 reg = <0 0x03401000 0 0x2200000>; 243 no-map; 244 }; 245 246 smem_mem: smem@6a00000 { 247 reg = <0 0x06a00000 0 0x200000>; 248 no-map; 249 }; 250 251 mpss_mem: memory@7000000 { 252 reg = <0 0x07000000 0 0x5a00000>; 253 no-map; 254 }; 255 256 peripheral_region: memory@ca00000 { 257 reg = <0 0x0ca00000 0 0x1f00000>; 258 no-map; 259 }; 260 261 rmtfs_mem: memory@c6400000 { 262 compatible = "qcom,rmtfs-mem"; 263 reg = <0 0xc6400000 0 0x180000>; 264 no-map; 265 266 qcom,client-id = <1>; 267 }; 268 269 mba_mem: memory@c6700000 { 270 reg = <0 0xc6700000 0 0x100000>; 271 no-map; 272 }; 273 274 audio_mem: memory@c7000000 { 275 reg = <0 0xc7000000 0 0x800000>; 276 no-map; 277 }; 278 279 adsp_mem: memory@c9400000 { 280 reg = <0 0xc9400000 0 0x3f00000>; 281 no-map; 282 }; 283 284 res_hyp_mem: reserved@6c00000 { 285 reg = <0 0x06c00000 0 0x400000>; 286 no-map; 287 }; 288 }; 289 290 smem { 291 compatible = "qcom,smem"; 292 memory-region = <&smem_mem>; 293 qcom,rpm-msg-ram = <&rpm_msg_ram>; 294 hwlocks = <&tcsr_mutex 3>; 295 }; 296 297 smp2p-lpass { 298 compatible = "qcom,smp2p"; 299 qcom,smem = <443>, <429>; 300 301 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>; 302 303 mboxes = <&apcs 10>; 304 305 qcom,local-pid = <0>; 306 qcom,remote-pid = <2>; 307 308 adsp_smp2p_out: master-kernel { 309 qcom,entry-name = "master-kernel"; 310 #qcom,smem-state-cells = <1>; 311 }; 312 313 adsp_smp2p_in: slave-kernel { 314 qcom,entry-name = "slave-kernel"; 315 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 }; 319 }; 320 321 smp2p-modem { 322 compatible = "qcom,smp2p"; 323 qcom,smem = <435>, <428>; 324 325 interrupt-parent = <&intc>; 326 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 327 328 mboxes = <&apcs 14>; 329 330 qcom,local-pid = <0>; 331 qcom,remote-pid = <1>; 332 333 modem_smp2p_out: master-kernel { 334 qcom,entry-name = "master-kernel"; 335 #qcom,smem-state-cells = <1>; 336 }; 337 338 modem_smp2p_in: slave-kernel { 339 qcom,entry-name = "slave-kernel"; 340 341 interrupt-controller; 342 #interrupt-cells = <2>; 343 }; 344 }; 345 346 soc: soc@0 { 347 #address-cells = <1>; 348 #size-cells = <1>; 349 ranges = <0 0 0 0xffffffff>; 350 compatible = "simple-bus"; 351 352 intc: interrupt-controller@f9000000 { 353 compatible = "qcom,msm-qgic2"; 354 interrupt-controller; 355 #interrupt-cells = <3>; 356 reg = <0xf9000000 0x1000>, 357 <0xf9002000 0x1000>; 358 }; 359 360 apcs: mailbox@f900d000 { 361 compatible = "qcom,msm8994-apcs-kpss-global", "syscon"; 362 reg = <0xf900d000 0x2000>; 363 #mbox-cells = <1>; 364 }; 365 366 watchdog@f9017000 { 367 compatible = "qcom,apss-wdt-msm8994", "qcom,kpss-wdt"; 368 reg = <0xf9017000 0x1000>; 369 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 370 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>; 371 clocks = <&sleep_clk>; 372 timeout-sec = <10>; 373 }; 374 375 timer@f9020000 { 376 #address-cells = <1>; 377 #size-cells = <1>; 378 ranges; 379 compatible = "arm,armv7-timer-mem"; 380 reg = <0xf9020000 0x1000>; 381 382 frame@f9021000 { 383 frame-number = <0>; 384 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 385 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 386 reg = <0xf9021000 0x1000>, 387 <0xf9022000 0x1000>; 388 }; 389 390 frame@f9023000 { 391 frame-number = <1>; 392 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 393 reg = <0xf9023000 0x1000>; 394 status = "disabled"; 395 }; 396 397 frame@f9024000 { 398 frame-number = <2>; 399 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 400 reg = <0xf9024000 0x1000>; 401 status = "disabled"; 402 }; 403 404 frame@f9025000 { 405 frame-number = <3>; 406 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 407 reg = <0xf9025000 0x1000>; 408 status = "disabled"; 409 }; 410 411 frame@f9026000 { 412 frame-number = <4>; 413 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 414 reg = <0xf9026000 0x1000>; 415 status = "disabled"; 416 }; 417 418 frame@f9027000 { 419 frame-number = <5>; 420 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 421 reg = <0xf9027000 0x1000>; 422 status = "disabled"; 423 }; 424 425 frame@f9028000 { 426 frame-number = <6>; 427 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 428 reg = <0xf9028000 0x1000>; 429 status = "disabled"; 430 }; 431 }; 432 433 usb3: usb@f92f8800 { 434 compatible = "qcom,msm8994-dwc3", "qcom,dwc3"; 435 reg = <0xf92f8800 0x400>; 436 #address-cells = <1>; 437 #size-cells = <1>; 438 ranges; 439 440 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 441 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 442 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 443 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 444 interrupt-names = "pwr_event", 445 "qusb2_phy", 446 "hs_phy_irq", 447 "ss_phy_irq"; 448 449 clocks = <&gcc GCC_USB30_MASTER_CLK>, 450 <&gcc GCC_SYS_NOC_USB3_AXI_CLK>, 451 <&gcc GCC_USB30_SLEEP_CLK>, 452 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 453 clock-names = "core", 454 "iface", 455 "sleep", 456 "mock_utmi"; 457 458 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 459 <&gcc GCC_USB30_MASTER_CLK>; 460 assigned-clock-rates = <19200000>, <120000000>; 461 462 power-domains = <&gcc USB30_GDSC>; 463 qcom,select-utmi-as-pipe-clk; 464 465 usb@f9200000 { 466 compatible = "snps,dwc3"; 467 reg = <0xf9200000 0xcc00>; 468 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 469 snps,dis_u2_susphy_quirk; 470 snps,dis_enblslpm_quirk; 471 maximum-speed = "high-speed"; 472 dr_mode = "peripheral"; 473 }; 474 }; 475 476 sdhc1: mmc@f9824900 { 477 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 478 reg = <0xf9824900 0x1a0>, <0xf9824000 0x800>; 479 reg-names = "hc", "core"; 480 481 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 483 interrupt-names = "hc_irq", "pwr_irq"; 484 485 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 486 <&gcc GCC_SDCC1_APPS_CLK>, 487 <&xo_board>; 488 clock-names = "iface", "core", "xo"; 489 490 pinctrl-names = "default", "sleep"; 491 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 492 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 493 494 bus-width = <8>; 495 non-removable; 496 status = "disabled"; 497 }; 498 499 sdhc2: mmc@f98a4900 { 500 compatible = "qcom,msm8994-sdhci", "qcom,sdhci-msm-v4"; 501 reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; 502 reg-names = "hc", "core"; 503 504 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 506 interrupt-names = "hc_irq", "pwr_irq"; 507 508 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 509 <&gcc GCC_SDCC2_APPS_CLK>, 510 <&xo_board>; 511 clock-names = "iface", "core", "xo"; 512 513 pinctrl-names = "default", "sleep"; 514 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 515 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 516 517 cd-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; 518 bus-width = <4>; 519 status = "disabled"; 520 }; 521 522 blsp1_dma: dma-controller@f9904000 { 523 compatible = "qcom,bam-v1.7.0"; 524 reg = <0xf9904000 0x19000>; 525 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 526 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 527 clock-names = "bam_clk"; 528 #dma-cells = <1>; 529 qcom,ee = <0>; 530 qcom,controlled-remotely; 531 num-channels = <24>; 532 qcom,num-ees = <4>; 533 }; 534 535 blsp1_uart2: serial@f991e000 { 536 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 537 reg = <0xf991e000 0x1000>; 538 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 539 clock-names = "core", "iface"; 540 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 541 <&gcc GCC_BLSP1_AHB_CLK>; 542 pinctrl-names = "default", "sleep"; 543 pinctrl-0 = <&blsp1_uart2_default>; 544 pinctrl-1 = <&blsp1_uart2_sleep>; 545 status = "disabled"; 546 }; 547 548 blsp1_i2c1: i2c@f9923000 { 549 compatible = "qcom,i2c-qup-v2.2.1"; 550 reg = <0xf9923000 0x500>; 551 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 553 <&gcc GCC_BLSP1_AHB_CLK>; 554 clock-names = "core", "iface"; 555 clock-frequency = <400000>; 556 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 557 dma-names = "tx", "rx"; 558 pinctrl-names = "default", "sleep"; 559 pinctrl-0 = <&i2c1_default>; 560 pinctrl-1 = <&i2c1_sleep>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 status = "disabled"; 564 }; 565 566 blsp1_spi1: spi@f9923000 { 567 compatible = "qcom,spi-qup-v2.2.1"; 568 reg = <0xf9923000 0x500>; 569 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 571 <&gcc GCC_BLSP1_AHB_CLK>; 572 clock-names = "core", "iface"; 573 dmas = <&blsp1_dma 12>, <&blsp1_dma 13>; 574 dma-names = "tx", "rx"; 575 pinctrl-names = "default", "sleep"; 576 pinctrl-0 = <&blsp1_spi1_default>; 577 pinctrl-1 = <&blsp1_spi1_sleep>; 578 #address-cells = <1>; 579 #size-cells = <0>; 580 status = "disabled"; 581 }; 582 583 blsp1_i2c2: i2c@f9924000 { 584 compatible = "qcom,i2c-qup-v2.2.1"; 585 reg = <0xf9924000 0x500>; 586 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 588 <&gcc GCC_BLSP1_AHB_CLK>; 589 clock-names = "core", "iface"; 590 clock-frequency = <400000>; 591 dmas = <&blsp1_dma 14>, <&blsp1_dma 15>; 592 dma-names = "tx", "rx"; 593 pinctrl-names = "default", "sleep"; 594 pinctrl-0 = <&i2c2_default>; 595 pinctrl-1 = <&i2c2_sleep>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 status = "disabled"; 599 }; 600 601 /* I2C3 doesn't exist */ 602 603 blsp1_i2c4: i2c@f9926000 { 604 compatible = "qcom,i2c-qup-v2.2.1"; 605 reg = <0xf9926000 0x500>; 606 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 607 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 608 <&gcc GCC_BLSP1_AHB_CLK>; 609 clock-names = "core", "iface"; 610 clock-frequency = <400000>; 611 dmas = <&blsp1_dma 18>, <&blsp1_dma 19>; 612 dma-names = "tx", "rx"; 613 pinctrl-names = "default", "sleep"; 614 pinctrl-0 = <&i2c4_default>; 615 pinctrl-1 = <&i2c4_sleep>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 status = "disabled"; 619 }; 620 621 blsp1_i2c5: i2c@f9927000 { 622 compatible = "qcom,i2c-qup-v2.2.1"; 623 reg = <0xf9927000 0x500>; 624 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 625 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 626 <&gcc GCC_BLSP1_AHB_CLK>; 627 clock-names = "core", "iface"; 628 clock-frequency = <400000>; 629 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 630 dma-names = "tx", "rx"; 631 pinctrl-names = "default", "sleep"; 632 pinctrl-0 = <&i2c5_default>; 633 pinctrl-1 = <&i2c5_sleep>; 634 #address-cells = <1>; 635 #size-cells = <0>; 636 status = "disabled"; 637 }; 638 639 blsp1_i2c6: i2c@f9928000 { 640 compatible = "qcom,i2c-qup-v2.2.1"; 641 reg = <0xf9928000 0x500>; 642 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 643 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 644 <&gcc GCC_BLSP1_AHB_CLK>; 645 clock-names = "core", "iface"; 646 clock-frequency = <400000>; 647 dmas = <&blsp1_dma 22>, <&blsp1_dma 23>; 648 dma-names = "tx", "rx"; 649 pinctrl-names = "default", "sleep"; 650 pinctrl-0 = <&i2c6_default>; 651 pinctrl-1 = <&i2c6_sleep>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 status = "disabled"; 655 }; 656 657 blsp2_dma: dma-controller@f9944000 { 658 compatible = "qcom,bam-v1.7.0"; 659 reg = <0xf9944000 0x19000>; 660 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 661 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 662 clock-names = "bam_clk"; 663 #dma-cells = <1>; 664 qcom,ee = <0>; 665 qcom,controlled-remotely; 666 num-channels = <24>; 667 qcom,num-ees = <4>; 668 }; 669 670 blsp2_uart2: serial@f995e000 { 671 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 672 reg = <0xf995e000 0x1000>; 673 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 674 clock-names = "core", "iface"; 675 clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, 676 <&gcc GCC_BLSP2_AHB_CLK>; 677 dmas = <&blsp2_dma 2>, <&blsp2_dma 3>; 678 dma-names = "tx", "rx"; 679 pinctrl-names = "default", "sleep"; 680 pinctrl-0 = <&blsp2_uart2_default>; 681 pinctrl-1 = <&blsp2_uart2_sleep>; 682 status = "disabled"; 683 }; 684 685 blsp2_i2c1: i2c@f9963000 { 686 compatible = "qcom,i2c-qup-v2.2.1"; 687 reg = <0xf9963000 0x500>; 688 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 689 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 690 <&gcc GCC_BLSP2_AHB_CLK>; 691 clock-names = "core", "iface"; 692 clock-frequency = <400000>; 693 dmas = <&blsp2_dma 12>, <&blsp2_dma 13>; 694 dma-names = "tx", "rx"; 695 pinctrl-names = "default", "sleep"; 696 pinctrl-0 = <&i2c7_default>; 697 pinctrl-1 = <&i2c7_sleep>; 698 #address-cells = <1>; 699 #size-cells = <0>; 700 status = "disabled"; 701 }; 702 703 blsp2_spi4: spi@f9966000 { 704 compatible = "qcom,spi-qup-v2.2.1"; 705 reg = <0xf9966000 0x500>; 706 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 707 clocks = <&gcc GCC_BLSP2_QUP4_SPI_APPS_CLK>, 708 <&gcc GCC_BLSP2_AHB_CLK>; 709 clock-names = "core", "iface"; 710 dmas = <&blsp2_dma 18>, <&blsp2_dma 19>; 711 dma-names = "tx", "rx"; 712 pinctrl-names = "default", "sleep"; 713 pinctrl-0 = <&blsp2_spi10_default>; 714 pinctrl-1 = <&blsp2_spi10_sleep>; 715 #address-cells = <1>; 716 #size-cells = <0>; 717 status = "disabled"; 718 }; 719 720 blsp2_i2c5: i2c@f9967000 { 721 compatible = "qcom,i2c-qup-v2.2.1"; 722 reg = <0xf9967000 0x500>; 723 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 724 clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>, 725 <&gcc GCC_BLSP2_AHB_CLK>; 726 clock-names = "core", "iface"; 727 clock-frequency = <355000>; 728 dmas = <&blsp2_dma 20>, <&blsp2_dma 21>; 729 dma-names = "tx", "rx"; 730 pinctrl-names = "default", "sleep"; 731 pinctrl-0 = <&i2c11_default>; 732 pinctrl-1 = <&i2c11_sleep>; 733 #address-cells = <1>; 734 #size-cells = <0>; 735 status = "disabled"; 736 }; 737 738 gcc: clock-controller@fc400000 { 739 compatible = "qcom,gcc-msm8994"; 740 #clock-cells = <1>; 741 #reset-cells = <1>; 742 #power-domain-cells = <1>; 743 reg = <0xfc400000 0x2000>; 744 745 clock-names = "xo", "sleep"; 746 clocks = <&xo_board>, <&sleep_clk>; 747 }; 748 749 rpm_msg_ram: sram@fc428000 { 750 compatible = "qcom,rpm-msg-ram"; 751 reg = <0xfc428000 0x4000>; 752 }; 753 754 restart@fc4ab000 { 755 compatible = "qcom,pshold"; 756 reg = <0xfc4ab000 0x4>; 757 }; 758 759 spmi_bus: spmi@fc4cf000 { 760 compatible = "qcom,spmi-pmic-arb"; 761 reg = <0xfc4cf000 0x1000>, 762 <0xfc4cb000 0x1000>, 763 <0xfc4ca000 0x1000>; 764 reg-names = "core", "intr", "cnfg"; 765 interrupt-names = "periph_irq"; 766 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 767 qcom,ee = <0>; 768 qcom,channel = <0>; 769 #address-cells = <2>; 770 #size-cells = <0>; 771 interrupt-controller; 772 #interrupt-cells = <4>; 773 }; 774 775 tcsr_mutex: hwlock@fd484000 { 776 compatible = "qcom,msm8994-tcsr-mutex", "qcom,tcsr-mutex"; 777 reg = <0xfd484000 0x1000>; 778 #hwlock-cells = <1>; 779 }; 780 781 tlmm: pinctrl@fd510000 { 782 compatible = "qcom,msm8994-pinctrl"; 783 reg = <0xfd510000 0x4000>; 784 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 785 gpio-controller; 786 gpio-ranges = <&tlmm 0 0 146>; 787 #gpio-cells = <2>; 788 interrupt-controller; 789 #interrupt-cells = <2>; 790 791 blsp1_uart2_default: blsp1-uart2-default-state { 792 pins = "gpio4", "gpio5"; 793 function = "blsp_uart2"; 794 drive-strength = <16>; 795 bias-disable; 796 }; 797 798 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 799 pins = "gpio4", "gpio5"; 800 function = "gpio"; 801 drive-strength = <2>; 802 bias-pull-down; 803 }; 804 805 blsp2_uart2_default: blsp2-uart2-default-state { 806 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 807 function = "blsp_uart8"; 808 drive-strength = <16>; 809 bias-disable; 810 }; 811 812 blsp2_uart2_sleep: blsp2-uart2-sleep-state { 813 pins = "gpio45", "gpio46", "gpio47", "gpio48"; 814 function = "gpio"; 815 drive-strength = <2>; 816 bias-disable; 817 }; 818 819 i2c1_default: i2c1-default-state { 820 pins = "gpio2", "gpio3"; 821 function = "blsp_i2c1"; 822 drive-strength = <2>; 823 bias-disable; 824 }; 825 826 i2c1_sleep: i2c1-sleep-state { 827 pins = "gpio2", "gpio3"; 828 function = "gpio"; 829 drive-strength = <2>; 830 bias-disable; 831 }; 832 833 i2c2_default: i2c2-default-state { 834 pins = "gpio6", "gpio7"; 835 function = "blsp_i2c2"; 836 drive-strength = <2>; 837 bias-disable; 838 }; 839 840 i2c2_sleep: i2c2-sleep-state { 841 pins = "gpio6", "gpio7"; 842 function = "gpio"; 843 drive-strength = <2>; 844 bias-disable; 845 }; 846 847 i2c4_default: i2c4-default-state { 848 pins = "gpio19", "gpio20"; 849 function = "blsp_i2c4"; 850 drive-strength = <2>; 851 bias-disable; 852 }; 853 854 i2c4_sleep: i2c4-sleep-state { 855 pins = "gpio19", "gpio20"; 856 function = "gpio"; 857 drive-strength = <2>; 858 bias-pull-down; 859 }; 860 861 i2c5_default: i2c5-default-state { 862 pins = "gpio23", "gpio24"; 863 function = "blsp_i2c5"; 864 drive-strength = <2>; 865 bias-disable; 866 }; 867 868 i2c5_sleep: i2c5-sleep-state { 869 pins = "gpio23", "gpio24"; 870 function = "gpio"; 871 drive-strength = <2>; 872 bias-disable; 873 }; 874 875 i2c6_default: i2c6-default-state { 876 pins = "gpio28", "gpio27"; 877 function = "blsp_i2c6"; 878 drive-strength = <2>; 879 bias-disable; 880 }; 881 882 i2c6_sleep: i2c6-sleep-state { 883 pins = "gpio28", "gpio27"; 884 function = "gpio"; 885 drive-strength = <2>; 886 bias-disable; 887 }; 888 889 i2c7_default: i2c7-default-state { 890 pins = "gpio44", "gpio43"; 891 function = "blsp_i2c7"; 892 drive-strength = <2>; 893 bias-disable; 894 }; 895 896 i2c7_sleep: i2c7-sleep-state { 897 pins = "gpio44", "gpio43"; 898 function = "gpio"; 899 drive-strength = <2>; 900 bias-disable; 901 }; 902 903 blsp2_spi10_default: blsp2-spi10-default-state { 904 default-pins { 905 pins = "gpio53", "gpio54", "gpio55"; 906 function = "blsp_spi10"; 907 drive-strength = <10>; 908 bias-pull-down; 909 }; 910 911 cs-pins { 912 pins = "gpio67"; 913 function = "gpio"; 914 drive-strength = <2>; 915 bias-disable; 916 }; 917 }; 918 919 blsp2_spi10_sleep: blsp2-spi10-sleep-state { 920 pins = "gpio53", "gpio54", "gpio55"; 921 function = "gpio"; 922 drive-strength = <2>; 923 bias-disable; 924 }; 925 926 i2c11_default: i2c11-default-state { 927 pins = "gpio83", "gpio84"; 928 function = "blsp_i2c11"; 929 drive-strength = <2>; 930 bias-disable; 931 }; 932 933 i2c11_sleep: i2c11-sleep-state { 934 pins = "gpio83", "gpio84"; 935 function = "gpio"; 936 drive-strength = <2>; 937 bias-disable; 938 }; 939 940 blsp1_spi1_default: blsp1-spi1-default-state { 941 default-pins { 942 pins = "gpio0", "gpio1", "gpio3"; 943 function = "blsp_spi1"; 944 drive-strength = <10>; 945 bias-pull-down; 946 }; 947 948 cs-pins { 949 pins = "gpio8"; 950 function = "gpio"; 951 drive-strength = <2>; 952 bias-disable; 953 }; 954 }; 955 956 blsp1_spi1_sleep: blsp1-spi1-sleep-state { 957 pins = "gpio0", "gpio1", "gpio3"; 958 function = "gpio"; 959 drive-strength = <2>; 960 bias-disable; 961 }; 962 963 sdc1_clk_on: clk-on-state { 964 pins = "sdc1_clk"; 965 bias-disable; 966 drive-strength = <16>; 967 }; 968 969 sdc1_clk_off: clk-off-state { 970 pins = "sdc1_clk"; 971 bias-disable; 972 drive-strength = <2>; 973 }; 974 975 sdc1_cmd_on: cmd-on-state { 976 pins = "sdc1_cmd"; 977 bias-pull-up; 978 drive-strength = <8>; 979 }; 980 981 sdc1_cmd_off: cmd-off-state { 982 pins = "sdc1_cmd"; 983 bias-pull-up; 984 drive-strength = <2>; 985 }; 986 987 sdc1_data_on: data-on-state { 988 pins = "sdc1_data"; 989 bias-pull-up; 990 drive-strength = <8>; 991 }; 992 993 sdc1_data_off: data-off-state { 994 pins = "sdc1_data"; 995 bias-pull-up; 996 drive-strength = <2>; 997 }; 998 999 sdc1_rclk_on: rclk-on-state { 1000 pins = "sdc1_rclk"; 1001 bias-pull-down; 1002 }; 1003 1004 sdc1_rclk_off: rclk-off-state { 1005 pins = "sdc1_rclk"; 1006 bias-pull-down; 1007 }; 1008 1009 sdc2_clk_on: sdc2-clk-on-state { 1010 pins = "sdc2_clk"; 1011 bias-disable; 1012 drive-strength = <10>; 1013 }; 1014 1015 sdc2_clk_off: sdc2-clk-off-state { 1016 pins = "sdc2_clk"; 1017 bias-disable; 1018 drive-strength = <2>; 1019 }; 1020 1021 sdc2_cmd_on: sdc2-cmd-on-state { 1022 pins = "sdc2_cmd"; 1023 bias-pull-up; 1024 drive-strength = <10>; 1025 }; 1026 1027 sdc2_cmd_off: sdc2-cmd-off-state { 1028 pins = "sdc2_cmd"; 1029 bias-pull-up; 1030 drive-strength = <2>; 1031 }; 1032 1033 sdc2_data_on: sdc2-data-on-state { 1034 pins = "sdc2_data"; 1035 bias-pull-up; 1036 drive-strength = <10>; 1037 }; 1038 1039 sdc2_data_off: sdc2-data-off-state { 1040 pins = "sdc2_data"; 1041 bias-pull-up; 1042 drive-strength = <2>; 1043 }; 1044 }; 1045 1046 mmcc: clock-controller@fd8c0000 { 1047 compatible = "qcom,mmcc-msm8994"; 1048 reg = <0xfd8c0000 0x5200>; 1049 #clock-cells = <1>; 1050 #reset-cells = <1>; 1051 #power-domain-cells = <1>; 1052 1053 clock-names = "xo", 1054 "gpll0", 1055 "mmssnoc_ahb", 1056 "oxili_gfx3d_clk_src", 1057 "dsi0pll", 1058 "dsi0pllbyte", 1059 "dsi1pll", 1060 "dsi1pllbyte", 1061 "hdmipll"; 1062 clocks = <&xo_board>, 1063 <&gcc GPLL0_OUT_MMSSCC>, 1064 <&rpmcc RPM_SMD_MMSSNOC_AHB_CLK>, 1065 <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, 1066 <0>, 1067 <0>, 1068 <0>, 1069 <0>, 1070 <0>; 1071 1072 assigned-clocks = <&mmcc MMPLL0_PLL>, 1073 <&mmcc MMPLL1_PLL>, 1074 <&mmcc MMPLL3_PLL>, 1075 <&mmcc MMPLL4_PLL>, 1076 <&mmcc MMPLL5_PLL>; 1077 assigned-clock-rates = <800000000>, 1078 <1167000000>, 1079 <1020000000>, 1080 <960000000>, 1081 <600000000>; 1082 }; 1083 1084 ocmem: sram@fdd00000 { 1085 compatible = "qcom,msm8974-ocmem"; 1086 reg = <0xfdd00000 0x2000>, 1087 <0xfec00000 0x200000>; 1088 reg-names = "ctrl", "mem"; 1089 ranges = <0 0xfec00000 0x200000>; 1090 clocks = <&rpmcc RPM_SMD_OCMEMGX_CLK>, 1091 <&mmcc OCMEMCX_OCMEMNOC_CLK>; 1092 clock-names = "core", "iface"; 1093 1094 #address-cells = <1>; 1095 #size-cells = <1>; 1096 1097 gmu_sram: gmu-sram@0 { 1098 reg = <0x0 0x180000>; 1099 }; 1100 }; 1101 }; 1102 1103 timer: timer { 1104 compatible = "arm,armv8-timer"; 1105 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1106 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1107 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 1108 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 1109 }; 1110 1111 vph_pwr: vph-pwr-regulator { 1112 compatible = "regulator-fixed"; 1113 regulator-name = "vph_pwr"; 1114 1115 regulator-min-microvolt = <3600000>; 1116 regulator-max-microvolt = <3600000>; 1117 1118 regulator-always-on; 1119 }; 1120}; 1121
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