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msm8953.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/msm8953.dtsi
1// SPDX-License-Identifier: BSD-3-Clause 2/* Copyright (c) 2022, The Linux Foundation. All rights reserved. */ 3 4#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 5#include <dt-bindings/clock/qcom,gcc-msm8953.h> 6#include <dt-bindings/clock/qcom,rpmcc.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interconnect/qcom,msm8953.h> 9#include <dt-bindings/interconnect/qcom,rpm-icc.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/qcom-rpmpd.h> 12#include <dt-bindings/soc/qcom,apr.h> 13#include <dt-bindings/sound/qcom,q6afe.h> 14#include <dt-bindings/sound/qcom,q6asm.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 chosen { }; 24 25 clocks { 26 sleep_clk: sleep-clk { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <32768>; 30 }; 31 32 xo_board: xo-board { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <19200000>; 36 clock-output-names = "xo"; 37 }; 38 }; 39 40 cpus { 41 #address-cells = <1>; 42 #size-cells = <0>; 43 44 cpu0: cpu@0 { 45 device_type = "cpu"; 46 compatible = "arm,cortex-a53"; 47 reg = <0x0>; 48 enable-method = "psci"; 49 capacity-dmips-mhz = <1024>; 50 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 51 &bimc SLV_EBI RPM_ACTIVE_TAG>; 52 next-level-cache = <&l2_0>; 53 #cooling-cells = <2>; 54 }; 55 56 cpu1: cpu@1 { 57 device_type = "cpu"; 58 compatible = "arm,cortex-a53"; 59 reg = <0x1>; 60 enable-method = "psci"; 61 capacity-dmips-mhz = <1024>; 62 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 63 &bimc SLV_EBI RPM_ACTIVE_TAG>; 64 next-level-cache = <&l2_0>; 65 #cooling-cells = <2>; 66 }; 67 68 cpu2: cpu@2 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x2>; 72 enable-method = "psci"; 73 capacity-dmips-mhz = <1024>; 74 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 75 &bimc SLV_EBI RPM_ACTIVE_TAG>; 76 next-level-cache = <&l2_0>; 77 #cooling-cells = <2>; 78 }; 79 80 cpu3: cpu@3 { 81 device_type = "cpu"; 82 compatible = "arm,cortex-a53"; 83 reg = <0x3>; 84 enable-method = "psci"; 85 capacity-dmips-mhz = <1024>; 86 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 87 &bimc SLV_EBI RPM_ACTIVE_TAG>; 88 next-level-cache = <&l2_0>; 89 #cooling-cells = <2>; 90 }; 91 92 cpu4: cpu@100 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x100>; 96 enable-method = "psci"; 97 capacity-dmips-mhz = <1024>; 98 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 99 &bimc SLV_EBI RPM_ACTIVE_TAG>; 100 next-level-cache = <&l2_1>; 101 #cooling-cells = <2>; 102 }; 103 104 cpu5: cpu@101 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a53"; 107 reg = <0x101>; 108 enable-method = "psci"; 109 capacity-dmips-mhz = <1024>; 110 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 111 &bimc SLV_EBI RPM_ACTIVE_TAG>; 112 next-level-cache = <&l2_1>; 113 #cooling-cells = <2>; 114 }; 115 116 cpu6: cpu@102 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53"; 119 reg = <0x102>; 120 enable-method = "psci"; 121 capacity-dmips-mhz = <1024>; 122 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 123 &bimc SLV_EBI RPM_ACTIVE_TAG>; 124 next-level-cache = <&l2_1>; 125 #cooling-cells = <2>; 126 }; 127 128 cpu7: cpu@103 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a53"; 131 reg = <0x103>; 132 enable-method = "psci"; 133 capacity-dmips-mhz = <1024>; 134 interconnects = <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 135 &bimc SLV_EBI RPM_ACTIVE_TAG>; 136 next-level-cache = <&l2_1>; 137 #cooling-cells = <2>; 138 }; 139 140 cpu-map { 141 cluster0 { 142 core0 { 143 cpu = <&cpu0>; 144 }; 145 core1 { 146 cpu = <&cpu1>; 147 }; 148 core2 { 149 cpu = <&cpu2>; 150 }; 151 core3 { 152 cpu = <&cpu3>; 153 }; 154 }; 155 156 cluster1 { 157 core0 { 158 cpu = <&cpu4>; 159 }; 160 core1 { 161 cpu = <&cpu5>; 162 }; 163 core2 { 164 cpu = <&cpu6>; 165 }; 166 core3 { 167 cpu = <&cpu7>; 168 }; 169 }; 170 }; 171 172 l2_0: l2-cache-0 { 173 compatible = "cache"; 174 cache-level = <2>; 175 cache-unified; 176 }; 177 178 l2_1: l2-cache-1 { 179 compatible = "cache"; 180 cache-level = <2>; 181 cache-unified; 182 }; 183 }; 184 185 firmware { 186 scm: scm { 187 compatible = "qcom,scm-msm8953", "qcom,scm"; 188 clocks = <&gcc GCC_CRYPTO_CLK>, 189 <&gcc GCC_CRYPTO_AXI_CLK>, 190 <&gcc GCC_CRYPTO_AHB_CLK>; 191 clock-names = "core", "bus", "iface"; 192 #reset-cells = <1>; 193 }; 194 }; 195 196 memory@10000000 { 197 device_type = "memory"; 198 /* We expect the bootloader to fill in the reg */ 199 reg = <0 0x10000000 0 0>; 200 }; 201 202 pmu { 203 compatible = "arm,cortex-a53-pmu"; 204 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 205 }; 206 207 psci { 208 compatible = "arm,psci-1.0"; 209 method = "smc"; 210 }; 211 212 rpm: remoteproc { 213 compatible = "qcom,msm8953-rpm-proc", "qcom,rpm-proc"; 214 215 smd-edge { 216 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 217 mboxes = <&apcs 0>; 218 qcom,smd-edge = <15>; 219 220 rpm_requests: rpm-requests { 221 compatible = "qcom,rpm-msm8953", "qcom,smd-rpm"; 222 qcom,smd-channels = "rpm_requests"; 223 224 rpmcc: clock-controller { 225 compatible = "qcom,rpmcc-msm8953", "qcom,rpmcc"; 226 clocks = <&xo_board>; 227 clock-names = "xo"; 228 #clock-cells = <1>; 229 }; 230 231 rpmpd: power-controller { 232 compatible = "qcom,msm8953-rpmpd"; 233 #power-domain-cells = <1>; 234 operating-points-v2 = <&rpmpd_opp_table>; 235 236 rpmpd_opp_table: opp-table { 237 compatible = "operating-points-v2"; 238 239 rpmpd_opp_ret: opp1 { 240 opp-level = <RPM_SMD_LEVEL_RETENTION>; 241 }; 242 243 rpmpd_opp_ret_plus: opp2 { 244 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 245 }; 246 247 rpmpd_opp_min_svs: opp3 { 248 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 249 }; 250 251 rpmpd_opp_low_svs: opp4 { 252 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 253 }; 254 255 rpmpd_opp_svs: opp5 { 256 opp-level = <RPM_SMD_LEVEL_SVS>; 257 }; 258 259 rpmpd_opp_svs_plus: opp6 { 260 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 261 }; 262 263 rpmpd_opp_nom: opp7 { 264 opp-level = <RPM_SMD_LEVEL_NOM>; 265 }; 266 267 rpmpd_opp_nom_plus: opp8 { 268 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 269 }; 270 271 rpmpd_opp_turbo: opp9 { 272 opp-level = <RPM_SMD_LEVEL_TURBO>; 273 }; 274 }; 275 }; 276 }; 277 }; 278 }; 279 280 reserved-memory { 281 #address-cells = <2>; 282 #size-cells = <2>; 283 ranges; 284 285 zap_shader_region: zap@81800000 { 286 compatible = "shared-dma-pool"; 287 reg = <0x0 0x81800000 0x0 0x2000>; 288 no-map; 289 }; 290 291 qseecom_mem: qseecom@85b00000 { 292 reg = <0x0 0x85b00000 0x0 0x800000>; 293 no-map; 294 }; 295 296 smem_mem: smem@86300000 { 297 compatible = "qcom,smem"; 298 reg = <0x0 0x86300000 0x0 0x100000>; 299 qcom,rpm-msg-ram = <&rpm_msg_ram>; 300 hwlocks = <&tcsr_mutex 3>; 301 no-map; 302 }; 303 304 reserved@86400000 { 305 reg = <0x0 0x86400000 0x0 0x400000>; 306 no-map; 307 }; 308 309 mpss_mem: mpss@86c00000 { 310 reg = <0x0 0x86c00000 0x0 0x6a00000>; 311 no-map; 312 }; 313 314 adsp_fw_mem: adsp@8d600000 { 315 reg = <0x0 0x8d600000 0x0 0x1100000>; 316 no-map; 317 }; 318 319 wcnss_fw_mem: wcnss@8e700000 { 320 reg = <0x0 0x8e700000 0x0 0x700000>; 321 no-map; 322 }; 323 324 dfps_data_mem: dfps-data@90000000 { 325 reg = <0 0x90000000 0 0x1000>; 326 no-map; 327 }; 328 329 cont_splash_mem: cont-splash@90001000 { 330 reg = <0x0 0x90001000 0x0 0x13ff000>; 331 no-map; 332 }; 333 334 venus_mem: venus@91400000 { 335 reg = <0x0 0x91400000 0x0 0x700000>; 336 no-map; 337 }; 338 339 mba_mem: mba@92000000 { 340 reg = <0x0 0x92000000 0x0 0x100000>; 341 no-map; 342 }; 343 344 rmtfs@f2d00000 { 345 compatible = "qcom,rmtfs-mem"; 346 reg = <0x0 0xf2d00000 0x0 0x180000>; 347 no-map; 348 349 qcom,client-id = <1>; 350 }; 351 }; 352 353 smp2p-adsp { 354 compatible = "qcom,smp2p"; 355 qcom,smem = <443>, <429>; 356 357 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 358 359 mboxes = <&apcs 10>; 360 361 qcom,local-pid = <0>; 362 qcom,remote-pid = <2>; 363 364 smp2p_adsp_out: master-kernel { 365 qcom,entry-name = "master-kernel"; 366 #qcom,smem-state-cells = <1>; 367 }; 368 369 smp2p_adsp_in: slave-kernel { 370 qcom,entry-name = "slave-kernel"; 371 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 }; 375 }; 376 377 smp2p-modem { 378 compatible = "qcom,smp2p"; 379 qcom,smem = <435>, <428>; 380 381 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 382 383 mboxes = <&apcs 14>; 384 385 qcom,local-pid = <0>; 386 qcom,remote-pid = <1>; 387 388 smp2p_modem_out: master-kernel { 389 qcom,entry-name = "master-kernel"; 390 391 #qcom,smem-state-cells = <1>; 392 }; 393 394 smp2p_modem_in: slave-kernel { 395 qcom,entry-name = "slave-kernel"; 396 397 interrupt-controller; 398 #interrupt-cells = <2>; 399 }; 400 }; 401 402 smp2p-wcnss { 403 compatible = "qcom,smp2p"; 404 qcom,smem = <451>, <431>; 405 406 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 407 408 mboxes = <&apcs 18>; 409 410 qcom,local-pid = <0>; 411 qcom,remote-pid = <4>; 412 413 smp2p_wcnss_out: master-kernel { 414 qcom,entry-name = "master-kernel"; 415 416 #qcom,smem-state-cells = <1>; 417 }; 418 419 smp2p_wcnss_in: slave-kernel { 420 qcom,entry-name = "slave-kernel"; 421 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 }; 425 }; 426 427 smsm { 428 compatible = "qcom,smsm"; 429 430 #address-cells = <1>; 431 #size-cells = <0>; 432 433 mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; 434 435 apps_smsm: apps@0 { 436 reg = <0>; 437 438 #qcom,smem-state-cells = <1>; 439 }; 440 441 modem_smsm: modem@1 { 442 reg = <1>; 443 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 444 445 interrupt-controller; 446 #interrupt-cells = <2>; 447 }; 448 449 wcnss_smsm: wcnss@6 { 450 reg = <6>; 451 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 452 453 interrupt-controller; 454 #interrupt-cells = <2>; 455 }; 456 }; 457 458 soc: soc@0 { 459 #address-cells = <1>; 460 #size-cells = <1>; 461 ranges = <0 0 0 0xffffffff>; 462 compatible = "simple-bus"; 463 464 rpm_msg_ram: sram@60000 { 465 compatible = "qcom,rpm-msg-ram"; 466 reg = <0x00060000 0x8000>; 467 }; 468 469 hsusb_phy: phy@79000 { 470 compatible = "qcom,msm8953-qusb2-phy"; 471 reg = <0x00079000 0x180>; 472 #phy-cells = <0>; 473 474 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 475 <&gcc GCC_QUSB_REF_CLK>; 476 clock-names = "cfg_ahb", "ref"; 477 478 qcom,tcsr-syscon = <&tcsr_phy_clk_scheme_sel>; 479 480 resets = <&gcc GCC_QUSB2_PHY_BCR>; 481 482 status = "disabled"; 483 }; 484 485 rng@e3000 { 486 compatible = "qcom,prng"; 487 reg = <0x000e3000 0x1000>; 488 clocks = <&gcc GCC_PRNG_AHB_CLK>; 489 clock-names = "core"; 490 }; 491 492 bimc: interconnect@400000 { 493 compatible = "qcom,msm8953-bimc"; 494 reg = <0x00400000 0x5a000>; 495 496 #interconnect-cells = <2>; 497 }; 498 499 tsens0: thermal-sensor@4a9000 { 500 compatible = "qcom,msm8953-tsens", "qcom,tsens-v2"; 501 reg = <0x004a9000 0x1000>, /* TM */ 502 <0x004a8000 0x1000>; /* SROT */ 503 #qcom,sensors = <16>; 504 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>; 506 interrupt-names = "uplow", "critical"; 507 #thermal-sensor-cells = <1>; 508 }; 509 510 restart@4ab000 { 511 compatible = "qcom,pshold"; 512 reg = <0x004ab000 0x4>; 513 }; 514 515 pcnoc: interconnect@500000 { 516 compatible = "qcom,msm8953-pcnoc"; 517 reg = <0x00500000 0x12080>; 518 519 clocks = <&gcc GCC_PCNOC_USB3_AXI_CLK>; 520 clock-names = "pcnoc_usb3_axi"; 521 522 #interconnect-cells = <2>; 523 }; 524 525 snoc: interconnect@580000 { 526 compatible = "qcom,msm8953-snoc"; 527 reg = <0x00580000 0x16080>; 528 529 #interconnect-cells = <2>; 530 531 snoc_mm: interconnect-snoc { 532 compatible = "qcom,msm8953-snoc-mm"; 533 534 #interconnect-cells = <2>; 535 }; 536 }; 537 538 tlmm: pinctrl@1000000 { 539 compatible = "qcom,msm8953-pinctrl"; 540 reg = <0x01000000 0x300000>; 541 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 542 gpio-controller; 543 gpio-ranges = <&tlmm 0 0 142>; 544 #gpio-cells = <2>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 548 uart_console_active: uart-console-active-state { 549 pins = "gpio4", "gpio5"; 550 function = "blsp_uart2"; 551 drive-strength = <2>; 552 bias-disable; 553 }; 554 555 uart_console_sleep: uart-console-sleep-state { 556 pins = "gpio4", "gpio5"; 557 function = "blsp_uart2"; 558 drive-strength = <2>; 559 bias-pull-down; 560 }; 561 562 sdc1_clk_on: sdc1-clk-on-state { 563 pins = "sdc1_clk"; 564 bias-disable; 565 drive-strength = <16>; 566 }; 567 568 sdc1_clk_off: sdc1-clk-off-state { 569 pins = "sdc1_clk"; 570 bias-disable; 571 drive-strength = <2>; 572 }; 573 574 sdc1_cmd_on: sdc1-cmd-on-state { 575 pins = "sdc1_cmd"; 576 bias-disable; 577 drive-strength = <10>; 578 }; 579 580 sdc1_cmd_off: sdc1-cmd-off-state { 581 pins = "sdc1_cmd"; 582 bias-disable; 583 drive-strength = <2>; 584 }; 585 586 sdc1_data_on: sdc1-data-on-state { 587 pins = "sdc1_data"; 588 bias-pull-up; 589 drive-strength = <10>; 590 }; 591 592 sdc1_data_off: sdc1-data-off-state { 593 pins = "sdc1_data"; 594 bias-pull-up; 595 drive-strength = <2>; 596 }; 597 598 sdc1_rclk_on: sdc1-rclk-on-state { 599 pins = "sdc1_rclk"; 600 bias-pull-down; 601 }; 602 603 sdc1_rclk_off: sdc1-rclk-off-state { 604 pins = "sdc1_rclk"; 605 bias-pull-down; 606 }; 607 608 sdc2_clk_on: sdc2-clk-on-state { 609 pins = "sdc2_clk"; 610 drive-strength = <16>; 611 bias-disable; 612 }; 613 614 sdc2_clk_off: sdc2-clk-off-state { 615 pins = "sdc2_clk"; 616 bias-disable; 617 drive-strength = <2>; 618 }; 619 620 sdc2_cmd_on: sdc2-cmd-on-state { 621 pins = "sdc2_cmd"; 622 bias-pull-up; 623 drive-strength = <10>; 624 }; 625 626 sdc2_cmd_off: sdc2-cmd-off-state { 627 pins = "sdc2_cmd"; 628 bias-pull-up; 629 drive-strength = <2>; 630 }; 631 632 sdc2_data_on: sdc2-data-on-state { 633 pins = "sdc2_data"; 634 bias-pull-up; 635 drive-strength = <10>; 636 }; 637 638 sdc2_data_off: sdc2-data-off-state { 639 pins = "sdc2_data"; 640 bias-pull-up; 641 drive-strength = <2>; 642 }; 643 644 sdc2_cd_on: cd-on-state { 645 pins = "gpio133"; 646 function = "gpio"; 647 drive-strength = <2>; 648 bias-pull-up; 649 }; 650 651 sdc2_cd_off: cd-off-state { 652 pins = "gpio133"; 653 function = "gpio"; 654 drive-strength = <2>; 655 bias-disable; 656 }; 657 658 gpio_key_default: gpio-key-default-state { 659 pins = "gpio85"; 660 function = "gpio"; 661 drive-strength = <2>; 662 bias-pull-up; 663 }; 664 665 i2c_1_default: i2c-1-default-state { 666 pins = "gpio2", "gpio3"; 667 function = "blsp_i2c1"; 668 drive-strength = <2>; 669 bias-disable; 670 }; 671 672 i2c_1_sleep: i2c-1-sleep-state { 673 pins = "gpio2", "gpio3"; 674 function = "gpio"; 675 drive-strength = <2>; 676 bias-disable; 677 }; 678 679 i2c_2_default: i2c-2-default-state { 680 pins = "gpio6", "gpio7"; 681 function = "blsp_i2c2"; 682 drive-strength = <2>; 683 bias-disable; 684 }; 685 686 i2c_2_sleep: i2c-2-sleep-state { 687 pins = "gpio6", "gpio7"; 688 function = "gpio"; 689 drive-strength = <2>; 690 bias-disable; 691 }; 692 693 i2c_3_default: i2c-3-default-state { 694 pins = "gpio10", "gpio11"; 695 function = "blsp_i2c3"; 696 drive-strength = <2>; 697 bias-disable; 698 }; 699 700 i2c_3_sleep: i2c-3-sleep-state { 701 pins = "gpio10", "gpio11"; 702 function = "gpio"; 703 drive-strength = <2>; 704 bias-disable; 705 }; 706 707 i2c_4_default: i2c-4-default-state { 708 pins = "gpio14", "gpio15"; 709 function = "blsp_i2c4"; 710 drive-strength = <2>; 711 bias-disable; 712 }; 713 714 i2c_4_sleep: i2c-4-sleep-state { 715 pins = "gpio14", "gpio15"; 716 function = "gpio"; 717 drive-strength = <2>; 718 bias-disable; 719 }; 720 721 i2c_5_default: i2c-5-default-state { 722 pins = "gpio18", "gpio19"; 723 function = "blsp_i2c5"; 724 drive-strength = <2>; 725 bias-disable; 726 }; 727 728 i2c_5_sleep: i2c-5-sleep-state { 729 pins = "gpio18", "gpio19"; 730 function = "gpio"; 731 drive-strength = <2>; 732 bias-disable; 733 }; 734 735 i2c_6_default: i2c-6-default-state { 736 pins = "gpio22", "gpio23"; 737 function = "blsp_i2c6"; 738 drive-strength = <2>; 739 bias-disable; 740 }; 741 742 i2c_6_sleep: i2c-6-sleep-state { 743 pins = "gpio22", "gpio23"; 744 function = "gpio"; 745 drive-strength = <2>; 746 bias-disable; 747 }; 748 749 i2c_7_default: i2c-7-default-state { 750 pins = "gpio135", "gpio136"; 751 function = "blsp_i2c7"; 752 drive-strength = <2>; 753 bias-disable; 754 }; 755 756 i2c_7_sleep: i2c-7-sleep-state { 757 pins = "gpio135", "gpio136"; 758 function = "gpio"; 759 drive-strength = <2>; 760 bias-disable; 761 }; 762 763 i2c_8_default: i2c-8-default-state { 764 pins = "gpio98", "gpio99"; 765 function = "blsp_i2c8"; 766 drive-strength = <2>; 767 bias-disable; 768 }; 769 770 i2c_8_sleep: i2c-8-sleep-state { 771 pins = "gpio98", "gpio99"; 772 function = "gpio"; 773 drive-strength = <2>; 774 bias-disable; 775 }; 776 777 spi_3_default: spi-3-default-state { 778 cs-pins { 779 pins = "gpio10"; 780 function = "blsp_spi3"; 781 drive-strength = <2>; 782 bias-disable; 783 }; 784 785 spi-pins { 786 pins = "gpio8", "gpio9", "gpio11"; 787 function = "blsp_spi3"; 788 drive-strength = <12>; 789 bias-disable; 790 }; 791 }; 792 793 spi_3_sleep: spi-3-sleep-state { 794 cs-pins { 795 pins = "gpio10"; 796 function = "gpio"; 797 drive-strength = <2>; 798 bias-disable; 799 }; 800 801 spi-pins { 802 pins = "gpio8", "gpio9", "gpio11"; 803 function = "gpio"; 804 drive-strength = <2>; 805 bias-pull-down; 806 }; 807 }; 808 809 spi_5_default: spi-5-default-state { 810 cs-pins { 811 pins = "gpio18"; 812 function = "blsp_spi5"; 813 drive-strength = <2>; 814 bias-disable; 815 }; 816 817 spi-pins { 818 pins = "gpio16", "gpio17", "gpio19"; 819 function = "blsp_spi5"; 820 drive-strength = <12>; 821 bias-disable; 822 }; 823 }; 824 825 spi_5_sleep: spi-5-sleep-state { 826 cs-pins { 827 pins = "gpio18"; 828 function = "gpio"; 829 drive-strength = <2>; 830 bias-disable; 831 }; 832 833 spi-pins { 834 pins = "gpio16", "gpio17", "gpio19"; 835 function = "gpio"; 836 drive-strength = <2>; 837 bias-pull-down; 838 }; 839 }; 840 841 spi_6_default: spi-6-default-state { 842 cs-pins { 843 pins = "gpio22"; 844 function = "blsp_spi6"; 845 drive-strength = <2>; 846 bias-disable; 847 }; 848 849 spi-pins { 850 pins = "gpio20", "gpio21", "gpio23"; 851 function = "blsp_spi6"; 852 drive-strength = <12>; 853 bias-disable; 854 }; 855 }; 856 857 spi_6_sleep: spi-6-sleep-state { 858 cs-pins { 859 pins = "gpio22"; 860 function = "gpio"; 861 drive-strength = <2>; 862 bias-disable; 863 }; 864 865 spi-pins { 866 pins = "gpio20", "gpio21", "gpio23"; 867 function = "gpio"; 868 drive-strength = <2>; 869 bias-pull-down; 870 }; 871 }; 872 873 spi_7_default: spi-7-default-state { 874 cs-pins { 875 pins = "gpio136"; 876 function = "blsp_spi7"; 877 drive-strength = <2>; 878 bias-disable; 879 }; 880 881 spi-pins { 882 pins = "gpio135", "gpio137", "gpio138"; 883 function = "blsp_spi7"; 884 drive-strength = <12>; 885 bias-disable; 886 }; 887 }; 888 889 spi_7_sleep: spi-7-sleep-state { 890 cs-pins { 891 pins = "gpio136"; 892 function = "gpio"; 893 drive-strength = <2>; 894 bias-disable; 895 }; 896 897 spi-pins { 898 pins = "gpio135", "gpio137", "gpio138"; 899 function = "gpio"; 900 drive-strength = <2>; 901 bias-pull-down; 902 }; 903 }; 904 905 uart_5_default: uart-5-default-state { 906 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 907 function = "blsp_uart5"; 908 drive-strength = <16>; 909 bias-disable; 910 }; 911 912 uart_5_sleep: uart-5-sleep-state { 913 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 914 function = "gpio"; 915 drive-strength = <2>; 916 bias-disable; 917 }; 918 919 wcnss_pin_a: wcnss-active-state { 920 921 wcss-wlan2-pins { 922 pins = "gpio76"; 923 function = "wcss_wlan2"; 924 drive-strength = <6>; 925 bias-pull-up; 926 }; 927 928 wcss-wlan1-pins { 929 pins = "gpio77"; 930 function = "wcss_wlan1"; 931 drive-strength = <6>; 932 bias-pull-up; 933 }; 934 935 wcss-wlan0-pins { 936 pins = "gpio78"; 937 function = "wcss_wlan0"; 938 drive-strength = <6>; 939 bias-pull-up; 940 }; 941 942 wcss-wlan-pins { 943 pins = "gpio79", "gpio80"; 944 function = "wcss_wlan"; 945 drive-strength = <6>; 946 bias-pull-up; 947 }; 948 }; 949 }; 950 951 gcc: clock-controller@1800000 { 952 compatible = "qcom,gcc-msm8953"; 953 reg = <0x01800000 0x80000>; 954 #clock-cells = <1>; 955 #reset-cells = <1>; 956 #power-domain-cells = <1>; 957 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 958 <&sleep_clk>, 959 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 960 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 961 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 962 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; 963 clock-names = "xo", 964 "sleep", 965 "dsi0pll", 966 "dsi0pllbyte", 967 "dsi1pll", 968 "dsi1pllbyte"; 969 }; 970 971 tcsr_mutex: hwlock@1905000 { 972 compatible = "qcom,tcsr-mutex"; 973 reg = <0x01905000 0x20000>; 974 #hwlock-cells = <1>; 975 }; 976 977 tcsr: syscon@1937000 { 978 compatible = "qcom,tcsr-msm8953", "syscon"; 979 reg = <0x01937000 0x30000>; 980 }; 981 982 tcsr_phy_clk_scheme_sel: syscon@193f044 { 983 compatible = "qcom,tcsr-msm8953", "syscon"; 984 reg = <0x0193f044 0x4>; 985 }; 986 987 mdss: display-subsystem@1a00000 { 988 compatible = "qcom,mdss"; 989 990 reg = <0x01a00000 0x1000>, 991 <0x01ab0000 0x1040>; 992 reg-names = "mdss_phys", 993 "vbif_phys"; 994 995 power-domains = <&gcc MDSS_GDSC>; 996 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 997 998 interrupt-controller; 999 #interrupt-cells = <1>; 1000 1001 interconnects = <&snoc_mm MAS_MDP RPM_ALWAYS_TAG 1002 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1003 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1004 &pcnoc SLV_DISP_SS_CFG RPM_ACTIVE_TAG>; 1005 interconnect-names = "mdp0-mem", 1006 "cpu-cfg"; 1007 1008 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1009 <&gcc GCC_MDSS_AXI_CLK>, 1010 <&gcc GCC_MDSS_VSYNC_CLK>, 1011 <&gcc GCC_MDSS_MDP_CLK>; 1012 clock-names = "iface", 1013 "bus", 1014 "vsync", 1015 "core"; 1016 1017 resets = <&gcc GCC_MDSS_BCR>; 1018 1019 #address-cells = <1>; 1020 #size-cells = <1>; 1021 ranges; 1022 1023 status = "disabled"; 1024 1025 mdp: display-controller@1a01000 { 1026 compatible = "qcom,msm8953-mdp5", "qcom,mdp5"; 1027 reg = <0x01a01000 0x89000>; 1028 reg-names = "mdp_phys"; 1029 1030 interrupt-parent = <&mdss>; 1031 interrupts = <0>; 1032 1033 power-domains = <&gcc MDSS_GDSC>; 1034 1035 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1036 <&gcc GCC_MDSS_AXI_CLK>, 1037 <&gcc GCC_MDSS_MDP_CLK>, 1038 <&gcc GCC_MDSS_VSYNC_CLK>; 1039 clock-names = "iface", 1040 "bus", 1041 "core", 1042 "vsync"; 1043 1044 iommus = <&apps_iommu 0x15>; 1045 1046 ports { 1047 #address-cells = <1>; 1048 #size-cells = <0>; 1049 1050 port@0 { 1051 reg = <0>; 1052 mdp5_intf1_out: endpoint { 1053 remote-endpoint = <&mdss_dsi0_in>; 1054 }; 1055 }; 1056 1057 port@1 { 1058 reg = <1>; 1059 mdp5_intf2_out: endpoint { 1060 remote-endpoint = <&mdss_dsi1_in>; 1061 }; 1062 }; 1063 }; 1064 }; 1065 1066 mdss_dsi0: dsi@1a94000 { 1067 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1068 reg = <0x01a94000 0x400>; 1069 reg-names = "dsi_ctrl"; 1070 1071 interrupt-parent = <&mdss>; 1072 interrupts = <4>; 1073 1074 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1075 <&gcc PCLK0_CLK_SRC>; 1076 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1077 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1078 1079 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1080 <&gcc GCC_MDSS_AHB_CLK>, 1081 <&gcc GCC_MDSS_AXI_CLK>, 1082 <&gcc GCC_MDSS_BYTE0_CLK>, 1083 <&gcc GCC_MDSS_PCLK0_CLK>, 1084 <&gcc GCC_MDSS_ESC0_CLK>; 1085 clock-names = "mdp_core", 1086 "iface", 1087 "bus", 1088 "byte", 1089 "pixel", 1090 "core"; 1091 1092 phys = <&mdss_dsi0_phy>; 1093 1094 #address-cells = <1>; 1095 #size-cells = <0>; 1096 1097 status = "disabled"; 1098 1099 ports { 1100 #address-cells = <1>; 1101 #size-cells = <0>; 1102 1103 port@0 { 1104 reg = <0>; 1105 mdss_dsi0_in: endpoint { 1106 remote-endpoint = <&mdp5_intf1_out>; 1107 }; 1108 }; 1109 1110 port@1 { 1111 reg = <1>; 1112 mdss_dsi0_out: endpoint { 1113 }; 1114 }; 1115 }; 1116 }; 1117 1118 mdss_dsi0_phy: phy@1a94400 { 1119 compatible = "qcom,dsi-phy-14nm-8953"; 1120 reg = <0x01a94400 0x100>, 1121 <0x01a94500 0x300>, 1122 <0x01a94800 0x188>; 1123 reg-names = "dsi_phy", 1124 "dsi_phy_lane", 1125 "dsi_pll"; 1126 1127 #clock-cells = <1>; 1128 #phy-cells = <0>; 1129 1130 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1131 clock-names = "iface", "ref"; 1132 1133 status = "disabled"; 1134 }; 1135 1136 mdss_dsi1: dsi@1a96000 { 1137 compatible = "qcom,msm8953-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1138 reg = <0x01a96000 0x400>; 1139 reg-names = "dsi_ctrl"; 1140 1141 interrupt-parent = <&mdss>; 1142 interrupts = <5>; 1143 1144 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 1145 <&gcc PCLK1_CLK_SRC>; 1146 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1147 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 1148 1149 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1150 <&gcc GCC_MDSS_AHB_CLK>, 1151 <&gcc GCC_MDSS_AXI_CLK>, 1152 <&gcc GCC_MDSS_BYTE1_CLK>, 1153 <&gcc GCC_MDSS_PCLK1_CLK>, 1154 <&gcc GCC_MDSS_ESC1_CLK>; 1155 clock-names = "mdp_core", 1156 "iface", 1157 "bus", 1158 "byte", 1159 "pixel", 1160 "core"; 1161 1162 phys = <&mdss_dsi1_phy>; 1163 1164 status = "disabled"; 1165 1166 ports { 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 1170 port@0 { 1171 reg = <0>; 1172 mdss_dsi1_in: endpoint { 1173 remote-endpoint = <&mdp5_intf2_out>; 1174 }; 1175 }; 1176 1177 port@1 { 1178 reg = <1>; 1179 mdss_dsi1_out: endpoint { 1180 }; 1181 }; 1182 }; 1183 }; 1184 1185 mdss_dsi1_phy: phy@1a96400 { 1186 compatible = "qcom,dsi-phy-14nm-8953"; 1187 reg = <0x01a96400 0x100>, 1188 <0x01a96500 0x300>, 1189 <0x01a96800 0x188>; 1190 reg-names = "dsi_phy", 1191 "dsi_phy_lane", 1192 "dsi_pll"; 1193 1194 #clock-cells = <1>; 1195 #phy-cells = <0>; 1196 1197 clocks = <&gcc GCC_MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1198 clock-names = "iface", "ref"; 1199 1200 status = "disabled"; 1201 }; 1202 }; 1203 1204 gpu: gpu@1c00000 { 1205 compatible = "qcom,adreno-506.0", "qcom,adreno"; 1206 reg = <0x01c00000 0x40000>; 1207 reg-names = "kgsl_3d0_reg_memory"; 1208 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1209 1210 clocks = <&gcc GCC_OXILI_GFX3D_CLK>, 1211 <&gcc GCC_OXILI_AHB_CLK>, 1212 <&gcc GCC_BIMC_GFX_CLK>, 1213 <&gcc GCC_BIMC_GPU_CLK>, 1214 <&gcc GCC_OXILI_TIMER_CLK>, 1215 <&gcc GCC_OXILI_AON_CLK>; 1216 clock-names = "core", 1217 "iface", 1218 "mem_iface", 1219 "alt_mem_iface", 1220 "rbbmtimer", 1221 "alwayson"; 1222 power-domains = <&gcc OXILI_GX_GDSC>; 1223 1224 interconnects = <&bimc MAS_OXILI RPM_ALWAYS_TAG 1225 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1226 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1227 &pcnoc SLV_GPU_CFG RPM_ACTIVE_TAG>; 1228 1229 iommus = <&gpu_iommu 0>; 1230 operating-points-v2 = <&gpu_opp_table>; 1231 1232 #cooling-cells = <2>; 1233 1234 status = "disabled"; 1235 1236 gpu_zap_shader: zap-shader { 1237 memory-region = <&zap_shader_region>; 1238 }; 1239 1240 gpu_opp_table: opp-table { 1241 compatible = "operating-points-v2"; 1242 1243 opp-19200000 { 1244 opp-hz = /bits/ 64 <19200000>; 1245 opp-supported-hw = <0xff>; 1246 required-opps = <&rpmpd_opp_min_svs>; 1247 }; 1248 1249 opp-133300000 { 1250 opp-hz = /bits/ 64 <133300000>; 1251 opp-supported-hw = <0xff>; 1252 required-opps = <&rpmpd_opp_min_svs>; 1253 }; 1254 1255 opp-216000000 { 1256 opp-hz = /bits/ 64 <216000000>; 1257 opp-supported-hw = <0xff>; 1258 required-opps = <&rpmpd_opp_low_svs>; 1259 }; 1260 1261 opp-320000000 { 1262 opp-hz = /bits/ 64 <320000000>; 1263 opp-supported-hw = <0xff>; 1264 required-opps = <&rpmpd_opp_svs>; 1265 }; 1266 1267 opp-400000000 { 1268 opp-hz = /bits/ 64 <400000000>; 1269 opp-supported-hw = <0xff>; 1270 required-opps = <&rpmpd_opp_svs_plus>; 1271 }; 1272 1273 opp-510000000 { 1274 opp-hz = /bits/ 64 <510000000>; 1275 opp-supported-hw = <0xff>; 1276 required-opps = <&rpmpd_opp_nom>; 1277 }; 1278 1279 opp-560000000 { 1280 opp-hz = /bits/ 64 <560000000>; 1281 opp-supported-hw = <0xff>; 1282 required-opps = <&rpmpd_opp_nom_plus>; 1283 }; 1284 1285 /* 1286 * This opp is only available on msm8953 and 1287 * sdm632, the max for sdm450 is 600MHz. 1288 */ 1289 opp-650000000 { 1290 opp-hz = /bits/ 64 <650000000>; 1291 opp-supported-hw = <0xff>; 1292 required-opps = <&rpmpd_opp_turbo>; 1293 }; 1294 }; 1295 }; 1296 1297 gpu_iommu: iommu@1c48000 { 1298 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v2"; 1299 ranges = <0 0x01c48000 0x8000>; 1300 1301 clocks = <&gcc GCC_OXILI_AHB_CLK>, 1302 <&gcc GCC_BIMC_GFX_CLK>; 1303 clock-names = "iface", "bus"; 1304 1305 power-domains = <&gcc OXILI_CX_GDSC>; 1306 1307 qcom,iommu-secure-id = <18>; 1308 1309 #address-cells = <1>; 1310 #iommu-cells = <1>; 1311 #size-cells = <1>; 1312 1313 /* gfx3d_user */ 1314 iommu-ctx@0 { 1315 compatible = "qcom,msm-iommu-v2-ns"; 1316 reg = <0x0000 0x1000>; 1317 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1318 }; 1319 1320 /* gfx3d_secure */ 1321 iommu-ctx@2000 { 1322 compatible = "qcom,msm-iommu-v2-sec"; 1323 reg = <0x2000 0x1000>; 1324 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 1325 }; 1326 }; 1327 1328 apps_iommu: iommu@1e20000 { 1329 compatible = "qcom,msm8953-iommu", "qcom,msm-iommu-v1"; 1330 ranges = <0 0x01e20000 0x20000>; 1331 1332 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1333 <&gcc GCC_APSS_TCU_ASYNC_CLK>; 1334 clock-names = "iface", "bus"; 1335 1336 qcom,iommu-secure-id = <17>; 1337 1338 #address-cells = <1>; 1339 #iommu-cells = <1>; 1340 #size-cells = <1>; 1341 1342 /* VFE */ 1343 iommu-ctx@14000 { 1344 compatible = "qcom,msm-iommu-v1-ns"; 1345 reg = <0x14000 0x1000>; 1346 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1347 }; 1348 1349 /* MDP_0 */ 1350 iommu-ctx@15000 { 1351 compatible = "qcom,msm-iommu-v1-ns"; 1352 reg = <0x15000 0x1000>; 1353 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1354 }; 1355 1356 /* VENUS_NS */ 1357 iommu-ctx@16000 { 1358 compatible = "qcom,msm-iommu-v1-ns"; 1359 reg = <0x16000 0x1000>; 1360 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1361 }; 1362 }; 1363 1364 spmi_bus: spmi@200f000 { 1365 compatible = "qcom,spmi-pmic-arb"; 1366 reg = <0x0200f000 0x1000>, 1367 <0x02400000 0x800000>, 1368 <0x02c00000 0x800000>, 1369 <0x03800000 0x200000>, 1370 <0x0200a000 0x2100>; 1371 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1372 interrupt-names = "periph_irq"; 1373 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1374 qcom,ee = <0>; 1375 qcom,channel = <0>; 1376 interrupt-controller; 1377 1378 #interrupt-cells = <4>; 1379 #address-cells = <2>; 1380 #size-cells = <0>; 1381 }; 1382 1383 mpss: remoteproc@4080000 { 1384 compatible = "qcom,msm8953-mss-pil"; 1385 reg = <0x04080000 0x100>, 1386 <0x04020000 0x040>; 1387 reg-names = "qdsp6", "rmb"; 1388 1389 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1390 <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, 1391 <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, 1392 <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, 1393 <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>; 1394 interrupt-names = "wdog", "fatal", "ready", 1395 "handover", "stop-ack"; 1396 1397 power-domains = <&rpmpd MSM8953_VDDCX>, 1398 <&rpmpd MSM8953_VDDMX>, 1399 <&rpmpd MSM8953_VDDMD>; 1400 power-domain-names = "cx", "mx","mss"; 1401 1402 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1403 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1404 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1405 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1406 clock-names = "iface", "bus", "mem", "xo"; 1407 1408 qcom,smem-states = <&smp2p_modem_out 0>; 1409 qcom,smem-state-names = "stop"; 1410 1411 resets = <&gcc GCC_MSS_BCR>; 1412 reset-names = "mss_restart"; 1413 1414 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1415 1416 status = "disabled"; 1417 1418 mba { 1419 memory-region = <&mba_mem>; 1420 }; 1421 1422 mpss { 1423 memory-region = <&mpss_mem>; 1424 }; 1425 1426 smd-edge { 1427 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1428 1429 qcom,smd-edge = <0>; 1430 mboxes = <&apcs 12>; 1431 qcom,remote-pid = <1>; 1432 1433 label = "modem"; 1434 }; 1435 }; 1436 1437 usb3: usb@70f8800 { 1438 compatible = "qcom,msm8953-dwc3", "qcom,dwc3"; 1439 reg = <0x070f8800 0x400>; 1440 #address-cells = <1>; 1441 #size-cells = <1>; 1442 ranges; 1443 1444 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1445 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 1447 interrupt-names = "pwr_event", 1448 "qusb2_phy", 1449 "ss_phy_irq"; 1450 1451 clocks = <&gcc GCC_USB_PHY_CFG_AHB_CLK>, 1452 <&gcc GCC_USB30_MASTER_CLK>, 1453 <&gcc GCC_PCNOC_USB3_AXI_CLK>, 1454 <&gcc GCC_USB30_SLEEP_CLK>, 1455 <&gcc GCC_USB30_MOCK_UTMI_CLK>; 1456 clock-names = "cfg_noc", 1457 "core", 1458 "iface", 1459 "sleep", 1460 "mock_utmi"; 1461 1462 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>, 1463 <&gcc GCC_USB30_MASTER_CLK>; 1464 assigned-clock-rates = <19200000>, <133330000>; 1465 1466 interconnects = <&pcnoc MAS_USB3 RPM_ALWAYS_TAG 1467 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1468 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1469 &pcnoc SLV_USB3 RPM_ACTIVE_TAG>; 1470 interconnect-names = "usb-ddr", 1471 "apps-usb"; 1472 1473 power-domains = <&gcc USB30_GDSC>; 1474 1475 qcom,select-utmi-as-pipe-clk; 1476 1477 status = "disabled"; 1478 1479 usb3_dwc3: usb@7000000 { 1480 compatible = "snps,dwc3"; 1481 reg = <0x07000000 0xcc00>; 1482 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1483 phys = <&hsusb_phy>; 1484 phy-names = "usb2-phy"; 1485 1486 snps,usb2-gadget-lpm-disable; 1487 snps,dis-u1-entry-quirk; 1488 snps,dis-u2-entry-quirk; 1489 snps,is-utmi-l1-suspend; 1490 snps,hird-threshold = /bits/ 8 <0x00>; 1491 1492 maximum-speed = "high-speed"; 1493 1494 usb-role-switch; 1495 1496 ports { 1497 #address-cells = <1>; 1498 #size-cells = <0>; 1499 1500 port@0 { 1501 reg = <0>; 1502 1503 usb_dwc3_hs: endpoint { 1504 }; 1505 }; 1506 }; 1507 }; 1508 }; 1509 1510 sdhc_1: mmc@7824900 { 1511 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1512 1513 reg = <0x07824900 0x500>, <0x07824000 0x800>; 1514 reg-names = "hc", "core"; 1515 1516 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1518 interrupt-names = "hc_irq", "pwr_irq"; 1519 1520 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1521 <&gcc GCC_SDCC1_APPS_CLK>, 1522 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1523 clock-names = "iface", "core", "xo"; 1524 1525 interconnects = <&pcnoc MAS_SDCC_1 RPM_ALWAYS_TAG 1526 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1527 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1528 &pcnoc SLV_SDCC_1 RPM_ACTIVE_TAG>; 1529 interconnect-names = "sdhc-ddr", 1530 "cpu-sdhc"; 1531 1532 power-domains = <&rpmpd MSM8953_VDDCX>; 1533 operating-points-v2 = <&sdhc1_opp_table>; 1534 1535 pinctrl-names = "default", "sleep"; 1536 pinctrl-0 = <&sdc1_clk_on &sdc1_cmd_on &sdc1_data_on &sdc1_rclk_on>; 1537 pinctrl-1 = <&sdc1_clk_off &sdc1_cmd_off &sdc1_data_off &sdc1_rclk_off>; 1538 1539 mmc-hs400-1_8v; 1540 mmc-hs200-1_8v; 1541 mmc-ddr-1_8v; 1542 bus-width = <8>; 1543 non-removable; 1544 1545 status = "disabled"; 1546 1547 sdhc1_opp_table: opp-table-sdhc1 { 1548 compatible = "operating-points-v2"; 1549 1550 opp-25000000 { 1551 opp-hz = /bits/ 64 <25000000>; 1552 opp-peak-kBps = <200000>, <100000>; 1553 opp-avg-kBps = <65360>, <32768>; 1554 required-opps = <&rpmpd_opp_low_svs>; 1555 }; 1556 1557 opp-50000000 { 1558 opp-hz = /bits/ 64 <50000000>; 1559 opp-peak-kBps = <400000>, <200000>; 1560 opp-avg-kBps = <130718>, <65360>; 1561 required-opps = <&rpmpd_opp_svs>; 1562 }; 1563 1564 opp-100000000 { 1565 opp-hz = /bits/ 64 <100000000>; 1566 opp-peak-kBps = <400000>, <400000>; 1567 opp-avg-kBps = <130718>, <65360>; 1568 required-opps = <&rpmpd_opp_svs>; 1569 }; 1570 1571 opp-192000000 { 1572 opp-hz = /bits/ 64 <192000000>; 1573 opp-peak-kBps = <800000>, <600000>; 1574 opp-avg-kBps = <261438>, <130718>; 1575 required-opps = <&rpmpd_opp_nom>; 1576 }; 1577 1578 opp-384000000 { 1579 opp-hz = /bits/ 64 <384000000>; 1580 opp-peak-kBps = <800000>, <800000>; 1581 opp-avg-kBps = <261438>, <300000>; 1582 required-opps = <&rpmpd_opp_nom>; 1583 }; 1584 }; 1585 }; 1586 1587 sdhc_2: mmc@7864900 { 1588 compatible = "qcom,msm8953-sdhci", "qcom,sdhci-msm-v4"; 1589 1590 reg = <0x07864900 0x500>, <0x07864000 0x800>; 1591 reg-names = "hc", "core"; 1592 1593 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1594 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1595 interrupt-names = "hc_irq", "pwr_irq"; 1596 1597 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1598 <&gcc GCC_SDCC2_APPS_CLK>, 1599 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1600 clock-names = "iface", "core", "xo"; 1601 1602 interconnects = <&pcnoc MAS_SDCC_2 RPM_ALWAYS_TAG 1603 &bimc SLV_EBI RPM_ALWAYS_TAG>, 1604 <&bimc MAS_APPS_PROC RPM_ACTIVE_TAG 1605 &pcnoc SLV_SDCC_2 RPM_ACTIVE_TAG>; 1606 interconnect-names = "sdhc-ddr", 1607 "cpu-sdhc"; 1608 1609 power-domains = <&rpmpd MSM8953_VDDCX>; 1610 operating-points-v2 = <&sdhc2_opp_table>; 1611 1612 pinctrl-names = "default", "sleep"; 1613 pinctrl-0 = <&sdc2_clk_on &sdc2_cmd_on &sdc2_data_on>; 1614 pinctrl-1 = <&sdc2_clk_off &sdc2_cmd_off &sdc2_data_off>; 1615 1616 bus-width = <4>; 1617 1618 status = "disabled"; 1619 1620 sdhc2_opp_table: opp-table-sdhc2 { 1621 compatible = "operating-points-v2"; 1622 1623 opp-25000000 { 1624 opp-hz = /bits/ 64 <25000000>; 1625 opp-peak-kBps = <200000>, <100000>; 1626 opp-avg-kBps = <65360>, <32768>; 1627 required-opps = <&rpmpd_opp_low_svs>; 1628 }; 1629 1630 opp-50000000 { 1631 opp-hz = /bits/ 64 <50000000>; 1632 opp-peak-kBps = <400000>, <400000>; 1633 opp-avg-kBps = <130718>, <65360>; 1634 required-opps = <&rpmpd_opp_svs>; 1635 }; 1636 1637 opp-100000000 { 1638 opp-hz = /bits/ 64 <100000000>; 1639 opp-peak-kBps = <800000>, <400000>; 1640 opp-avg-kBps = <130718>, <130718>; 1641 required-opps = <&rpmpd_opp_svs>; 1642 }; 1643 1644 opp-177770000 { 1645 opp-hz = /bits/ 64 <177770000>; 1646 opp-peak-kBps = <600000>, <600000>; 1647 opp-avg-kBps = <261438>, <130718>; 1648 required-opps = <&rpmpd_opp_nom>; 1649 }; 1650 1651 opp-200000000 { 1652 opp-hz = /bits/ 64 <200000000>; 1653 opp-peak-kBps = <800000>, <800000>; 1654 opp-avg-kBps = <261438>, <130718>; 1655 required-opps = <&rpmpd_opp_nom>; 1656 }; 1657 }; 1658 }; 1659 1660 blsp1_dma: dma-controller@7884000 { 1661 compatible = "qcom,bam-v1.7.0"; 1662 reg = <0x07884000 0x1f000>; 1663 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1664 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1665 clock-names = "bam_clk"; 1666 num-channels = <12>; 1667 #dma-cells = <1>; 1668 qcom,ee = <0>; 1669 qcom,num-ees = <4>; 1670 qcom,controlled-remotely; 1671 }; 1672 1673 uart_0: serial@78af000 { 1674 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1675 reg = <0x078af000 0x200>; 1676 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1677 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1678 <&gcc GCC_BLSP1_AHB_CLK>; 1679 clock-names = "core", "iface"; 1680 1681 status = "disabled"; 1682 }; 1683 1684 i2c_1: i2c@78b5000 { 1685 compatible = "qcom,i2c-qup-v2.2.1"; 1686 reg = <0x078b5000 0x600>; 1687 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1688 clock-names = "core", "iface"; 1689 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1690 <&gcc GCC_BLSP1_AHB_CLK>; 1691 dmas = <&blsp1_dma 4>, <&blsp1_dma 5>; 1692 dma-names = "tx", "rx"; 1693 1694 pinctrl-names = "default", "sleep"; 1695 pinctrl-0 = <&i2c_1_default>; 1696 pinctrl-1 = <&i2c_1_sleep>; 1697 1698 #address-cells = <1>; 1699 #size-cells = <0>; 1700 1701 status = "disabled"; 1702 }; 1703 1704 i2c_2: i2c@78b6000 { 1705 compatible = "qcom,i2c-qup-v2.2.1"; 1706 reg = <0x078b6000 0x600>; 1707 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1708 clock-names = "core", "iface"; 1709 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1710 <&gcc GCC_BLSP1_AHB_CLK>; 1711 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1712 dma-names = "tx", "rx"; 1713 1714 pinctrl-names = "default", "sleep"; 1715 pinctrl-0 = <&i2c_2_default>; 1716 pinctrl-1 = <&i2c_2_sleep>; 1717 1718 #address-cells = <1>; 1719 #size-cells = <0>; 1720 1721 status = "disabled"; 1722 }; 1723 1724 i2c_3: i2c@78b7000 { 1725 compatible = "qcom,i2c-qup-v2.2.1"; 1726 reg = <0x078b7000 0x600>; 1727 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1728 clock-names = "core", "iface"; 1729 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1730 <&gcc GCC_BLSP1_AHB_CLK>; 1731 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1732 dma-names = "tx", "rx"; 1733 1734 pinctrl-names = "default", "sleep"; 1735 pinctrl-0 = <&i2c_3_default>; 1736 pinctrl-1 = <&i2c_3_sleep>; 1737 1738 #address-cells = <1>; 1739 #size-cells = <0>; 1740 1741 status = "disabled"; 1742 }; 1743 1744 spi_3: spi@78b7000 { 1745 compatible = "qcom,spi-qup-v2.2.1"; 1746 reg = <0x078b7000 0x600>; 1747 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1748 clock-names = "core", "iface"; 1749 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1750 <&gcc GCC_BLSP1_AHB_CLK>; 1751 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1752 dma-names = "tx", "rx"; 1753 1754 pinctrl-names = "default", "sleep"; 1755 pinctrl-0 = <&spi_3_default>; 1756 pinctrl-1 = <&spi_3_sleep>; 1757 1758 #address-cells = <1>; 1759 #size-cells = <0>; 1760 1761 status = "disabled"; 1762 }; 1763 1764 i2c_4: i2c@78b8000 { 1765 compatible = "qcom,i2c-qup-v2.2.1"; 1766 reg = <0x078b8000 0x600>; 1767 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1768 clock-names = "core", "iface"; 1769 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1770 <&gcc GCC_BLSP1_AHB_CLK>; 1771 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1772 dma-names = "tx", "rx"; 1773 1774 pinctrl-names = "default", "sleep"; 1775 pinctrl-0 = <&i2c_4_default>; 1776 pinctrl-1 = <&i2c_4_sleep>; 1777 1778 #address-cells = <1>; 1779 #size-cells = <0>; 1780 1781 status = "disabled"; 1782 }; 1783 1784 blsp2_dma: dma-controller@7ac4000 { 1785 compatible = "qcom,bam-v1.7.0"; 1786 reg = <0x07ac4000 0x1f000>; 1787 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1788 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1789 clock-names = "bam_clk"; 1790 num-channels = <12>; 1791 #dma-cells = <1>; 1792 qcom,ee = <0>; 1793 qcom,num-ees = <4>; 1794 qcom,controlled-remotely; 1795 }; 1796 1797 uart_5: serial@7aef000 { 1798 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1799 reg = <0x07aef000 0x200>; 1800 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 1801 clocks = <&gcc GCC_BLSP2_UART1_APPS_CLK>, 1802 <&gcc GCC_BLSP2_AHB_CLK>; 1803 clock-names = "core", 1804 "iface"; 1805 dmas = <&blsp2_dma 0>, <&blsp2_dma 1>; 1806 dma-names = "tx", "rx"; 1807 1808 pinctrl-0 = <&uart_5_default>; 1809 pinctrl-1 = <&uart_5_sleep>; 1810 pinctrl-names = "default", "sleep"; 1811 1812 status = "disabled"; 1813 }; 1814 1815 i2c_5: i2c@7af5000 { 1816 compatible = "qcom,i2c-qup-v2.2.1"; 1817 reg = <0x07af5000 0x600>; 1818 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1819 clock-names = "core", "iface"; 1820 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1821 <&gcc GCC_BLSP2_AHB_CLK>; 1822 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1823 dma-names = "tx", "rx"; 1824 1825 pinctrl-names = "default", "sleep"; 1826 pinctrl-0 = <&i2c_5_default>; 1827 pinctrl-1 = <&i2c_5_sleep>; 1828 1829 #address-cells = <1>; 1830 #size-cells = <0>; 1831 1832 status = "disabled"; 1833 }; 1834 1835 spi_5: spi@7af5000 { 1836 compatible = "qcom,spi-qup-v2.2.1"; 1837 reg = <0x07af5000 0x600>; 1838 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1839 clock-names = "core", "iface"; 1840 clocks = <&gcc GCC_BLSP2_QUP1_SPI_APPS_CLK>, 1841 <&gcc GCC_BLSP2_AHB_CLK>; 1842 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1843 dma-names = "tx", "rx"; 1844 1845 pinctrl-names = "default", "sleep"; 1846 pinctrl-0 = <&spi_5_default>; 1847 pinctrl-1 = <&spi_5_sleep>; 1848 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 1852 status = "disabled"; 1853 }; 1854 1855 i2c_6: i2c@7af6000 { 1856 compatible = "qcom,i2c-qup-v2.2.1"; 1857 reg = <0x07af6000 0x600>; 1858 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1859 clock-names = "core", "iface"; 1860 clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>, 1861 <&gcc GCC_BLSP2_AHB_CLK>; 1862 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1863 dma-names = "tx", "rx"; 1864 1865 pinctrl-names = "default", "sleep"; 1866 pinctrl-0 = <&i2c_6_default>; 1867 pinctrl-1 = <&i2c_6_sleep>; 1868 1869 #address-cells = <1>; 1870 #size-cells = <0>; 1871 1872 status = "disabled"; 1873 }; 1874 1875 spi_6: spi@7af6000 { 1876 compatible = "qcom,spi-qup-v2.2.1"; 1877 reg = <0x07af6000 0x600>; 1878 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1879 clock-names = "core", "iface"; 1880 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 1881 <&gcc GCC_BLSP2_AHB_CLK>; 1882 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1883 dma-names = "tx", "rx"; 1884 1885 pinctrl-names = "default", "sleep"; 1886 pinctrl-0 = <&spi_6_default>; 1887 pinctrl-1 = <&spi_6_sleep>; 1888 1889 #address-cells = <1>; 1890 #size-cells = <0>; 1891 1892 status = "disabled"; 1893 }; 1894 1895 i2c_7: i2c@7af7000 { 1896 compatible = "qcom,i2c-qup-v2.2.1"; 1897 reg = <0x07af7000 0x600>; 1898 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1899 clock-names = "core", "iface"; 1900 clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>, 1901 <&gcc GCC_BLSP2_AHB_CLK>; 1902 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1903 dma-names = "tx", "rx"; 1904 1905 pinctrl-names = "default", "sleep"; 1906 pinctrl-0 = <&i2c_7_default>; 1907 pinctrl-1 = <&i2c_7_sleep>; 1908 1909 #address-cells = <1>; 1910 #size-cells = <0>; 1911 1912 status = "disabled"; 1913 }; 1914 1915 spi_7: spi@7af7000 { 1916 compatible = "qcom,spi-qup-v2.2.1"; 1917 reg = <0x07af7000 0x600>; 1918 interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>; 1919 clock-names = "core", "iface"; 1920 clocks = <&gcc GCC_BLSP2_QUP3_SPI_APPS_CLK>, 1921 <&gcc GCC_BLSP2_AHB_CLK>; 1922 dmas = <&blsp2_dma 8>, <&blsp2_dma 9>; 1923 dma-names = "tx", "rx"; 1924 1925 pinctrl-names = "default", "sleep"; 1926 pinctrl-0 = <&spi_7_default>; 1927 pinctrl-1 = <&spi_7_sleep>; 1928 1929 #address-cells = <1>; 1930 #size-cells = <0>; 1931 1932 status = "disabled"; 1933 }; 1934 1935 i2c_8: i2c@7af8000 { 1936 compatible = "qcom,i2c-qup-v2.2.1"; 1937 reg = <0x07af8000 0x600>; 1938 interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>; 1939 clock-names = "core", "iface"; 1940 clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>, 1941 <&gcc GCC_BLSP2_AHB_CLK>; 1942 dmas = <&blsp2_dma 10>, <&blsp2_dma 11>; 1943 dma-names = "tx", "rx"; 1944 1945 pinctrl-names = "default", "sleep"; 1946 pinctrl-0 = <&i2c_8_default>; 1947 pinctrl-1 = <&i2c_8_sleep>; 1948 1949 #address-cells = <1>; 1950 #size-cells = <0>; 1951 1952 status = "disabled"; 1953 }; 1954 1955 wcnss: remoteproc@a204000 { 1956 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1957 reg = <0x0a204000 0x2000>, <0x0a202000 0x1000>, <0x0a21b000 0x3000>; 1958 reg-names = "ccu", "dxe", "pmu"; 1959 1960 memory-region = <&wcnss_fw_mem>; 1961 1962 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1963 <&smp2p_wcnss_in 0 IRQ_TYPE_EDGE_RISING>, 1964 <&smp2p_wcnss_in 1 IRQ_TYPE_EDGE_RISING>, 1965 <&smp2p_wcnss_in 2 IRQ_TYPE_EDGE_RISING>, 1966 <&smp2p_wcnss_in 3 IRQ_TYPE_EDGE_RISING>; 1967 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1968 1969 power-domains = <&rpmpd MSM8953_VDDCX>, 1970 <&rpmpd MSM8953_VDDMX>; 1971 power-domain-names = "cx", "mx"; 1972 1973 qcom,smem-states = <&smp2p_wcnss_out 0>; 1974 qcom,smem-state-names = "stop"; 1975 1976 pinctrl-names = "default"; 1977 pinctrl-0 = <&wcnss_pin_a>; 1978 1979 status = "disabled"; 1980 1981 wcnss_iris: iris { 1982 /* Separate chip, compatible is board-specific */ 1983 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1984 clock-names = "xo"; 1985 }; 1986 1987 smd-edge { 1988 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1989 1990 mboxes = <&apcs 17>; 1991 qcom,smd-edge = <6>; 1992 qcom,remote-pid = <4>; 1993 1994 label = "pronto"; 1995 1996 wcnss_ctrl: wcnss { 1997 compatible = "qcom,wcnss"; 1998 qcom,smd-channels = "WCNSS_CTRL"; 1999 2000 qcom,mmio = <&wcnss>; 2001 2002 wcnss_bt: bluetooth { 2003 compatible = "qcom,wcnss-bt"; 2004 }; 2005 2006 wcnss_wifi: wifi { 2007 compatible = "qcom,wcnss-wlan"; 2008 2009 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2010 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2011 interrupt-names = "tx", "rx"; 2012 2013 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 2014 qcom,smem-state-names = "tx-enable", 2015 "tx-rings-empty"; 2016 }; 2017 }; 2018 }; 2019 }; 2020 2021 intc: interrupt-controller@b000000 { 2022 compatible = "qcom,msm-qgic2"; 2023 interrupt-controller; 2024 #interrupt-cells = <3>; 2025 reg = <0x0b000000 0x1000>, <0x0b002000 0x1000>; 2026 }; 2027 2028 apcs: mailbox@b011000 { 2029 compatible = "qcom,msm8953-apcs-kpss-global", "syscon"; 2030 reg = <0x0b011000 0x1000>; 2031 #mbox-cells = <1>; 2032 }; 2033 2034 timer@b120000 { 2035 compatible = "arm,armv7-timer-mem"; 2036 reg = <0x0b120000 0x1000>; 2037 #address-cells = <1>; 2038 #size-cells = <1>; 2039 ranges; 2040 2041 frame@b121000 { 2042 frame-number = <0>; 2043 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2044 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2045 reg = <0x0b121000 0x1000>, 2046 <0x0b122000 0x1000>; 2047 }; 2048 2049 frame@b123000 { 2050 frame-number = <1>; 2051 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2052 reg = <0x0b123000 0x1000>; 2053 status = "disabled"; 2054 }; 2055 2056 frame@b124000 { 2057 frame-number = <2>; 2058 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2059 reg = <0x0b124000 0x1000>; 2060 status = "disabled"; 2061 }; 2062 2063 frame@b125000 { 2064 frame-number = <3>; 2065 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2066 reg = <0x0b125000 0x1000>; 2067 status = "disabled"; 2068 }; 2069 2070 frame@b126000 { 2071 frame-number = <4>; 2072 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2073 reg = <0x0b126000 0x1000>; 2074 status = "disabled"; 2075 }; 2076 2077 frame@b127000 { 2078 frame-number = <5>; 2079 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2080 reg = <0x0b127000 0x1000>; 2081 status = "disabled"; 2082 }; 2083 2084 frame@b128000 { 2085 frame-number = <6>; 2086 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2087 reg = <0x0b128000 0x1000>; 2088 status = "disabled"; 2089 }; 2090 }; 2091 2092 lpass: remoteproc@c200000 { 2093 compatible = "qcom,msm8953-adsp-pil"; 2094 reg = <0x0c200000 0x100>; 2095 2096 interrupts-extended = <&intc 0 293 IRQ_TYPE_EDGE_RISING>, 2097 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2098 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2099 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2100 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2101 interrupt-names = "wdog", "fatal", "ready", 2102 "handover", "stop-ack"; 2103 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2104 clock-names = "xo"; 2105 2106 power-domains = <&rpmpd MSM8953_VDDCX>; 2107 power-domain-names = "cx"; 2108 2109 memory-region = <&adsp_fw_mem>; 2110 2111 qcom,smem-states = <&smp2p_adsp_out 0>; 2112 qcom,smem-state-names = "stop"; 2113 2114 status = "disabled"; 2115 2116 smd-edge { 2117 interrupts = <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>; 2118 2119 label = "lpass"; 2120 mboxes = <&apcs 8>; 2121 qcom,smd-edge = <1>; 2122 qcom,remote-pid = <2>; 2123 2124 apr { 2125 compatible = "qcom,apr-v2"; 2126 qcom,smd-channels = "apr_audio_svc"; 2127 qcom,domain = <APR_DOMAIN_ADSP>; 2128 #address-cells = <1>; 2129 #size-cells = <0>; 2130 2131 q6core: service@3 { 2132 reg = <APR_SVC_ADSP_CORE>; 2133 compatible = "qcom,q6core"; 2134 }; 2135 2136 q6afe: service@4 { 2137 compatible = "qcom,q6afe"; 2138 reg = <APR_SVC_AFE>; 2139 q6afedai: dais { 2140 compatible = "qcom,q6afe-dais"; 2141 #address-cells = <1>; 2142 #size-cells = <0>; 2143 #sound-dai-cells = <1>; 2144 2145 dai@16 { 2146 reg = <PRIMARY_MI2S_RX>; 2147 qcom,sd-lines = <0 1>; 2148 }; 2149 dai@20 { 2150 reg = <TERTIARY_MI2S_TX>; 2151 qcom,sd-lines = <0 1>; 2152 }; 2153 dai@127 { 2154 reg = <QUINARY_MI2S_RX>; 2155 qcom,sd-lines = <0>; 2156 }; 2157 }; 2158 2159 q6afecc: clock-controller { 2160 compatible = "qcom,q6afe-clocks"; 2161 #clock-cells = <2>; 2162 }; 2163 }; 2164 2165 q6asm: service@7 { 2166 compatible = "qcom,q6asm"; 2167 reg = <APR_SVC_ASM>; 2168 q6asmdai: dais { 2169 compatible = "qcom,q6asm-dais"; 2170 #address-cells = <1>; 2171 #size-cells = <0>; 2172 #sound-dai-cells = <1>; 2173 2174 dai@0 { 2175 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 2176 direction = <Q6ASM_DAI_RX>; 2177 }; 2178 dai@1 { 2179 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 2180 direction = <Q6ASM_DAI_TX>; 2181 }; 2182 dai@2 { 2183 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 2184 direction = <Q6ASM_DAI_RX>; 2185 }; 2186 dai@3 { 2187 reg = <MSM_FRONTEND_DAI_MULTIMEDIA4>; 2188 direction = <Q6ASM_DAI_RX>; 2189 is-compress-dai; 2190 }; 2191 }; 2192 }; 2193 2194 q6adm: service@8 { 2195 compatible = "qcom,q6adm"; 2196 reg = <APR_SVC_ADM>; 2197 q6routing: routing { 2198 compatible = "qcom,q6adm-routing"; 2199 #sound-dai-cells = <0>; 2200 }; 2201 }; 2202 }; 2203 }; 2204 }; 2205 }; 2206 2207 thermal-zones { 2208 cpu0-thermal { 2209 polling-delay-passive = <250>; 2210 2211 thermal-sensors = <&tsens0 9>; 2212 2213 trips { 2214 cpu0_alert: trip-point0 { 2215 temperature = <80000>; 2216 hysteresis = <2000>; 2217 type = "passive"; 2218 }; 2219 cpu0_crit: crit { 2220 temperature = <100000>; 2221 hysteresis = <2000>; 2222 type = "critical"; 2223 }; 2224 }; 2225 cooling-maps { 2226 map0 { 2227 trip = <&cpu0_alert>; 2228 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2229 }; 2230 }; 2231 }; 2232 cpu1-thermal { 2233 polling-delay-passive = <250>; 2234 2235 thermal-sensors = <&tsens0 10>; 2236 2237 trips { 2238 cpu1_alert: trip-point0 { 2239 temperature = <80000>; 2240 hysteresis = <2000>; 2241 type = "passive"; 2242 }; 2243 cpu1_crit: crit { 2244 temperature = <100000>; 2245 hysteresis = <2000>; 2246 type = "critical"; 2247 }; 2248 }; 2249 cooling-maps { 2250 map0 { 2251 trip = <&cpu1_alert>; 2252 cooling-device = <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2253 }; 2254 }; 2255 }; 2256 cpu2-thermal { 2257 polling-delay-passive = <250>; 2258 2259 thermal-sensors = <&tsens0 11>; 2260 2261 trips { 2262 cpu2_alert: trip-point0 { 2263 temperature = <80000>; 2264 hysteresis = <2000>; 2265 type = "passive"; 2266 }; 2267 cpu2_crit: crit { 2268 temperature = <100000>; 2269 hysteresis = <2000>; 2270 type = "critical"; 2271 }; 2272 }; 2273 cooling-maps { 2274 map0 { 2275 trip = <&cpu2_alert>; 2276 cooling-device = <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2277 }; 2278 }; 2279 }; 2280 cpu3-thermal { 2281 polling-delay-passive = <250>; 2282 2283 thermal-sensors = <&tsens0 12>; 2284 2285 trips { 2286 cpu3_alert: trip-point0 { 2287 temperature = <80000>; 2288 hysteresis = <2000>; 2289 type = "passive"; 2290 }; 2291 cpu3_crit: crit { 2292 temperature = <100000>; 2293 hysteresis = <2000>; 2294 type = "critical"; 2295 }; 2296 }; 2297 cooling-maps { 2298 map0 { 2299 trip = <&cpu3_alert>; 2300 cooling-device = <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2301 }; 2302 }; 2303 }; 2304 cpu4-thermal { 2305 polling-delay-passive = <250>; 2306 thermal-sensors = <&tsens0 4>; 2307 trips { 2308 cpu4_alert: trip-point0 { 2309 temperature = <80000>; 2310 hysteresis = <2000>; 2311 type = "passive"; 2312 }; 2313 cpu4_crit: crit { 2314 temperature = <100000>; 2315 hysteresis = <2000>; 2316 type = "critical"; 2317 }; 2318 }; 2319 cooling-maps { 2320 map0 { 2321 trip = <&cpu4_alert>; 2322 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2323 }; 2324 }; 2325 }; 2326 cpu5-thermal { 2327 polling-delay-passive = <250>; 2328 thermal-sensors = <&tsens0 5>; 2329 trips { 2330 cpu5_alert: trip-point0 { 2331 temperature = <80000>; 2332 hysteresis = <2000>; 2333 type = "passive"; 2334 }; 2335 cpu5_crit: crit { 2336 temperature = <100000>; 2337 hysteresis = <2000>; 2338 type = "critical"; 2339 }; 2340 }; 2341 cooling-maps { 2342 map0 { 2343 trip = <&cpu5_alert>; 2344 cooling-device = <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2345 }; 2346 }; 2347 }; 2348 cpu6-thermal { 2349 polling-delay-passive = <250>; 2350 thermal-sensors = <&tsens0 6>; 2351 trips { 2352 cpu6_alert: trip-point0 { 2353 temperature = <80000>; 2354 hysteresis = <2000>; 2355 type = "passive"; 2356 }; 2357 cpu6_crit: crit { 2358 temperature = <100000>; 2359 hysteresis = <2000>; 2360 type = "critical"; 2361 }; 2362 }; 2363 cooling-maps { 2364 map0 { 2365 trip = <&cpu6_alert>; 2366 cooling-device = <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2367 }; 2368 }; 2369 }; 2370 cpu7-thermal { 2371 polling-delay-passive = <250>; 2372 thermal-sensors = <&tsens0 7>; 2373 trips { 2374 cpu7_alert: trip-point0 { 2375 temperature = <80000>; 2376 hysteresis = <2000>; 2377 type = "passive"; 2378 }; 2379 cpu7_crit: crit { 2380 temperature = <100000>; 2381 hysteresis = <2000>; 2382 type = "critical"; 2383 }; 2384 }; 2385 cooling-maps { 2386 map0 { 2387 trip = <&cpu7_alert>; 2388 cooling-device = <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2389 }; 2390 }; 2391 }; 2392 2393 gpu-thermal { 2394 polling-delay-passive = <250>; 2395 thermal-sensors = <&tsens0 15>; 2396 2397 trips { 2398 gpu_alert: trip-point0 { 2399 temperature = <70000>; 2400 hysteresis = <2000>; 2401 type = "passive"; 2402 }; 2403 2404 gpu_crit: crit { 2405 temperature = <90000>; 2406 hysteresis = <2000>; 2407 type = "critical"; 2408 }; 2409 }; 2410 2411 cooling-maps { 2412 map0 { 2413 trip = <&gpu_alert>; 2414 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2415 }; 2416 }; 2417 }; 2418 }; 2419 2420 timer { 2421 compatible = "arm,armv8-timer"; 2422 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2423 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2424 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2425 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2426 }; 2427};
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