FILE
msm8939.dtsi
File preview with syntax highlighting.
linux-6.19.14/arch/arm64/boot/dts/qcom/msm8939.dtsi
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2023, Linaro Limited 5 */ 6 7#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 8#include <dt-bindings/clock/qcom,gcc-msm8939.h> 9#include <dt-bindings/clock/qcom,rpmcc.h> 10#include <dt-bindings/interconnect/qcom,msm8939.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/power/qcom-rpmpd.h> 13#include <dt-bindings/reset/qcom,gcc-msm8939.h> 14#include <dt-bindings/soc/qcom,apr.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 interrupt-parent = <&intc>; 19 20 /* 21 * Stock LK wants address-cells/size-cells = 2 22 * A number of our drivers want address/size cells = 1 23 * hence the disparity between top-level and /soc below. 24 */ 25 #address-cells = <2>; 26 #size-cells = <2>; 27 28 clocks { 29 xo_board: xo-board { 30 compatible = "fixed-clock"; 31 #clock-cells = <0>; 32 clock-frequency = <19200000>; 33 }; 34 35 sleep_clk: sleep-clk { 36 compatible = "fixed-clock"; 37 #clock-cells = <0>; 38 clock-frequency = <32764>; 39 }; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 46 cpu0: cpu@100 { 47 compatible = "arm,cortex-a53"; 48 device_type = "cpu"; 49 enable-method = "spin-table"; 50 cpu-release-addr = /bits/ 64 <0>; 51 reg = <0x100>; 52 next-level-cache = <&l2_1>; 53 qcom,acc = <&acc0>; 54 qcom,saw = <&saw0>; 55 cpu-idle-states = <&cpu_sleep_0>; 56 clocks = <&apcs1_mbox>; 57 #cooling-cells = <2>; 58 l2_1: l2-cache { 59 compatible = "cache"; 60 cache-level = <2>; 61 cache-unified; 62 }; 63 }; 64 65 cpu1: cpu@101 { 66 compatible = "arm,cortex-a53"; 67 device_type = "cpu"; 68 enable-method = "spin-table"; 69 cpu-release-addr = /bits/ 64 <0>; 70 reg = <0x101>; 71 next-level-cache = <&l2_1>; 72 qcom,acc = <&acc1>; 73 qcom,saw = <&saw1>; 74 cpu-idle-states = <&cpu_sleep_0>; 75 clocks = <&apcs1_mbox>; 76 #cooling-cells = <2>; 77 }; 78 79 cpu2: cpu@102 { 80 compatible = "arm,cortex-a53"; 81 device_type = "cpu"; 82 enable-method = "spin-table"; 83 cpu-release-addr = /bits/ 64 <0>; 84 reg = <0x102>; 85 next-level-cache = <&l2_1>; 86 qcom,acc = <&acc2>; 87 qcom,saw = <&saw2>; 88 cpu-idle-states = <&cpu_sleep_0>; 89 clocks = <&apcs1_mbox>; 90 #cooling-cells = <2>; 91 }; 92 93 cpu3: cpu@103 { 94 compatible = "arm,cortex-a53"; 95 device_type = "cpu"; 96 enable-method = "spin-table"; 97 cpu-release-addr = /bits/ 64 <0>; 98 reg = <0x103>; 99 next-level-cache = <&l2_1>; 100 qcom,acc = <&acc3>; 101 qcom,saw = <&saw3>; 102 cpu-idle-states = <&cpu_sleep_0>; 103 clocks = <&apcs1_mbox>; 104 #cooling-cells = <2>; 105 }; 106 107 cpu4: cpu@0 { 108 compatible = "arm,cortex-a53"; 109 device_type = "cpu"; 110 enable-method = "spin-table"; 111 cpu-release-addr = /bits/ 64 <0>; 112 reg = <0x0>; 113 qcom,acc = <&acc4>; 114 qcom,saw = <&saw4>; 115 cpu-idle-states = <&cpu_sleep_0>; 116 clocks = <&apcs0_mbox>; 117 #cooling-cells = <2>; 118 next-level-cache = <&l2_0>; 119 l2_0: l2-cache { 120 compatible = "cache"; 121 cache-level = <2>; 122 cache-unified; 123 }; 124 }; 125 126 cpu5: cpu@1 { 127 compatible = "arm,cortex-a53"; 128 device_type = "cpu"; 129 enable-method = "spin-table"; 130 cpu-release-addr = /bits/ 64 <0>; 131 reg = <0x1>; 132 next-level-cache = <&l2_0>; 133 qcom,acc = <&acc5>; 134 qcom,saw = <&saw5>; 135 cpu-idle-states = <&cpu_sleep_0>; 136 clocks = <&apcs0_mbox>; 137 #cooling-cells = <2>; 138 }; 139 140 cpu6: cpu@2 { 141 compatible = "arm,cortex-a53"; 142 device_type = "cpu"; 143 enable-method = "spin-table"; 144 cpu-release-addr = /bits/ 64 <0>; 145 reg = <0x2>; 146 next-level-cache = <&l2_0>; 147 qcom,acc = <&acc6>; 148 qcom,saw = <&saw6>; 149 cpu-idle-states = <&cpu_sleep_0>; 150 clocks = <&apcs0_mbox>; 151 #cooling-cells = <2>; 152 }; 153 154 cpu7: cpu@3 { 155 compatible = "arm,cortex-a53"; 156 device_type = "cpu"; 157 enable-method = "spin-table"; 158 cpu-release-addr = /bits/ 64 <0>; 159 reg = <0x3>; 160 next-level-cache = <&l2_0>; 161 qcom,acc = <&acc7>; 162 qcom,saw = <&saw7>; 163 cpu-idle-states = <&cpu_sleep_0>; 164 clocks = <&apcs0_mbox>; 165 #cooling-cells = <2>; 166 }; 167 168 idle-states { 169 cpu_sleep_0: cpu-sleep-0 { 170 compatible = "arm,idle-state"; 171 entry-latency-us = <130>; 172 exit-latency-us = <150>; 173 min-residency-us = <2000>; 174 local-timer-stop; 175 }; 176 }; 177 }; 178 179 /* 180 * MSM8939 has a big.LITTLE heterogeneous computing architecture, 181 * consisting of two clusters of four ARM Cortex-A53s each. The 182 * LITTLE cluster runs at 1.0-1.2GHz, and the big cluster runs 183 * at 1.5-1.7GHz. 184 * 185 * The enable method used here is spin-table which presupposes use 186 * of a 2nd stage boot shim such as lk2nd to have installed a 187 * spin-table, the downstream non-psci/non-spin-table method that 188 * default msm8916/msm8936/msm8939 will not be supported upstream. 189 */ 190 cpu-map { 191 /* LITTLE (efficiency) cluster */ 192 cluster0 { 193 core0 { 194 cpu = <&cpu4>; 195 }; 196 197 core1 { 198 cpu = <&cpu5>; 199 }; 200 201 core2 { 202 cpu = <&cpu6>; 203 }; 204 205 core3 { 206 cpu = <&cpu7>; 207 }; 208 }; 209 210 /* big (performance) cluster */ 211 /* Boot CPU is cluster 1 core 0 */ 212 cluster1 { 213 core0 { 214 cpu = <&cpu0>; 215 }; 216 217 core1 { 218 cpu = <&cpu1>; 219 }; 220 221 core2 { 222 cpu = <&cpu2>; 223 }; 224 225 core3 { 226 cpu = <&cpu3>; 227 }; 228 }; 229 }; 230 231 firmware { 232 scm: scm { 233 compatible = "qcom,scm-msm8916", "qcom,scm"; 234 clocks = <&gcc GCC_CRYPTO_CLK>, 235 <&gcc GCC_CRYPTO_AXI_CLK>, 236 <&gcc GCC_CRYPTO_AHB_CLK>; 237 clock-names = "core", "bus", "iface"; 238 #reset-cells = <1>; 239 240 qcom,dload-mode = <&tcsr 0x6100>; 241 }; 242 }; 243 244 memory@80000000 { 245 device_type = "memory"; 246 /* We expect the bootloader to fill in the reg */ 247 reg = <0x0 0x80000000 0x0 0x0>; 248 }; 249 250 pmu { 251 compatible = "arm,cortex-a53-pmu"; 252 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 253 }; 254 255 rpm: remoteproc { 256 compatible = "qcom,msm8936-rpm-proc", "qcom,rpm-proc"; 257 258 smd-edge { 259 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 260 qcom,ipc = <&apcs1_mbox 8 0>; 261 qcom,smd-edge = <15>; 262 263 rpm_requests: rpm-requests { 264 compatible = "qcom,rpm-msm8936", "qcom,smd-rpm"; 265 qcom,smd-channels = "rpm_requests"; 266 267 rpmcc: clock-controller { 268 compatible = "qcom,rpmcc-msm8936", "qcom,rpmcc"; 269 #clock-cells = <1>; 270 clock-names = "xo"; 271 clocks = <&xo_board>; 272 }; 273 274 rpmpd: power-controller { 275 compatible = "qcom,msm8939-rpmpd"; 276 #power-domain-cells = <1>; 277 operating-points-v2 = <&rpmpd_opp_table>; 278 279 rpmpd_opp_table: opp-table { 280 compatible = "operating-points-v2"; 281 282 rpmpd_opp_ret: opp1 { 283 opp-level = <1>; 284 }; 285 286 rpmpd_opp_svs_krait: opp2 { 287 opp-level = <2>; 288 }; 289 290 rpmpd_opp_svs_soc: opp3 { 291 opp-level = <3>; 292 }; 293 294 rpmpd_opp_nom: opp4 { 295 opp-level = <4>; 296 }; 297 298 rpmpd_opp_turbo: opp5 { 299 opp-level = <5>; 300 }; 301 302 rpmpd_opp_super_turbo: opp6 { 303 opp-level = <6>; 304 }; 305 }; 306 }; 307 }; 308 }; 309 }; 310 311 reserved-memory { 312 #address-cells = <2>; 313 #size-cells = <2>; 314 ranges; 315 316 tz-apps@86000000 { 317 reg = <0x0 0x86000000 0x0 0x300000>; 318 no-map; 319 }; 320 321 smem@86300000 { 322 compatible = "qcom,smem"; 323 reg = <0x0 0x86300000 0x0 0x100000>; 324 no-map; 325 326 hwlocks = <&tcsr_mutex 3>; 327 qcom,rpm-msg-ram = <&rpm_msg_ram>; 328 }; 329 330 hypervisor@86400000 { 331 reg = <0x0 0x86400000 0x0 0x100000>; 332 no-map; 333 }; 334 335 tz@86500000 { 336 reg = <0x0 0x86500000 0x0 0x180000>; 337 no-map; 338 }; 339 340 reserved@86680000 { 341 reg = <0x0 0x86680000 0x0 0x80000>; 342 no-map; 343 }; 344 345 rmtfs@86700000 { 346 compatible = "qcom,rmtfs-mem"; 347 reg = <0x0 0x86700000 0x0 0xe0000>; 348 no-map; 349 350 qcom,client-id = <1>; 351 }; 352 353 rfsa@867e0000 { 354 reg = <0x0 0x867e0000 0x0 0x20000>; 355 no-map; 356 }; 357 358 mpss_mem: mpss@86800000 { 359 /* 360 * The memory region for the mpss firmware is generally 361 * relocatable and could be allocated dynamically. 362 * However, many firmware versions tend to fail when 363 * loaded to some special addresses, so it is hard to 364 * define reliable alloc-ranges. 365 * 366 * alignment = <0x0 0x400000>; 367 * alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 368 */ 369 reg = <0x0 0x86800000 0x0 0>; /* size is device-specific */ 370 no-map; 371 status = "disabled"; 372 }; 373 374 wcnss_mem: wcnss { 375 size = <0x0 0x600000>; 376 alignment = <0x0 0x100000>; 377 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 378 no-map; 379 status = "disabled"; 380 }; 381 382 venus_mem: venus { 383 size = <0x0 0x500000>; 384 alignment = <0x0 0x100000>; 385 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 386 no-map; 387 status = "disabled"; 388 }; 389 390 mba_mem: mba { 391 size = <0x0 0x100000>; 392 alignment = <0x0 0x100000>; 393 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 394 no-map; 395 status = "disabled"; 396 }; 397 }; 398 399 smp2p-hexagon { 400 compatible = "qcom,smp2p"; 401 qcom,smem = <435>, <428>; 402 403 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 404 405 mboxes = <&apcs1_mbox 14>; 406 407 qcom,local-pid = <0>; 408 qcom,remote-pid = <1>; 409 410 hexagon_smp2p_out: master-kernel { 411 qcom,entry-name = "master-kernel"; 412 413 #qcom,smem-state-cells = <1>; 414 }; 415 416 hexagon_smp2p_in: slave-kernel { 417 qcom,entry-name = "slave-kernel"; 418 419 interrupt-controller; 420 #interrupt-cells = <2>; 421 }; 422 }; 423 424 smp2p-wcnss { 425 compatible = "qcom,smp2p"; 426 qcom,smem = <451>, <431>; 427 428 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 429 430 mboxes = <&apcs1_mbox 18>; 431 432 qcom,local-pid = <0>; 433 qcom,remote-pid = <4>; 434 435 wcnss_smp2p_in: slave-kernel { 436 qcom,entry-name = "slave-kernel"; 437 438 interrupt-controller; 439 #interrupt-cells = <2>; 440 }; 441 442 wcnss_smp2p_out: master-kernel { 443 qcom,entry-name = "master-kernel"; 444 445 #qcom,smem-state-cells = <1>; 446 }; 447 }; 448 449 smsm { 450 compatible = "qcom,smsm"; 451 452 #address-cells = <1>; 453 #size-cells = <0>; 454 455 mboxes = <0>, <&apcs1_mbox 13>, <0>, <&apcs1_mbox 19>; 456 457 apps_smsm: apps@0 { 458 reg = <0>; 459 460 #qcom,smem-state-cells = <1>; 461 }; 462 463 hexagon_smsm: hexagon@1 { 464 reg = <1>; 465 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 466 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 }; 470 471 wcnss_smsm: wcnss@6 { 472 reg = <6>; 473 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 474 475 interrupt-controller; 476 #interrupt-cells = <2>; 477 }; 478 }; 479 480 soc: soc@0 { 481 compatible = "simple-bus"; 482 #address-cells = <1>; 483 #size-cells = <1>; 484 ranges = <0 0 0 0xffffffff>; 485 486 rng@22000 { 487 compatible = "qcom,prng"; 488 reg = <0x00022000 0x200>; 489 clocks = <&gcc GCC_PRNG_AHB_CLK>; 490 clock-names = "core"; 491 }; 492 493 qfprom: qfprom@5c000 { 494 compatible = "qcom,msm8916-qfprom", "qcom,qfprom"; 495 reg = <0x0005c000 0x1000>; 496 #address-cells = <1>; 497 #size-cells = <1>; 498 499 tsens_base1: base1@a0 { 500 reg = <0xa0 0x1>; 501 bits = <0 8>; 502 }; 503 504 tsens_s6_p1: s6-p1@a1 { 505 reg = <0xa1 0x1>; 506 bits = <0 6>; 507 }; 508 509 tsens_s6_p2: s6-p2@a1 { 510 reg = <0xa1 0x2>; 511 bits = <6 6>; 512 }; 513 514 tsens_s7_p1: s7-p1@a2 { 515 reg = <0xa2 0x2>; 516 bits = <4 6>; 517 }; 518 519 tsens_s7_p2: s7-p2@a3 { 520 reg = <0xa3 0x1>; 521 bits = <2 6>; 522 }; 523 524 tsens_s8_p1: s8-p1@a4 { 525 reg = <0xa4 0x1>; 526 bits = <0 6>; 527 }; 528 529 tsens_s8_p2: s8-p2@a4 { 530 reg = <0xa4 0x2>; 531 bits = <6 6>; 532 }; 533 534 tsens_s9_p1: s9-p1@a5 { 535 reg = <0xa5 0x2>; 536 bits = <4 6>; 537 }; 538 539 tsens_s9_p2: s9-p2@a6 { 540 reg = <0xa6 0x1>; 541 bits = <2 6>; 542 }; 543 544 tsens_base2: base2@a7 { 545 reg = <0xa7 0x1>; 546 bits = <0 8>; 547 }; 548 549 tsens_mode: mode@d0 { 550 reg = <0xd0 0x1>; 551 bits = <0 3>; 552 }; 553 554 tsens_s0_p1: s0-p1@d0 { 555 reg = <0xd0 0x2>; 556 bits = <3 6>; 557 }; 558 559 tsens_s0_p2: s0-p1@d1 { 560 reg = <0xd1 0x1>; 561 bits = <1 6>; 562 }; 563 564 tsens_s1_p1: s1-p1@d1 { 565 reg = <0xd1 0x2>; 566 bits = <7 6>; 567 }; 568 569 tsens_s1_p2: s1-p2@d2 { 570 reg = <0xd2 0x2>; 571 bits = <5 6>; 572 }; 573 574 tsens_s2_p1: s2-p1@d3 { 575 reg = <0xd3 0x2>; 576 bits = <3 6>; 577 }; 578 579 tsens_s2_p2: s2-p2@d4 { 580 reg = <0xd4 0x1>; 581 bits = <1 6>; 582 }; 583 584 tsens_s3_p1: s3-p1@d4 { 585 reg = <0xd4 0x2>; 586 bits = <7 6>; 587 }; 588 589 tsens_s3_p2: s3-p2@d5 { 590 reg = <0xd5 0x2>; 591 bits = <5 6>; 592 }; 593 594 tsens_s5_p1: s5-p1@d6 { 595 reg = <0xd6 0x2>; 596 bits = <3 6>; 597 }; 598 599 tsens_s5_p2: s5-p2@d7 { 600 reg = <0xd7 0x1>; 601 bits = <1 6>; 602 }; 603 }; 604 605 rpm_msg_ram: sram@60000 { 606 compatible = "qcom,rpm-msg-ram"; 607 reg = <0x00060000 0x8000>; 608 }; 609 610 bimc: interconnect@400000 { 611 compatible = "qcom,msm8939-bimc"; 612 reg = <0x00400000 0x62000>; 613 #interconnect-cells = <1>; 614 }; 615 616 tsens: thermal-sensor@4a9000 { 617 compatible = "qcom,msm8939-tsens", "qcom,tsens-v0_1"; 618 reg = <0x004a9000 0x1000>, /* TM */ 619 <0x004a8000 0x1000>; /* SROT */ 620 nvmem-cells = <&tsens_mode>, 621 <&tsens_base1>, <&tsens_base2>, 622 <&tsens_s0_p1>, <&tsens_s0_p2>, 623 <&tsens_s1_p1>, <&tsens_s1_p2>, 624 <&tsens_s2_p1>, <&tsens_s2_p2>, 625 <&tsens_s3_p1>, <&tsens_s3_p2>, 626 <&tsens_s5_p1>, <&tsens_s5_p2>, 627 <&tsens_s6_p1>, <&tsens_s6_p2>, 628 <&tsens_s7_p1>, <&tsens_s7_p2>, 629 <&tsens_s8_p1>, <&tsens_s8_p2>, 630 <&tsens_s9_p1>, <&tsens_s9_p2>; 631 nvmem-cell-names = "mode", 632 "base1", "base2", 633 "s0_p1", "s0_p2", 634 "s1_p1", "s1_p2", 635 "s2_p1", "s2_p2", 636 "s3_p1", "s3_p2", 637 "s5_p1", "s5_p2", 638 "s6_p1", "s6_p2", 639 "s7_p1", "s7_p2", 640 "s8_p1", "s8_p2", 641 "s9_p1", "s9_p2"; 642 #qcom,sensors = <9>; 643 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 644 interrupt-names = "uplow"; 645 #thermal-sensor-cells = <1>; 646 }; 647 648 restart@4ab000 { 649 compatible = "qcom,pshold"; 650 reg = <0x004ab000 0x4>; 651 }; 652 653 pcnoc: interconnect@500000 { 654 compatible = "qcom,msm8939-pcnoc"; 655 reg = <0x00500000 0x11000>; 656 #interconnect-cells = <1>; 657 }; 658 659 snoc: interconnect@580000 { 660 compatible = "qcom,msm8939-snoc"; 661 reg = <0x00580000 0x14080>; 662 #interconnect-cells = <1>; 663 664 snoc_mm: interconnect-snoc { 665 compatible = "qcom,msm8939-snoc-mm"; 666 #interconnect-cells = <1>; 667 }; 668 }; 669 670 tlmm: pinctrl@1000000 { 671 compatible = "qcom,msm8916-pinctrl"; 672 reg = <0x01000000 0x300000>; 673 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 674 gpio-controller; 675 gpio-ranges = <&tlmm 0 0 122>; 676 #gpio-cells = <2>; 677 interrupt-controller; 678 #interrupt-cells = <2>; 679 680 blsp_i2c1_default: blsp-i2c1-default-state { 681 pins = "gpio2", "gpio3"; 682 function = "blsp_i2c1"; 683 drive-strength = <2>; 684 bias-disable; 685 }; 686 687 blsp_i2c1_sleep: blsp-i2c1-sleep-state { 688 pins = "gpio2", "gpio3"; 689 function = "gpio"; 690 drive-strength = <2>; 691 bias-disable; 692 }; 693 694 blsp_i2c2_default: blsp-i2c2-default-state { 695 pins = "gpio6", "gpio7"; 696 function = "blsp_i2c2"; 697 drive-strength = <2>; 698 bias-disable; 699 }; 700 701 blsp_i2c2_sleep: blsp-i2c2-sleep-state { 702 pins = "gpio6", "gpio7"; 703 function = "gpio"; 704 drive-strength = <2>; 705 bias-disable; 706 }; 707 708 blsp_i2c3_default: blsp-i2c3-default-state { 709 pins = "gpio10", "gpio11"; 710 function = "blsp_i2c3"; 711 drive-strength = <2>; 712 bias-disable; 713 }; 714 715 blsp_i2c3_sleep: blsp-i2c3-sleep-state { 716 pins = "gpio10", "gpio11"; 717 function = "gpio"; 718 drive-strength = <2>; 719 bias-disable; 720 }; 721 722 blsp_i2c4_default: blsp-i2c4-default-state { 723 pins = "gpio14", "gpio15"; 724 function = "blsp_i2c4"; 725 drive-strength = <2>; 726 bias-disable; 727 }; 728 729 blsp_i2c4_sleep: blsp-i2c4-sleep-state { 730 pins = "gpio14", "gpio15"; 731 function = "gpio"; 732 drive-strength = <2>; 733 bias-disable; 734 }; 735 736 blsp_i2c5_default: blsp-i2c5-default-state { 737 pins = "gpio18", "gpio19"; 738 function = "blsp_i2c5"; 739 drive-strength = <2>; 740 bias-disable; 741 }; 742 743 blsp_i2c5_sleep: blsp-i2c5-sleep-state { 744 pins = "gpio18", "gpio19"; 745 function = "gpio"; 746 drive-strength = <2>; 747 bias-disable; 748 }; 749 750 blsp_i2c6_default: blsp-i2c6-default-state { 751 pins = "gpio22", "gpio23"; 752 function = "blsp_i2c6"; 753 drive-strength = <2>; 754 bias-disable; 755 }; 756 757 blsp_i2c6_sleep: blsp-i2c6-sleep-state { 758 pins = "gpio22", "gpio23"; 759 function = "gpio"; 760 drive-strength = <2>; 761 bias-disable; 762 }; 763 764 blsp_spi1_default: blsp-spi1-default-state { 765 spi-pins { 766 pins = "gpio0", "gpio1", "gpio3"; 767 function = "blsp_spi1"; 768 drive-strength = <12>; 769 bias-disable; 770 }; 771 772 cs-pins { 773 pins = "gpio2"; 774 function = "gpio"; 775 drive-strength = <16>; 776 bias-disable; 777 output-high; 778 }; 779 }; 780 781 blsp_spi1_sleep: blsp-spi1-sleep-state { 782 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 783 function = "gpio"; 784 drive-strength = <2>; 785 bias-pull-down; 786 }; 787 788 blsp_spi2_default: blsp-spi2-default-state { 789 spi-pins { 790 pins = "gpio4", "gpio5", "gpio7"; 791 function = "blsp_spi2"; 792 drive-strength = <12>; 793 bias-disable; 794 }; 795 796 cs-pins { 797 pins = "gpio6"; 798 function = "gpio"; 799 drive-strength = <16>; 800 bias-disable; 801 output-high; 802 }; 803 }; 804 805 blsp_spi2_sleep: blsp-spi2-sleep-state { 806 pins = "gpio4", "gpio5", "gpio6", "gpio7"; 807 function = "gpio"; 808 drive-strength = <2>; 809 bias-pull-down; 810 }; 811 812 blsp_spi3_default: blsp-spi3-default-state { 813 spi-pins { 814 pins = "gpio8", "gpio9", "gpio11"; 815 function = "blsp_spi3"; 816 drive-strength = <12>; 817 bias-disable; 818 }; 819 820 cs-pins { 821 pins = "gpio10"; 822 function = "gpio"; 823 drive-strength = <16>; 824 bias-disable; 825 output-high; 826 }; 827 }; 828 829 blsp_spi3_sleep: blsp-spi3-sleep-state { 830 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 831 function = "gpio"; 832 drive-strength = <2>; 833 bias-pull-down; 834 }; 835 836 blsp_spi4_default: blsp-spi4-default-state { 837 spi-pins { 838 pins = "gpio12", "gpio13", "gpio15"; 839 function = "blsp_spi4"; 840 drive-strength = <12>; 841 bias-disable; 842 }; 843 844 cs-pins { 845 pins = "gpio14"; 846 function = "gpio"; 847 drive-strength = <16>; 848 bias-disable; 849 output-high; 850 }; 851 }; 852 853 blsp_spi4_sleep: blsp-spi4-sleep-state { 854 pins = "gpio12", "gpio13", "gpio14", "gpio15"; 855 function = "gpio"; 856 drive-strength = <2>; 857 bias-pull-down; 858 }; 859 860 blsp_spi5_default: blsp-spi5-default-state { 861 spi-pins { 862 pins = "gpio16", "gpio17", "gpio19"; 863 function = "blsp_spi5"; 864 drive-strength = <12>; 865 bias-disable; 866 }; 867 868 cs-pins { 869 pins = "gpio18"; 870 function = "gpio"; 871 drive-strength = <16>; 872 bias-disable; 873 output-high; 874 }; 875 }; 876 877 blsp_spi5_sleep: blsp-spi5-sleep-state { 878 pins = "gpio16", "gpio17", "gpio18", "gpio19"; 879 function = "gpio"; 880 drive-strength = <2>; 881 bias-pull-down; 882 }; 883 884 blsp_spi6_default: blsp-spi6-default-state { 885 spi-pins { 886 pins = "gpio20", "gpio21", "gpio23"; 887 function = "blsp_spi6"; 888 drive-strength = <12>; 889 bias-disable; 890 }; 891 892 cs-pins { 893 pins = "gpio22"; 894 function = "gpio"; 895 drive-strength = <16>; 896 bias-disable; 897 output-high; 898 }; 899 }; 900 901 blsp_spi6_sleep: blsp-spi6-sleep-state { 902 pins = "gpio20", "gpio21", "gpio22", "gpio23"; 903 function = "gpio"; 904 drive-strength = <2>; 905 bias-pull-down; 906 }; 907 908 blsp_uart1_console_default: blsp-uart1-console-default-state { 909 tx-pins { 910 pins = "gpio0"; 911 function = "blsp_uart1"; 912 drive-strength = <16>; 913 bias-disable; 914 bootph-all; 915 }; 916 917 rx-pins { 918 pins = "gpio1"; 919 function = "blsp_uart1"; 920 drive-strength = <16>; 921 bias-pull-up; 922 bootph-all; 923 }; 924 }; 925 926 blsp_uart1_console_sleep: blsp-uart1-console-sleep-state { 927 pins = "gpio0", "gpio1"; 928 function = "gpio"; 929 drive-strength = <2>; 930 bias-pull-down; 931 }; 932 933 blsp_uart2_console_default: blsp-uart2-console-default-state { 934 tx-pins { 935 pins = "gpio4"; 936 function = "blsp_uart2"; 937 drive-strength = <16>; 938 bias-disable; 939 bootph-all; 940 }; 941 942 rx-pins { 943 pins = "gpio5"; 944 function = "blsp_uart2"; 945 drive-strength = <16>; 946 bias-pull-up; 947 bootph-all; 948 }; 949 }; 950 951 blsp_uart2_console_sleep: blsp-uart2-console-sleep-state { 952 pins = "gpio4", "gpio5"; 953 function = "gpio"; 954 drive-strength = <2>; 955 bias-pull-down; 956 }; 957 958 camera_front_default: camera-front-default-state { 959 pwdn-pins { 960 pins = "gpio33"; 961 function = "gpio"; 962 drive-strength = <16>; 963 bias-disable; 964 }; 965 966 rst-pins { 967 pins = "gpio28"; 968 function = "gpio"; 969 drive-strength = <16>; 970 bias-disable; 971 }; 972 973 mclk1-pins { 974 pins = "gpio27"; 975 function = "cam_mclk1"; 976 drive-strength = <16>; 977 bias-disable; 978 }; 979 }; 980 981 camera_rear_default: camera-rear-default-state { 982 pwdn-pins { 983 pins = "gpio34"; 984 function = "gpio"; 985 drive-strength = <16>; 986 bias-disable; 987 }; 988 989 rst-pins { 990 pins = "gpio35"; 991 function = "gpio"; 992 drive-strength = <16>; 993 bias-disable; 994 }; 995 996 mclk0-pins { 997 pins = "gpio26"; 998 function = "cam_mclk0"; 999 drive-strength = <16>; 1000 bias-disable; 1001 }; 1002 }; 1003 1004 cci0_default: cci0-default-state { 1005 pins = "gpio29", "gpio30"; 1006 function = "cci_i2c"; 1007 drive-strength = <16>; 1008 bias-disable; 1009 }; 1010 1011 cdc_dmic_default: cdc-dmic-default-state { 1012 clk-pins { 1013 pins = "gpio0"; 1014 function = "dmic0_clk"; 1015 drive-strength = <8>; 1016 }; 1017 1018 data-pins { 1019 pins = "gpio1"; 1020 function = "dmic0_data"; 1021 drive-strength = <8>; 1022 }; 1023 }; 1024 1025 cdc_dmic_sleep: cdc-dmic-sleep-state { 1026 clk-pins { 1027 pins = "gpio0"; 1028 function = "dmic0_clk"; 1029 drive-strength = <2>; 1030 bias-disable; 1031 }; 1032 1033 data-pins { 1034 pins = "gpio1"; 1035 function = "dmic0_data"; 1036 drive-strength = <2>; 1037 bias-disable; 1038 }; 1039 }; 1040 1041 cdc_pdm_default: cdc-pdm-default-state { 1042 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1043 "gpio67", "gpio68"; 1044 function = "cdc_pdm0"; 1045 drive-strength = <8>; 1046 bias-disable; 1047 }; 1048 1049 cdc_pdm_sleep: cdc-pdm-sleep-state { 1050 pins = "gpio63", "gpio64", "gpio65", "gpio66", 1051 "gpio67", "gpio68"; 1052 function = "cdc_pdm0"; 1053 drive-strength = <2>; 1054 bias-pull-down; 1055 }; 1056 1057 pri_mi2s_default: mi2s-pri-default-state { 1058 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1059 function = "pri_mi2s"; 1060 drive-strength = <8>; 1061 bias-disable; 1062 }; 1063 1064 pri_mi2s_sleep: mi2s-pri-sleep-state { 1065 pins = "gpio113", "gpio114", "gpio115", "gpio116"; 1066 function = "pri_mi2s"; 1067 drive-strength = <2>; 1068 bias-disable; 1069 }; 1070 1071 pri_mi2s_mclk_default: mi2s-pri-mclk-default-state { 1072 pins = "gpio116"; 1073 function = "pri_mi2s"; 1074 drive-strength = <8>; 1075 bias-disable; 1076 }; 1077 1078 pri_mi2s_mclk_sleep: mi2s-pri-mclk-sleep-state { 1079 pins = "gpio116"; 1080 function = "pri_mi2s"; 1081 drive-strength = <2>; 1082 bias-disable; 1083 }; 1084 1085 pri_mi2s_ws_default: mi2s-pri-ws-default-state { 1086 pins = "gpio110"; 1087 function = "pri_mi2s_ws"; 1088 drive-strength = <8>; 1089 bias-disable; 1090 }; 1091 1092 pri_mi2s_ws_sleep: mi2s-pri-ws-sleep-state { 1093 pins = "gpio110"; 1094 function = "pri_mi2s_ws"; 1095 drive-strength = <2>; 1096 bias-disable; 1097 }; 1098 1099 sec_mi2s_default: mi2s-sec-default-state { 1100 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1101 function = "sec_mi2s"; 1102 drive-strength = <8>; 1103 bias-disable; 1104 }; 1105 1106 sec_mi2s_sleep: mi2s-sec-sleep-state { 1107 pins = "gpio112", "gpio117", "gpio118", "gpio119"; 1108 function = "sec_mi2s"; 1109 drive-strength = <2>; 1110 bias-disable; 1111 }; 1112 1113 sdc1_default: sdc1-default-state { 1114 clk-pins { 1115 pins = "sdc1_clk"; 1116 bias-disable; 1117 drive-strength = <16>; 1118 }; 1119 1120 cmd-pins { 1121 pins = "sdc1_cmd"; 1122 bias-pull-up; 1123 drive-strength = <10>; 1124 }; 1125 1126 data-pins { 1127 pins = "sdc1_data"; 1128 bias-pull-up; 1129 drive-strength = <10>; 1130 }; 1131 }; 1132 1133 sdc1_sleep: sdc1-sleep-state { 1134 clk-pins { 1135 pins = "sdc1_clk"; 1136 bias-disable; 1137 drive-strength = <2>; 1138 }; 1139 1140 cmd-pins { 1141 pins = "sdc1_cmd"; 1142 bias-pull-up; 1143 drive-strength = <2>; 1144 }; 1145 1146 data-pins { 1147 pins = "sdc1_data"; 1148 bias-pull-up; 1149 drive-strength = <2>; 1150 }; 1151 }; 1152 1153 sdc2_default: sdc2-default-state { 1154 clk-pins { 1155 pins = "sdc2_clk"; 1156 bias-disable; 1157 drive-strength = <16>; 1158 }; 1159 1160 cmd-pins { 1161 pins = "sdc2_cmd"; 1162 bias-pull-up; 1163 drive-strength = <10>; 1164 }; 1165 1166 data-pins { 1167 pins = "sdc2_data"; 1168 bias-pull-up; 1169 drive-strength = <10>; 1170 }; 1171 }; 1172 1173 sdc2_sleep: sdc2-sleep-state { 1174 clk-pins { 1175 pins = "sdc2_clk"; 1176 bias-disable; 1177 drive-strength = <2>; 1178 }; 1179 1180 cmd-pins { 1181 pins = "sdc2_cmd"; 1182 bias-pull-up; 1183 drive-strength = <2>; 1184 }; 1185 1186 data-pins { 1187 pins = "sdc2_data"; 1188 bias-pull-up; 1189 drive-strength = <2>; 1190 }; 1191 }; 1192 1193 wcss_wlan_default: wcss-wlan-default-state { 1194 pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44"; 1195 function = "wcss_wlan"; 1196 drive-strength = <6>; 1197 bias-pull-up; 1198 }; 1199 }; 1200 1201 gcc: clock-controller@1800000 { 1202 compatible = "qcom,gcc-msm8939"; 1203 reg = <0x01800000 0x80000>; 1204 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1205 <&sleep_clk>, 1206 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1207 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1208 <0>, 1209 <0>, 1210 <0>; 1211 clock-names = "xo", 1212 "sleep_clk", 1213 "dsi0pll", 1214 "dsi0pllbyte", 1215 "ext_mclk", 1216 "ext_pri_i2s", 1217 "ext_sec_i2s"; 1218 #clock-cells = <1>; 1219 #reset-cells = <1>; 1220 #power-domain-cells = <1>; 1221 }; 1222 1223 tcsr_mutex: hwlock@1905000 { 1224 compatible = "qcom,tcsr-mutex"; 1225 reg = <0x01905000 0x20000>; 1226 #hwlock-cells = <1>; 1227 }; 1228 1229 tcsr: syscon@1937000 { 1230 compatible = "qcom,tcsr-msm8916", "syscon"; 1231 reg = <0x01937000 0x30000>; 1232 }; 1233 1234 mdss: display-subsystem@1a00000 { 1235 compatible = "qcom,mdss"; 1236 reg = <0x01a00000 0x1000>, 1237 <0x01ac8000 0x3000>; 1238 reg-names = "mdss_phys", "vbif_phys"; 1239 1240 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1241 interrupt-controller; 1242 1243 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1244 <&gcc GCC_MDSS_AXI_CLK>, 1245 <&gcc GCC_MDSS_VSYNC_CLK>; 1246 clock-names = "iface", 1247 "bus", 1248 "vsync"; 1249 1250 power-domains = <&gcc MDSS_GDSC>; 1251 1252 resets = <&gcc GCC_MDSS_BCR>; 1253 1254 #address-cells = <1>; 1255 #size-cells = <1>; 1256 #interrupt-cells = <1>; 1257 ranges; 1258 1259 status = "disabled"; 1260 1261 mdss_mdp: display-controller@1a01000 { 1262 compatible = "qcom,mdp5"; 1263 reg = <0x01a01000 0x89000>; 1264 reg-names = "mdp_phys"; 1265 1266 interrupt-parent = <&mdss>; 1267 interrupts = <0>; 1268 1269 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1270 <&gcc GCC_MDSS_AXI_CLK>, 1271 <&gcc GCC_MDSS_MDP_CLK>, 1272 <&gcc GCC_MDSS_VSYNC_CLK>; 1273 clock-names = "iface", 1274 "bus", 1275 "core", 1276 "vsync"; 1277 1278 iommus = <&apps_iommu 4>; 1279 1280 interconnects = <&snoc_mm MASTER_MDP_PORT0 &bimc SLAVE_EBI_CH0>, 1281 <&snoc_mm MASTER_MDP_PORT1 &bimc SLAVE_EBI_CH0>; 1282 interconnect-names = "mdp0-mem", "mdp1-mem"; 1283 1284 ports { 1285 #address-cells = <1>; 1286 #size-cells = <0>; 1287 1288 port@0 { 1289 reg = <0>; 1290 mdss_mdp_intf1_out: endpoint { 1291 remote-endpoint = <&mdss_dsi0_in>; 1292 }; 1293 }; 1294 1295 port@1 { 1296 reg = <1>; 1297 mdss_mdp_intf2_out: endpoint { 1298 remote-endpoint = <&mdss_dsi1_in>; 1299 }; 1300 }; 1301 }; 1302 }; 1303 1304 mdss_dsi0: dsi@1a98000 { 1305 compatible = "qcom,msm8916-dsi-ctrl", 1306 "qcom,mdss-dsi-ctrl"; 1307 reg = <0x01a98000 0x25c>; 1308 reg-names = "dsi_ctrl"; 1309 1310 interrupt-parent = <&mdss>; 1311 interrupts = <4>; 1312 1313 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1314 <&gcc GCC_MDSS_AHB_CLK>, 1315 <&gcc GCC_MDSS_AXI_CLK>, 1316 <&gcc GCC_MDSS_BYTE0_CLK>, 1317 <&gcc GCC_MDSS_PCLK0_CLK>, 1318 <&gcc GCC_MDSS_ESC0_CLK>; 1319 clock-names = "mdp_core", 1320 "iface", 1321 "bus", 1322 "byte", 1323 "pixel", 1324 "core"; 1325 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1326 <&gcc PCLK0_CLK_SRC>; 1327 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1328 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1329 1330 phys = <&mdss_dsi0_phy>; 1331 status = "disabled"; 1332 1333 #address-cells = <1>; 1334 #size-cells = <0>; 1335 1336 ports { 1337 #address-cells = <1>; 1338 #size-cells = <0>; 1339 1340 port@0 { 1341 reg = <0>; 1342 mdss_dsi0_in: endpoint { 1343 remote-endpoint = <&mdss_mdp_intf1_out>; 1344 }; 1345 }; 1346 1347 port@1 { 1348 reg = <1>; 1349 mdss_dsi0_out: endpoint { 1350 }; 1351 }; 1352 }; 1353 }; 1354 1355 mdss_dsi0_phy: phy@1a98300 { 1356 compatible = "qcom,dsi-phy-28nm-lp"; 1357 reg = <0x01a98300 0xd4>, 1358 <0x01a98500 0x280>, 1359 <0x01a98780 0x30>; 1360 reg-names = "dsi_pll", 1361 "dsi_phy", 1362 "dsi_phy_regulator"; 1363 1364 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1365 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1366 clock-names = "iface", "ref"; 1367 1368 #clock-cells = <1>; 1369 #phy-cells = <0>; 1370 status = "disabled"; 1371 }; 1372 1373 mdss_dsi1: dsi@1aa0000 { 1374 compatible = "qcom,msm8916-dsi-ctrl", 1375 "qcom,mdss-dsi-ctrl"; 1376 reg = <0x01aa0000 0x25c>; 1377 reg-names = "dsi_ctrl"; 1378 1379 interrupt-parent = <&mdss>; 1380 interrupts = <5>; 1381 1382 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1383 <&gcc GCC_MDSS_AHB_CLK>, 1384 <&gcc GCC_MDSS_AXI_CLK>, 1385 <&gcc GCC_MDSS_BYTE1_CLK>, 1386 <&gcc GCC_MDSS_PCLK1_CLK>, 1387 <&gcc GCC_MDSS_ESC1_CLK>; 1388 clock-names = "mdp_core", 1389 "iface", 1390 "bus", 1391 "byte", 1392 "pixel", 1393 "core"; 1394 assigned-clocks = <&gcc BYTE1_CLK_SRC>, 1395 <&gcc PCLK1_CLK_SRC>; 1396 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1397 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1398 phys = <&mdss_dsi1_phy>; 1399 status = "disabled"; 1400 1401 ports { 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 1405 port@0 { 1406 reg = <0>; 1407 mdss_dsi1_in: endpoint { 1408 remote-endpoint = <&mdss_mdp_intf2_out>; 1409 }; 1410 }; 1411 1412 port@1 { 1413 reg = <1>; 1414 mdss_dsi1_out: endpoint { 1415 }; 1416 }; 1417 }; 1418 }; 1419 1420 mdss_dsi1_phy: phy@1aa0300 { 1421 compatible = "qcom,dsi-phy-28nm-lp"; 1422 reg = <0x01aa0300 0xd4>, 1423 <0x01aa0500 0x280>, 1424 <0x01aa0780 0x30>; 1425 reg-names = "dsi_pll", 1426 "dsi_phy", 1427 "dsi_phy_regulator"; 1428 1429 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1430 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1431 clock-names = "iface", "ref"; 1432 1433 #clock-cells = <1>; 1434 #phy-cells = <0>; 1435 status = "disabled"; 1436 }; 1437 }; 1438 1439 gpu: gpu@1c00000 { 1440 compatible = "qcom,adreno-405.0", "qcom,adreno"; 1441 reg = <0x01c00000 0x10000>; 1442 reg-names = "kgsl_3d0_reg_memory"; 1443 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1444 interrupt-names = "kgsl_3d0_irq"; 1445 clock-names = "core", 1446 "iface", 1447 "mem", 1448 "mem_iface", 1449 "alt_mem_iface", 1450 "gfx3d", 1451 "rbbmtimer"; 1452 clocks = <&gcc GCC_OXILI_GFX3D_CLK>, 1453 <&gcc GCC_OXILI_AHB_CLK>, 1454 <&gcc GCC_OXILI_GMEM_CLK>, 1455 <&gcc GCC_BIMC_GFX_CLK>, 1456 <&gcc GCC_BIMC_GPU_CLK>, 1457 <&gcc GFX3D_CLK_SRC>, 1458 <&gcc GCC_OXILI_TIMER_CLK>; 1459 power-domains = <&gcc OXILI_GDSC>; 1460 operating-points-v2 = <&opp_table>; 1461 iommus = <&gpu_iommu 1>, <&gpu_iommu 2>; 1462 #cooling-cells = <2>; 1463 1464 status = "disabled"; 1465 1466 opp_table: opp-table { 1467 compatible = "operating-points-v2"; 1468 1469 opp-550000000 { 1470 opp-hz = /bits/ 64 <550000000>; 1471 }; 1472 1473 opp-465000000 { 1474 opp-hz = /bits/ 64 <465000000>; 1475 }; 1476 1477 opp-400000000 { 1478 opp-hz = /bits/ 64 <400000000>; 1479 }; 1480 1481 opp-220000000 { 1482 opp-hz = /bits/ 64 <220000000>; 1483 }; 1484 1485 opp-19200000 { 1486 opp-hz = /bits/ 64 <19200000>; 1487 }; 1488 }; 1489 }; 1490 1491 apps_iommu: iommu@1ef0000 { 1492 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1493 reg = <0x01ef0000 0x3000>; 1494 ranges = <0 0x01e20000 0x20000>; 1495 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1496 <&gcc GCC_APSS_TCU_CLK>; 1497 clock-names = "iface", "bus"; 1498 #address-cells = <1>; 1499 #size-cells = <1>; 1500 #iommu-cells = <1>; 1501 qcom,iommu-secure-id = <17>; 1502 1503 /* mdp_0: */ 1504 iommu-ctx@4000 { 1505 compatible = "qcom,msm-iommu-v1-ns"; 1506 reg = <0x4000 0x1000>; 1507 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1508 }; 1509 1510 /* venus_ns: */ 1511 iommu-ctx@5000 { 1512 compatible = "qcom,msm-iommu-v1-sec"; 1513 reg = <0x5000 0x1000>; 1514 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1515 }; 1516 }; 1517 1518 gpu_iommu: iommu@1f08000 { 1519 compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1"; 1520 ranges = <0 0x1f08000 0x10000>; 1521 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1522 <&gcc GCC_GFX_TCU_CLK>, 1523 <&gcc GCC_GFX_TBU_CLK>; 1524 clock-names = "iface", "bus", "tbu"; 1525 #address-cells = <1>; 1526 #size-cells = <1>; 1527 #iommu-cells = <1>; 1528 qcom,iommu-secure-id = <18>; 1529 1530 /* gfx3d_user: */ 1531 iommu-ctx@1000 { 1532 compatible = "qcom,msm-iommu-v1-ns"; 1533 reg = <0x1000 0x1000>; 1534 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 1535 }; 1536 1537 /* gfx3d_priv: */ 1538 iommu-ctx@2000 { 1539 compatible = "qcom,msm-iommu-v1-ns"; 1540 reg = <0x2000 0x1000>; 1541 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 1542 }; 1543 }; 1544 1545 spmi_bus: spmi@200f000 { 1546 compatible = "qcom,spmi-pmic-arb"; 1547 reg = <0x0200f000 0x001000>, 1548 <0x02400000 0x400000>, 1549 <0x02c00000 0x400000>, 1550 <0x03800000 0x200000>, 1551 <0x0200a000 0x002100>; 1552 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 1553 interrupt-names = "periph_irq"; 1554 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1555 qcom,ee = <0>; 1556 qcom,channel = <0>; 1557 #address-cells = <2>; 1558 #size-cells = <0>; 1559 interrupt-controller; 1560 #interrupt-cells = <4>; 1561 }; 1562 1563 bam_dmux_dma: dma-controller@4044000 { 1564 compatible = "qcom,bam-v1.7.0"; 1565 reg = <0x04044000 0x19000>; 1566 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1567 #dma-cells = <1>; 1568 qcom,ee = <0>; 1569 1570 num-channels = <6>; 1571 qcom,num-ees = <1>; 1572 qcom,powered-remotely; 1573 1574 status = "disabled"; 1575 }; 1576 1577 mpss: remoteproc@4080000 { 1578 compatible = "qcom,msm8916-mss-pil"; 1579 reg = <0x04080000 0x100>, <0x04020000 0x040>; 1580 reg-names = "qdsp6", "rmb"; 1581 interrupts-extended = <&intc GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1582 <&hexagon_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1583 <&hexagon_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1584 <&hexagon_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1585 <&hexagon_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1586 interrupt-names = "wdog", 1587 "fatal", 1588 "ready", 1589 "handover", 1590 "stop-ack"; 1591 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>, 1592 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>, 1593 <&gcc GCC_BOOT_ROM_AHB_CLK>, 1594 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1595 clock-names = "iface", 1596 "bus", 1597 "mem", 1598 "xo"; 1599 power-domains = <&rpmpd MSM8939_VDDMDCX>, 1600 <&rpmpd MSM8939_VDDMX>; 1601 power-domain-names = "cx", "mx"; 1602 qcom,smem-states = <&hexagon_smp2p_out 0>; 1603 qcom,smem-state-names = "stop"; 1604 resets = <&scm 0>; 1605 reset-names = "mss_restart"; 1606 qcom,halt-regs = <&tcsr 0x18000 0x19000 0x1a000>; 1607 status = "disabled"; 1608 1609 bam_dmux: bam-dmux { 1610 compatible = "qcom,bam-dmux"; 1611 1612 interrupt-parent = <&hexagon_smsm>; 1613 interrupts = <1 IRQ_TYPE_EDGE_BOTH>, <11 IRQ_TYPE_EDGE_BOTH>; 1614 interrupt-names = "pc", "pc-ack"; 1615 1616 qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; 1617 qcom,smem-state-names = "pc", "pc-ack"; 1618 1619 dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; 1620 dma-names = "tx", "rx"; 1621 1622 status = "disabled"; 1623 }; 1624 1625 mba { 1626 memory-region = <&mba_mem>; 1627 }; 1628 1629 mpss { 1630 memory-region = <&mpss_mem>; 1631 }; 1632 1633 smd-edge { 1634 interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>; 1635 1636 qcom,smd-edge = <0>; 1637 mboxes = <&apcs1_mbox 12>; 1638 qcom,remote-pid = <1>; 1639 1640 label = "hexagon"; 1641 1642 apr: apr { 1643 compatible = "qcom,apr-v2"; 1644 qcom,smd-channels = "apr_audio_svc"; 1645 qcom,domain = <APR_DOMAIN_ADSP>; 1646 #address-cells = <1>; 1647 #size-cells = <0>; 1648 status = "disabled"; 1649 1650 q6core: service@3 { 1651 compatible = "qcom,q6core"; 1652 reg = <APR_SVC_ADSP_CORE>; 1653 }; 1654 1655 q6afe: service@4 { 1656 compatible = "qcom,q6afe"; 1657 reg = <APR_SVC_AFE>; 1658 1659 q6afedai: dais { 1660 compatible = "qcom,q6afe-dais"; 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 #sound-dai-cells = <1>; 1664 }; 1665 }; 1666 1667 q6asm: service@7 { 1668 compatible = "qcom,q6asm"; 1669 reg = <APR_SVC_ASM>; 1670 1671 q6asmdai: dais { 1672 compatible = "qcom,q6asm-dais"; 1673 #address-cells = <1>; 1674 #size-cells = <0>; 1675 #sound-dai-cells = <1>; 1676 }; 1677 }; 1678 1679 q6adm: service@8 { 1680 compatible = "qcom,q6adm"; 1681 reg = <APR_SVC_ADM>; 1682 1683 q6routing: routing { 1684 compatible = "qcom,q6adm-routing"; 1685 #sound-dai-cells = <0>; 1686 }; 1687 }; 1688 }; 1689 }; 1690 }; 1691 1692 sound: sound@7702000 { 1693 compatible = "qcom,apq8016-sbc-sndcard"; 1694 reg = <0x07702000 0x4>, 1695 <0x07702004 0x4>; 1696 reg-names = "mic-iomux", "spkr-iomux"; 1697 status = "disabled"; 1698 }; 1699 1700 lpass: audio-controller@7708000 { 1701 compatible = "qcom,apq8016-lpass-cpu"; 1702 reg = <0x07708000 0x10000>; 1703 reg-names = "lpass-lpaif"; 1704 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1705 interrupt-names = "lpass-irq-lpaif"; 1706 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1707 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1708 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>, 1709 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>, 1710 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>, 1711 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>, 1712 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>; 1713 clock-names = "ahbix-clk", 1714 "mi2s-bit-clk0", 1715 "mi2s-bit-clk1", 1716 "mi2s-bit-clk2", 1717 "mi2s-bit-clk3", 1718 "pcnoc-mport-clk", 1719 "pcnoc-sway-clk"; 1720 #sound-dai-cells = <1>; 1721 #address-cells = <1>; 1722 #size-cells = <0>; 1723 status = "disabled"; 1724 }; 1725 1726 lpass_codec: audio-codec@771c000 { 1727 compatible = "qcom,msm8916-wcd-digital-codec"; 1728 reg = <0x0771c000 0x400>; 1729 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, 1730 <&gcc GCC_CODEC_DIGCODEC_CLK>; 1731 clock-names = "ahbix-clk", "mclk"; 1732 #sound-dai-cells = <1>; 1733 status = "disabled"; 1734 }; 1735 1736 sdhc_1: mmc@7824900 { 1737 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1738 reg = <0x07824900 0x11c>, <0x07824000 0x800>; 1739 reg-names = "hc", "core"; 1740 1741 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1743 interrupt-names = "hc_irq", "pwr_irq"; 1744 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1745 <&gcc GCC_SDCC1_APPS_CLK>, 1746 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1747 clock-names = "iface", "core", "xo"; 1748 resets = <&gcc GCC_SDCC1_BCR>; 1749 pinctrl-0 = <&sdc1_default>; 1750 pinctrl-1 = <&sdc1_sleep>; 1751 pinctrl-names = "default", "sleep"; 1752 mmc-ddr-1_8v; 1753 bus-width = <8>; 1754 non-removable; 1755 status = "disabled"; 1756 }; 1757 1758 sdhc_2: mmc@7864900 { 1759 compatible = "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"; 1760 reg = <0x07864900 0x11c>, <0x07864000 0x800>; 1761 reg-names = "hc", "core"; 1762 1763 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1764 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1765 interrupt-names = "hc_irq", "pwr_irq"; 1766 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1767 <&gcc GCC_SDCC2_APPS_CLK>, 1768 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1769 clock-names = "iface", "core", "xo"; 1770 resets = <&gcc GCC_SDCC2_BCR>; 1771 pinctrl-0 = <&sdc2_default>; 1772 pinctrl-1 = <&sdc2_sleep>; 1773 pinctrl-names = "default", "sleep"; 1774 bus-width = <4>; 1775 status = "disabled"; 1776 }; 1777 1778 blsp_dma: dma-controller@7884000 { 1779 compatible = "qcom,bam-v1.7.0"; 1780 reg = <0x07884000 0x23000>; 1781 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1782 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1783 clock-names = "bam_clk"; 1784 #dma-cells = <1>; 1785 qcom,ee = <0>; 1786 qcom,controlled-remotely; 1787 }; 1788 1789 blsp_uart1: serial@78af000 { 1790 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1791 reg = <0x078af000 0x200>; 1792 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1793 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1794 clock-names = "core", "iface"; 1795 dmas = <&blsp_dma 0>, <&blsp_dma 1>; 1796 dma-names = "tx", "rx"; 1797 status = "disabled"; 1798 }; 1799 1800 blsp_uart2: serial@78b0000 { 1801 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1802 reg = <0x078b0000 0x200>; 1803 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1804 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; 1805 clock-names = "core", "iface"; 1806 dmas = <&blsp_dma 2>, <&blsp_dma 3>; 1807 dma-names = "tx", "rx"; 1808 status = "disabled"; 1809 }; 1810 1811 blsp_i2c1: i2c@78b5000 { 1812 compatible = "qcom,i2c-qup-v2.2.1"; 1813 reg = <0x078b5000 0x500>; 1814 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1815 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, 1816 <&gcc GCC_BLSP1_AHB_CLK>; 1817 clock-names = "core", "iface"; 1818 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1819 dma-names = "tx", "rx"; 1820 pinctrl-0 = <&blsp_i2c1_default>; 1821 pinctrl-1 = <&blsp_i2c1_sleep>; 1822 pinctrl-names = "default", "sleep"; 1823 #address-cells = <1>; 1824 #size-cells = <0>; 1825 status = "disabled"; 1826 }; 1827 1828 blsp_spi1: spi@78b5000 { 1829 compatible = "qcom,spi-qup-v2.2.1"; 1830 reg = <0x078b5000 0x500>; 1831 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1832 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 1833 <&gcc GCC_BLSP1_AHB_CLK>; 1834 clock-names = "core", "iface"; 1835 dmas = <&blsp_dma 4>, <&blsp_dma 5>; 1836 dma-names = "tx", "rx"; 1837 pinctrl-0 = <&blsp_spi1_default>; 1838 pinctrl-1 = <&blsp_spi1_sleep>; 1839 pinctrl-names = "default", "sleep"; 1840 #address-cells = <1>; 1841 #size-cells = <0>; 1842 status = "disabled"; 1843 }; 1844 1845 blsp_i2c2: i2c@78b6000 { 1846 compatible = "qcom,i2c-qup-v2.2.1"; 1847 reg = <0x078b6000 0x500>; 1848 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1849 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1850 <&gcc GCC_BLSP1_AHB_CLK>; 1851 clock-names = "core", "iface"; 1852 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1853 dma-names = "tx", "rx"; 1854 pinctrl-0 = <&blsp_i2c2_default>; 1855 pinctrl-1 = <&blsp_i2c2_sleep>; 1856 pinctrl-names = "default", "sleep"; 1857 #address-cells = <1>; 1858 #size-cells = <0>; 1859 status = "disabled"; 1860 }; 1861 1862 blsp_spi2: spi@78b6000 { 1863 compatible = "qcom,spi-qup-v2.2.1"; 1864 reg = <0x078b6000 0x500>; 1865 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1866 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 1867 <&gcc GCC_BLSP1_AHB_CLK>; 1868 clock-names = "core", "iface"; 1869 dmas = <&blsp_dma 6>, <&blsp_dma 7>; 1870 dma-names = "tx", "rx"; 1871 pinctrl-0 = <&blsp_spi2_default>; 1872 pinctrl-1 = <&blsp_spi2_sleep>; 1873 pinctrl-names = "default", "sleep"; 1874 #address-cells = <1>; 1875 #size-cells = <0>; 1876 status = "disabled"; 1877 }; 1878 1879 blsp_i2c3: i2c@78b7000 { 1880 compatible = "qcom,i2c-qup-v2.2.1"; 1881 reg = <0x078b7000 0x500>; 1882 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1883 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1884 <&gcc GCC_BLSP1_AHB_CLK>; 1885 clock-names = "core", "iface"; 1886 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1887 dma-names = "tx", "rx"; 1888 pinctrl-0 = <&blsp_i2c3_default>; 1889 pinctrl-1 = <&blsp_i2c3_sleep>; 1890 pinctrl-names = "default", "sleep"; 1891 #address-cells = <1>; 1892 #size-cells = <0>; 1893 status = "disabled"; 1894 }; 1895 1896 blsp_spi3: spi@78b7000 { 1897 compatible = "qcom,spi-qup-v2.2.1"; 1898 reg = <0x078b7000 0x500>; 1899 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1900 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1901 <&gcc GCC_BLSP1_AHB_CLK>; 1902 clock-names = "core", "iface"; 1903 dmas = <&blsp_dma 8>, <&blsp_dma 9>; 1904 dma-names = "tx", "rx"; 1905 pinctrl-0 = <&blsp_spi3_default>; 1906 pinctrl-1 = <&blsp_spi3_sleep>; 1907 pinctrl-names = "default", "sleep"; 1908 #address-cells = <1>; 1909 #size-cells = <0>; 1910 status = "disabled"; 1911 }; 1912 1913 blsp_i2c4: i2c@78b8000 { 1914 compatible = "qcom,i2c-qup-v2.2.1"; 1915 reg = <0x078b8000 0x500>; 1916 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1917 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1918 <&gcc GCC_BLSP1_AHB_CLK>; 1919 clock-names = "core", "iface"; 1920 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1921 dma-names = "tx", "rx"; 1922 pinctrl-0 = <&blsp_i2c4_default>; 1923 pinctrl-1 = <&blsp_i2c4_sleep>; 1924 pinctrl-names = "default", "sleep"; 1925 #address-cells = <1>; 1926 #size-cells = <0>; 1927 status = "disabled"; 1928 }; 1929 1930 blsp_spi4: spi@78b8000 { 1931 compatible = "qcom,spi-qup-v2.2.1"; 1932 reg = <0x078b8000 0x500>; 1933 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1934 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>, 1935 <&gcc GCC_BLSP1_AHB_CLK>; 1936 clock-names = "core", "iface"; 1937 dmas = <&blsp_dma 10>, <&blsp_dma 11>; 1938 dma-names = "tx", "rx"; 1939 pinctrl-0 = <&blsp_spi4_default>; 1940 pinctrl-1 = <&blsp_spi4_sleep>; 1941 pinctrl-names = "default", "sleep"; 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 status = "disabled"; 1945 }; 1946 1947 blsp_i2c5: i2c@78b9000 { 1948 compatible = "qcom,i2c-qup-v2.2.1"; 1949 reg = <0x078b9000 0x500>; 1950 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1951 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>, 1952 <&gcc GCC_BLSP1_AHB_CLK>; 1953 clock-names = "core", "iface"; 1954 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1955 dma-names = "tx", "rx"; 1956 pinctrl-0 = <&blsp_i2c5_default>; 1957 pinctrl-1 = <&blsp_i2c5_sleep>; 1958 pinctrl-names = "default", "sleep"; 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 status = "disabled"; 1962 }; 1963 1964 blsp_spi5: spi@78b9000 { 1965 compatible = "qcom,spi-qup-v2.2.1"; 1966 reg = <0x078b9000 0x500>; 1967 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 1968 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 1969 <&gcc GCC_BLSP1_AHB_CLK>; 1970 clock-names = "core", "iface"; 1971 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 1972 dma-names = "tx", "rx"; 1973 pinctrl-0 = <&blsp_spi5_default>; 1974 pinctrl-1 = <&blsp_spi5_sleep>; 1975 pinctrl-names = "default", "sleep"; 1976 #address-cells = <1>; 1977 #size-cells = <0>; 1978 status = "disabled"; 1979 }; 1980 1981 blsp_i2c6: i2c@78ba000 { 1982 compatible = "qcom,i2c-qup-v2.2.1"; 1983 reg = <0x078ba000 0x500>; 1984 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1985 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 1986 <&gcc GCC_BLSP1_AHB_CLK>; 1987 clock-names = "core", "iface"; 1988 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 1989 dma-names = "tx", "rx"; 1990 pinctrl-0 = <&blsp_i2c6_default>; 1991 pinctrl-1 = <&blsp_i2c6_sleep>; 1992 pinctrl-names = "default", "sleep"; 1993 #address-cells = <1>; 1994 #size-cells = <0>; 1995 status = "disabled"; 1996 }; 1997 1998 blsp_spi6: spi@78ba000 { 1999 compatible = "qcom,spi-qup-v2.2.1"; 2000 reg = <0x078ba000 0x500>; 2001 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 2002 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>, 2003 <&gcc GCC_BLSP1_AHB_CLK>; 2004 clock-names = "core", "iface"; 2005 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 2006 dma-names = "tx", "rx"; 2007 pinctrl-0 = <&blsp_spi6_default>; 2008 pinctrl-1 = <&blsp_spi6_sleep>; 2009 pinctrl-names = "default", "sleep"; 2010 #address-cells = <1>; 2011 #size-cells = <0>; 2012 status = "disabled"; 2013 }; 2014 2015 usb: usb@78d9000 { 2016 compatible = "qcom,ci-hdrc"; 2017 reg = <0x078d9000 0x200>, 2018 <0x078d9200 0x200>; 2019 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2020 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2021 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 2022 <&gcc GCC_USB_HS_SYSTEM_CLK>; 2023 clock-names = "iface", "core"; 2024 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 2025 assigned-clock-rates = <80000000>; 2026 resets = <&gcc GCC_USB_HS_BCR>; 2027 reset-names = "core"; 2028 #reset-cells = <1>; 2029 phy_type = "ulpi"; 2030 dr_mode = "otg"; 2031 adp-disable; 2032 hnp-disable; 2033 srp-disable; 2034 ahb-burst-config = <0>; 2035 phy-names = "usb-phy"; 2036 phys = <&usb_hs_phy>; 2037 status = "disabled"; 2038 2039 ulpi { 2040 usb_hs_phy: phy { 2041 compatible = "qcom,usb-hs-phy-msm8916", 2042 "qcom,usb-hs-phy"; 2043 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2044 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 2045 clock-names = "ref", "sleep"; 2046 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>; 2047 reset-names = "phy", "por"; 2048 #phy-cells = <0>; 2049 qcom,init-seq = /bits/ 8 <0x0 0x44>, 2050 <0x1 0x6b>, 2051 <0x2 0x24>, 2052 <0x3 0x13>; 2053 }; 2054 }; 2055 }; 2056 2057 wcnss: remoteproc@a204000 { 2058 compatible = "qcom,pronto-v2-pil", "qcom,pronto"; 2059 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 2060 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2061 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2062 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2063 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2064 interrupt-names = "wdog", 2065 "fatal", 2066 "ready", 2067 "handover", 2068 "stop-ack"; 2069 reg = <0x0a204000 0x2000>, 2070 <0x0a202000 0x1000>, 2071 <0x0a21b000 0x3000>; 2072 reg-names = "ccu", "dxe", "pmu"; 2073 2074 memory-region = <&wcnss_mem>; 2075 2076 power-domains = <&rpmpd MSM8939_VDDCX>, 2077 <&rpmpd MSM8939_VDDMX>; 2078 power-domain-names = "cx", "mx"; 2079 2080 qcom,smem-states = <&wcnss_smp2p_out 0>; 2081 qcom,smem-state-names = "stop"; 2082 2083 pinctrl-names = "default"; 2084 pinctrl-0 = <&wcss_wlan_default>; 2085 2086 status = "disabled"; 2087 2088 wcnss_iris: iris { 2089 /* Separate chip, compatible is board-specific */ 2090 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 2091 clock-names = "xo"; 2092 }; 2093 2094 smd-edge { 2095 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 2096 mboxes = <&apcs1_mbox 17>; 2097 qcom,smd-edge = <6>; 2098 qcom,remote-pid = <4>; 2099 2100 label = "pronto"; 2101 2102 wcnss { 2103 compatible = "qcom,wcnss"; 2104 qcom,smd-channels = "WCNSS_CTRL"; 2105 2106 qcom,mmio = <&wcnss>; 2107 2108 wcnss_bt: bluetooth { 2109 compatible = "qcom,wcnss-bt"; 2110 }; 2111 2112 wcnss_wifi: wifi { 2113 compatible = "qcom,wcnss-wlan"; 2114 2115 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2116 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 2117 interrupt-names = "tx", "rx"; 2118 2119 qcom,smem-states = <&apps_smsm 10>, 2120 <&apps_smsm 9>; 2121 qcom,smem-state-names = "tx-enable", 2122 "tx-rings-empty"; 2123 }; 2124 }; 2125 }; 2126 }; 2127 2128 intc: interrupt-controller@b000000 { 2129 compatible = "qcom,msm-qgic2"; 2130 reg = <0x0b000000 0x1000>, <0x0b002000 0x2000>, 2131 <0x0b001000 0x1000>, <0x0b004000 0x2000>; 2132 interrupt-controller; 2133 #interrupt-cells = <3>; 2134 interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 2135 }; 2136 2137 apcs1_mbox: mailbox@b011000 { 2138 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2139 reg = <0x0b011000 0x1000>; 2140 clocks = <&a53pll_c1>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2141 clock-names = "pll", "aux", "ref"; 2142 #clock-cells = <0>; 2143 assigned-clocks = <&apcs2>; 2144 assigned-clock-rates = <297600000>; 2145 #mbox-cells = <1>; 2146 }; 2147 2148 a53pll_c1: clock@b016000 { 2149 compatible = "qcom,msm8939-a53pll"; 2150 reg = <0x0b016000 0x40>; 2151 #clock-cells = <0>; 2152 }; 2153 2154 acc0: clock-controller@b088000 { 2155 compatible = "qcom,kpss-acc-v2"; 2156 reg = <0x0b088000 0x1000>; 2157 }; 2158 2159 saw0: power-manager@b089000 { 2160 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2161 reg = <0x0b089000 0x1000>; 2162 }; 2163 2164 acc1: clock-controller@b098000 { 2165 compatible = "qcom,kpss-acc-v2"; 2166 reg = <0x0b098000 0x1000>; 2167 }; 2168 2169 saw1: power-manager@b099000 { 2170 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2171 reg = <0x0b099000 0x1000>; 2172 }; 2173 2174 acc2: clock-controller@b0a8000 { 2175 compatible = "qcom,kpss-acc-v2"; 2176 reg = <0x0b0a8000 0x1000>; 2177 }; 2178 2179 saw2: power-manager@b0a9000 { 2180 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2181 reg = <0x0b0a9000 0x1000>; 2182 }; 2183 2184 acc3: clock-controller@b0b8000 { 2185 compatible = "qcom,kpss-acc-v2"; 2186 reg = <0x0b0b8000 0x1000>; 2187 }; 2188 2189 saw3: power-manager@b0b9000 { 2190 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2191 reg = <0x0b0b9000 0x1000>; 2192 }; 2193 2194 apcs0_mbox: mailbox@b111000 { 2195 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2196 reg = <0x0b111000 0x1000>; 2197 clocks = <&a53pll_c0>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2198 clock-names = "pll", "aux", "ref"; 2199 #clock-cells = <0>; 2200 #mbox-cells = <1>; 2201 }; 2202 2203 a53pll_c0: clock@b116000 { 2204 compatible = "qcom,msm8939-a53pll"; 2205 reg = <0x0b116000 0x40>; 2206 #clock-cells = <0>; 2207 }; 2208 2209 timer@b120000 { 2210 compatible = "arm,armv7-timer-mem"; 2211 reg = <0x0b120000 0x1000>; 2212 #address-cells = <1>; 2213 #size-cells = <1>; 2214 ranges; 2215 /* Necessary because firmware does not configure this correctly */ 2216 clock-frequency = <19200000>; 2217 2218 frame@b121000 { 2219 reg = <0x0b121000 0x1000>, 2220 <0x0b122000 0x1000>; 2221 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2222 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2223 frame-number = <0>; 2224 }; 2225 2226 frame@b123000 { 2227 reg = <0x0b123000 0x1000>; 2228 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2229 frame-number = <1>; 2230 status = "disabled"; 2231 }; 2232 2233 frame@b124000 { 2234 reg = <0x0b124000 0x1000>; 2235 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2236 frame-number = <2>; 2237 status = "disabled"; 2238 }; 2239 2240 frame@b125000 { 2241 reg = <0x0b125000 0x1000>; 2242 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2243 frame-number = <3>; 2244 status = "disabled"; 2245 }; 2246 2247 frame@b126000 { 2248 reg = <0x0b126000 0x1000>; 2249 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2250 frame-number = <4>; 2251 status = "disabled"; 2252 }; 2253 2254 frame@b127000 { 2255 reg = <0x0b127000 0x1000>; 2256 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2257 frame-number = <5>; 2258 status = "disabled"; 2259 }; 2260 2261 frame@b128000 { 2262 reg = <0x0b128000 0x1000>; 2263 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2264 frame-number = <6>; 2265 status = "disabled"; 2266 }; 2267 }; 2268 2269 acc4: clock-controller@b188000 { 2270 compatible = "qcom,kpss-acc-v2"; 2271 reg = <0x0b188000 0x1000>; 2272 }; 2273 2274 saw4: power-manager@b189000 { 2275 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2276 reg = <0x0b189000 0x1000>; 2277 }; 2278 2279 acc5: clock-controller@b198000 { 2280 compatible = "qcom,kpss-acc-v2"; 2281 reg = <0x0b198000 0x1000>; 2282 }; 2283 2284 saw5: power-manager@b199000 { 2285 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2286 reg = <0x0b199000 0x1000>; 2287 }; 2288 2289 acc6: clock-controller@b1a8000 { 2290 compatible = "qcom,kpss-acc-v2"; 2291 reg = <0x0b1a8000 0x1000>; 2292 }; 2293 2294 saw6: power-manager@b1a9000 { 2295 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2296 reg = <0x0b1a9000 0x1000>; 2297 }; 2298 2299 acc7: clock-controller@b1b8000 { 2300 compatible = "qcom,kpss-acc-v2"; 2301 reg = <0x0b1b8000 0x1000>; 2302 }; 2303 2304 saw7: power-manager@b1b9000 { 2305 compatible = "qcom,msm8939-saw2-v3.0-cpu", "qcom,saw2"; 2306 reg = <0x0b1b9000 0x1000>; 2307 }; 2308 2309 a53pll_cci: clock@b1d0000 { 2310 compatible = "qcom,msm8939-a53pll"; 2311 reg = <0x0b1d0000 0x40>; 2312 #clock-cells = <0>; 2313 }; 2314 2315 apcs2: mailbox@b1d1000 { 2316 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 2317 reg = <0x0b1d1000 0x1000>; 2318 clocks = <&a53pll_cci>, <&gcc GPLL0_VOTE>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 2319 clock-names = "pll", "aux", "ref"; 2320 #clock-cells = <0>; 2321 #mbox-cells = <1>; 2322 }; 2323 }; 2324 2325 thermal_zones: thermal-zones { 2326 cpu0-thermal { 2327 polling-delay-passive = <250>; 2328 2329 thermal-sensors = <&tsens 5>; 2330 2331 trips { 2332 cpu0_alert: trip0 { 2333 temperature = <75000>; 2334 hysteresis = <2000>; 2335 type = "passive"; 2336 }; 2337 2338 cpu0_crit: trip1 { 2339 temperature = <115000>; 2340 hysteresis = <0>; 2341 type = "critical"; 2342 }; 2343 }; 2344 2345 cooling-maps { 2346 map0 { 2347 trip = <&cpu0_alert>; 2348 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2349 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2350 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2351 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2352 }; 2353 }; 2354 }; 2355 2356 cpu1-thermal { 2357 polling-delay-passive = <250>; 2358 2359 thermal-sensors = <&tsens 6>; 2360 2361 trips { 2362 cpu1_alert: trip0 { 2363 temperature = <75000>; 2364 hysteresis = <2000>; 2365 type = "passive"; 2366 }; 2367 2368 cpu1_crit: trip1 { 2369 temperature = <110000>; 2370 hysteresis = <2000>; 2371 type = "critical"; 2372 }; 2373 }; 2374 2375 cooling-maps { 2376 map0 { 2377 trip = <&cpu1_alert>; 2378 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2379 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2380 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2381 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2382 }; 2383 }; 2384 }; 2385 2386 cpu2-thermal { 2387 polling-delay-passive = <250>; 2388 2389 thermal-sensors = <&tsens 7>; 2390 2391 trips { 2392 cpu2_alert: trip0 { 2393 temperature = <75000>; 2394 hysteresis = <2000>; 2395 type = "passive"; 2396 }; 2397 2398 cpu2_crit: trip1 { 2399 temperature = <110000>; 2400 hysteresis = <2000>; 2401 type = "critical"; 2402 }; 2403 }; 2404 2405 cooling-maps { 2406 map0 { 2407 trip = <&cpu2_alert>; 2408 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2409 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2410 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2411 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2412 }; 2413 }; 2414 }; 2415 2416 cpu3-thermal { 2417 polling-delay-passive = <250>; 2418 2419 thermal-sensors = <&tsens 8>; 2420 2421 trips { 2422 cpu3_alert: trip0 { 2423 temperature = <75000>; 2424 hysteresis = <2000>; 2425 type = "passive"; 2426 }; 2427 2428 cpu3_crit: trip1 { 2429 temperature = <110000>; 2430 hysteresis = <2000>; 2431 type = "critical"; 2432 }; 2433 }; 2434 2435 cooling-maps { 2436 map0 { 2437 trip = <&cpu3_alert>; 2438 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2439 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2440 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2441 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2442 }; 2443 }; 2444 }; 2445 2446 cpu4567-thermal { 2447 polling-delay-passive = <250>; 2448 2449 thermal-sensors = <&tsens 9>; 2450 2451 trips { 2452 cpu4567_alert: trip0 { 2453 temperature = <75000>; 2454 hysteresis = <2000>; 2455 type = "passive"; 2456 }; 2457 2458 cpu4567_crit: trip1 { 2459 temperature = <110000>; 2460 hysteresis = <2000>; 2461 type = "critical"; 2462 }; 2463 }; 2464 2465 cooling-maps { 2466 map0 { 2467 trip = <&cpu4567_alert>; 2468 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2469 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2470 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2471 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2472 }; 2473 }; 2474 }; 2475 2476 gpu-thermal { 2477 polling-delay-passive = <250>; 2478 2479 thermal-sensors = <&tsens 3>; 2480 2481 cooling-maps { 2482 map0 { 2483 trip = <&gpu_alert0>; 2484 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2485 }; 2486 }; 2487 2488 trips { 2489 gpu_alert0: trip-point0 { 2490 temperature = <75000>; 2491 hysteresis = <2000>; 2492 type = "passive"; 2493 }; 2494 2495 gpu_crit: gpu-crit { 2496 temperature = <95000>; 2497 hysteresis = <2000>; 2498 type = "critical"; 2499 }; 2500 }; 2501 }; 2502 2503 modem1-thermal { 2504 polling-delay-passive = <250>; 2505 2506 thermal-sensors = <&tsens 0>; 2507 2508 trips { 2509 modem1_alert0: trip-point0 { 2510 temperature = <85000>; 2511 hysteresis = <2000>; 2512 type = "hot"; 2513 }; 2514 }; 2515 }; 2516 2517 modem2-thermal { 2518 polling-delay-passive = <250>; 2519 2520 thermal-sensors = <&tsens 2>; 2521 2522 trips { 2523 modem2_alert0: trip-point0 { 2524 temperature = <85000>; 2525 hysteresis = <2000>; 2526 type = "hot"; 2527 }; 2528 }; 2529 }; 2530 2531 camera-thermal { 2532 polling-delay-passive = <250>; 2533 2534 thermal-sensors = <&tsens 1>; 2535 2536 trips { 2537 cam_alert0: trip-point0 { 2538 temperature = <75000>; 2539 hysteresis = <2000>; 2540 type = "hot"; 2541 }; 2542 }; 2543 }; 2544 }; 2545 2546 timer { 2547 compatible = "arm,armv8-timer"; 2548 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2549 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2550 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2551 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2552 }; 2553};
~/
Read-only file preview.