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msm8937.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/msm8937.dtsi
1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2023, Dang Huynh <danct12@riseup.net> 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,gcc-msm8917.h> 8#include <dt-bindings/clock/qcom,rpmcc.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/qcom-rpmpd.h> 11#include <dt-bindings/thermal/thermal.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clocks { 20 xo_board: xo-board { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 }; 24 25 sleep_clk: sleep-clk { 26 compatible = "fixed-clock"; 27 #clock-cells = <0>; 28 }; 29 }; 30 31 cpus { 32 #address-cells = <1>; 33 #size-cells = <0>; 34 35 cpu0: cpu@0 { 36 compatible = "arm,cortex-a53"; 37 reg = <0x0>; 38 device_type = "cpu"; 39 enable-method = "psci"; 40 operating-points-v2 = <&cpu_opp_table_c0>; 41 next-level-cache = <&l2_0>; 42 #cooling-cells = <2>; 43 44 l2_0: l2-cache { 45 compatible = "cache"; 46 cache-level = <2>; 47 cache-size = <0x80000>; 48 cache-unified; 49 }; 50 }; 51 52 cpu1: cpu@1 { 53 compatible = "arm,cortex-a53"; 54 reg = <0x1>; 55 device_type = "cpu"; 56 enable-method = "psci"; 57 operating-points-v2 = <&cpu_opp_table_c0>; 58 next-level-cache = <&l2_0>; 59 #cooling-cells = <2>; 60 }; 61 62 cpu2: cpu@2 { 63 compatible = "arm,cortex-a53"; 64 reg = <0x2>; 65 device_type = "cpu"; 66 enable-method = "psci"; 67 operating-points-v2 = <&cpu_opp_table_c0>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu3: cpu@3 { 73 compatible = "arm,cortex-a53"; 74 reg = <0x3>; 75 device_type = "cpu"; 76 enable-method = "psci"; 77 operating-points-v2 = <&cpu_opp_table_c0>; 78 next-level-cache = <&l2_0>; 79 #cooling-cells = <2>; 80 }; 81 82 cpu4: cpu@100 { 83 compatible = "arm,cortex-a53"; 84 reg = <0x100>; 85 device_type = "cpu"; 86 next-level-cache = <&l2_1>; 87 enable-method = "psci"; 88 operating-points-v2 = <&cpu_opp_table_c1>; 89 #cooling-cells = <2>; 90 91 l2_1: l2-cache { 92 compatible = "cache"; 93 cache-level = <2>; 94 cache-size = <0x100000>; 95 cache-unified; 96 }; 97 }; 98 99 cpu5: cpu@101 { 100 compatible = "arm,cortex-a53"; 101 reg = <0x101>; 102 device_type = "cpu"; 103 next-level-cache = <&l2_1>; 104 enable-method = "psci"; 105 operating-points-v2 = <&cpu_opp_table_c1>; 106 #cooling-cells = <2>; 107 }; 108 109 cpu6: cpu@102 { 110 compatible = "arm,cortex-a53"; 111 reg = <0x102>; 112 device_type = "cpu"; 113 next-level-cache = <&l2_1>; 114 enable-method = "psci"; 115 operating-points-v2 = <&cpu_opp_table_c1>; 116 #cooling-cells = <2>; 117 }; 118 119 cpu7: cpu@103 { 120 compatible = "arm,cortex-a53"; 121 reg = <0x103>; 122 device_type = "cpu"; 123 next-level-cache = <&l2_1>; 124 enable-method = "psci"; 125 operating-points-v2 = <&cpu_opp_table_c1>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu-map { 130 /* Little Cores */ 131 cluster0 { 132 core0 { 133 cpu = <&cpu0>; 134 }; 135 136 core1 { 137 cpu = <&cpu1>; 138 }; 139 140 core2 { 141 cpu = <&cpu2>; 142 }; 143 144 core3 { 145 cpu = <&cpu3>; 146 }; 147 }; 148 149 /* Big Cores */ 150 cluster1 { 151 core0 { 152 cpu = <&cpu4>; 153 }; 154 155 core1 { 156 cpu = <&cpu5>; 157 }; 158 159 core2 { 160 cpu = <&cpu6>; 161 }; 162 163 core3 { 164 cpu = <&cpu7>; 165 }; 166 }; 167 }; 168 }; 169 170 firmware { 171 scm: scm { 172 compatible = "qcom,scm-msm8937", "qcom,scm"; 173 clocks = <&gcc GCC_CRYPTO_CLK>, 174 <&gcc GCC_CRYPTO_AXI_CLK>, 175 <&gcc GCC_CRYPTO_AHB_CLK>; 176 clock-names = "core", 177 "bus", 178 "iface"; 179 #reset-cells = <1>; 180 181 qcom,dload-mode = <&tcsr 0x6100>; 182 }; 183 }; 184 185 memory@80000000 { 186 /* We expect the bootloader to fill in the reg */ 187 reg = <0 0x80000000 0 0>; 188 device_type = "memory"; 189 }; 190 191 reserved-memory { 192 ranges; 193 #address-cells = <2>; 194 #size-cells = <2>; 195 196 qseecom_mem: reserved@85b00000 { 197 reg = <0x0 0x85b00000 0x0 0x800000>; 198 no-map; 199 }; 200 201 smem@86300000 { 202 compatible = "qcom,smem"; 203 reg = <0x0 0x86300000 0x0 0x100000>; 204 no-map; 205 206 hwlocks = <&tcsr_mutex 3>; 207 qcom,rpm-msg-ram = <&rpm_msg_ram>; 208 }; 209 210 reserved@86400000 { 211 reg = <0x0 0x86400000 0x0 0x400000>; 212 no-map; 213 }; 214 215 rmtfs@92100000 { 216 compatible = "qcom,rmtfs-mem"; 217 reg = <0x0 0x92100000 0x0 0x180000>; 218 no-map; 219 220 qcom,client-id = <1>; 221 }; 222 223 adsp_mem: adsp { 224 size = <0x0 0x1100000>; 225 alignment = <0x0 0x100000>; 226 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 227 no-map; 228 status = "disabled"; 229 }; 230 231 mba_mem: mba { 232 size = <0x0 0x100000>; 233 alignment = <0x0 0x100000>; 234 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 235 no-map; 236 status = "disabled"; 237 }; 238 239 wcnss_mem: wcnss { 240 size = <0x0 0x700000>; 241 alignment = <0x0 0x100000>; 242 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 243 no-map; 244 status = "disabled"; 245 }; 246 247 venus_mem: venus { 248 size = <0x0 0x400000>; 249 alignment = <0x0 0x100000>; 250 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 251 no-map; 252 status = "disabled"; 253 }; 254 }; 255 256 cpu_opp_table_c0: opp-table-c0 { 257 compatible = "operating-points-v2"; 258 opp-shared; 259 260 opp-768000000 { 261 opp-hz = /bits/ 64 <768000000>; 262 }; 263 264 opp-902400000 { 265 opp-hz = /bits/ 64 <902400000>; 266 }; 267 268 opp-998400000 { 269 opp-hz = /bits/ 64 <998400000>; 270 }; 271 272 opp-1094400000 { 273 opp-hz = /bits/ 64 <1094400000>; 274 }; 275 }; 276 277 cpu_opp_table_c1: opp-table-c1 { 278 compatible = "operating-points-v2"; 279 opp-shared; 280 281 opp-960000000 { 282 opp-hz = /bits/ 64 <960000000>; 283 }; 284 285 opp-1094400000 { 286 opp-hz = /bits/ 64 <1094400000>; 287 }; 288 289 opp-1209600000 { 290 opp-hz = /bits/ 64 <1209600000>; 291 }; 292 293 opp-1248000000 { 294 opp-hz = /bits/ 64 <1248000000>; 295 }; 296 297 opp-1344000000 { 298 opp-hz = /bits/ 64 <1344000000>; 299 }; 300 301 opp-1401600000 { 302 opp-hz = /bits/ 64 <1401600000>; 303 }; 304 }; 305 306 pmu { 307 compatible = "arm,cortex-a53-pmu"; 308 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 309 }; 310 311 psci { 312 compatible = "arm,psci-1.0"; 313 method = "smc"; 314 }; 315 316 rpm: remoteproc { 317 compatible = "qcom,msm8937-rpm-proc", "qcom,rpm-proc"; 318 319 smd-edge { 320 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 321 qcom,ipc = <&apcs1 8 0>; 322 qcom,smd-edge = <15>; 323 324 rpm_requests: rpm-requests { 325 compatible = "qcom,rpm-msm8937", "qcom,smd-rpm"; 326 qcom,smd-channels = "rpm_requests"; 327 328 rpmcc: clock-controller { 329 compatible = "qcom,rpmcc-msm8937", "qcom,rpmcc"; 330 #clock-cells = <1>; 331 clocks = <&xo_board>; 332 clock-names = "xo"; 333 }; 334 335 rpmpd: power-controller { 336 compatible = "qcom,msm8937-rpmpd", "qcom,msm8917-rpmpd"; 337 #power-domain-cells = <1>; 338 operating-points-v2 = <&rpmpd_opp_table>; 339 340 rpmpd_opp_table: opp-table { 341 compatible = "operating-points-v2"; 342 343 rpmpd_opp_ret: opp1 { 344 opp-level = <RPM_SMD_LEVEL_RETENTION>; 345 }; 346 347 rpmpd_opp_ret_plus: opp2 { 348 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 349 }; 350 351 rpmpd_opp_min_svs: opp3 { 352 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 353 }; 354 355 rpmpd_opp_low_svs: opp4 { 356 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 357 }; 358 359 rpmpd_opp_svs: opp5 { 360 opp-level = <RPM_SMD_LEVEL_SVS>; 361 }; 362 363 rpmpd_opp_svs_plus: opp6 { 364 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 365 }; 366 367 rpmpd_opp_nom: opp7 { 368 opp-level = <RPM_SMD_LEVEL_NOM>; 369 }; 370 371 rpmpd_opp_nom_plus: opp8 { 372 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 373 }; 374 375 rpmpd_opp_turbo: opp9 { 376 opp-level = <RPM_SMD_LEVEL_TURBO>; 377 }; 378 }; 379 }; 380 }; 381 }; 382 }; 383 384 smp2p-adsp { 385 compatible = "qcom,smp2p"; 386 qcom,smem = <443>, <429>; 387 388 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 389 390 mboxes = <&apcs1 10>; 391 392 qcom,local-pid = <0>; 393 qcom,remote-pid = <2>; 394 395 adsp_smp2p_out: master-kernel { 396 qcom,entry-name = "master-kernel"; 397 398 #qcom,smem-state-cells = <1>; 399 }; 400 401 adsp_smp2p_in: slave-kernel { 402 qcom,entry-name = "slave-kernel"; 403 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 }; 407 }; 408 409 smp2p-modem { 410 compatible = "qcom,smp2p"; 411 qcom,smem = <435>, <428>; 412 413 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 414 415 mboxes = <&apcs1 14>; 416 417 qcom,local-pid = <0>; 418 qcom,remote-pid = <1>; 419 420 modem_smp2p_out: master-kernel { 421 qcom,entry-name = "master-kernel"; 422 423 #qcom,smem-state-cells = <1>; 424 }; 425 426 modem_smp2p_in: slave-kernel { 427 qcom,entry-name = "slave-kernel"; 428 429 interrupt-controller; 430 #interrupt-cells = <2>; 431 }; 432 }; 433 434 smp2p-wcnss { 435 compatible = "qcom,smp2p"; 436 qcom,smem = <451>, <431>; 437 438 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 439 440 mboxes = <&apcs1 18>; 441 442 qcom,local-pid = <0>; 443 qcom,remote-pid = <4>; 444 445 wcnss_smp2p_out: master-kernel { 446 qcom,entry-name = "master-kernel"; 447 448 #qcom,smem-state-cells = <1>; 449 }; 450 451 wcnss_smp2p_in: slave-kernel { 452 qcom,entry-name = "slave-kernel"; 453 454 interrupt-controller; 455 #interrupt-cells = <2>; 456 }; 457 }; 458 459 smsm { 460 compatible = "qcom,smsm"; 461 462 #address-cells = <1>; 463 #size-cells = <0>; 464 465 mboxes = <0>, <&apcs1 13>, <0>, <&apcs1 19>; 466 467 apps_smsm: apps@0 { 468 reg = <0>; 469 470 #qcom,smem-state-cells = <1>; 471 }; 472 473 hexagon_smsm: hexagon@1 { 474 reg = <1>; 475 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 476 477 interrupt-controller; 478 #interrupt-cells = <2>; 479 }; 480 481 wcnss_smsm: wcnss@6 { 482 reg = <6>; 483 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 484 485 interrupt-controller; 486 #interrupt-cells = <2>; 487 }; 488 }; 489 490 soc: soc@0 { 491 compatible = "simple-bus"; 492 ranges = <0 0 0 0xffffffff>; 493 #address-cells = <1>; 494 #size-cells = <1>; 495 496 qfprom: qfprom@a4000 { 497 compatible = "qcom,msm8937-qfprom", "qcom,qfprom"; 498 reg = <0x000a4000 0x3000>; 499 #address-cells = <1>; 500 #size-cells = <1>; 501 502 tsens_base1: base1@1d8 { 503 reg = <0x1d8 0x1>; 504 bits = <0 8>; 505 }; 506 507 tsens_s5_p1: s5-p1@1d9 { 508 reg = <0x1d9 0x1>; 509 bits = <0 6>; 510 }; 511 512 tsens_s5_p2: s5-p2@1d9 { 513 reg = <0x1d9 0x2>; 514 bits = <6 6>; 515 }; 516 517 tsens_s6_p1: s6-p1@1da { 518 reg = <0x1da 0x2>; 519 bits = <4 6>; 520 }; 521 522 tsens_s6_p2: s6-p2@1db { 523 reg = <0x1db 0x1>; 524 bits = <2 6>; 525 }; 526 527 tsens_s7_p1: s7-p1@1dc { 528 reg = <0x1dc 0x1>; 529 bits = <0 6>; 530 }; 531 532 tsens_s7_p2: s7-p2@1dc { 533 reg = <0x1dc 0x2>; 534 bits = <6 6>; 535 }; 536 537 tsens_s8_p1: s8-p1@1dd { 538 reg = <0x1dd 0x2>; 539 bits = <4 6>; 540 }; 541 542 tsens_s8_p2: s8-p2@1de { 543 reg = <0x1de 0x1>; 544 bits = <2 6>; 545 }; 546 547 tsens_base2: base2@1df { 548 reg = <0x1df 0x1>; 549 bits = <0 8>; 550 }; 551 552 tsens_mode: mode@210 { 553 reg = <0x210 0x1>; 554 bits = <0 3>; 555 }; 556 557 tsens_s0_p1: s0-p1@210 { 558 reg = <0x210 0x2>; 559 bits = <3 6>; 560 }; 561 562 tsens_s0_p2: s0-p2@211 { 563 reg = <0x211 0x1>; 564 bits = <1 6>; 565 }; 566 567 tsens_s1_p1: s1-p1@211 { 568 reg = <0x211 0x2>; 569 bits = <7 6>; 570 }; 571 572 tsens_s1_p2: s1-p2@212 { 573 reg = <0x212 0x2>; 574 bits = <5 6>; 575 }; 576 577 tsens_s2_p1: s2-p1@213 { 578 reg = <0x213 0x2>; 579 bits = <3 6>; 580 }; 581 582 tsens_s2_p2: s2-p2@214 { 583 reg = <0x214 0x1>; 584 bits = <1 6>; 585 }; 586 587 tsens_s3_p1: s3-p1@214 { 588 reg = <0x214 0x2>; 589 bits = <7 6>; 590 }; 591 592 tsens_s3_p2: s3-p2@215 { 593 reg = <0x215 0x2>; 594 bits = <5 6>; 595 }; 596 597 tsens_s4_p1: s4-p1@216 { 598 reg = <0x216 0x2>; 599 bits = <3 6>; 600 }; 601 602 tsens_s4_p2: s4-p2@217 { 603 reg = <0x217 0x1>; 604 bits = <1 6>; 605 }; 606 607 tsens_s9_p1: s9-p1@230 { 608 reg = <0x230 0x1>; 609 bits = <0 6>; 610 }; 611 612 tsens_s9_p2: s9-p2@230 { 613 reg = <0x230 0x2>; 614 bits = <6 6>; 615 }; 616 617 tsens_s10_p1: s10-p1@231 { 618 reg = <0x231 0x2>; 619 bits = <4 6>; 620 }; 621 622 tsens_s10_p2: s10-p2@232 { 623 reg = <0x232 0x1>; 624 bits = <2 6>; 625 }; 626 627 gpu_speed_bin: gpu-speed-bin@201b { 628 reg = <0x201b 0x1>; 629 bits = <7 1>; 630 }; 631 }; 632 633 rpm_msg_ram: sram@60000 { 634 compatible = "qcom,rpm-msg-ram"; 635 reg = <0x00060000 0x8000>; 636 }; 637 638 usb_hs_phy: phy@6c000 { 639 compatible = "qcom,usb-hs-28nm-femtophy"; 640 reg = <0x0006c000 0x200>; 641 #phy-cells = <0>; 642 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 643 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 644 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 645 clock-names = "ref", 646 "ahb", 647 "sleep"; 648 resets = <&gcc GCC_QUSB2_PHY_BCR>, 649 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 650 reset-names = "phy", 651 "por"; 652 status = "disabled"; 653 }; 654 655 rng@e3000 { 656 compatible = "qcom,prng"; 657 reg = <0x000e3000 0x1000>; 658 clocks = <&gcc GCC_PRNG_AHB_CLK>; 659 clock-names = "core"; 660 }; 661 662 tsens: thermal-sensor@4a9000 { 663 compatible = "qcom,msm8937-tsens", "qcom,tsens-v1"; 664 reg = <0x004a9000 0x1000>, 665 <0x004a8000 0x1000>; 666 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 667 interrupt-names = "uplow"; 668 nvmem-cells = <&tsens_mode>, 669 <&tsens_base1>, <&tsens_base2>, 670 <&tsens_s0_p1>, <&tsens_s0_p2>, 671 <&tsens_s1_p1>, <&tsens_s1_p2>, 672 <&tsens_s2_p1>, <&tsens_s2_p2>, 673 <&tsens_s3_p1>, <&tsens_s3_p2>, 674 <&tsens_s4_p1>, <&tsens_s4_p2>, 675 <&tsens_s5_p1>, <&tsens_s5_p2>, 676 <&tsens_s6_p1>, <&tsens_s6_p2>, 677 <&tsens_s7_p1>, <&tsens_s7_p2>, 678 <&tsens_s8_p1>, <&tsens_s8_p2>, 679 <&tsens_s9_p1>, <&tsens_s9_p2>, 680 <&tsens_s10_p1>, <&tsens_s10_p2>; 681 nvmem-cell-names = "mode", 682 "base1", "base2", 683 "s0_p1", "s0_p2", 684 "s1_p1", "s1_p2", 685 "s2_p1", "s2_p2", 686 "s3_p1", "s3_p2", 687 "s4_p1", "s4_p2", 688 "s5_p1", "s5_p2", 689 "s6_p1", "s6_p2", 690 "s7_p1", "s7_p2", 691 "s8_p1", "s8_p2", 692 "s9_p1", "s9_p2", 693 "s10_p1", "s10_p2"; 694 #qcom,sensors = <11>; 695 #thermal-sensor-cells = <1>; 696 }; 697 698 restart@4ab000 { 699 compatible = "qcom,pshold"; 700 reg = <0x004ab000 0x4>; 701 }; 702 703 tlmm: pinctrl@1000000 { 704 compatible = "qcom,msm8917-pinctrl"; 705 reg = <0x01000000 0x300000>; 706 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 707 gpio-controller; 708 gpio-ranges = <&tlmm 0 0 134>; 709 #gpio-cells = <2>; 710 interrupt-controller; 711 #interrupt-cells = <2>; 712 713 blsp1_i2c2_default: blsp1-i2c2-default-state { 714 pins = "gpio6", "gpio7"; 715 function = "blsp_i2c2"; 716 drive-strength = <2>; 717 bias-disable; 718 }; 719 720 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 721 pins = "gpio6", "gpio7"; 722 function = "gpio"; 723 drive-strength = <2>; 724 bias-disable; 725 }; 726 727 blsp1_i2c3_default: blsp1-i2c3-default-state { 728 pins = "gpio10", "gpio11"; 729 function = "blsp_i2c3"; 730 drive-strength = <2>; 731 bias-disable; 732 }; 733 734 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 735 pins = "gpio10", "gpio11"; 736 function = "gpio"; 737 drive-strength = <2>; 738 bias-disable; 739 }; 740 741 blsp1_i2c4_default: blsp1-i2c4-default-state { 742 pins = "gpio14", "gpio15"; 743 function = "blsp_i2c4"; 744 drive-strength = <2>; 745 bias-disable; 746 }; 747 748 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 749 pins = "gpio14", "gpio15"; 750 function = "gpio"; 751 drive-strength = <2>; 752 bias-disable; 753 }; 754 755 blsp2_i2c1_default: blsp2-i2c1-default-state { 756 pins = "gpio18", "gpio19"; 757 function = "blsp_i2c5"; 758 drive-strength = <2>; 759 bias-disable; 760 }; 761 762 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 763 pins = "gpio18", "gpio19"; 764 function = "gpio"; 765 drive-strength = <2>; 766 bias-disable; 767 }; 768 769 blsp1_spi3_default: blsp1-spi3-default-state { 770 cs-pins { 771 pins = "gpio10"; 772 function = "blsp_spi3"; 773 drive-strength = <2>; 774 bias-disable; 775 }; 776 777 spi-pins { 778 pins = "gpio8", "gpio9", "gpio11"; 779 function = "blsp_spi3"; 780 drive-strength = <12>; 781 bias-disable; 782 }; 783 }; 784 785 blsp1_spi3_sleep: blsp1-spi3-sleep-state { 786 cs-pins { 787 pins = "gpio10"; 788 function = "gpio"; 789 drive-strength = <2>; 790 bias-disable; 791 }; 792 793 spi-pins { 794 pins = "gpio8", "gpio9", "gpio11"; 795 function = "gpio"; 796 drive-strength = <2>; 797 bias-pull-down; 798 }; 799 }; 800 801 blsp2_spi2_default: blsp2-spi2-default-state { 802 cs0-pins { 803 pins = "gpio47"; 804 function = "blsp_spi6"; 805 drive-strength = <16>; 806 bias-disable; 807 }; 808 809 cs1-pins { 810 pins = "gpio22"; 811 function = "blsp_spi6"; 812 drive-strength = <16>; 813 bias-disable; 814 }; 815 816 spi-pins { 817 pins = "gpio20", "gpio21", "gpio23"; 818 function = "blsp_spi6"; 819 drive-strength = <16>; 820 bias-disable; 821 }; 822 }; 823 824 blsp2_spi2_sleep: blsp2-spi2-sleep-state { 825 cs0-pins { 826 pins = "gpio47"; 827 function = "gpio"; 828 drive-strength = <2>; 829 bias-disable; 830 }; 831 832 cs1-pins { 833 pins = "gpio22"; 834 function = "gpio"; 835 drive-strength = <2>; 836 bias-disable; 837 }; 838 839 spi-pins { 840 pins = "gpio20", "gpio21", "gpio23"; 841 function = "gpio"; 842 drive-strength = <2>; 843 bias-pull-down; 844 }; 845 }; 846 847 blsp1_uart1_default: blsp1-uart1-default-state { 848 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 849 function = "blsp_uart1"; 850 drive-strength = <2>; 851 bias-disable; 852 }; 853 854 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 855 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 856 function = "gpio"; 857 drive-strength = <2>; 858 bias-disable; 859 }; 860 861 blsp1_uart2_default: blsp1-uart2-default-state { 862 pins = "gpio4", "gpio5"; 863 function = "blsp_uart2"; 864 drive-strength = <2>; 865 bias-disable; 866 }; 867 868 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 869 pins = "gpio4", "gpio5"; 870 function = "gpio"; 871 drive-strength = <2>; 872 bias-pull-down; 873 }; 874 875 sdc1_default: sdc1-default-state { 876 clk-pins { 877 pins = "sdc1_clk"; 878 drive-strength = <16>; 879 bias-disable; 880 }; 881 882 cmd-pins { 883 pins = "sdc1_cmd"; 884 drive-strength = <10>; 885 bias-pull-up; 886 }; 887 888 data-pins { 889 pins = "sdc1_data"; 890 drive-strength = <10>; 891 bias-pull-up; 892 }; 893 894 rclk-pins { 895 pins = "sdc1_rclk"; 896 bias-pull-down; 897 }; 898 }; 899 900 sdc1_sleep: sdc1-sleep-state { 901 clk-pins { 902 pins = "sdc1_clk"; 903 drive-strength = <2>; 904 bias-disable; 905 }; 906 907 cmd-pins { 908 pins = "sdc1_cmd"; 909 drive-strength = <2>; 910 bias-pull-up; 911 }; 912 913 data-pins { 914 pins = "sdc1_data"; 915 drive-strength = <2>; 916 bias-pull-up; 917 }; 918 919 rclk-pins { 920 pins = "sdc1_rclk"; 921 bias-pull-down; 922 }; 923 }; 924 925 sdc2_default: sdc2-default-state { 926 clk-pins { 927 pins = "sdc2_clk"; 928 drive-strength = <16>; 929 bias-disable; 930 }; 931 932 sdc2_cmd_default: cmd-pins { 933 pins = "sdc2_cmd"; 934 drive-strength = <16>; 935 bias-pull-up; 936 }; 937 938 sdc2_data_default: data-pins { 939 pins = "sdc2_data"; 940 drive-strength = <16>; 941 bias-pull-up; 942 }; 943 }; 944 945 sdc2_sleep: sdc2-sleep-state { 946 clk-pins { 947 pins = "sdc2_clk"; 948 drive-strength = <2>; 949 bias-disable; 950 }; 951 952 cmd-pins { 953 pins = "sdc2_cmd"; 954 drive-strength = <2>; 955 bias-pull-up; 956 }; 957 958 data-pins { 959 pins = "sdc2_data"; 960 drive-strength = <2>; 961 bias-pull-up; 962 }; 963 }; 964 965 wcnss_pin_a: wcnss-active-state { 966 wcss-wlan-pins { 967 pins = "gpio79", "gpio80"; 968 function = "wcss_wlan"; 969 drive-strength = <6>; 970 bias-pull-up; 971 972 }; 973 974 wcss-wlan0-pins { 975 pins = "gpio78"; 976 function = "wcss_wlan0"; 977 drive-strength = <6>; 978 bias-pull-up; 979 980 }; 981 982 wcss-wlan1-pins { 983 pins = "gpio77"; 984 function = "wcss_wlan1"; 985 drive-strength = <6>; 986 bias-pull-up; 987 988 }; 989 990 wcss-wlan2-pins { 991 pins = "gpio76"; 992 function = "wcss_wlan2"; 993 drive-strength = <6>; 994 bias-pull-up; 995 996 }; 997 }; 998 }; 999 1000 gcc: clock-controller@1800000 { 1001 compatible = "qcom,gcc-msm8937"; 1002 reg = <0x01800000 0x80000>; 1003 #clock-cells = <1>; 1004 #reset-cells = <1>; 1005 #power-domain-cells = <1>; 1006 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 1007 <&sleep_clk>, 1008 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 1009 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1010 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>, 1011 <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>; 1012 clock-names = "xo", 1013 "sleep", 1014 "dsi0pll", 1015 "dsi0pllbyte", 1016 "dsi1pll", 1017 "dsi1pllbyte"; 1018 }; 1019 1020 tcsr_mutex: hwlock@1905000 { 1021 compatible = "qcom,tcsr-mutex"; 1022 reg = <0x01905000 0x20000>; 1023 #hwlock-cells = <1>; 1024 }; 1025 1026 tcsr: syscon@1937000 { 1027 compatible = "qcom,tcsr-msm8937", "syscon"; 1028 reg = <0x01937000 0x30000>; 1029 }; 1030 1031 mdss: display-subsystem@1a00000 { 1032 compatible = "qcom,mdss"; 1033 reg = <0x01a00000 0x1000>, 1034 <0x01ab0000 0x3000>; 1035 reg-names = "mdss_phys", 1036 "vbif_phys"; 1037 ranges; 1038 1039 power-domains = <&gcc MDSS_GDSC>; 1040 1041 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1042 <&gcc GCC_MDSS_AXI_CLK>, 1043 <&gcc GCC_MDSS_VSYNC_CLK>; 1044 clock-names = "iface", 1045 "bus", 1046 "vsync"; 1047 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1048 1049 interrupt-controller; 1050 #interrupt-cells = <1>; 1051 1052 #address-cells = <1>; 1053 #size-cells = <1>; 1054 1055 status = "disabled"; 1056 1057 mdp: display-controller@1a01000 { 1058 compatible = "qcom,msm8937-mdp5", "qcom,mdp5"; 1059 reg = <0x01a01000 0x89000>; 1060 reg-names = "mdp_phys"; 1061 1062 interrupt-parent = <&mdss>; 1063 interrupts = <0>; 1064 1065 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1066 <&gcc GCC_MDSS_AXI_CLK>, 1067 <&gcc GCC_MDSS_MDP_CLK>, 1068 <&gcc GCC_MDSS_VSYNC_CLK>; 1069 clock-names = "iface", 1070 "bus", 1071 "core", 1072 "vsync"; 1073 1074 iommus = <&apps_iommu 0x15>; 1075 1076 ports { 1077 #address-cells = <1>; 1078 #size-cells = <0>; 1079 1080 port@0 { 1081 reg = <0>; 1082 mdp5_intf1_out: endpoint { 1083 remote-endpoint = <&mdss_dsi0_in>; 1084 }; 1085 }; 1086 1087 port@1 { 1088 reg = <1>; 1089 mdp5_intf2_out: endpoint { 1090 remote-endpoint = <&mdss_dsi1_in>; 1091 }; 1092 }; 1093 }; 1094 }; 1095 1096 mdss_dsi0: dsi@1a94000 { 1097 compatible = "qcom,mdss-dsi-ctrl"; 1098 reg = <0x01a94000 0x300>; 1099 reg-names = "dsi_ctrl"; 1100 1101 interrupt-parent = <&mdss>; 1102 interrupts = <4>; 1103 1104 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1105 <&gcc PCLK0_CLK_SRC>; 1106 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1107 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1108 1109 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1110 <&gcc GCC_MDSS_AHB_CLK>, 1111 <&gcc GCC_MDSS_AXI_CLK>, 1112 <&gcc GCC_MDSS_BYTE0_CLK>, 1113 <&gcc GCC_MDSS_PCLK0_CLK>, 1114 <&gcc GCC_MDSS_ESC0_CLK>; 1115 clock-names = "mdp_core", 1116 "iface", 1117 "bus", 1118 "byte", 1119 "pixel", 1120 "core"; 1121 phys = <&mdss_dsi0_phy>; 1122 1123 operating-points-v2 = <&mdss_dsi0_opp_table>; 1124 power-domains = <&rpmpd MSM8937_VDDCX>; 1125 1126 #address-cells = <1>; 1127 #size-cells = <0>; 1128 1129 status = "disabled"; 1130 1131 ports { 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 1135 port@0 { 1136 reg = <0>; 1137 mdss_dsi0_in: endpoint { 1138 remote-endpoint = <&mdp5_intf1_out>; 1139 }; 1140 }; 1141 1142 port@1 { 1143 reg = <1>; 1144 mdss_dsi0_out: endpoint { 1145 }; 1146 }; 1147 }; 1148 1149 mdss_dsi0_opp_table: opp-table { 1150 compatible = "operating-points-v2"; 1151 1152 opp-125000000 { 1153 opp-hz = /bits/ 64 <125000000>; 1154 required-opps = <&rpmpd_opp_svs>; 1155 }; 1156 1157 opp-187500000 { 1158 opp-hz = /bits/ 64 <187500000>; 1159 required-opps = <&rpmpd_opp_nom>; 1160 }; 1161 }; 1162 }; 1163 1164 mdss_dsi0_phy: phy@1a94400 { 1165 compatible = "qcom,dsi-phy-28nm-8937"; 1166 reg = <0x01a94a00 0xd4>, 1167 <0x01a94400 0x280>, 1168 <0x01a94b80 0x30>; 1169 reg-names = "dsi_pll", 1170 "dsi_phy", 1171 "dsi_phy_regulator"; 1172 1173 #clock-cells = <1>; 1174 #phy-cells = <0>; 1175 1176 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1177 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1178 clock-names = "iface", 1179 "ref"; 1180 1181 status = "disabled"; 1182 }; 1183 1184 mdss_dsi1: dsi@1a96000 { 1185 compatible = "qcom,mdss-dsi-ctrl"; 1186 reg = <0x01a96000 0x300>; 1187 reg-names = "dsi_ctrl"; 1188 1189 interrupt-parent = <&mdss>; 1190 interrupts = <4>; 1191 1192 assigned-clocks = <&gcc MSM8937_BYTE1_CLK_SRC>, 1193 <&gcc MSM8937_PCLK1_CLK_SRC>; 1194 assigned-clock-parents = <&mdss_dsi1_phy DSI_BYTE_PLL_CLK>, 1195 <&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>; 1196 1197 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1198 <&gcc GCC_MDSS_AHB_CLK>, 1199 <&gcc GCC_MDSS_AXI_CLK>, 1200 <&gcc MSM8937_GCC_MDSS_BYTE1_CLK>, 1201 <&gcc MSM8937_GCC_MDSS_PCLK1_CLK>, 1202 <&gcc MSM8937_GCC_MDSS_ESC1_CLK>; 1203 clock-names = "mdp_core", 1204 "iface", 1205 "bus", 1206 "byte", 1207 "pixel", 1208 "core"; 1209 phys = <&mdss_dsi1_phy>; 1210 1211 operating-points-v2 = <&mdss_dsi1_opp_table>; 1212 power-domains = <&rpmpd MSM8937_VDDCX>; 1213 1214 #address-cells = <1>; 1215 #size-cells = <0>; 1216 1217 status = "disabled"; 1218 1219 ports { 1220 #address-cells = <1>; 1221 #size-cells = <0>; 1222 1223 port@0 { 1224 reg = <0>; 1225 mdss_dsi1_in: endpoint { 1226 remote-endpoint = <&mdp5_intf2_out>; 1227 }; 1228 }; 1229 1230 port@1 { 1231 reg = <1>; 1232 mdss_dsi1_out: endpoint { 1233 }; 1234 }; 1235 }; 1236 1237 mdss_dsi1_opp_table: opp-table { 1238 compatible = "operating-points-v2"; 1239 1240 opp-125000000 { 1241 opp-hz = /bits/ 64 <125000000>; 1242 required-opps = <&rpmpd_opp_svs>; 1243 }; 1244 1245 opp-187500000 { 1246 opp-hz = /bits/ 64 <187500000>; 1247 required-opps = <&rpmpd_opp_nom>; 1248 }; 1249 }; 1250 }; 1251 1252 mdss_dsi1_phy: phy@1a96a00 { 1253 compatible = "qcom,dsi-phy-28nm-8937"; 1254 reg = <0x01a96a00 0xd4>, 1255 <0x01a96400 0x280>, 1256 <0x01a94b80 0x30>; 1257 reg-names = "dsi_pll", 1258 "dsi_phy", 1259 "dsi_phy_regulator"; 1260 1261 #clock-cells = <1>; 1262 #phy-cells = <0>; 1263 1264 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1265 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1266 clock-names = "iface", 1267 "ref"; 1268 1269 status = "disabled"; 1270 }; 1271 }; 1272 1273 gpu: gpu@1c00000 { 1274 compatible = "qcom,adreno-505.0", "qcom,adreno"; 1275 reg = <0x01c00000 0x40000>; 1276 reg-names = "kgsl_3d0_reg_memory"; 1277 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1278 interrupt-names = "kgsl_3d0_irq"; 1279 #cooling-cells = <2>; 1280 clocks = <&gcc GCC_OXILI_GFX3D_CLK>, 1281 <&gcc GCC_OXILI_AHB_CLK>, 1282 <&gcc GCC_BIMC_GFX_CLK>, 1283 <&gcc GCC_BIMC_GPU_CLK>, 1284 <&gcc MSM8937_GCC_OXILI_TIMER_CLK>, 1285 <&gcc MSM8937_GCC_OXILI_AON_CLK>; 1286 clock-names = "core", 1287 "iface", 1288 "mem_iface", 1289 "alt_mem_iface", 1290 "rbbmtimer", 1291 "alwayson"; 1292 operating-points-v2 = <&gpu_opp_table>; 1293 power-domains = <&gcc OXILI_GX_GDSC>; 1294 1295 iommus = <&adreno_smmu 0>; 1296 1297 nvmem-cells = <&gpu_speed_bin>; 1298 nvmem-cell-names = "speed_bin"; 1299 1300 status = "disabled"; 1301 1302 gpu_opp_table: opp-table { 1303 compatible = "operating-points-v2"; 1304 1305 opp-19200000 { 1306 opp-hz = /bits/ 64 <19200000>; 1307 opp-supported-hw = <0xff>; 1308 required-opps = <&rpmpd_opp_min_svs>; 1309 }; 1310 1311 opp-216000000 { 1312 opp-hz = /bits/ 64 <216000000>; 1313 opp-supported-hw = <0xff>; 1314 required-opps = <&rpmpd_opp_svs>; 1315 }; 1316 1317 opp-300000000 { 1318 opp-hz = /bits/ 64 <300000000>; 1319 opp-supported-hw = <0xff>; 1320 required-opps = <&rpmpd_opp_svs_plus>; 1321 }; 1322 1323 opp-375000000 { 1324 opp-hz = /bits/ 64 <375000000>; 1325 opp-supported-hw = <0xff>; 1326 required-opps = <&rpmpd_opp_nom>; 1327 }; 1328 1329 opp-400000000 { 1330 opp-hz = /bits/ 64 <400000000>; 1331 opp-supported-hw = <0xff>; 1332 required-opps = <&rpmpd_opp_nom_plus>; 1333 }; 1334 1335 opp-450000000 { 1336 opp-hz = /bits/ 64 <450000000>; 1337 opp-supported-hw = <0xff>; 1338 required-opps = <&rpmpd_opp_turbo>; 1339 }; 1340 }; 1341 }; 1342 1343 adreno_smmu: iommu@1c40000 { 1344 compatible = "qcom,msm8996-smmu-v2", 1345 "qcom,adreno-smmu", 1346 "qcom,smmu-v2"; 1347 reg = <0x01c40000 0x10000>; 1348 1349 #global-interrupts = <1>; 1350 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1351 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1352 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 1353 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 1355 #iommu-cells = <1>; 1356 1357 clocks = <&gcc GCC_BIMC_GFX_CLK>, 1358 <&gcc GCC_OXILI_AHB_CLK>; 1359 clock-names = "bus", 1360 "iface"; 1361 1362 power-domains = <&gcc MSM8937_OXILI_CX_GDSC>; 1363 }; 1364 1365 apps_iommu: iommu@1e20000 { 1366 compatible = "qcom,msm8937-iommu", "qcom,msm-iommu-v1"; 1367 ranges = <0 0x01e20000 0x20000>; 1368 1369 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1370 <&gcc GCC_APSS_TCU_CLK>; 1371 clock-names = "iface", 1372 "bus"; 1373 1374 qcom,iommu-secure-id = <17>; 1375 1376 #address-cells = <1>; 1377 #iommu-cells = <1>; 1378 #size-cells = <1>; 1379 1380 /* VFE */ 1381 iommu-ctx@14000 { 1382 compatible = "qcom,msm-iommu-v1-ns"; 1383 reg = <0x14000 0x1000>; 1384 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1385 }; 1386 1387 /* MDP_0 */ 1388 iommu-ctx@15000 { 1389 compatible = "qcom,msm-iommu-v1-ns"; 1390 reg = <0x15000 0x1000>; 1391 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1392 }; 1393 1394 /* VENUS_NS */ 1395 iommu-ctx@16000 { 1396 compatible = "qcom,msm-iommu-v1-ns"; 1397 reg = <0x16000 0x1000>; 1398 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1399 }; 1400 }; 1401 1402 spmi_bus: spmi@200f000 { 1403 compatible = "qcom,spmi-pmic-arb"; 1404 reg = <0x0200f000 0x001000>, 1405 <0x02400000 0x800000>, 1406 <0x02c00000 0x800000>, 1407 <0x03800000 0x200000>, 1408 <0x0200a000 0x002100>; 1409 reg-names = "core", 1410 "chnls", 1411 "obsrvr", 1412 "intr", 1413 "cnfg"; 1414 interrupt-names = "periph_irq"; 1415 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1416 qcom,ee = <0>; 1417 qcom,channel = <0>; 1418 #address-cells = <2>; 1419 #size-cells = <0>; 1420 interrupt-controller; 1421 #interrupt-cells = <4>; 1422 }; 1423 1424 bam_dmux_dma: dma-controller@4044000 { 1425 compatible = "qcom,bam-v1.7.0"; 1426 reg = <0x04044000 0x19000>; 1427 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1428 #dma-cells = <1>; 1429 qcom,ee = <0>; 1430 1431 num-channels = <6>; 1432 qcom,num-ees = <1>; 1433 qcom,powered-remotely; 1434 1435 status = "disabled"; 1436 }; 1437 1438 sdhc_1: mmc@7824900 { 1439 compatible = "qcom,sdhci-msm-v4"; 1440 reg = <0x07824900 0x500>, 1441 <0x07824000 0x800>; 1442 reg-names = "hc", 1443 "core"; 1444 1445 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1446 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1447 interrupt-names = "hc_irq", 1448 "pwr_irq"; 1449 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1450 <&gcc GCC_SDCC1_APPS_CLK>, 1451 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1452 clock-names = "iface", 1453 "core", 1454 "xo"; 1455 pinctrl-0 = <&sdc1_default>; 1456 pinctrl-1 = <&sdc1_sleep>; 1457 pinctrl-names = "default", 1458 "sleep"; 1459 power-domains = <&rpmpd MSM8937_VDDCX>; 1460 mmc-hs200-1_8v; 1461 mmc-hs400-1_8v; 1462 mmc-ddr-1_8v; 1463 bus-width = <8>; 1464 non-removable; 1465 status = "disabled"; 1466 }; 1467 1468 sdhc_2: mmc@7864900 { 1469 compatible = "qcom,sdhci-msm-v4"; 1470 reg = <0x07864900 0x500>, 1471 <0x07864000 0x800>; 1472 reg-names = "hc", 1473 "core"; 1474 1475 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1476 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1477 interrupt-names = "hc_irq", 1478 "pwr_irq"; 1479 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1480 <&gcc GCC_SDCC2_APPS_CLK>, 1481 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1482 clock-names = "iface", 1483 "core", 1484 "xo"; 1485 pinctrl-0 = <&sdc2_default>; 1486 pinctrl-1 = <&sdc2_sleep>; 1487 pinctrl-names = "default", 1488 "sleep"; 1489 power-domains = <&rpmpd MSM8937_VDDCX>; 1490 bus-width = <4>; 1491 status = "disabled"; 1492 }; 1493 1494 blsp1_dma: dma-controller@7884000 { 1495 compatible = "qcom,bam-v1.7.0"; 1496 reg = <0x07884000 0x1f000>; 1497 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1498 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1499 clock-names = "bam_clk"; 1500 qcom,controlled-remotely; 1501 #dma-cells = <1>; 1502 num-channels = <12>; 1503 qcom,num-ees = <4>; 1504 qcom,ee = <0>; 1505 }; 1506 1507 blsp1_uart2: serial@78b0000 { 1508 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1509 reg = <0x078b0000 0x200>; 1510 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1511 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1512 <&gcc GCC_BLSP1_AHB_CLK>; 1513 clock-names = "core", 1514 "iface"; 1515 dmas = <&blsp1_dma 2>, 1516 <&blsp1_dma 3>; 1517 dma-names = "tx", 1518 "rx"; 1519 pinctrl-0 = <&blsp1_uart2_default>; 1520 pinctrl-1 = <&blsp1_uart2_sleep>; 1521 pinctrl-names = "default", 1522 "sleep"; 1523 status = "disabled"; 1524 }; 1525 1526 blsp1_i2c2: i2c@78b6000 { 1527 compatible = "qcom,i2c-qup-v2.2.1"; 1528 reg = <0x078b6000 0x600>; 1529 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1530 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1531 <&gcc GCC_BLSP1_AHB_CLK>; 1532 clock-names = "core", "iface"; 1533 dmas = <&blsp1_dma 6>, 1534 <&blsp1_dma 7>; 1535 dma-names = "tx", 1536 "rx"; 1537 pinctrl-0 = <&blsp1_i2c2_default>; 1538 pinctrl-1 = <&blsp1_i2c2_sleep>; 1539 pinctrl-names = "default", 1540 "sleep"; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 status = "disabled"; 1544 }; 1545 1546 blsp1_i2c3: i2c@78b7000 { 1547 compatible = "qcom,i2c-qup-v2.2.1"; 1548 reg = <0x078b7000 0x600>; 1549 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1550 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1551 <&gcc GCC_BLSP1_AHB_CLK>; 1552 clock-names = "core", 1553 "iface"; 1554 dmas = <&blsp1_dma 8>, 1555 <&blsp1_dma 9>; 1556 dma-names = "tx", 1557 "rx"; 1558 pinctrl-0 = <&blsp1_i2c3_default>; 1559 pinctrl-1 = <&blsp1_i2c3_sleep>; 1560 pinctrl-names = "default", 1561 "sleep"; 1562 #address-cells = <1>; 1563 #size-cells = <0>; 1564 status = "disabled"; 1565 }; 1566 1567 blsp1_spi3: spi@78b7000 { 1568 compatible = "qcom,spi-qup-v2.2.1"; 1569 reg = <0x078b7000 0x600>; 1570 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1571 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1572 <&gcc GCC_BLSP1_AHB_CLK>; 1573 clock-names = "core", 1574 "iface"; 1575 dmas = <&blsp1_dma 8>, 1576 <&blsp1_dma 9>; 1577 dma-names = "tx", 1578 "rx"; 1579 pinctrl-0 = <&blsp1_spi3_default>; 1580 pinctrl-1 = <&blsp1_spi3_sleep>; 1581 pinctrl-names = "default", 1582 "sleep"; 1583 #address-cells = <1>; 1584 #size-cells = <0>; 1585 status = "disabled"; 1586 }; 1587 1588 blsp1_i2c4: i2c@78b8000 { 1589 compatible = "qcom,i2c-qup-v2.2.1"; 1590 reg = <0x078b8000 0x500>; 1591 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1592 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1593 <&gcc GCC_BLSP1_AHB_CLK>; 1594 clock-names = "core", 1595 "iface"; 1596 dmas = <&blsp1_dma 10>, 1597 <&blsp1_dma 11>; 1598 dma-names = "tx", 1599 "rx"; 1600 pinctrl-0 = <&blsp1_i2c4_default>; 1601 pinctrl-1 = <&blsp1_i2c4_sleep>; 1602 pinctrl-names = "default", 1603 "sleep"; 1604 #address-cells = <1>; 1605 #size-cells = <0>; 1606 status = "disabled"; 1607 }; 1608 1609 blsp2_dma: dma-controller@7ac4000 { 1610 compatible = "qcom,bam-v1.7.0"; 1611 reg = <0x07ac4000 0x1d000>; 1612 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1613 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1614 clock-names = "bam_clk"; 1615 qcom,controlled-remotely; 1616 #dma-cells = <1>; 1617 num-channels = <10>; 1618 qcom,num-ees = <4>; 1619 qcom,ee = <0>; 1620 }; 1621 1622 blsp2_i2c1: i2c@7af5000 { 1623 compatible = "qcom,i2c-qup-v2.2.1"; 1624 reg = <0x07af5000 0x600>; 1625 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1626 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1627 <&gcc GCC_BLSP2_AHB_CLK>; 1628 clock-names = "core", 1629 "iface"; 1630 dmas = <&blsp2_dma 4>, 1631 <&blsp2_dma 5>; 1632 dma-names = "tx", 1633 "rx"; 1634 pinctrl-0 = <&blsp2_i2c1_default>; 1635 pinctrl-1 = <&blsp2_i2c1_sleep>; 1636 pinctrl-names = "default", 1637 "sleep"; 1638 #address-cells = <1>; 1639 #size-cells = <0>; 1640 status = "disabled"; 1641 }; 1642 1643 blsp2_spi2: spi@7af6000 { 1644 compatible = "qcom,spi-qup-v2.2.1"; 1645 reg = <0x07af6000 0x600>; 1646 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1647 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 1648 <&gcc GCC_BLSP2_AHB_CLK>; 1649 clock-names = "core", 1650 "iface"; 1651 dmas = <&blsp2_dma 6>, 1652 <&blsp2_dma 7>; 1653 dma-names = "tx", 1654 "rx"; 1655 pinctrl-0 = <&blsp2_spi2_default>; 1656 pinctrl-1 = <&blsp2_spi2_sleep>; 1657 pinctrl-names = "default", 1658 "sleep"; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 status = "disabled"; 1662 }; 1663 1664 usb: usb@78db000 { 1665 compatible = "qcom,ci-hdrc"; 1666 reg = <0x078db000 0x200>, 1667 <0x078db200 0x200>; 1668 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1669 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1670 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1671 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1672 clock-names = "iface", 1673 "core"; 1674 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1675 assigned-clock-rates = <80000000>; 1676 resets = <&gcc GCC_USB_HS_BCR>; 1677 reset-names = "core"; 1678 phy_type = "ulpi"; 1679 dr_mode = "otg"; 1680 hnp-disable; 1681 srp-disable; 1682 adp-disable; 1683 ahb-burst-config = <0>; 1684 phy-names = "usb-phy"; 1685 phys = <&usb_hs_phy>; 1686 status = "disabled"; 1687 #reset-cells = <1>; 1688 }; 1689 1690 wcnss: remoteproc@a204000 { 1691 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1692 reg = <0x0a204000 0x2000>, 1693 <0x0a202000 0x1000>, 1694 <0x0a21b000 0x3000>; 1695 reg-names = "ccu", 1696 "dxe", 1697 "pmu"; 1698 1699 memory-region = <&wcnss_mem>; 1700 1701 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1702 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1703 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1704 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1705 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1706 interrupt-names = "wdog", 1707 "fatal", 1708 "ready", 1709 "handover", 1710 "stop-ack"; 1711 1712 power-domains = <&rpmpd MSM8937_VDDCX>, 1713 <&rpmpd MSM8937_VDDMX>; 1714 power-domain-names = "cx", 1715 "mx"; 1716 1717 qcom,smem-states = <&wcnss_smp2p_out 0>; 1718 qcom,smem-state-names = "stop"; 1719 1720 pinctrl-0 = <&wcnss_pin_a>; 1721 pinctrl-names = "default"; 1722 1723 status = "disabled"; 1724 1725 wcnss_iris: iris { 1726 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1727 clock-names = "xo"; 1728 }; 1729 1730 smd-edge { 1731 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1732 1733 mboxes = <&apcs1 17>; 1734 qcom,smd-edge = <6>; 1735 qcom,remote-pid = <4>; 1736 1737 label = "pronto"; 1738 1739 wcnss_ctrl: wcnss { 1740 compatible = "qcom,wcnss"; 1741 qcom,smd-channels = "WCNSS_CTRL"; 1742 1743 qcom,mmio = <&wcnss>; 1744 1745 wcnss_bt: bluetooth { 1746 compatible = "qcom,wcnss-bt"; 1747 }; 1748 1749 wcnss_wifi: wifi { 1750 compatible = "qcom,wcnss-wlan"; 1751 1752 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1753 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1754 interrupt-names = "tx", 1755 "rx"; 1756 1757 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1758 qcom,smem-state-names = "tx-enable", 1759 "tx-rings-empty"; 1760 }; 1761 }; 1762 }; 1763 }; 1764 1765 intc: interrupt-controller@b000000 { 1766 compatible = "qcom,msm-qgic2"; 1767 interrupt-controller; 1768 #interrupt-cells = <3>; 1769 reg = <0x0b000000 0x1000>, 1770 <0x0b002000 0x1000>; 1771 }; 1772 1773 apcs1: mailbox@b011000 { 1774 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 1775 reg = <0x0b011000 0x1000>; 1776 #mbox-cells = <1>; 1777 }; 1778 1779 watchdog@b017000 { 1780 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1781 reg = <0x0b017000 0x1000>; 1782 clocks = <&sleep_clk>; 1783 }; 1784 1785 timer@b120000 { 1786 compatible = "arm,armv7-timer-mem"; 1787 reg = <0x0b120000 0x1000>; 1788 ranges; 1789 #address-cells = <1>; 1790 #size-cells = <1>; 1791 1792 frame@b121000 { 1793 reg = <0x0b121000 0x1000>, 1794 <0x0b122000 0x1000>; 1795 frame-number = <0>; 1796 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1797 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1798 }; 1799 1800 frame@b123000 { 1801 reg = <0x0b123000 0x1000>; 1802 frame-number = <1>; 1803 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1804 status = "disabled"; 1805 }; 1806 1807 frame@b124000 { 1808 reg = <0x0b124000 0x1000>; 1809 frame-number = <2>; 1810 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1811 status = "disabled"; 1812 }; 1813 1814 frame@b125000 { 1815 reg = <0x0b125000 0x1000>; 1816 frame-number = <3>; 1817 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1818 status = "disabled"; 1819 }; 1820 1821 frame@b126000 { 1822 reg = <0x0b126000 0x1000>; 1823 frame-number = <4>; 1824 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1825 status = "disabled"; 1826 }; 1827 1828 frame@b127000 { 1829 reg = <0x0b127000 0x1000>; 1830 frame-number = <5>; 1831 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1832 status = "disabled"; 1833 }; 1834 1835 frame@b128000 { 1836 reg = <0x0b128000 0x1000>; 1837 frame-number = <6>; 1838 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1839 status = "disabled"; 1840 }; 1841 }; 1842 }; 1843 1844 thermal_zones: thermal-zones { 1845 aoss-thermal { 1846 thermal-sensors = <&tsens 0>; 1847 1848 trips { 1849 aoss_alert0: trip-point0 { 1850 temperature = <85000>; 1851 hysteresis = <2000>; 1852 type = "critical"; 1853 }; 1854 }; 1855 }; 1856 1857 mdm-core-thermal { 1858 thermal-sensors = <&tsens 1>; 1859 1860 trips { 1861 mdm_core_alert0: trip-point0 { 1862 temperature = <85000>; 1863 hysteresis = <2000>; 1864 type = "critical"; 1865 }; 1866 }; 1867 }; 1868 1869 q6-thermal { 1870 thermal-sensors = <&tsens 2>; 1871 1872 trips { 1873 q6_alert0: trip-point0 { 1874 temperature = <85000>; 1875 hysteresis = <2000>; 1876 type = "critical"; 1877 }; 1878 }; 1879 }; 1880 1881 camera-thermal { 1882 thermal-sensors = <&tsens 3>; 1883 1884 trips { 1885 camera_alert0: trip-point0 { 1886 temperature = <85000>; 1887 hysteresis = <2000>; 1888 type = "critical"; 1889 }; 1890 }; 1891 }; 1892 1893 cpuss1-thermal { 1894 thermal-sensors = <&tsens 4>; 1895 1896 cooling-maps { 1897 map0 { 1898 trip = <&cpuss1_alert0>; 1899 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1900 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1901 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1902 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1903 }; 1904 }; 1905 1906 trips { 1907 cpuss1_alert0: trip-point0 { 1908 temperature = <75000>; 1909 hysteresis = <2000>; 1910 type = "passive"; 1911 }; 1912 1913 cpuss1_alert1: trip-point1 { 1914 temperature = <85000>; 1915 hysteresis = <2000>; 1916 type = "hot"; 1917 }; 1918 1919 cpuss1_crit: cpuss1-crit { 1920 temperature = <100000>; 1921 hysteresis = <2000>; 1922 type = "critical"; 1923 }; 1924 }; 1925 }; 1926 1927 cpu4-thermal { 1928 thermal-sensors = <&tsens 5>; 1929 1930 cooling-maps { 1931 map0 { 1932 trip = <&cpu4_alert1>; 1933 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1934 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1935 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1936 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1937 }; 1938 }; 1939 1940 trips { 1941 cpu4_alert0: trip-point0 { 1942 temperature = <75000>; 1943 hysteresis = <2000>; 1944 type = "passive"; 1945 }; 1946 1947 cpu4_alert1: trip-point1 { 1948 temperature = <85000>; 1949 hysteresis = <2000>; 1950 type = "hot"; 1951 }; 1952 1953 cpu4_crit: cpu-crit { 1954 temperature = <100000>; 1955 hysteresis = <2000>; 1956 type = "critical"; 1957 }; 1958 }; 1959 }; 1960 1961 cpu5-thermal { 1962 thermal-sensors = <&tsens 6>; 1963 1964 cooling-maps { 1965 map0 { 1966 trip = <&cpu5_alert1>; 1967 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1968 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1969 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1970 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1971 }; 1972 }; 1973 1974 trips { 1975 cpu5_alert0: trip-point0 { 1976 temperature = <75000>; 1977 hysteresis = <2000>; 1978 type = "hot"; 1979 }; 1980 1981 cpu5_alert1: trip-point1 { 1982 temperature = <85000>; 1983 hysteresis = <2000>; 1984 type = "passive"; 1985 }; 1986 1987 cpu5_crit: cpu-crit { 1988 temperature = <100000>; 1989 hysteresis = <2000>; 1990 type = "critical"; 1991 }; 1992 }; 1993 }; 1994 1995 cpu6-thermal { 1996 thermal-sensors = <&tsens 7>; 1997 1998 cooling-maps { 1999 map0 { 2000 trip = <&cpu6_alert1>; 2001 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2002 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2003 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2004 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2005 }; 2006 }; 2007 2008 trips { 2009 cpu6_alert0: trip-point0 { 2010 temperature = <75000>; 2011 hysteresis = <2000>; 2012 type = "hot"; 2013 }; 2014 2015 cpu6_alert1: trip-point1 { 2016 temperature = <85000>; 2017 hysteresis = <2000>; 2018 type = "passive"; 2019 }; 2020 2021 cpu6_crit: cpu-crit { 2022 temperature = <100000>; 2023 hysteresis = <2000>; 2024 type = "critical"; 2025 }; 2026 }; 2027 }; 2028 2029 cpu7-thermal { 2030 thermal-sensors = <&tsens 8>; 2031 2032 cooling-maps { 2033 map0 { 2034 trip = <&cpu7_alert1>; 2035 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2036 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2037 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2038 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2039 }; 2040 }; 2041 2042 trips { 2043 cpu7_alert0: trip-point0 { 2044 temperature = <75000>; 2045 hysteresis = <2000>; 2046 type = "hot"; 2047 }; 2048 2049 cpu7_alert1: trip-point1 { 2050 temperature = <85000>; 2051 hysteresis = <2000>; 2052 type = "passive"; 2053 }; 2054 2055 cpu7_crit: cpu-crit { 2056 temperature = <100000>; 2057 hysteresis = <2000>; 2058 type = "critical"; 2059 }; 2060 }; 2061 }; 2062 2063 cpuss0-thermal { 2064 thermal-sensors = <&tsens 9>; 2065 2066 cooling-maps { 2067 map0 { 2068 trip = <&cpuss0_alert0>; 2069 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2070 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2071 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 2072 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2073 }; 2074 }; 2075 2076 trips { 2077 cpuss0_alert0: trip-point0 { 2078 temperature = <75000>; 2079 hysteresis = <2000>; 2080 type = "passive"; 2081 }; 2082 2083 cpuss0_alert1: trip-point1 { 2084 temperature = <85000>; 2085 hysteresis = <2000>; 2086 type = "hot"; 2087 }; 2088 2089 cpuss0_crit: cpuss0-crit { 2090 temperature = <100000>; 2091 hysteresis = <2000>; 2092 type = "critical"; 2093 }; 2094 }; 2095 }; 2096 2097 gpu-thermal { 2098 polling-delay-passive = <250>; 2099 2100 thermal-sensors = <&tsens 10>; 2101 2102 cooling-maps { 2103 map0 { 2104 trip = <&gpu_alert>; 2105 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 2106 }; 2107 }; 2108 2109 trips { 2110 gpu_alert: trip-point0 { 2111 temperature = <70000>; 2112 hysteresis = <2000>; 2113 type = "passive"; 2114 }; 2115 2116 gpu_crit: gpu-crit { 2117 temperature = <90000>; 2118 hysteresis = <2000>; 2119 type = "critical"; 2120 }; 2121 }; 2122 }; 2123 }; 2124 2125 timer { 2126 compatible = "arm,armv8-timer"; 2127 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2128 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2129 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 2130 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 2131 }; 2132}; 2133
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