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msm8917.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/msm8917.dtsi
1// SPDX-License-Identifier: GPL-2.0-only 2 3#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 4#include <dt-bindings/clock/qcom,gcc-msm8917.h> 5#include <dt-bindings/clock/qcom,rpmcc.h> 6#include <dt-bindings/interrupt-controller/arm-gic.h> 7#include <dt-bindings/power/qcom-rpmpd.h> 8#include <dt-bindings/thermal/thermal.h> 9 10/ { 11 interrupt-parent = <&intc>; 12 13 #address-cells = <2>; 14 #size-cells = <2>; 15 16 chosen { }; 17 18 clocks { 19 sleep_clk: sleep-clk { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 }; 23 24 xo_board: xo-board { 25 compatible = "fixed-clock"; 26 #clock-cells = <0>; 27 }; 28 }; 29 30 cpus { 31 #address-cells = <1>; 32 #size-cells = <0>; 33 34 cpu0: cpu@100 { 35 compatible = "arm,cortex-a53"; 36 reg = <0x100>; 37 device_type = "cpu"; 38 next-level-cache = <&l2_0>; 39 enable-method = "psci"; 40 clocks = <&apcs>; 41 operating-points-v2 = <&cpu_opp_table>; 42 #cooling-cells = <2>; 43 power-domains = <&cpu_pd0>; 44 power-domain-names = "psci"; 45 46 l2_0: l2-cache { 47 compatible = "cache"; 48 cache-level = <2>; 49 cache-unified; 50 }; 51 }; 52 53 cpu1: cpu@101 { 54 compatible = "arm,cortex-a53"; 55 reg = <0x101>; 56 device_type = "cpu"; 57 next-level-cache = <&l2_0>; 58 enable-method = "psci"; 59 clocks = <&apcs>; 60 operating-points-v2 = <&cpu_opp_table>; 61 #cooling-cells = <2>; 62 power-domains = <&cpu_pd1>; 63 power-domain-names = "psci"; 64 }; 65 66 cpu2: cpu@102 { 67 compatible = "arm,cortex-a53"; 68 reg = <0x102>; 69 device_type = "cpu"; 70 next-level-cache = <&l2_0>; 71 enable-method = "psci"; 72 clocks = <&apcs>; 73 operating-points-v2 = <&cpu_opp_table>; 74 #cooling-cells = <2>; 75 power-domains = <&cpu_pd2>; 76 power-domain-names = "psci"; 77 }; 78 79 cpu3: cpu@103 { 80 compatible = "arm,cortex-a53"; 81 reg = <0x103>; 82 device_type = "cpu"; 83 next-level-cache = <&l2_0>; 84 enable-method = "psci"; 85 clocks = <&apcs>; 86 operating-points-v2 = <&cpu_opp_table>; 87 #cooling-cells = <2>; 88 power-domains = <&cpu_pd3>; 89 power-domain-names = "psci"; 90 }; 91 92 cpu-map { 93 cluster0 { 94 core0 { 95 cpu = <&cpu0>; 96 }; 97 98 core1 { 99 cpu = <&cpu1>; 100 }; 101 102 core2 { 103 cpu = <&cpu2>; 104 }; 105 106 core3 { 107 cpu = <&cpu3>; 108 }; 109 }; 110 }; 111 112 domain-idle-states { 113 cluster_sleep_0: cluster-sleep-0 { 114 compatible = "domain-idle-state"; 115 arm,psci-suspend-param = <0x41000053>; 116 entry-latency-us = <700>; 117 exit-latency-us = <1000>; 118 min-residency-us = <6500>; 119 }; 120 }; 121 122 idle-states { 123 entry-method = "psci"; 124 125 cpu_sleep_0: cpu-sleep-0 { 126 compatible = "arm,idle-state"; 127 idle-state-name = "standalone-power-collapse"; 128 arm,psci-suspend-param = <0x40000003>; 129 entry-latency-us = <125>; 130 exit-latency-us = <180>; 131 min-residency-us = <595>; 132 local-timer-stop; 133 }; 134 }; 135 136 cpu_opp_table: opp-table-cpu { 137 compatible = "operating-points-v2"; 138 opp-shared; 139 140 opp-960000000 { 141 opp-hz = /bits/ 64 <960000000>; 142 }; 143 144 opp-1094400000 { 145 opp-hz = /bits/ 64 <1094400000>; 146 }; 147 148 opp-1248000000 { 149 opp-hz = /bits/ 64 <1248000000>; 150 }; 151 152 opp-1401600000 { 153 opp-hz = /bits/ 64 <1401600000>; 154 }; 155 }; 156 }; 157 158 firmware { 159 scm: scm { 160 compatible = "qcom,scm-msm8916", "qcom,scm"; 161 clocks = <&gcc GCC_CRYPTO_CLK>, 162 <&gcc GCC_CRYPTO_AXI_CLK>, 163 <&gcc GCC_CRYPTO_AHB_CLK>; 164 clock-names = "core", "bus", "iface"; 165 #reset-cells = <1>; 166 167 qcom,dload-mode = <&tcsr 0x6100>; 168 }; 169 }; 170 171 memory@80000000 { 172 /* We expect the bootloader to fill in the reg */ 173 reg = <0 0x80000000 0 0>; 174 device_type = "memory"; 175 }; 176 177 pmu { 178 compatible = "arm,cortex-a53-pmu"; 179 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 180 }; 181 182 psci { 183 compatible = "arm,psci-1.0"; 184 method = "smc"; 185 186 cluster_pd: power-domain-cluster { 187 #power-domain-cells = <0>; 188 domain-idle-states = <&cluster_sleep_0>; 189 }; 190 191 cpu_pd0: power-domain-cpu0 { 192 #power-domain-cells = <0>; 193 power-domains = <&cluster_pd>; 194 domain-idle-states = <&cpu_sleep_0>; 195 }; 196 197 cpu_pd1: power-domain-cpu1 { 198 #power-domain-cells = <0>; 199 power-domains = <&cluster_pd>; 200 domain-idle-states = <&cpu_sleep_0>; 201 }; 202 203 cpu_pd2: power-domain-cpu2 { 204 #power-domain-cells = <0>; 205 power-domains = <&cluster_pd>; 206 domain-idle-states = <&cpu_sleep_0>; 207 }; 208 209 cpu_pd3: power-domain-cpu3 { 210 #power-domain-cells = <0>; 211 power-domains = <&cluster_pd>; 212 domain-idle-states = <&cpu_sleep_0>; 213 }; 214 }; 215 216 rpm: remoteproc { 217 compatible = "qcom,msm8917-rpm-proc", "qcom,rpm-proc"; 218 219 smd-edge { 220 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 221 qcom,ipc = <&apcs 8 0>; 222 qcom,smd-edge = <15>; 223 224 rpm_requests: rpm-requests { 225 compatible = "qcom,rpm-msm8917", "qcom,smd-rpm"; 226 qcom,smd-channels = "rpm_requests"; 227 228 rpmcc: clock-controller { 229 compatible = "qcom,rpmcc-msm8917", "qcom,rpmcc"; 230 #clock-cells = <1>; 231 clocks = <&xo_board>; 232 clock-names = "xo"; 233 }; 234 235 rpmpd: power-controller { 236 compatible = "qcom,msm8917-rpmpd"; 237 #power-domain-cells = <1>; 238 operating-points-v2 = <&rpmpd_opp_table>; 239 240 rpmpd_opp_table: opp-table { 241 compatible = "operating-points-v2"; 242 243 rpmpd_opp_ret: opp1 { 244 opp-level = <RPM_SMD_LEVEL_RETENTION>; 245 }; 246 247 rpmpd_opp_ret_plus: opp2 { 248 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>; 249 }; 250 251 rpmpd_opp_min_svs: opp3 { 252 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 253 }; 254 255 rpmpd_opp_low_svs: opp4 { 256 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 257 }; 258 259 rpmpd_opp_svs: opp5 { 260 opp-level = <RPM_SMD_LEVEL_SVS>; 261 }; 262 263 rpmpd_opp_svs_plus: opp6 { 264 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 265 }; 266 267 rpmpd_opp_nom: opp7 { 268 opp-level = <RPM_SMD_LEVEL_NOM>; 269 }; 270 271 rpmpd_opp_nom_plus: opp8 { 272 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 273 }; 274 275 rpmpd_opp_turbo: opp9 { 276 opp-level = <RPM_SMD_LEVEL_TURBO>; 277 }; 278 }; 279 }; 280 }; 281 }; 282 }; 283 284 reserved-memory { 285 ranges; 286 #address-cells = <2>; 287 #size-cells = <2>; 288 289 qseecom_mem: qseecom@85b00000 { 290 reg = <0x0 0x85b00000 0x0 0x800000>; 291 no-map; 292 }; 293 294 smem@86300000 { 295 compatible = "qcom,smem"; 296 reg = <0x0 0x86300000 0x0 0x100000>; 297 no-map; 298 299 hwlocks = <&tcsr_mutex 3>; 300 qcom,rpm-msg-ram = <&rpm_msg_ram>; 301 }; 302 303 reserved@86400000 { 304 reg = <0x0 0x86400000 0x0 0x400000>; 305 no-map; 306 }; 307 308 rmtfs@92100000 { 309 compatible = "qcom,rmtfs-mem"; 310 reg = <0x0 0x92100000 0x0 0x180000>; 311 no-map; 312 313 qcom,client-id = <1>; 314 }; 315 316 adsp_mem: adsp { 317 size = <0x0 0x1100000>; 318 alignment = <0x0 0x100000>; 319 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 320 no-map; 321 status = "disabled"; 322 }; 323 324 mba_mem: mba { 325 size = <0x0 0x100000>; 326 alignment = <0x0 0x100000>; 327 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 328 no-map; 329 status = "disabled"; 330 }; 331 332 venus_mem: venus { 333 size = <0x0 0x400000>; 334 alignment = <0x0 0x100000>; 335 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 336 no-map; 337 status = "disabled"; 338 }; 339 340 wcnss_mem: wcnss { 341 size = <0x0 0x700000>; 342 alignment = <0x0 0x100000>; 343 alloc-ranges = <0x0 0x86800000 0x0 0x8000000>; 344 no-map; 345 status = "disabled"; 346 }; 347 }; 348 349 smp2p-adsp { 350 compatible = "qcom,smp2p"; 351 qcom,smem = <443>, <429>; 352 353 interrupts = <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>; 354 355 mboxes = <&apcs 10>; 356 357 qcom,local-pid = <0>; 358 qcom,remote-pid = <2>; 359 360 adsp_smp2p_out: master-kernel { 361 qcom,entry-name = "master-kernel"; 362 363 #qcom,smem-state-cells = <1>; 364 }; 365 366 adsp_smp2p_in: slave-kernel { 367 qcom,entry-name = "slave-kernel"; 368 369 interrupt-controller; 370 #interrupt-cells = <2>; 371 }; 372 }; 373 374 smp2p-modem { 375 compatible = "qcom,smp2p"; 376 qcom,smem = <435>, <428>; 377 378 interrupts = <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>; 379 380 mboxes = <&apcs 14>; 381 382 qcom,local-pid = <0>; 383 qcom,remote-pid = <1>; 384 385 modem_smp2p_out: master-kernel { 386 qcom,entry-name = "master-kernel"; 387 388 #qcom,smem-state-cells = <1>; 389 }; 390 391 modem_smp2p_in: slave-kernel { 392 qcom,entry-name = "slave-kernel"; 393 394 interrupt-controller; 395 #interrupt-cells = <2>; 396 }; 397 }; 398 399 smp2p-wcnss { 400 compatible = "qcom,smp2p"; 401 qcom,smem = <451>, <431>; 402 403 interrupts = <GIC_SPI 143 IRQ_TYPE_EDGE_RISING>; 404 405 mboxes = <&apcs 18>; 406 407 qcom,local-pid = <0>; 408 qcom,remote-pid = <4>; 409 410 wcnss_smp2p_out: master-kernel { 411 qcom,entry-name = "master-kernel"; 412 413 #qcom,smem-state-cells = <1>; 414 }; 415 416 wcnss_smp2p_in: slave-kernel { 417 qcom,entry-name = "slave-kernel"; 418 419 interrupt-controller; 420 #interrupt-cells = <2>; 421 }; 422 }; 423 424 smsm { 425 compatible = "qcom,smsm"; 426 427 #address-cells = <1>; 428 #size-cells = <0>; 429 430 mboxes = <0>, <&apcs 13>, <0>, <&apcs 19>; 431 432 apps_smsm: apps@0 { 433 reg = <0>; 434 435 #qcom,smem-state-cells = <1>; 436 }; 437 438 hexagon_smsm: hexagon@1 { 439 reg = <1>; 440 interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; 441 442 interrupt-controller; 443 #interrupt-cells = <2>; 444 }; 445 446 wcnss_smsm: wcnss@6 { 447 reg = <6>; 448 interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; 449 450 interrupt-controller; 451 #interrupt-cells = <2>; 452 }; 453 }; 454 455 soc: soc@0 { 456 compatible = "simple-bus"; 457 ranges = <0 0 0 0xffffffff>; 458 #address-cells = <1>; 459 #size-cells = <1>; 460 461 rpm_msg_ram: sram@60000 { 462 compatible = "qcom,rpm-msg-ram"; 463 reg = <0x00060000 0x8000>; 464 }; 465 466 usb_hs_phy: phy@6c000 { 467 compatible = "qcom,usb-hs-28nm-femtophy"; 468 reg = <0x0006c000 0x200>; 469 #phy-cells = <0>; 470 clocks = <&xo_board>, 471 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>, 472 <&gcc GCC_USB2A_PHY_SLEEP_CLK>; 473 clock-names = "ref", "ahb", "sleep"; 474 resets = <&gcc GCC_QUSB2_PHY_BCR>, 475 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>; 476 reset-names = "phy", "por"; 477 status = "disabled"; 478 }; 479 480 qfprom: qfprom@a4000 { 481 compatible = "qcom,msm8917-qfprom", "qcom,qfprom"; 482 reg = <0x000a4000 0x1000>; 483 #address-cells = <1>; 484 #size-cells = <1>; 485 486 tsens_base1: base1@1d8 { 487 reg = <0x1d8 1>; 488 bits = <0 8>; 489 }; 490 491 tsens_s5_p1: s5-p1@1d9 { 492 reg = <0x1d9 1>; 493 bits = <0 6>; 494 }; 495 496 tsens_s5_p2: s5-p2@1d9 { 497 reg = <0x1d9 2>; 498 bits = <6 6>; 499 }; 500 501 tsens_s6_p1: s6-p1@1da { 502 reg = <0x1da 2>; 503 bits = <4 6>; 504 }; 505 506 tsens_s6_p2: s6-p2@1db { 507 reg = <0x1db 1>; 508 bits = <2 6>; 509 }; 510 511 tsens_s7_p1: s7-p1@1dc { 512 reg = <0x1dc 1>; 513 bits = <0 6>; 514 }; 515 516 tsens_s7_p2: s7-p2@1dc { 517 reg = <0x1dc 2>; 518 bits = <6 6>; 519 }; 520 521 tsens_s8_p1: s8-p1@1dd { 522 reg = <0x1dd 2>; 523 bits = <4 6>; 524 }; 525 526 tsens_s8_p2: s8-p2@1de { 527 reg = <0x1de 1>; 528 bits = <2 6>; 529 }; 530 531 tsens_base2: base2@1df { 532 reg = <0x1df 1>; 533 bits = <0 8>; 534 }; 535 536 tsens_mode: mode@210 { 537 reg = <0x210 1>; 538 bits = <0 3>; 539 }; 540 541 tsens_s0_p1: s0-p1@210 { 542 reg = <0x210 2>; 543 bits = <3 6>; 544 }; 545 546 tsens_s0_p2: s0-p2@211 { 547 reg = <0x211 1>; 548 bits = <1 6>; 549 }; 550 551 tsens_s1_p1: s1-p1@211 { 552 reg = <0x211 2>; 553 bits = <7 6>; 554 }; 555 556 tsens_s1_p2: s1-p2@212 { 557 reg = <0x212 2>; 558 bits = <5 6>; 559 }; 560 561 tsens_s2_p1: s2-p1@213 { 562 reg = <0x213 2>; 563 bits = <3 6>; 564 }; 565 566 tsens_s2_p2: s2-p2@214 { 567 reg = <0x214 1>; 568 bits = <1 6>; 569 }; 570 571 tsens_s3_p1: s3-p1@214 { 572 reg = <0x214 2>; 573 bits = <7 6>; 574 }; 575 576 tsens_s3_p2: s3-p2@215 { 577 reg = <0x215 2>; 578 bits = <5 6>; 579 }; 580 581 tsens_s4_p1: s4-p1@216 { 582 reg = <0x216 2>; 583 bits = <3 6>; 584 }; 585 586 tsens_s4_p2: s4-p2@217 { 587 reg = <0x217 1>; 588 bits = <1 6>; 589 }; 590 591 tsens_s9_p1: s9-p1@230 { 592 reg = <0x230 1>; 593 bits = <0 6>; 594 }; 595 596 tsens_s9_p2: s9-p2@230 { 597 reg = <0x230 2>; 598 bits = <6 6>; 599 }; 600 601 tsens_s10_p1: s10-p1@231 { 602 reg = <0x231 2>; 603 bits = <4 6>; 604 }; 605 606 tsens_s10_p2: s10-p2@232 { 607 reg = <0x232 1>; 608 bits = <2 6>; 609 }; 610 }; 611 612 rng@e3000 { 613 compatible = "qcom,prng"; 614 reg = <0x000e3000 0x1000>; 615 clocks = <&gcc GCC_PRNG_AHB_CLK>; 616 clock-names = "core"; 617 }; 618 619 tsens: thermal-sensor@4a9000 { 620 compatible = "qcom,msm8937-tsens", "qcom,tsens-v1"; 621 reg = <0x004a9000 0x1000>, 622 <0x004a8000 0x1000>; 623 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 624 interrupt-names = "uplow"; 625 nvmem-cells = <&tsens_mode>, 626 <&tsens_base1>, <&tsens_base2>, 627 <&tsens_s0_p1>, <&tsens_s0_p2>, 628 <&tsens_s1_p1>, <&tsens_s1_p2>, 629 <&tsens_s2_p1>, <&tsens_s2_p2>, 630 <&tsens_s3_p1>, <&tsens_s3_p2>, 631 <&tsens_s4_p1>, <&tsens_s4_p2>, 632 <&tsens_s5_p1>, <&tsens_s5_p2>, 633 <&tsens_s6_p1>, <&tsens_s6_p2>, 634 <&tsens_s7_p1>, <&tsens_s7_p2>, 635 <&tsens_s8_p1>, <&tsens_s8_p2>, 636 <&tsens_s9_p1>, <&tsens_s9_p2>, 637 <&tsens_s10_p1>, <&tsens_s10_p2>; 638 nvmem-cell-names = "mode", 639 "base1", "base2", 640 "s0_p1", "s0_p2", 641 "s1_p1", "s1_p2", 642 "s2_p1", "s2_p2", 643 "s3_p1", "s3_p2", 644 "s4_p1", "s4_p2", 645 "s5_p1", "s5_p2", 646 "s6_p1", "s6_p2", 647 "s7_p1", "s7_p2", 648 "s8_p1", "s8_p2", 649 "s9_p1", "s9_p2", 650 "s10_p1", "s10_p2"; 651 #qcom,sensors = <11>; 652 #thermal-sensor-cells = <1>; 653 }; 654 655 restart@4ab000 { 656 compatible = "qcom,pshold"; 657 reg = <0x004ab000 0x4>; 658 }; 659 660 tlmm: pinctrl@1000000 { 661 compatible = "qcom,msm8917-pinctrl"; 662 reg = <0x01000000 0x300000>; 663 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 664 gpio-controller; 665 gpio-ranges = <&tlmm 0 0 134>; 666 #gpio-cells = <2>; 667 interrupt-controller; 668 #interrupt-cells = <2>; 669 670 blsp1_i2c2_default: blsp1-i2c2-default-state { 671 pins = "gpio6", "gpio7"; 672 function = "blsp_i2c2"; 673 drive-strength = <2>; 674 bias-disable; 675 }; 676 677 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state { 678 pins = "gpio6", "gpio7"; 679 function = "gpio"; 680 drive-strength = <2>; 681 bias-disable; 682 }; 683 684 blsp1_i2c3_default: blsp1-i2c3-default-state { 685 pins = "gpio10", "gpio11"; 686 function = "blsp_i2c3"; 687 drive-strength = <2>; 688 bias-disable; 689 }; 690 691 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state { 692 pins = "gpio10", "gpio11"; 693 function = "gpio"; 694 drive-strength = <2>; 695 bias-disable; 696 }; 697 698 blsp1_i2c4_default: blsp1-i2c4-default-state { 699 pins = "gpio14", "gpio15"; 700 function = "blsp_i2c4"; 701 drive-strength = <2>; 702 bias-disable; 703 }; 704 705 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state { 706 pins = "gpio14", "gpio15"; 707 function = "gpio"; 708 drive-strength = <2>; 709 bias-disable; 710 }; 711 712 blsp2_i2c1_default: blsp2-i2c1-default-state { 713 pins = "gpio18", "gpio19"; 714 function = "blsp_i2c5"; 715 drive-strength = <2>; 716 bias-disable; 717 }; 718 719 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state { 720 pins = "gpio18", "gpio19"; 721 function = "gpio"; 722 drive-strength = <2>; 723 bias-disable; 724 }; 725 726 blsp1_spi3_default: blsp1-spi3-default-state { 727 cs-pins { 728 pins = "gpio10"; 729 function = "blsp_spi3"; 730 drive-strength = <2>; 731 bias-disable; 732 }; 733 734 spi-pins { 735 pins = "gpio8", "gpio9", "gpio11"; 736 function = "blsp_spi3"; 737 drive-strength = <12>; 738 bias-disable; 739 }; 740 }; 741 742 blsp1_spi3_sleep: blsp1-spi3-sleep-state { 743 cs-pins { 744 pins = "gpio10"; 745 function = "gpio"; 746 drive-strength = <2>; 747 bias-disable; 748 }; 749 750 spi-pins { 751 pins = "gpio8", "gpio9", "gpio11"; 752 function = "gpio"; 753 drive-strength = <2>; 754 bias-pull-down; 755 }; 756 }; 757 758 blsp2_spi2_default: blsp2-spi2-default-state { 759 cs0-pins { 760 pins = "gpio47"; 761 function = "blsp_spi6"; 762 drive-strength = <16>; 763 bias-disable; 764 }; 765 766 cs1-pins { 767 pins = "gpio22"; 768 function = "blsp_spi6"; 769 drive-strength = <16>; 770 bias-disable; 771 }; 772 773 spi-pins { 774 pins = "gpio20", "gpio21", "gpio23"; 775 function = "blsp_spi6"; 776 drive-strength = <16>; 777 bias-disable; 778 }; 779 }; 780 781 blsp2_spi2_sleep: blsp2-spi2-sleep-state { 782 cs0-pins { 783 pins = "gpio47"; 784 function = "gpio"; 785 drive-strength = <2>; 786 bias-disable; 787 }; 788 789 cs1-pins { 790 pins = "gpio22"; 791 function = "gpio"; 792 drive-strength = <2>; 793 bias-disable; 794 }; 795 796 spi-pins { 797 pins = "gpio20", "gpio21", "gpio23"; 798 function = "gpio"; 799 drive-strength = <2>; 800 bias-pull-down; 801 }; 802 }; 803 804 blsp1_uart1_default: blsp1-uart1-default-state { 805 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 806 function = "blsp_uart1"; 807 drive-strength = <2>; 808 bias-disable; 809 }; 810 811 blsp1_uart1_sleep: blsp1-uart1-sleep-state { 812 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 813 function = "gpio"; 814 drive-strength = <2>; 815 bias-disable; 816 }; 817 818 blsp1_uart2_default: blsp1-uart2-default-state { 819 pins = "gpio4", "gpio5"; 820 function = "blsp_uart2"; 821 drive-strength = <2>; 822 bias-disable; 823 }; 824 825 blsp1_uart2_sleep: blsp1-uart2-sleep-state { 826 pins = "gpio4", "gpio5"; 827 function = "gpio"; 828 drive-strength = <2>; 829 bias-pull-down; 830 }; 831 832 sdc1_default: sdc1-default-state { 833 clk-pins { 834 pins = "sdc1_clk"; 835 bias-disable; 836 drive-strength = <16>; 837 }; 838 839 cmd-pins { 840 pins = "sdc1_cmd"; 841 bias-pull-up; 842 drive-strength = <10>; 843 }; 844 845 data-pins { 846 pins = "sdc1_data"; 847 bias-pull-up; 848 drive-strength = <10>; 849 }; 850 851 rclk-pins { 852 pins = "sdc1_rclk"; 853 bias-pull-down; 854 }; 855 }; 856 857 sdc1_sleep: sdc1-sleep-state { 858 clk-pins { 859 pins = "sdc1_clk"; 860 bias-disable; 861 drive-strength = <2>; 862 }; 863 864 cmd-pins { 865 pins = "sdc1_cmd"; 866 bias-pull-up; 867 drive-strength = <2>; 868 }; 869 870 data-pins { 871 pins = "sdc1_data"; 872 bias-pull-up; 873 drive-strength = <2>; 874 }; 875 876 rclk-pins { 877 pins = "sdc1_rclk"; 878 bias-pull-down; 879 }; 880 }; 881 882 sdc2_default: sdc2-default-state { 883 clk-pins { 884 pins = "sdc2_clk"; 885 bias-disable; 886 drive-strength = <16>; 887 }; 888 889 cmd-pins { 890 pins = "sdc2_cmd"; 891 bias-pull-up; 892 drive-strength = <10>; 893 }; 894 895 data-pins { 896 pins = "sdc2_data"; 897 bias-pull-up; 898 drive-strength = <10>; 899 }; 900 }; 901 902 sdc2_sleep: sdc2-sleep-state { 903 clk-pins { 904 pins = "sdc2_clk"; 905 bias-disable; 906 drive-strength = <2>; 907 }; 908 909 cmd-pins { 910 pins = "sdc2_cmd"; 911 bias-pull-up; 912 drive-strength = <2>; 913 }; 914 915 data-pins { 916 pins = "sdc2_data"; 917 bias-pull-up; 918 drive-strength = <2>; 919 }; 920 }; 921 922 wcnss_pin_a: wcnss-active-state { 923 wcss-wlan-pins { 924 pins = "gpio79", "gpio80"; 925 function = "wcss_wlan"; 926 drive-strength = <6>; 927 bias-pull-up; 928 929 }; 930 931 wcss-wlan0-pins { 932 pins = "gpio78"; 933 function = "wcss_wlan0"; 934 drive-strength = <6>; 935 bias-pull-up; 936 937 }; 938 939 wcss-wlan1-pins { 940 pins = "gpio77"; 941 function = "wcss_wlan1"; 942 drive-strength = <6>; 943 bias-pull-up; 944 945 }; 946 947 wcss-wlan2-pins { 948 pins = "gpio76"; 949 function = "wcss_wlan2"; 950 drive-strength = <6>; 951 bias-pull-up; 952 953 }; 954 }; 955 }; 956 957 gcc: clock-controller@1800000 { 958 compatible = "qcom,gcc-msm8917"; 959 reg = <0x01800000 0x80000>; 960 #clock-cells = <1>; 961 #reset-cells = <1>; 962 #power-domain-cells = <1>; 963 clocks = <&xo_board>, 964 <&sleep_clk>, 965 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 966 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>; 967 clock-names = "xo", 968 "sleep_clk", 969 "dsi0pll", 970 "dsi0pllbyte"; 971 }; 972 973 tcsr_mutex: hwlock@1905000 { 974 compatible = "qcom,tcsr-mutex"; 975 reg = <0x01905000 0x20000>; 976 #hwlock-cells = <1>; 977 }; 978 979 tcsr: syscon@1937000 { 980 compatible = "qcom,tcsr-msm8917", "syscon"; 981 reg = <0x01937000 0x30000>; 982 }; 983 984 mdss: display-subsystem@1a00000 { 985 compatible = "qcom,mdss"; 986 reg = <0x01a00000 0x1000>, 987 <0x01ab0000 0x1040>; 988 reg-names = "mdss_phys", "vbif_phys"; 989 ranges; 990 991 power-domains = <&gcc MDSS_GDSC>; 992 993 clocks = <&gcc GCC_MDSS_AHB_CLK>, 994 <&gcc GCC_MDSS_AXI_CLK>, 995 <&gcc GCC_MDSS_VSYNC_CLK>; 996 clock-names = "iface", 997 "bus", 998 "vsync"; 999 1000 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1001 1002 interrupt-controller; 1003 #interrupt-cells = <1>; 1004 1005 #address-cells = <1>; 1006 #size-cells = <1>; 1007 1008 status = "disabled"; 1009 1010 mdp: display-controller@1a01000 { 1011 compatible = "qcom,msm8917-mdp5", "qcom,mdp5"; 1012 reg = <0x01a01000 0x89000>; 1013 reg-names = "mdp_phys"; 1014 1015 interrupt-parent = <&mdss>; 1016 interrupts = <0>; 1017 1018 power-domains = <&gcc MDSS_GDSC>; 1019 1020 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1021 <&gcc GCC_MDSS_AXI_CLK>, 1022 <&gcc GCC_MDSS_MDP_CLK>, 1023 <&gcc GCC_MDSS_VSYNC_CLK>; 1024 clock-names = "iface", 1025 "bus", 1026 "core", 1027 "vsync"; 1028 1029 iommus = <&apps_iommu 0x15>; 1030 1031 ports { 1032 #address-cells = <1>; 1033 #size-cells = <0>; 1034 1035 port@0 { 1036 reg = <0>; 1037 1038 mdp5_intf1_out: endpoint { 1039 remote-endpoint = <&mdss_dsi0_in>; 1040 }; 1041 }; 1042 }; 1043 }; 1044 1045 mdss_dsi0: dsi@1a94000 { 1046 compatible = "qcom,mdss-dsi-ctrl"; 1047 reg = <0x01a94000 0x300>; 1048 reg-names = "dsi_ctrl"; 1049 1050 interrupt-parent = <&mdss>; 1051 interrupts = <4>; 1052 1053 assigned-clocks = <&gcc BYTE0_CLK_SRC>, 1054 <&gcc PCLK0_CLK_SRC>; 1055 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 1056 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 1057 1058 clocks = <&gcc GCC_MDSS_MDP_CLK>, 1059 <&gcc GCC_MDSS_AHB_CLK>, 1060 <&gcc GCC_MDSS_AXI_CLK>, 1061 <&gcc GCC_MDSS_BYTE0_CLK>, 1062 <&gcc GCC_MDSS_PCLK0_CLK>, 1063 <&gcc GCC_MDSS_ESC0_CLK>; 1064 clock-names = "mdp_core", 1065 "iface", 1066 "bus", 1067 "byte", 1068 "pixel", 1069 "core"; 1070 phys = <&mdss_dsi0_phy>; 1071 1072 operating-points-v2 = <&mdss_dsi0_opp_table>; 1073 power-domains = <&rpmpd MSM8917_VDDCX>; 1074 1075 #address-cells = <1>; 1076 #size-cells = <0>; 1077 1078 ports { 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 1082 port@0 { 1083 reg = <0>; 1084 1085 mdss_dsi0_in: endpoint { 1086 remote-endpoint = <&mdp5_intf1_out>; 1087 }; 1088 }; 1089 1090 port@1 { 1091 reg = <1>; 1092 1093 mdss_dsi0_out: endpoint { 1094 }; 1095 }; 1096 }; 1097 1098 mdss_dsi0_opp_table: opp-table { 1099 compatible = "operating-points-v2"; 1100 1101 opp-125000000 { 1102 opp-hz = /bits/ 64 <125000000>; 1103 required-opps = <&rpmpd_opp_svs>; 1104 }; 1105 1106 opp-187500000 { 1107 opp-hz = /bits/ 64 <187500000>; 1108 required-opps = <&rpmpd_opp_nom>; 1109 }; 1110 }; 1111 }; 1112 1113 mdss_dsi0_phy: phy@1a94a00 { 1114 compatible = "qcom,dsi-phy-28nm-8937"; 1115 reg = <0x01a94a00 0xd4>, 1116 <0x01a94400 0x280>, 1117 <0x01a94b80 0x30>; 1118 reg-names = "dsi_pll", 1119 "dsi_phy", 1120 "dsi_phy_regulator"; 1121 1122 #clock-cells = <1>; 1123 #phy-cells = <0>; 1124 1125 clocks = <&gcc GCC_MDSS_AHB_CLK>, 1126 <&xo_board>; 1127 clock-names = "iface", "ref"; 1128 }; 1129 }; 1130 1131 apps_iommu: iommu@1e20000 { 1132 compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1"; 1133 ranges = <0 0x01e20000 0x20000>; 1134 #address-cells = <1>; 1135 #size-cells = <1>; 1136 #iommu-cells = <1>; 1137 1138 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1139 <&gcc GCC_APSS_TCU_CLK>; 1140 clock-names = "iface", "bus"; 1141 1142 qcom,iommu-secure-id = <17>; 1143 1144 /* VFE */ 1145 iommu-ctx@14000 { 1146 compatible = "qcom,msm-iommu-v1-ns"; 1147 reg = <0x14000 0x1000>; 1148 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1149 }; 1150 1151 /* MDP_0 */ 1152 iommu-ctx@15000 { 1153 compatible = "qcom,msm-iommu-v1-ns"; 1154 reg = <0x15000 0x1000>; 1155 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1156 }; 1157 1158 /* VENUS_NS */ 1159 iommu-ctx@16000 { 1160 compatible = "qcom,msm-iommu-v1-ns"; 1161 reg = <0x16000 0x1000>; 1162 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 1163 }; 1164 }; 1165 1166 gpu_iommu: iommu@1f08000 { 1167 compatible = "qcom,msm8917-iommu", "qcom,msm-iommu-v1"; 1168 ranges = <0 0x01f08000 0x10000>; 1169 1170 #address-cells = <1>; 1171 #size-cells = <1>; 1172 #iommu-cells = <1>; 1173 1174 clocks = <&gcc GCC_SMMU_CFG_CLK>, 1175 <&gcc GCC_GFX_TCU_CLK>; 1176 clock-names = "iface", "bus"; 1177 qcom,iommu-secure-id = <18>; 1178 1179 iommu-ctx@0 { 1180 compatible = "qcom,msm-iommu-v2-ns"; 1181 reg = <0 0x1000>; 1182 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 1183 }; 1184 }; 1185 1186 gpu: gpu@1c00000 { 1187 compatible = "qcom,adreno-306.32", "qcom,adreno"; 1188 reg = <0x01c00000 0x20000>; 1189 reg-names = "kgsl_3d0_reg_memory"; 1190 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1191 interrupt-names = "kgsl_3d0_irq"; 1192 clock-names = "core", 1193 "iface", 1194 "mem_iface", 1195 "alt_mem_iface", 1196 "gfx3d"; 1197 clocks = <&gcc GCC_OXILI_GFX3D_CLK>, 1198 <&gcc GCC_OXILI_AHB_CLK>, 1199 <&gcc GCC_BIMC_GFX_CLK>, 1200 <&gcc GCC_BIMC_GPU_CLK>, 1201 <&gcc GFX3D_CLK_SRC>; 1202 power-domains = <&gcc OXILI_GX_GDSC>; 1203 operating-points-v2 = <&gpu_opp_table>; 1204 #cooling-cells = <2>; 1205 1206 iommus = <&gpu_iommu 0>; 1207 1208 status = "disabled"; 1209 1210 gpu_opp_table: opp-table { 1211 compatible = "operating-points-v2"; 1212 1213 opp-19200000 { 1214 opp-hz = /bits/ 64 <19200000>; 1215 }; 1216 1217 opp-270000000 { 1218 opp-hz = /bits/ 64 <270000000>; 1219 }; 1220 1221 opp-400000000 { 1222 opp-hz = /bits/ 64 <400000000>; 1223 }; 1224 1225 opp-484800000 { 1226 opp-hz = /bits/ 64 <484800000>; 1227 }; 1228 1229 opp-523200000 { 1230 opp-hz = /bits/ 64 <523200000>; 1231 }; 1232 1233 opp-598000000 { 1234 opp-hz = /bits/ 64 <598000000>; 1235 }; 1236 }; 1237 }; 1238 1239 spmi_bus: spmi@200f000 { 1240 compatible = "qcom,spmi-pmic-arb"; 1241 reg = <0x0200f000 0x001000>, 1242 <0x02400000 0x800000>, 1243 <0x02c00000 0x800000>, 1244 <0x03800000 0x200000>, 1245 <0x0200a000 0x002100>; 1246 reg-names = "core", 1247 "chnls", 1248 "obsrvr", 1249 "intr", 1250 "cnfg"; 1251 interrupt-names = "periph_irq"; 1252 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1253 qcom,ee = <0>; 1254 qcom,channel = <0>; 1255 #address-cells = <2>; 1256 #size-cells = <0>; 1257 interrupt-controller; 1258 #interrupt-cells = <4>; 1259 }; 1260 1261 bam_dmux_dma: dma-controller@4044000 { 1262 compatible = "qcom,bam-v1.7.0"; 1263 reg = <0x04044000 0x19000>; 1264 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; 1265 #dma-cells = <1>; 1266 qcom,ee = <0>; 1267 1268 num-channels = <6>; 1269 qcom,num-ees = <1>; 1270 qcom,powered-remotely; 1271 1272 status = "disabled"; 1273 }; 1274 1275 sdhc_1: mmc@7824900 { 1276 compatible = "qcom,sdhci-msm-v4"; 1277 reg = <0x07824900 0x500>, 1278 <0x07824000 0x800>; 1279 reg-names = "hc", "core"; 1280 1281 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1283 interrupt-names = "hc_irq", "pwr_irq"; 1284 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1285 <&gcc GCC_SDCC1_APPS_CLK>, 1286 <&xo_board>; 1287 clock-names = "iface", "core", "xo"; 1288 pinctrl-0 = <&sdc1_default>; 1289 pinctrl-1 = <&sdc1_sleep>; 1290 pinctrl-names = "default", "sleep"; 1291 power-domains = <&rpmpd MSM8917_VDDCX>; 1292 mmc-hs200-1_8v; 1293 mmc-hs400-1_8v; 1294 mmc-ddr-1_8v; 1295 bus-width = <8>; 1296 non-removable; 1297 status = "disabled"; 1298 }; 1299 1300 sdhc_2: mmc@7864900 { 1301 compatible = "qcom,sdhci-msm-v4"; 1302 reg = <0x07864900 0x500>, 1303 <0x07864000 0x800>; 1304 reg-names = "hc", "core"; 1305 1306 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1307 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 1308 interrupt-names = "hc_irq", "pwr_irq"; 1309 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1310 <&gcc GCC_SDCC2_APPS_CLK>, 1311 <&xo_board>; 1312 clock-names = "iface", "core", "xo"; 1313 pinctrl-0 = <&sdc2_default>; 1314 pinctrl-1 = <&sdc2_sleep>; 1315 pinctrl-names = "default", "sleep"; 1316 power-domains = <&rpmpd MSM8917_VDDCX>; 1317 bus-width = <4>; 1318 status = "disabled"; 1319 }; 1320 1321 blsp1_dma: dma-controller@7884000 { 1322 compatible = "qcom,bam-v1.7.0"; 1323 reg = <0x07884000 0x1f000>; 1324 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 1326 clock-names = "bam_clk"; 1327 qcom,controlled-remotely; 1328 #dma-cells = <1>; 1329 num-channels = <12>; 1330 qcom,num-ees = <4>; 1331 qcom,ee = <0>; 1332 }; 1333 1334 blsp2_dma: dma-controller@7ac4000 { 1335 compatible = "qcom,bam-v1.7.0"; 1336 reg = <0x07ac4000 0x1d000>; 1337 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1338 clocks = <&gcc GCC_BLSP2_AHB_CLK>; 1339 clock-names = "bam_clk"; 1340 qcom,controlled-remotely; 1341 #dma-cells = <1>; 1342 num-channels = <10>; 1343 qcom,num-ees = <4>; 1344 qcom,ee = <0>; 1345 }; 1346 1347 blsp1_uart1: serial@78af000 { 1348 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1349 reg = <0x078af000 0x200>; 1350 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1351 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 1352 <&gcc GCC_BLSP1_AHB_CLK>; 1353 clock-names = "core", "iface"; 1354 dmas = <&blsp1_dma 0>, <&blsp1_dma 1>; 1355 dma-names = "tx", "rx"; 1356 pinctrl-0 = <&blsp1_uart1_default>; 1357 pinctrl-1 = <&blsp1_uart1_sleep>; 1358 pinctrl-names = "default", "sleep"; 1359 status = "disabled"; 1360 }; 1361 1362 blsp1_uart2: serial@78b0000 { 1363 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 1364 reg = <0x078b0000 0x200>; 1365 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1366 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 1367 <&gcc GCC_BLSP1_AHB_CLK>; 1368 clock-names = "core", "iface"; 1369 dmas = <&blsp1_dma 2>, <&blsp1_dma 3>; 1370 dma-names = "tx", "rx"; 1371 pinctrl-0 = <&blsp1_uart2_default>; 1372 pinctrl-1 = <&blsp1_uart2_sleep>; 1373 pinctrl-names = "default", "sleep"; 1374 status = "disabled"; 1375 }; 1376 1377 blsp1_i2c2: i2c@78b6000 { 1378 compatible = "qcom,i2c-qup-v2.2.1"; 1379 reg = <0x078b6000 0x600>; 1380 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1381 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 1382 <&gcc GCC_BLSP1_AHB_CLK>; 1383 clock-names = "core", "iface"; 1384 dmas = <&blsp1_dma 6>, <&blsp1_dma 7>; 1385 dma-names = "tx", "rx"; 1386 pinctrl-0 = <&blsp1_i2c2_default>; 1387 pinctrl-1 = <&blsp1_i2c2_sleep>; 1388 pinctrl-names = "default", "sleep"; 1389 #address-cells = <1>; 1390 #size-cells = <0>; 1391 status = "disabled"; 1392 }; 1393 1394 blsp1_i2c3: i2c@78b7000 { 1395 compatible = "qcom,i2c-qup-v2.2.1"; 1396 reg = <0x078b7000 0x600>; 1397 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1398 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 1399 <&gcc GCC_BLSP1_AHB_CLK>; 1400 clock-names = "core", "iface"; 1401 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1402 dma-names = "tx", "rx"; 1403 pinctrl-0 = <&blsp1_i2c3_default>; 1404 pinctrl-1 = <&blsp1_i2c3_sleep>; 1405 pinctrl-names = "default", "sleep"; 1406 #address-cells = <1>; 1407 #size-cells = <0>; 1408 status = "disabled"; 1409 }; 1410 1411 blsp1_spi3: spi@78b7000 { 1412 compatible = "qcom,spi-qup-v2.2.1"; 1413 reg = <0x078b7000 0x600>; 1414 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1415 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>, 1416 <&gcc GCC_BLSP1_AHB_CLK>; 1417 clock-names = "core", "iface"; 1418 dmas = <&blsp1_dma 8>, <&blsp1_dma 9>; 1419 dma-names = "tx", "rx"; 1420 pinctrl-0 = <&blsp1_spi3_default>; 1421 pinctrl-1 = <&blsp1_spi3_sleep>; 1422 pinctrl-names = "default", "sleep"; 1423 #address-cells = <1>; 1424 #size-cells = <0>; 1425 status = "disabled"; 1426 }; 1427 1428 blsp1_i2c4: i2c@78b8000 { 1429 compatible = "qcom,i2c-qup-v2.2.1"; 1430 reg = <0x078b8000 0x500>; 1431 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1432 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>, 1433 <&gcc GCC_BLSP1_AHB_CLK>; 1434 clock-names = "core", "iface"; 1435 dmas = <&blsp1_dma 10>, <&blsp1_dma 11>; 1436 dma-names = "tx", "rx"; 1437 pinctrl-0 = <&blsp1_i2c4_default>; 1438 pinctrl-1 = <&blsp1_i2c4_sleep>; 1439 pinctrl-names = "default", "sleep"; 1440 #address-cells = <1>; 1441 #size-cells = <0>; 1442 status = "disabled"; 1443 }; 1444 1445 blsp2_i2c1: i2c@7af5000 { 1446 compatible = "qcom,i2c-qup-v2.2.1"; 1447 reg = <0x07af5000 0x600>; 1448 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 1449 clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>, 1450 <&gcc GCC_BLSP2_AHB_CLK>; 1451 clock-names = "core", "iface"; 1452 dmas = <&blsp2_dma 4>, <&blsp2_dma 5>; 1453 dma-names = "tx", "rx"; 1454 pinctrl-0 = <&blsp2_i2c1_default>; 1455 pinctrl-1 = <&blsp2_i2c1_sleep>; 1456 pinctrl-names = "default", "sleep"; 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 status = "disabled"; 1460 }; 1461 1462 blsp2_spi2: spi@7af6000 { 1463 compatible = "qcom,spi-qup-v2.2.1"; 1464 reg = <0x07af6000 0x600>; 1465 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 1466 clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, 1467 <&gcc GCC_BLSP2_AHB_CLK>; 1468 clock-names = "core", "iface"; 1469 dmas = <&blsp2_dma 6>, <&blsp2_dma 7>; 1470 dma-names = "tx", "rx"; 1471 pinctrl-0 = <&blsp2_spi2_default>; 1472 pinctrl-1 = <&blsp2_spi2_sleep>; 1473 pinctrl-names = "default", "sleep"; 1474 #address-cells = <1>; 1475 #size-cells = <0>; 1476 status = "disabled"; 1477 }; 1478 1479 usb: usb@78db000 { 1480 compatible = "qcom,ci-hdrc"; 1481 reg = <0x078db000 0x200>, 1482 <0x078db200 0x200>; 1483 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 1484 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 1485 clocks = <&gcc GCC_USB_HS_AHB_CLK>, 1486 <&gcc GCC_USB_HS_SYSTEM_CLK>; 1487 clock-names = "iface", "core"; 1488 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>; 1489 assigned-clock-rates = <80000000>; 1490 resets = <&gcc GCC_USB_HS_BCR>; 1491 reset-names = "core"; 1492 phy_type = "ulpi"; 1493 dr_mode = "otg"; 1494 hnp-disable; 1495 srp-disable; 1496 adp-disable; 1497 ahb-burst-config = <0>; 1498 phy-names = "usb-phy"; 1499 phys = <&usb_hs_phy>; 1500 status = "disabled"; 1501 #reset-cells = <1>; 1502 }; 1503 1504 wcnss: remoteproc@a204000 { 1505 compatible = "qcom,pronto-v3-pil", "qcom,pronto"; 1506 reg = <0x0a204000 0x2000>, 1507 <0x0a202000 0x1000>, 1508 <0x0a21b000 0x3000>; 1509 reg-names = "ccu", "dxe", "pmu"; 1510 1511 memory-region = <&wcnss_mem>; 1512 1513 interrupts-extended = <&intc GIC_SPI 149 IRQ_TYPE_EDGE_RISING>, 1514 <&wcnss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 1515 <&wcnss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 1516 <&wcnss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 1517 <&wcnss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 1518 interrupt-names = "wdog", "fatal", "ready", "handover", "stop-ack"; 1519 1520 power-domains = <&rpmpd MSM8917_VDDCX>, 1521 <&rpmpd MSM8917_VDDMX>; 1522 power-domain-names = "cx", "mx"; 1523 1524 qcom,smem-states = <&wcnss_smp2p_out 0>; 1525 qcom,smem-state-names = "stop"; 1526 1527 pinctrl-0 = <&wcnss_pin_a>; 1528 pinctrl-names = "default"; 1529 1530 status = "disabled"; 1531 1532 wcnss_iris: iris { 1533 clocks = <&rpmcc RPM_SMD_RF_CLK2>; 1534 clock-names = "xo"; 1535 }; 1536 1537 smd-edge { 1538 interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; 1539 1540 mboxes = <&apcs 17>; 1541 qcom,smd-edge = <6>; 1542 qcom,remote-pid = <4>; 1543 1544 label = "pronto"; 1545 1546 wcnss_ctrl: wcnss { 1547 compatible = "qcom,wcnss"; 1548 qcom,smd-channels = "WCNSS_CTRL"; 1549 1550 qcom,mmio = <&wcnss>; 1551 1552 wcnss_bt: bluetooth { 1553 compatible = "qcom,wcnss-bt"; 1554 }; 1555 1556 wcnss_wifi: wifi { 1557 compatible = "qcom,wcnss-wlan"; 1558 1559 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 1560 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1561 interrupt-names = "tx", "rx"; 1562 1563 qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>; 1564 qcom,smem-state-names = "tx-enable", 1565 "tx-rings-empty"; 1566 }; 1567 }; 1568 }; 1569 }; 1570 1571 intc: interrupt-controller@b000000 { 1572 compatible = "qcom,msm-qgic2"; 1573 reg = <0x0b000000 0x1000>, 1574 <0x0b002000 0x1000>; 1575 interrupt-controller; 1576 #interrupt-cells = <3>; 1577 }; 1578 1579 apcs: mailbox@b011000 { 1580 compatible = "qcom,msm8939-apcs-kpss-global", "syscon"; 1581 reg = <0x0b011000 0x1000>; 1582 #mbox-cells = <1>; 1583 clocks = <&a53pll>, <&gcc GPLL0_EARLY>, <&rpmcc RPM_SMD_XO_CLK_SRC>; 1584 clock-names = "pll", "aux", "ref"; 1585 #clock-cells = <0>; 1586 }; 1587 1588 a53pll: clock@b016000 { 1589 compatible = "qcom,msm8939-a53pll"; 1590 reg = <0x0b016000 0x40>; 1591 clocks = <&xo_board>; 1592 clock-names = "xo"; 1593 #clock-cells = <0>; 1594 operating-points-v2 = <&pll_opp_table>; 1595 1596 pll_opp_table: opp-table { 1597 compatible = "operating-points-v2"; 1598 1599 opp-960000000 { 1600 opp-hz = /bits/ 64 <960000000>; 1601 }; 1602 1603 opp-1094400000 { 1604 opp-hz = /bits/ 64 <1094400000>; 1605 }; 1606 1607 opp-1248000000 { 1608 opp-hz = /bits/ 64 <1248000000>; 1609 }; 1610 1611 opp-1401600000 { 1612 opp-hz = /bits/ 64 <1401600000>; 1613 }; 1614 }; 1615 }; 1616 1617 watchdog@b017000 { 1618 compatible = "qcom,apss-wdt-qcs404", "qcom,kpss-wdt"; 1619 reg = <0x0b017000 0x1000>; 1620 clocks = <&sleep_clk>; 1621 }; 1622 1623 timer@b120000 { 1624 compatible = "arm,armv7-timer-mem"; 1625 reg = <0x0b120000 0x1000>; 1626 ranges; 1627 #address-cells = <1>; 1628 #size-cells = <1>; 1629 1630 frame@b121000 { 1631 reg = <0x0b121000 0x1000>, 1632 <0x0b122000 0x1000>; 1633 frame-number = <0>; 1634 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1636 }; 1637 1638 frame@b123000 { 1639 reg = <0x0b123000 0x1000>; 1640 frame-number = <1>; 1641 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1642 status = "disabled"; 1643 }; 1644 1645 frame@b124000 { 1646 reg = <0x0b124000 0x1000>; 1647 frame-number = <2>; 1648 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1649 status = "disabled"; 1650 }; 1651 1652 frame@b125000 { 1653 reg = <0x0b125000 0x1000>; 1654 frame-number = <3>; 1655 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1656 status = "disabled"; 1657 }; 1658 1659 frame@b126000 { 1660 reg = <0x0b126000 0x1000>; 1661 frame-number = <4>; 1662 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1663 status = "disabled"; 1664 }; 1665 1666 frame@b127000 { 1667 reg = <0x0b127000 0x1000>; 1668 frame-number = <5>; 1669 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1670 status = "disabled"; 1671 }; 1672 1673 frame@b128000 { 1674 reg = <0x0b128000 0x1000>; 1675 frame-number = <6>; 1676 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1677 status = "disabled"; 1678 }; 1679 }; 1680 }; 1681 1682 timer { 1683 compatible = "arm,armv8-timer"; 1684 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1685 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1686 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1687 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1688 }; 1689 1690 thermal_zones: thermal-zones { 1691 aoss-thermal { 1692 polling-delay-passive = <250>; 1693 1694 thermal-sensors = <&tsens 0>; 1695 1696 trips { 1697 aoss_alert0: trip-point0 { 1698 temperature = <85000>; 1699 hysteresis = <2000>; 1700 type = "hot"; 1701 }; 1702 }; 1703 }; 1704 1705 camera-thermal { 1706 polling-delay-passive = <250>; 1707 1708 thermal-sensors = <&tsens 3>; 1709 1710 trips { 1711 camera_alert0: trip-point0 { 1712 temperature = <85000>; 1713 hysteresis = <2000>; 1714 type = "hot"; 1715 }; 1716 }; 1717 }; 1718 1719 cpuss1-thermal { 1720 polling-delay-passive = <250>; 1721 1722 thermal-sensors = <&tsens 4>; 1723 1724 cooling-maps { 1725 map0 { 1726 trip = <&cpuss1_alert0>; 1727 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1728 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1729 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1730 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1731 }; 1732 }; 1733 1734 trips { 1735 cpuss1_alert0: trip-point0 { 1736 temperature = <75000>; 1737 hysteresis = <2000>; 1738 type = "passive"; 1739 }; 1740 1741 cpuss1_alert1: trip-point1 { 1742 temperature = <85000>; 1743 hysteresis = <2000>; 1744 type = "hot"; 1745 }; 1746 1747 cpuss1_crit: cpuss1-crit { 1748 temperature = <100000>; 1749 hysteresis = <2000>; 1750 type = "critical"; 1751 }; 1752 }; 1753 }; 1754 1755 cpu0-thermal { 1756 polling-delay-passive = <250>; 1757 1758 thermal-sensors = <&tsens 5>; 1759 1760 cooling-maps { 1761 map0 { 1762 trip = <&cpu0_alert1>; 1763 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1764 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1765 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1766 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1767 }; 1768 }; 1769 1770 trips { 1771 cpu0_alert0: trip-point0 { 1772 temperature = <75000>; 1773 hysteresis = <2000>; 1774 type = "passive"; 1775 }; 1776 1777 cpu0_alert1: trip-point1 { 1778 temperature = <85000>; 1779 hysteresis = <2000>; 1780 type = "hot"; 1781 }; 1782 1783 cpu0_crit: cpu-crit { 1784 temperature = <100000>; 1785 hysteresis = <2000>; 1786 type = "critical"; 1787 }; 1788 }; 1789 }; 1790 1791 cpu1-thermal { 1792 polling-delay-passive = <250>; 1793 1794 thermal-sensors = <&tsens 6>; 1795 1796 cooling-maps { 1797 map0 { 1798 trip = <&cpu1_alert1>; 1799 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1800 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1801 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1802 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1803 }; 1804 }; 1805 1806 trips { 1807 cpu1_alert0: trip-point0 { 1808 temperature = <75000>; 1809 hysteresis = <2000>; 1810 type = "hot"; 1811 }; 1812 1813 cpu1_alert1: trip-point1 { 1814 temperature = <85000>; 1815 hysteresis = <2000>; 1816 type = "passive"; 1817 }; 1818 1819 cpu1_crit: cpu-crit { 1820 temperature = <100000>; 1821 hysteresis = <2000>; 1822 type = "critical"; 1823 }; 1824 }; 1825 }; 1826 1827 cpu2-thermal { 1828 polling-delay-passive = <250>; 1829 1830 thermal-sensors = <&tsens 7>; 1831 1832 cooling-maps { 1833 map0 { 1834 trip = <&cpu2_alert1>; 1835 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1836 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1837 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1838 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1839 }; 1840 }; 1841 1842 trips { 1843 cpu2_alert0: trip-point0 { 1844 temperature = <75000>; 1845 hysteresis = <2000>; 1846 type = "hot"; 1847 }; 1848 1849 cpu2_alert1: trip-point1 { 1850 temperature = <85000>; 1851 hysteresis = <2000>; 1852 type = "passive"; 1853 }; 1854 1855 cpu2_crit: cpu-crit { 1856 temperature = <100000>; 1857 hysteresis = <2000>; 1858 type = "critical"; 1859 }; 1860 }; 1861 }; 1862 1863 cpu3-thermal { 1864 polling-delay-passive = <250>; 1865 1866 thermal-sensors = <&tsens 8>; 1867 1868 cooling-maps { 1869 map0 { 1870 trip = <&cpu3_alert1>; 1871 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1872 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1873 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1874 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1875 }; 1876 }; 1877 1878 trips { 1879 cpu3_alert0: trip-point0 { 1880 temperature = <75000>; 1881 hysteresis = <2000>; 1882 type = "hot"; 1883 }; 1884 1885 cpu3_alert1: trip-point1 { 1886 temperature = <85000>; 1887 hysteresis = <2000>; 1888 type = "passive"; 1889 }; 1890 1891 cpu3_crit: cpu-crit { 1892 temperature = <100000>; 1893 hysteresis = <2000>; 1894 type = "critical"; 1895 }; 1896 }; 1897 }; 1898 1899 gpu-thermal { 1900 polling-delay-passive = <250>; 1901 1902 thermal-sensors = <&tsens 9>; 1903 1904 cooling-maps { 1905 map0 { 1906 trip = <&gpu_alert>; 1907 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1908 }; 1909 }; 1910 1911 trips { 1912 gpu_alert: trip-point0 { 1913 temperature = <70000>; 1914 hysteresis = <2000>; 1915 type = "passive"; 1916 }; 1917 1918 gpu_crit: gpu-crit { 1919 temperature = <90000>; 1920 hysteresis = <2000>; 1921 type = "critical"; 1922 }; 1923 }; 1924 1925 }; 1926 1927 mdm-core-thermal { 1928 polling-delay-passive = <250>; 1929 1930 thermal-sensors = <&tsens 1>; 1931 1932 trips { 1933 mdm_core_alert0: trip-point0 { 1934 temperature = <85000>; 1935 hysteresis = <2000>; 1936 type = "hot"; 1937 }; 1938 }; 1939 }; 1940 1941 q6-thermal { 1942 polling-delay-passive = <250>; 1943 1944 thermal-sensors = <&tsens 2>; 1945 1946 trips { 1947 q6_alert0: trip-point0 { 1948 temperature = <85000>; 1949 hysteresis = <2000>; 1950 type = "hot"; 1951 }; 1952 }; 1953 }; 1954 }; 1955};
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