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monaco.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/monaco.dtsi
1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6#include <dt-bindings/clock/qcom,qcs8300-gcc.h> 7#include <dt-bindings/clock/qcom,rpmh.h> 8#include <dt-bindings/clock/qcom,sa8775p-camcc.h> 9#include <dt-bindings/clock/qcom,sa8775p-dispcc.h> 10#include <dt-bindings/clock/qcom,sa8775p-gpucc.h> 11#include <dt-bindings/clock/qcom,sa8775p-videocc.h> 12#include <dt-bindings/dma/qcom-gpi.h> 13#include <dt-bindings/firmware/qcom,scm.h> 14#include <dt-bindings/interconnect/qcom,icc.h> 15#include <dt-bindings/interconnect/qcom,osm-l3.h> 16#include <dt-bindings/interconnect/qcom,qcs8300-rpmh.h> 17#include <dt-bindings/interrupt-controller/arm-gic.h> 18#include <dt-bindings/mailbox/qcom-ipcc.h> 19#include <dt-bindings/power/qcom,rpmhpd.h> 20#include <dt-bindings/power/qcom-rpmpd.h> 21#include <dt-bindings/soc/qcom,gpr.h> 22#include <dt-bindings/soc/qcom,rpmh-rsc.h> 23#include <dt-bindings/thermal/thermal.h> 24 25/ { 26 interrupt-parent = <&intc>; 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 clocks { 31 xo_board_clk: xo-board-clk { 32 compatible = "fixed-clock"; 33 #clock-cells = <0>; 34 clock-frequency = <38400000>; 35 }; 36 37 sleep_clk: sleep-clk { 38 compatible = "fixed-clock"; 39 #clock-cells = <0>; 40 clock-frequency = <32000>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <2>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 device_type = "cpu"; 50 compatible = "arm,cortex-a78c"; 51 reg = <0x0 0x0>; 52 enable-method = "psci"; 53 next-level-cache = <&l2_0>; 54 power-domains = <&cpu_pd0>; 55 power-domain-names = "psci"; 56 capacity-dmips-mhz = <1946>; 57 dynamic-power-coefficient = <472>; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 operating-points-v2 = <&cpu0_opp_table>; 60 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 61 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 62 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 63 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 64 65 l2_0: l2-cache { 66 compatible = "cache"; 67 cache-level = <2>; 68 cache-unified; 69 next-level-cache = <&l3_0>; 70 }; 71 }; 72 73 cpu1: cpu@100 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a78c"; 76 reg = <0x0 0x100>; 77 enable-method = "psci"; 78 next-level-cache = <&l2_1>; 79 power-domains = <&cpu_pd1>; 80 power-domain-names = "psci"; 81 capacity-dmips-mhz = <1946>; 82 dynamic-power-coefficient = <472>; 83 qcom,freq-domain = <&cpufreq_hw 0>; 84 operating-points-v2 = <&cpu0_opp_table>; 85 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 86 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 87 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 88 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 89 90 l2_1: l2-cache { 91 compatible = "cache"; 92 cache-level = <2>; 93 cache-unified; 94 next-level-cache = <&l3_0>; 95 }; 96 }; 97 98 cpu2: cpu@200 { 99 device_type = "cpu"; 100 compatible = "arm,cortex-a78c"; 101 reg = <0x0 0x200>; 102 enable-method = "psci"; 103 next-level-cache = <&l2_2>; 104 power-domains = <&cpu_pd2>; 105 power-domain-names = "psci"; 106 capacity-dmips-mhz = <1946>; 107 dynamic-power-coefficient = <507>; 108 qcom,freq-domain = <&cpufreq_hw 2>; 109 operating-points-v2 = <&cpu2_opp_table>; 110 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 111 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 112 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 113 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 114 115 l2_2: l2-cache { 116 compatible = "cache"; 117 cache-level = <2>; 118 cache-unified; 119 next-level-cache = <&l3_0>; 120 }; 121 }; 122 123 cpu3: cpu@300 { 124 device_type = "cpu"; 125 compatible = "arm,cortex-a78c"; 126 reg = <0x0 0x300>; 127 enable-method = "psci"; 128 next-level-cache = <&l2_3>; 129 power-domains = <&cpu_pd3>; 130 power-domain-names = "psci"; 131 capacity-dmips-mhz = <1946>; 132 dynamic-power-coefficient = <507>; 133 qcom,freq-domain = <&cpufreq_hw 2>; 134 operating-points-v2 = <&cpu2_opp_table>; 135 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 136 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 137 <&epss_l3_cl0 MASTER_EPSS_L3_APPS 138 &epss_l3_cl0 SLAVE_EPSS_L3_SHARED>; 139 140 l2_3: l2-cache { 141 compatible = "cache"; 142 cache-level = <2>; 143 cache-unified; 144 next-level-cache = <&l3_0>; 145 }; 146 }; 147 148 cpu4: cpu@10000 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a55"; 151 reg = <0x0 0x10000>; 152 enable-method = "psci"; 153 next-level-cache = <&l2_4>; 154 power-domains = <&cpu_pd4>; 155 power-domain-names = "psci"; 156 capacity-dmips-mhz = <1024>; 157 dynamic-power-coefficient = <100>; 158 qcom,freq-domain = <&cpufreq_hw 1>; 159 operating-points-v2 = <&cpu4_opp_table>; 160 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 161 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 162 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 163 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 164 165 l2_4: l2-cache { 166 compatible = "cache"; 167 cache-level = <2>; 168 cache-unified; 169 next-level-cache = <&l3_1>; 170 }; 171 }; 172 173 cpu5: cpu@10100 { 174 device_type = "cpu"; 175 compatible = "arm,cortex-a55"; 176 reg = <0x0 0x10100>; 177 enable-method = "psci"; 178 next-level-cache = <&l2_5>; 179 power-domains = <&cpu_pd5>; 180 power-domain-names = "psci"; 181 capacity-dmips-mhz = <1024>; 182 dynamic-power-coefficient = <100>; 183 qcom,freq-domain = <&cpufreq_hw 1>; 184 operating-points-v2 = <&cpu4_opp_table>; 185 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 186 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 187 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 188 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 189 190 l2_5: l2-cache { 191 compatible = "cache"; 192 cache-level = <2>; 193 cache-unified; 194 next-level-cache = <&l3_1>; 195 }; 196 }; 197 198 cpu6: cpu@10200 { 199 device_type = "cpu"; 200 compatible = "arm,cortex-a55"; 201 reg = <0x0 0x10200>; 202 enable-method = "psci"; 203 next-level-cache = <&l2_6>; 204 power-domains = <&cpu_pd6>; 205 power-domain-names = "psci"; 206 capacity-dmips-mhz = <1024>; 207 dynamic-power-coefficient = <100>; 208 qcom,freq-domain = <&cpufreq_hw 1>; 209 operating-points-v2 = <&cpu4_opp_table>; 210 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 211 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 212 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 213 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 214 215 l2_6: l2-cache { 216 compatible = "cache"; 217 cache-level = <2>; 218 cache-unified; 219 next-level-cache = <&l3_1>; 220 }; 221 }; 222 223 cpu7: cpu@10300 { 224 device_type = "cpu"; 225 compatible = "arm,cortex-a55"; 226 reg = <0x0 0x10300>; 227 enable-method = "psci"; 228 next-level-cache = <&l2_7>; 229 power-domains = <&cpu_pd7>; 230 power-domain-names = "psci"; 231 capacity-dmips-mhz = <1024>; 232 dynamic-power-coefficient = <100>; 233 qcom,freq-domain = <&cpufreq_hw 1>; 234 operating-points-v2 = <&cpu4_opp_table>; 235 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 236 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>, 237 <&epss_l3_cl1 MASTER_EPSS_L3_APPS 238 &epss_l3_cl1 SLAVE_EPSS_L3_SHARED>; 239 240 l2_7: l2-cache { 241 compatible = "cache"; 242 cache-level = <2>; 243 cache-unified; 244 next-level-cache = <&l3_1>; 245 }; 246 }; 247 248 cpu-map { 249 cluster0 { 250 core0 { 251 cpu = <&cpu0>; 252 }; 253 254 core1 { 255 cpu = <&cpu1>; 256 }; 257 258 core2 { 259 cpu = <&cpu2>; 260 }; 261 262 core3 { 263 cpu = <&cpu3>; 264 }; 265 }; 266 267 cluster1 { 268 core0 { 269 cpu = <&cpu4>; 270 }; 271 272 core1 { 273 cpu = <&cpu5>; 274 }; 275 276 core2 { 277 cpu = <&cpu6>; 278 }; 279 280 core3 { 281 cpu = <&cpu7>; 282 }; 283 }; 284 }; 285 286 l3_0: l3-cache-0 { 287 compatible = "cache"; 288 cache-level = <3>; 289 cache-unified; 290 }; 291 292 l3_1: l3-cache-1 { 293 compatible = "cache"; 294 cache-level = <3>; 295 cache-unified; 296 }; 297 298 idle-states { 299 entry-method = "psci"; 300 301 little_cpu_sleep_0: cpu-sleep-0-0 { 302 compatible = "arm,idle-state"; 303 idle-state-name = "silver-power-collapse"; 304 arm,psci-suspend-param = <0x40000003>; 305 entry-latency-us = <449>; 306 exit-latency-us = <801>; 307 min-residency-us = <1574>; 308 local-timer-stop; 309 }; 310 311 little_cpu_sleep_1: cpu-sleep-0-1 { 312 compatible = "arm,idle-state"; 313 idle-state-name = "silver-rail-power-collapse"; 314 arm,psci-suspend-param = <0x40000004>; 315 entry-latency-us = <602>; 316 exit-latency-us = <961>; 317 min-residency-us = <4288>; 318 local-timer-stop; 319 }; 320 321 big_cpu_sleep_0: cpu-sleep-1-0 { 322 compatible = "arm,idle-state"; 323 idle-state-name = "gold-power-collapse"; 324 arm,psci-suspend-param = <0x40000003>; 325 entry-latency-us = <549>; 326 exit-latency-us = <901>; 327 min-residency-us = <1774>; 328 local-timer-stop; 329 }; 330 331 big_cpu_sleep_1: cpu-sleep-1-1 { 332 compatible = "arm,idle-state"; 333 idle-state-name = "gold-rail-power-collapse"; 334 arm,psci-suspend-param = <0x40000004>; 335 entry-latency-us = <702>; 336 exit-latency-us = <1061>; 337 min-residency-us = <4488>; 338 local-timer-stop; 339 }; 340 }; 341 342 domain-idle-states { 343 silver_cluster_sleep: cluster-sleep-0 { 344 compatible = "domain-idle-state"; 345 arm,psci-suspend-param = <0x41000044>; 346 entry-latency-us = <2552>; 347 exit-latency-us = <2848>; 348 min-residency-us = <5908>; 349 }; 350 351 gold_cluster_sleep: cluster-sleep-1 { 352 compatible = "domain-idle-state"; 353 arm,psci-suspend-param = <0x41000044>; 354 entry-latency-us = <2752>; 355 exit-latency-us = <3048>; 356 min-residency-us = <6118>; 357 }; 358 359 system_sleep: domain-sleep { 360 compatible = "domain-idle-state"; 361 arm,psci-suspend-param = <0x42000144>; 362 entry-latency-us = <3263>; 363 exit-latency-us = <6562>; 364 min-residency-us = <9987>; 365 }; 366 }; 367 }; 368 369 cpu0_opp_table: opp-table-cpu0 { 370 compatible = "operating-points-v2"; 371 opp-shared; 372 373 opp-902400000 { 374 opp-hz = /bits/ 64 <902400000>; 375 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 376 }; 377 378 opp-1017600000 { 379 opp-hz = /bits/ 64 <1017600000>; 380 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 381 }; 382 383 opp-1190400000 { 384 opp-hz = /bits/ 64 <1190400000>; 385 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 386 }; 387 388 opp-1267200000 { 389 opp-hz = /bits/ 64 <1267200000>; 390 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 391 }; 392 393 opp-1344000000 { 394 opp-hz = /bits/ 64 <1344000000>; 395 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 396 }; 397 398 opp-1420800000 { 399 opp-hz = /bits/ 64 <1420800000>; 400 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 401 }; 402 403 opp-1497600000 { 404 opp-hz = /bits/ 64 <1497600000>; 405 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 406 }; 407 408 opp-1574400000 { 409 opp-hz = /bits/ 64 <1574400000>; 410 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 411 }; 412 413 opp-1670400000 { 414 opp-hz = /bits/ 64 <1670400000>; 415 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 416 }; 417 418 opp-1747200000 { 419 opp-hz = /bits/ 64 <1747200000>; 420 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 421 }; 422 423 opp-1824000000 { 424 opp-hz = /bits/ 64 <1824000000>; 425 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 426 }; 427 428 opp-1900800000 { 429 opp-hz = /bits/ 64 <1900800000>; 430 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 431 }; 432 433 opp-1977600000 { 434 opp-hz = /bits/ 64 <1977600000>; 435 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 436 }; 437 438 opp-2054400000 { 439 opp-hz = /bits/ 64 <2054400000>; 440 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 441 }; 442 443 opp-2112000000 { 444 opp-hz = /bits/ 64 <2112000000>; 445 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 446 }; 447 448 }; 449 450 cpu2_opp_table: opp-table-cpu2 { 451 compatible = "operating-points-v2"; 452 opp-shared; 453 454 opp-940800000 { 455 opp-hz = /bits/ 64 <940800000>; 456 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 457 }; 458 459 opp-1094400000 { 460 opp-hz = /bits/ 64 <1094400000>; 461 opp-peak-kBps = <(1017600 * 4) (921600 * 32)>; 462 }; 463 464 opp-1267200000 { 465 opp-hz = /bits/ 64 <1267200000>; 466 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 467 }; 468 469 opp-1344000000 { 470 opp-hz = /bits/ 64 <1344000000>; 471 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 472 }; 473 474 opp-1420800000 { 475 opp-hz = /bits/ 64 <1420800000>; 476 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 477 }; 478 479 opp-1497600000 { 480 opp-hz = /bits/ 64 <1497600000>; 481 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 482 }; 483 484 opp-1574400000 { 485 opp-hz = /bits/ 64 <1574400000>; 486 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 487 }; 488 489 opp-1632000000 { 490 opp-hz = /bits/ 64 <1632000000>; 491 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 492 }; 493 494 opp-1708800000 { 495 opp-hz = /bits/ 64 <1708800000>; 496 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 497 }; 498 499 opp-1804800000 { 500 opp-hz = /bits/ 64 <1804800000>; 501 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 502 }; 503 504 opp-1900800000 { 505 opp-hz = /bits/ 64 <1900800000>; 506 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 507 }; 508 509 opp-1977600000 { 510 opp-hz = /bits/ 64 <1977600000>; 511 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 512 }; 513 514 opp-2054400000 { 515 opp-hz = /bits/ 64 <2054400000>; 516 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 517 }; 518 519 opp-2131200000 { 520 opp-hz = /bits/ 64 <2131200000>; 521 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 522 }; 523 524 opp-2208000000 { 525 opp-hz = /bits/ 64 <2208000000>; 526 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 527 }; 528 529 opp-2284800000 { 530 opp-hz = /bits/ 64 <2284800000>; 531 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 532 }; 533 534 opp-2361600000 { 535 opp-hz = /bits/ 64 <2361600000>; 536 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 537 }; 538 539 }; 540 541 cpu4_opp_table: opp-table-cpu4 { 542 compatible = "operating-points-v2"; 543 opp-shared; 544 545 opp-844800000 { 546 opp-hz = /bits/ 64 <844800000>; 547 opp-peak-kBps = <(681600 * 4) (921600 * 32)>; 548 }; 549 550 opp-1113600000 { 551 opp-hz = /bits/ 64 <1113600000>; 552 opp-peak-kBps = <(1708800 * 4) (921600 * 32)>; 553 }; 554 555 opp-1209600000 { 556 opp-hz = /bits/ 64 <1209600000>; 557 opp-peak-kBps = <(2092800 * 4) (998400 * 32)>; 558 }; 559 560 opp-1305600000 { 561 opp-hz = /bits/ 64 <1305600000>; 562 opp-peak-kBps = <(2092800 * 4) (1075200 * 32)>; 563 }; 564 565 opp-1382400000 { 566 opp-hz = /bits/ 64 <1382400000>; 567 opp-peak-kBps = <(2092800 * 4) (1152000 * 32)>; 568 }; 569 570 opp-1459200000 { 571 opp-hz = /bits/ 64 <1459200000>; 572 opp-peak-kBps = <(2092800 * 4) (1228800 * 32)>; 573 }; 574 575 opp-1497600000 { 576 opp-hz = /bits/ 64 <1497600000>; 577 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 578 }; 579 580 opp-1574400000 { 581 opp-hz = /bits/ 64 <1574400000>; 582 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 583 }; 584 585 opp-1651200000 { 586 opp-hz = /bits/ 64 <1651200000>; 587 opp-peak-kBps = <(2736000 * 4) (1324800 * 32)>; 588 }; 589 590 opp-1728000000 { 591 opp-hz = /bits/ 64 <1728000000>; 592 opp-peak-kBps = <(2736000 * 4) (1401600 * 32)>; 593 }; 594 595 opp-1804800000 { 596 opp-hz = /bits/ 64 <1804800000>; 597 opp-peak-kBps = <(2736000 * 4) (1478400 * 32)>; 598 }; 599 600 opp-1881600000 { 601 opp-hz = /bits/ 64 <1881600000>; 602 opp-peak-kBps = <(3196800 * 4) (1555200 * 32)>; 603 }; 604 605 opp-1958400000 { 606 opp-hz = /bits/ 64 <1958400000>; 607 opp-peak-kBps = <(3196800 * 4) (1612800 * 32)>; 608 }; 609 }; 610 611 dummy_eud: dummy-sink { 612 compatible = "arm,coresight-dummy-sink"; 613 614 in-ports { 615 port { 616 eud_in: endpoint { 617 remote-endpoint = <&swao_rep_out1>; 618 }; 619 }; 620 }; 621 }; 622 623 firmware { 624 scm: scm { 625 compatible = "qcom,scm-qcs8300", "qcom,scm"; 626 qcom,dload-mode = <&tcsr 0x13000>; 627 }; 628 }; 629 630 memory@80000000 { 631 device_type = "memory"; 632 /* We expect the bootloader to fill in the size */ 633 reg = <0x0 0x80000000 0x0 0x0>; 634 }; 635 636 clk_virt: interconnect-0 { 637 compatible = "qcom,qcs8300-clk-virt"; 638 #interconnect-cells = <2>; 639 qcom,bcm-voters = <&apps_bcm_voter>; 640 }; 641 642 mc_virt: interconnect-1 { 643 compatible = "qcom,qcs8300-mc-virt"; 644 #interconnect-cells = <2>; 645 qcom,bcm-voters = <&apps_bcm_voter>; 646 }; 647 648 qup_opp_table: opp-table-qup { 649 compatible = "operating-points-v2"; 650 651 opp-120000000 { 652 opp-hz = /bits/ 64 <120000000>; 653 required-opps = <&rpmhpd_opp_svs_l1>; 654 }; 655 }; 656 657 pmu-a55 { 658 compatible = "arm,cortex-a55-pmu"; 659 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 660 }; 661 662 pmu-a78 { 663 compatible = "arm,cortex-a78-pmu"; 664 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 665 }; 666 667 psci { 668 compatible = "arm,psci-1.0"; 669 method = "smc"; 670 671 cpu_pd0: power-domain-cpu0 { 672 #power-domain-cells = <0>; 673 power-domains = <&cluster_pd0>; 674 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 675 }; 676 677 cpu_pd1: power-domain-cpu1 { 678 #power-domain-cells = <0>; 679 power-domains = <&cluster_pd0>; 680 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 681 }; 682 683 cpu_pd2: power-domain-cpu2 { 684 #power-domain-cells = <0>; 685 power-domains = <&cluster_pd0>; 686 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 687 }; 688 689 cpu_pd3: power-domain-cpu3 { 690 #power-domain-cells = <0>; 691 power-domains = <&cluster_pd0>; 692 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 693 }; 694 695 cpu_pd4: power-domain-cpu4 { 696 #power-domain-cells = <0>; 697 power-domains = <&cluster_pd1>; 698 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 699 }; 700 701 cpu_pd5: power-domain-cpu5 { 702 #power-domain-cells = <0>; 703 power-domains = <&cluster_pd1>; 704 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 705 }; 706 707 cpu_pd6: power-domain-cpu6 { 708 #power-domain-cells = <0>; 709 power-domains = <&cluster_pd1>; 710 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 711 }; 712 713 cpu_pd7: power-domain-cpu7 { 714 #power-domain-cells = <0>; 715 power-domains = <&cluster_pd1>; 716 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 717 }; 718 719 cluster_pd0: power-domain-cluster0 { 720 #power-domain-cells = <0>; 721 power-domains = <&system_pd>; 722 domain-idle-states = <&gold_cluster_sleep>; 723 }; 724 725 cluster_pd1: power-domain-cluster1 { 726 #power-domain-cells = <0>; 727 power-domains = <&system_pd>; 728 domain-idle-states = <&silver_cluster_sleep>; 729 }; 730 731 system_pd: power-domain-system { 732 #power-domain-cells = <0>; 733 domain-idle-states = <&system_sleep>; 734 }; 735 }; 736 737 reserved-memory { 738 #address-cells = <2>; 739 #size-cells = <2>; 740 ranges; 741 742 aop_image_mem: aop-image-region@90800000 { 743 reg = <0x0 0x90800000 0x0 0x60000>; 744 no-map; 745 }; 746 747 aop_cmd_db_mem: aop-cmd-db-region@90860000 { 748 compatible = "qcom,cmd-db"; 749 reg = <0x0 0x90860000 0x0 0x20000>; 750 no-map; 751 }; 752 753 smem_mem: smem@90900000 { 754 compatible = "qcom,smem"; 755 reg = <0x0 0x90900000 0x0 0x200000>; 756 no-map; 757 hwlocks = <&tcsr_mutex 3>; 758 }; 759 760 gunyah_md_mem: gunyah-md-region@91a80000 { 761 reg = <0x0 0x91a80000 0x0 0x80000>; 762 no-map; 763 }; 764 765 lpass_machine_learning_mem: lpass-machine-learning-region@93b00000 { 766 reg = <0x0 0x93b00000 0x0 0xf00000>; 767 no-map; 768 }; 769 770 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap-region@94a00000 { 771 reg = <0x0 0x94a00000 0x0 0x800000>; 772 no-map; 773 }; 774 775 camera_mem: camera-region@95200000 { 776 reg = <0x0 0x95200000 0x0 0x500000>; 777 no-map; 778 }; 779 780 adsp_mem: adsp-region@95c00000 { 781 no-map; 782 reg = <0x0 0x95c00000 0x0 0x1e00000>; 783 }; 784 785 q6_adsp_dtb_mem: q6-adsp-dtb-region@97a00000 { 786 reg = <0x0 0x97a00000 0x0 0x80000>; 787 no-map; 788 }; 789 790 q6_gpdsp_dtb_mem: q6-gpdsp-dtb-region@97a80000 { 791 reg = <0x0 0x97a80000 0x0 0x80000>; 792 no-map; 793 }; 794 795 gpdsp_mem: gpdsp-region@97b00000 { 796 reg = <0x0 0x97b00000 0x0 0x1e00000>; 797 no-map; 798 }; 799 800 q6_cdsp_dtb_mem: q6-cdsp-dtb-region@99900000 { 801 reg = <0x0 0x99900000 0x0 0x80000>; 802 no-map; 803 }; 804 805 cdsp_mem: cdsp-region@99980000 { 806 reg = <0x0 0x99980000 0x0 0x1e00000>; 807 no-map; 808 }; 809 810 gpu_microcode_mem: gpu-microcode-region@9b780000 { 811 reg = <0x0 0x9b780000 0x0 0x2000>; 812 no-map; 813 }; 814 815 cvp_mem: cvp-region@9b782000 { 816 reg = <0x0 0x9b782000 0x0 0x700000>; 817 no-map; 818 }; 819 820 video_mem: video-region@9be82000 { 821 reg = <0x0 0x9be82000 0x0 0x700000>; 822 no-map; 823 }; 824 }; 825 826 smp2p-adsp { 827 compatible = "qcom,smp2p"; 828 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 829 IPCC_MPROC_SIGNAL_SMP2P 830 IRQ_TYPE_EDGE_RISING>; 831 mboxes = <&ipcc IPCC_CLIENT_LPASS 832 IPCC_MPROC_SIGNAL_SMP2P>; 833 834 qcom,smem = <443>, <429>; 835 qcom,local-pid = <0>; 836 qcom,remote-pid = <2>; 837 838 smp2p_adsp_in: slave-kernel { 839 qcom,entry-name = "slave-kernel"; 840 interrupt-controller; 841 #interrupt-cells = <2>; 842 }; 843 844 smp2p_adsp_out: master-kernel { 845 qcom,entry-name = "master-kernel"; 846 #qcom,smem-state-cells = <1>; 847 }; 848 }; 849 850 smp2p-cdsp { 851 compatible = "qcom,smp2p"; 852 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 853 IPCC_MPROC_SIGNAL_SMP2P 854 IRQ_TYPE_EDGE_RISING>; 855 mboxes = <&ipcc IPCC_CLIENT_CDSP 856 IPCC_MPROC_SIGNAL_SMP2P>; 857 858 qcom,smem = <94>, <432>; 859 qcom,local-pid = <0>; 860 qcom,remote-pid = <5>; 861 862 smp2p_cdsp_in: slave-kernel { 863 qcom,entry-name = "slave-kernel"; 864 interrupt-controller; 865 #interrupt-cells = <2>; 866 }; 867 868 smp2p_cdsp_out: master-kernel { 869 qcom,entry-name = "master-kernel"; 870 #qcom,smem-state-cells = <1>; 871 }; 872 }; 873 874 smp2p-gpdsp { 875 compatible = "qcom,smp2p"; 876 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 877 IPCC_MPROC_SIGNAL_SMP2P 878 IRQ_TYPE_EDGE_RISING>; 879 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 880 IPCC_MPROC_SIGNAL_SMP2P>; 881 882 qcom,smem = <617>, <616>; 883 qcom,local-pid = <0>; 884 qcom,remote-pid = <17>; 885 886 smp2p_gpdsp_in: slave-kernel { 887 qcom,entry-name = "slave-kernel"; 888 interrupt-controller; 889 #interrupt-cells = <2>; 890 }; 891 892 smp2p_gpdsp_out: master-kernel { 893 qcom,entry-name = "master-kernel"; 894 #qcom,smem-state-cells = <1>; 895 }; 896 }; 897 898 soc: soc@0 { 899 compatible = "simple-bus"; 900 ranges = <0 0 0 0 0x10 0>; 901 #address-cells = <2>; 902 #size-cells = <2>; 903 904 gcc: clock-controller@100000 { 905 compatible = "qcom,qcs8300-gcc"; 906 reg = <0x0 0x00100000 0x0 0xc7018>; 907 #clock-cells = <1>; 908 #reset-cells = <1>; 909 #power-domain-cells = <1>; 910 clocks = <&rpmhcc RPMH_CXO_CLK>, 911 <&sleep_clk>, 912 <0>, 913 <0>, 914 <0>, 915 <0>, 916 <0>, 917 <0>, 918 <0>, 919 <0>; 920 }; 921 922 ipcc: mailbox@408000 { 923 compatible = "qcom,qcs8300-ipcc", "qcom,ipcc"; 924 reg = <0x0 0x408000 0x0 0x1000>; 925 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-controller; 927 #interrupt-cells = <3>; 928 #mbox-cells = <2>; 929 }; 930 931 qfprom: efuse@784000 { 932 compatible = "qcom,qcs8300-qfprom", "qcom,qfprom"; 933 reg = <0x0 0x00784000 0x0 0x2410>; 934 #address-cells = <1>; 935 #size-cells = <1>; 936 937 gpu_speed_bin: gpu_speed_bin@240c { 938 reg = <0x240c 0x1>; 939 bits = <0 8>; 940 }; 941 }; 942 943 gpi_dma0: dma-controller@900000 { 944 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 945 reg = <0x0 0x900000 0x0 0x60000>; 946 #dma-cells = <3>; 947 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 948 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 949 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 950 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 951 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 956 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 957 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 958 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 959 iommus = <&apps_smmu 0x416 0x0>; 960 dma-channels = <12>; 961 dma-channel-mask = <0xfff>; 962 dma-coherent; 963 status = "disabled"; 964 }; 965 966 qupv3_id_0: geniqup@9c0000 { 967 compatible = "qcom,geni-se-qup"; 968 reg = <0x0 0x9c0000 0x0 0x2000>; 969 ranges; 970 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 971 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 972 clock-names = "m-ahb", 973 "s-ahb"; 974 #address-cells = <2>; 975 #size-cells = <2>; 976 iommus = <&apps_smmu 0x403 0x0>; 977 dma-coherent; 978 status = "disabled"; 979 980 i2c0: i2c@980000 { 981 compatible = "qcom,geni-i2c"; 982 reg = <0x0 0x980000 0x0 0x4000>; 983 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 984 clock-names = "se"; 985 pinctrl-0 = <&qup_i2c0_data_clk>; 986 pinctrl-names = "default"; 987 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 988 #address-cells = <1>; 989 #size-cells = <0>; 990 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 991 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 992 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 993 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 994 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 995 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 996 interconnect-names = "qup-core", 997 "qup-config", 998 "qup-memory"; 999 power-domains = <&rpmhpd RPMHPD_CX>; 1000 required-opps = <&rpmhpd_opp_low_svs>; 1001 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1002 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1003 dma-names = "tx", 1004 "rx"; 1005 status = "disabled"; 1006 }; 1007 1008 spi0: spi@980000 { 1009 compatible = "qcom,geni-spi"; 1010 reg = <0x0 0x980000 0x0 0x4000>; 1011 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1012 clock-names = "se"; 1013 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1014 pinctrl-names = "default"; 1015 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1016 #address-cells = <1>; 1017 #size-cells = <0>; 1018 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1019 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1020 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1021 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1022 interconnect-names = "qup-core", 1023 "qup-config"; 1024 power-domains = <&rpmhpd RPMHPD_CX>; 1025 operating-points-v2 = <&qup_opp_table>; 1026 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1027 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1028 dma-names = "tx", 1029 "rx"; 1030 status = "disabled"; 1031 }; 1032 1033 uart0: serial@980000 { 1034 compatible = "qcom,geni-uart"; 1035 reg = <0x0 0x980000 0x0 0x4000>; 1036 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1037 clock-names = "se"; 1038 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, 1039 <&qup_uart0_tx>, <&qup_uart0_rx>; 1040 pinctrl-names = "default"; 1041 interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; 1042 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1043 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1044 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1045 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1046 interconnect-names = "qup-core", 1047 "qup-config"; 1048 power-domains = <&rpmhpd RPMHPD_CX>; 1049 operating-points-v2 = <&qup_opp_table>; 1050 status = "disabled"; 1051 }; 1052 1053 i2c1: i2c@984000 { 1054 compatible = "qcom,geni-i2c"; 1055 reg = <0x0 0x984000 0x0 0x4000>; 1056 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1057 clock-names = "se"; 1058 pinctrl-0 = <&qup_i2c1_data_clk>; 1059 pinctrl-names = "default"; 1060 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1061 #address-cells = <1>; 1062 #size-cells = <0>; 1063 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1064 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1065 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1066 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1067 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1068 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1069 interconnect-names = "qup-core", 1070 "qup-config", 1071 "qup-memory"; 1072 power-domains = <&rpmhpd RPMHPD_CX>; 1073 required-opps = <&rpmhpd_opp_low_svs>; 1074 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1075 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1076 dma-names = "tx", 1077 "rx"; 1078 status = "disabled"; 1079 }; 1080 1081 spi1: spi@984000 { 1082 compatible = "qcom,geni-spi"; 1083 reg = <0x0 0x984000 0x0 0x4000>; 1084 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1085 clock-names = "se"; 1086 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1087 pinctrl-names = "default"; 1088 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1089 #address-cells = <1>; 1090 #size-cells = <0>; 1091 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1092 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1093 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1094 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1095 interconnect-names = "qup-core", 1096 "qup-config"; 1097 power-domains = <&rpmhpd RPMHPD_CX>; 1098 operating-points-v2 = <&qup_opp_table>; 1099 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1100 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1101 dma-names = "tx", 1102 "rx"; 1103 status = "disabled"; 1104 }; 1105 1106 uart1: serial@984000 { 1107 compatible = "qcom,geni-uart"; 1108 reg = <0x0 0x984000 0x0 0x4000>; 1109 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1110 clock-names = "se"; 1111 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, 1112 <&qup_uart1_tx>, <&qup_uart1_rx>; 1113 pinctrl-names = "default"; 1114 interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; 1115 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1116 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1117 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1118 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1119 interconnect-names = "qup-core", 1120 "qup-config"; 1121 power-domains = <&rpmhpd RPMHPD_CX>; 1122 operating-points-v2 = <&qup_opp_table>; 1123 status = "disabled"; 1124 }; 1125 1126 i2c2: i2c@988000 { 1127 compatible = "qcom,geni-i2c"; 1128 reg = <0x0 0x988000 0x0 0x4000>; 1129 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1130 clock-names = "se"; 1131 pinctrl-0 = <&qup_i2c2_data_clk>; 1132 pinctrl-names = "default"; 1133 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1134 #address-cells = <1>; 1135 #size-cells = <0>; 1136 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1137 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1138 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1139 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1140 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1141 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1142 interconnect-names = "qup-core", 1143 "qup-config", 1144 "qup-memory"; 1145 power-domains = <&rpmhpd RPMHPD_CX>; 1146 required-opps = <&rpmhpd_opp_low_svs>; 1147 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1148 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1149 dma-names = "tx", 1150 "rx"; 1151 status = "disabled"; 1152 }; 1153 1154 spi2: spi@988000 { 1155 compatible = "qcom,geni-spi"; 1156 reg = <0x0 0x988000 0x0 0x4000>; 1157 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1158 clock-names = "se"; 1159 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1160 pinctrl-names = "default"; 1161 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1162 #address-cells = <1>; 1163 #size-cells = <0>; 1164 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1165 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1166 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1167 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1168 interconnect-names = "qup-core", 1169 "qup-config"; 1170 power-domains = <&rpmhpd RPMHPD_CX>; 1171 operating-points-v2 = <&qup_opp_table>; 1172 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1173 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1174 dma-names = "tx", 1175 "rx"; 1176 status = "disabled"; 1177 }; 1178 1179 uart2: serial@988000 { 1180 compatible = "qcom,geni-uart"; 1181 reg = <0x0 0x988000 0x0 0x4000>; 1182 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1183 clock-names = "se"; 1184 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, 1185 <&qup_uart2_tx>, <&qup_uart2_rx>; 1186 pinctrl-names = "default"; 1187 interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; 1188 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1189 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1190 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1191 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1192 interconnect-names = "qup-core", 1193 "qup-config"; 1194 power-domains = <&rpmhpd RPMHPD_CX>; 1195 operating-points-v2 = <&qup_opp_table>; 1196 status = "disabled"; 1197 }; 1198 1199 i2c3: i2c@98c000 { 1200 compatible = "qcom,geni-i2c"; 1201 reg = <0x0 0x98c000 0x0 0x4000>; 1202 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1203 clock-names = "se"; 1204 pinctrl-0 = <&qup_i2c3_data_clk>; 1205 pinctrl-names = "default"; 1206 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1207 #address-cells = <1>; 1208 #size-cells = <0>; 1209 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1210 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1211 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1212 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1213 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1214 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1215 interconnect-names = "qup-core", 1216 "qup-config", 1217 "qup-memory"; 1218 power-domains = <&rpmhpd RPMHPD_CX>; 1219 required-opps = <&rpmhpd_opp_low_svs>; 1220 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1221 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1222 dma-names = "tx", 1223 "rx"; 1224 status = "disabled"; 1225 }; 1226 1227 spi3: spi@98c000 { 1228 compatible = "qcom,geni-spi"; 1229 reg = <0x0 0x98c000 0x0 0x4000>; 1230 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1231 clock-names = "se"; 1232 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1233 pinctrl-names = "default"; 1234 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1238 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1239 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1240 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1241 interconnect-names = "qup-core", 1242 "qup-config"; 1243 power-domains = <&rpmhpd RPMHPD_CX>; 1244 operating-points-v2 = <&qup_opp_table>; 1245 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1246 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1247 dma-names = "tx", 1248 "rx"; 1249 status = "disabled"; 1250 }; 1251 1252 uart3: serial@98c000 { 1253 compatible = "qcom,geni-uart"; 1254 reg = <0x0 0x98c000 0x0 0x4000>; 1255 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1256 clock-names = "se"; 1257 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, 1258 <&qup_uart3_tx>, <&qup_uart3_rx>; 1259 pinctrl-names = "default"; 1260 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; 1261 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1262 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1263 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1264 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1265 interconnect-names = "qup-core", 1266 "qup-config"; 1267 power-domains = <&rpmhpd RPMHPD_CX>; 1268 operating-points-v2 = <&qup_opp_table>; 1269 status = "disabled"; 1270 }; 1271 1272 i2c4: i2c@990000 { 1273 compatible = "qcom,geni-i2c"; 1274 reg = <0x0 0x990000 0x0 0x4000>; 1275 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1276 clock-names = "se"; 1277 pinctrl-0 = <&qup_i2c4_data_clk>; 1278 pinctrl-names = "default"; 1279 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1283 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1284 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1285 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1286 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1287 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1288 interconnect-names = "qup-core", 1289 "qup-config", 1290 "qup-memory"; 1291 power-domains = <&rpmhpd RPMHPD_CX>; 1292 required-opps = <&rpmhpd_opp_low_svs>; 1293 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1294 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1295 dma-names = "tx", 1296 "rx"; 1297 status = "disabled"; 1298 }; 1299 1300 spi4: spi@990000 { 1301 compatible = "qcom,geni-spi"; 1302 reg = <0x0 0x990000 0x0 0x4000>; 1303 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1304 clock-names = "se"; 1305 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1306 pinctrl-names = "default"; 1307 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1308 #address-cells = <1>; 1309 #size-cells = <0>; 1310 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1311 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1312 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1313 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1314 interconnect-names = "qup-core", 1315 "qup-config"; 1316 power-domains = <&rpmhpd RPMHPD_CX>; 1317 operating-points-v2 = <&qup_opp_table>; 1318 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1319 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1320 dma-names = "tx", 1321 "rx"; 1322 status = "disabled"; 1323 }; 1324 1325 uart4: serial@990000 { 1326 compatible = "qcom,geni-uart"; 1327 reg = <0x0 0x990000 0x0 0x4000>; 1328 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1329 clock-names = "se"; 1330 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, 1331 <&qup_uart4_tx>, <&qup_uart4_rx>; 1332 pinctrl-names = "default"; 1333 interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; 1334 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1335 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1336 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1337 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1338 interconnect-names = "qup-core", 1339 "qup-config"; 1340 power-domains = <&rpmhpd RPMHPD_CX>; 1341 operating-points-v2 = <&qup_opp_table>; 1342 status = "disabled"; 1343 }; 1344 1345 i2c5: i2c@994000 { 1346 compatible = "qcom,geni-i2c"; 1347 reg = <0x0 0x994000 0x0 0x4000>; 1348 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1349 clock-names = "se"; 1350 pinctrl-0 = <&qup_i2c5_data_clk>; 1351 pinctrl-names = "default"; 1352 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1353 #address-cells = <1>; 1354 #size-cells = <0>; 1355 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1356 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1357 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1358 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1359 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1360 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1361 interconnect-names = "qup-core", 1362 "qup-config", 1363 "qup-memory"; 1364 power-domains = <&rpmhpd RPMHPD_CX>; 1365 required-opps = <&rpmhpd_opp_low_svs>; 1366 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1367 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1368 dma-names = "tx", 1369 "rx"; 1370 status = "disabled"; 1371 }; 1372 1373 spi5: spi@994000 { 1374 compatible = "qcom,geni-spi"; 1375 reg = <0x0 0x994000 0x0 0x4000>; 1376 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1377 clock-names = "se"; 1378 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1379 pinctrl-names = "default"; 1380 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1381 #address-cells = <1>; 1382 #size-cells = <0>; 1383 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1384 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1385 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1386 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1387 interconnect-names = "qup-core", 1388 "qup-config"; 1389 power-domains = <&rpmhpd RPMHPD_CX>; 1390 operating-points-v2 = <&qup_opp_table>; 1391 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1392 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1393 dma-names = "tx", 1394 "rx"; 1395 status = "disabled"; 1396 }; 1397 1398 uart5: serial@994000 { 1399 compatible = "qcom,geni-uart"; 1400 reg = <0x0 0x994000 0x0 0x4000>; 1401 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1402 clock-names = "se"; 1403 pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, 1404 <&qup_uart5_tx>, <&qup_uart5_rx>; 1405 pinctrl-names = "default"; 1406 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1408 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1409 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1410 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1411 interconnect-names = "qup-core", 1412 "qup-config"; 1413 power-domains = <&rpmhpd RPMHPD_CX>; 1414 operating-points-v2 = <&qup_opp_table>; 1415 status = "disabled"; 1416 }; 1417 1418 i2c6: i2c@998000 { 1419 compatible = "qcom,geni-i2c"; 1420 reg = <0x0 0x998000 0x0 0x4000>; 1421 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1422 clock-names = "se"; 1423 pinctrl-0 = <&qup_i2c6_data_clk>; 1424 pinctrl-names = "default"; 1425 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1426 #address-cells = <1>; 1427 #size-cells = <0>; 1428 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1429 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1430 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1431 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, 1432 <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS 1433 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1434 interconnect-names = "qup-core", 1435 "qup-config", 1436 "qup-memory"; 1437 power-domains = <&rpmhpd RPMHPD_CX>; 1438 required-opps = <&rpmhpd_opp_low_svs>; 1439 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1440 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1441 dma-names = "tx", 1442 "rx"; 1443 status = "disabled"; 1444 }; 1445 1446 spi6: spi@998000 { 1447 compatible = "qcom,geni-spi"; 1448 reg = <0x0 0x998000 0x0 0x4000>; 1449 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1450 clock-names = "se"; 1451 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1452 pinctrl-names = "default"; 1453 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1454 #address-cells = <1>; 1455 #size-cells = <0>; 1456 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1457 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1458 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1459 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1460 interconnect-names = "qup-core", 1461 "qup-config"; 1462 power-domains = <&rpmhpd RPMHPD_CX>; 1463 operating-points-v2 = <&qup_opp_table>; 1464 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1465 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1466 dma-names = "tx", 1467 "rx"; 1468 status = "disabled"; 1469 }; 1470 1471 uart6: serial@998000 { 1472 compatible = "qcom,geni-uart"; 1473 reg = <0x0 0x998000 0x0 0x4000>; 1474 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1475 clock-names = "se"; 1476 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, 1477 <&qup_uart6_tx>, <&qup_uart6_rx>; 1478 pinctrl-names = "default"; 1479 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; 1480 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1481 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1482 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1483 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1484 interconnect-names = "qup-core", 1485 "qup-config"; 1486 power-domains = <&rpmhpd RPMHPD_CX>; 1487 operating-points-v2 = <&qup_opp_table>; 1488 status = "disabled"; 1489 }; 1490 1491 uart7: serial@99c000 { 1492 compatible = "qcom,geni-debug-uart"; 1493 reg = <0x0 0x0099c000 0x0 0x4000>; 1494 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1495 clock-names = "se"; 1496 pinctrl-0 = <&qup_uart7_tx>, <&qup_uart7_rx>; 1497 pinctrl-names = "default"; 1498 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1499 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 1500 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 1501 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1502 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; 1503 interconnect-names = "qup-core", 1504 "qup-config"; 1505 power-domains = <&rpmhpd RPMHPD_CX>; 1506 operating-points-v2 = <&qup_opp_table>; 1507 status = "disabled"; 1508 }; 1509 }; 1510 1511 gpi_dma1: dma-controller@a00000 { 1512 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 1513 reg = <0x0 0xa00000 0x0 0x60000>; 1514 #dma-cells = <3>; 1515 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1516 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1517 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1518 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1519 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1520 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1521 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1522 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1523 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1524 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1525 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1526 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1527 iommus = <&apps_smmu 0x456 0x0>; 1528 dma-channels = <12>; 1529 dma-channel-mask = <0xfff>; 1530 dma-coherent; 1531 status = "disabled"; 1532 }; 1533 1534 qupv3_id_1: geniqup@ac0000 { 1535 compatible = "qcom,geni-se-qup"; 1536 reg = <0x0 0xac0000 0x0 0x2000>; 1537 ranges; 1538 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1539 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1540 clock-names = "m-ahb", 1541 "s-ahb"; 1542 #address-cells = <2>; 1543 #size-cells = <2>; 1544 iommus = <&apps_smmu 0x443 0x0>; 1545 dma-coherent; 1546 status = "disabled"; 1547 1548 i2c8: i2c@a80000 { 1549 compatible = "qcom,geni-i2c"; 1550 reg = <0x0 0xa80000 0x0 0x4000>; 1551 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1552 clock-names = "se"; 1553 pinctrl-0 = <&qup_i2c8_data_clk>; 1554 pinctrl-names = "default"; 1555 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1556 #address-cells = <1>; 1557 #size-cells = <0>; 1558 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1559 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1560 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1561 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1562 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1563 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1564 interconnect-names = "qup-core", 1565 "qup-config", 1566 "qup-memory"; 1567 power-domains = <&rpmhpd RPMHPD_CX>; 1568 required-opps = <&rpmhpd_opp_low_svs>; 1569 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1570 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1571 dma-names = "tx", 1572 "rx"; 1573 status = "disabled"; 1574 }; 1575 1576 spi8: spi@a80000 { 1577 compatible = "qcom,geni-spi"; 1578 reg = <0x0 0xa80000 0x0 0x4000>; 1579 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1580 clock-names = "se"; 1581 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1582 pinctrl-names = "default"; 1583 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1584 #address-cells = <1>; 1585 #size-cells = <0>; 1586 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1587 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1588 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1589 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1590 interconnect-names = "qup-core", 1591 "qup-config"; 1592 power-domains = <&rpmhpd RPMHPD_CX>; 1593 operating-points-v2 = <&qup_opp_table>; 1594 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1595 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1596 dma-names = "tx", 1597 "rx"; 1598 status = "disabled"; 1599 }; 1600 1601 uart8: serial@a80000 { 1602 compatible = "qcom,geni-uart"; 1603 reg = <0x0 0xa80000 0x0 0x4000>; 1604 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1605 clock-names = "se"; 1606 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, 1607 <&qup_uart8_tx>, <&qup_uart8_rx>; 1608 pinctrl-names = "default"; 1609 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1610 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1611 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1612 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1613 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1614 interconnect-names = "qup-core", 1615 "qup-config"; 1616 power-domains = <&rpmhpd RPMHPD_CX>; 1617 operating-points-v2 = <&qup_opp_table>; 1618 status = "disabled"; 1619 }; 1620 1621 i2c9: i2c@a84000 { 1622 compatible = "qcom,geni-i2c"; 1623 reg = <0x0 0xa84000 0x0 0x4000>; 1624 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1625 clock-names = "se"; 1626 pinctrl-0 = <&qup_i2c9_data_clk>; 1627 pinctrl-names = "default"; 1628 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1629 #address-cells = <1>; 1630 #size-cells = <0>; 1631 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1632 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1633 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1634 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1635 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1636 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1637 interconnect-names = "qup-core", 1638 "qup-config", 1639 "qup-memory"; 1640 power-domains = <&rpmhpd RPMHPD_CX>; 1641 required-opps = <&rpmhpd_opp_low_svs>; 1642 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1643 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1644 dma-names = "tx", 1645 "rx"; 1646 status = "disabled"; 1647 }; 1648 1649 spi9: spi@a84000 { 1650 compatible = "qcom,geni-spi"; 1651 reg = <0x0 0xa84000 0x0 0x4000>; 1652 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1653 clock-names = "se"; 1654 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1655 pinctrl-names = "default"; 1656 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1657 #address-cells = <1>; 1658 #size-cells = <0>; 1659 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1660 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1661 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1662 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1663 interconnect-names = "qup-core", 1664 "qup-config"; 1665 power-domains = <&rpmhpd RPMHPD_CX>; 1666 operating-points-v2 = <&qup_opp_table>; 1667 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1668 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1669 dma-names = "tx", 1670 "rx"; 1671 status = "disabled"; 1672 }; 1673 1674 uart9: serial@a84000 { 1675 compatible = "qcom,geni-uart"; 1676 reg = <0x0 0xa84000 0x0 0x4000>; 1677 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1678 clock-names = "se"; 1679 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, 1680 <&qup_uart9_tx>, <&qup_uart9_rx>; 1681 pinctrl-names = "default"; 1682 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1683 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1684 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1685 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1686 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1687 interconnect-names = "qup-core", 1688 "qup-config"; 1689 power-domains = <&rpmhpd RPMHPD_CX>; 1690 operating-points-v2 = <&qup_opp_table>; 1691 status = "disabled"; 1692 }; 1693 1694 i2c10: i2c@a88000 { 1695 compatible = "qcom,geni-i2c"; 1696 reg = <0x0 0xa88000 0x0 0x4000>; 1697 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1698 clock-names = "se"; 1699 pinctrl-0 = <&qup_i2c10_data_clk>; 1700 pinctrl-names = "default"; 1701 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1702 #address-cells = <1>; 1703 #size-cells = <0>; 1704 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1705 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1706 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1707 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1708 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1709 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1710 interconnect-names = "qup-core", 1711 "qup-config", 1712 "qup-memory"; 1713 power-domains = <&rpmhpd RPMHPD_CX>; 1714 required-opps = <&rpmhpd_opp_low_svs>; 1715 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1716 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1717 dma-names = "tx", 1718 "rx"; 1719 status = "disabled"; 1720 }; 1721 1722 spi10: spi@a88000 { 1723 compatible = "qcom,geni-spi"; 1724 reg = <0x0 0xa88000 0x0 0x4000>; 1725 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1726 clock-names = "se"; 1727 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1728 pinctrl-names = "default"; 1729 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1730 #address-cells = <1>; 1731 #size-cells = <0>; 1732 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1733 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1734 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1735 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1736 interconnect-names = "qup-core", 1737 "qup-config"; 1738 power-domains = <&rpmhpd RPMHPD_CX>; 1739 operating-points-v2 = <&qup_opp_table>; 1740 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1741 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1742 dma-names = "tx", 1743 "rx"; 1744 status = "disabled"; 1745 }; 1746 1747 uart10: serial@a88000 { 1748 compatible = "qcom,geni-uart"; 1749 reg = <0x0 0xa88000 0x0 0x4000>; 1750 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1751 clock-names = "se"; 1752 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, 1753 <&qup_uart10_tx>, <&qup_uart10_rx>; 1754 pinctrl-names = "default"; 1755 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1756 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1757 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1758 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1759 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1760 interconnect-names = "qup-core", 1761 "qup-config"; 1762 power-domains = <&rpmhpd RPMHPD_CX>; 1763 operating-points-v2 = <&qup_opp_table>; 1764 status = "disabled"; 1765 }; 1766 1767 i2c11: i2c@a8c000 { 1768 compatible = "qcom,geni-i2c"; 1769 reg = <0x0 0xa8c000 0x0 0x4000>; 1770 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1771 clock-names = "se"; 1772 pinctrl-0 = <&qup_i2c11_data_clk>; 1773 pinctrl-names = "default"; 1774 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1778 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1779 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1780 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1781 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1782 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1783 interconnect-names = "qup-core", 1784 "qup-config", 1785 "qup-memory"; 1786 power-domains = <&rpmhpd RPMHPD_CX>; 1787 required-opps = <&rpmhpd_opp_low_svs>; 1788 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1789 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1790 dma-names = "tx", 1791 "rx"; 1792 status = "disabled"; 1793 }; 1794 1795 uart11: serial@a8c000 { 1796 compatible = "qcom,geni-uart"; 1797 reg = <0x0 0xa8c000 0x0 0x4000>; 1798 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1799 clock-names = "se"; 1800 pinctrl-0 = <&qup_uart11_tx>, <&qup_uart11_rx>; 1801 pinctrl-names = "default"; 1802 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1803 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1804 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1805 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1806 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1807 interconnect-names = "qup-core", 1808 "qup-config"; 1809 power-domains = <&rpmhpd RPMHPD_CX>; 1810 operating-points-v2 = <&qup_opp_table>; 1811 status = "disabled"; 1812 }; 1813 1814 i2c12: i2c@a90000 { 1815 compatible = "qcom,geni-i2c"; 1816 reg = <0x0 0xa90000 0x0 0x4000>; 1817 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1818 clock-names = "se"; 1819 pinctrl-0 = <&qup_i2c12_data_clk>; 1820 pinctrl-names = "default"; 1821 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1822 #address-cells = <1>; 1823 #size-cells = <0>; 1824 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1825 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1826 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1827 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1828 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1829 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1830 interconnect-names = "qup-core", 1831 "qup-config", 1832 "qup-memory"; 1833 power-domains = <&rpmhpd RPMHPD_CX>; 1834 required-opps = <&rpmhpd_opp_low_svs>; 1835 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1836 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1837 dma-names = "tx", 1838 "rx"; 1839 status = "disabled"; 1840 }; 1841 1842 spi12: spi@a90000 { 1843 compatible = "qcom,geni-spi"; 1844 reg = <0x0 0xa90000 0x0 0x4000>; 1845 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1846 clock-names = "se"; 1847 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1848 pinctrl-names = "default"; 1849 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1850 #address-cells = <1>; 1851 #size-cells = <0>; 1852 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1853 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1854 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1855 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1856 interconnect-names = "qup-core", 1857 "qup-config"; 1858 power-domains = <&rpmhpd RPMHPD_CX>; 1859 operating-points-v2 = <&qup_opp_table>; 1860 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1861 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1862 dma-names = "tx", 1863 "rx"; 1864 status = "disabled"; 1865 }; 1866 1867 uart12: serial@a90000 { 1868 compatible = "qcom,geni-uart"; 1869 reg = <0x0 0xa90000 0x0 0x4000>; 1870 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1871 clock-names = "se"; 1872 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, 1873 <&qup_uart12_tx>, <&qup_uart12_rx>; 1874 pinctrl-names = "default"; 1875 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1876 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1877 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1878 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1879 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1880 interconnect-names = "qup-core", 1881 "qup-config"; 1882 power-domains = <&rpmhpd RPMHPD_CX>; 1883 operating-points-v2 = <&qup_opp_table>; 1884 status = "disabled"; 1885 }; 1886 1887 i2c13: i2c@a94000 { 1888 compatible = "qcom,geni-i2c"; 1889 reg = <0x0 0xa94000 0x0 0x4000>; 1890 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1891 clock-names = "se"; 1892 pinctrl-0 = <&qup_i2c13_data_clk>; 1893 pinctrl-names = "default"; 1894 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1895 #address-cells = <1>; 1896 #size-cells = <0>; 1897 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1898 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1899 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1900 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1901 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1902 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1903 interconnect-names = "qup-core", 1904 "qup-config", 1905 "qup-memory"; 1906 power-domains = <&rpmhpd RPMHPD_CX>; 1907 required-opps = <&rpmhpd_opp_low_svs>; 1908 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1909 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1910 dma-names = "tx", 1911 "rx"; 1912 status = "disabled"; 1913 }; 1914 1915 spi13: spi@a94000 { 1916 compatible = "qcom,geni-spi"; 1917 reg = <0x0 0xa94000 0x0 0x4000>; 1918 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1919 clock-names = "se"; 1920 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1921 pinctrl-names = "default"; 1922 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1923 #address-cells = <1>; 1924 #size-cells = <0>; 1925 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1926 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1927 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1928 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1929 interconnect-names = "qup-core", 1930 "qup-config"; 1931 power-domains = <&rpmhpd RPMHPD_CX>; 1932 operating-points-v2 = <&qup_opp_table>; 1933 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1934 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1935 dma-names = "tx", 1936 "rx"; 1937 status = "disabled"; 1938 }; 1939 1940 uart13: serial@a94000 { 1941 compatible = "qcom,geni-uart"; 1942 reg = <0x0 0xa94000 0x0 0x4000>; 1943 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1944 clock-names = "se"; 1945 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, 1946 <&qup_uart13_tx>, <&qup_uart13_rx>; 1947 pinctrl-names = "default"; 1948 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1949 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1950 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1951 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1952 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 1953 interconnect-names = "qup-core", 1954 "qup-config"; 1955 power-domains = <&rpmhpd RPMHPD_CX>; 1956 operating-points-v2 = <&qup_opp_table>; 1957 status = "disabled"; 1958 }; 1959 1960 i2c14: i2c@a98000 { 1961 compatible = "qcom,geni-i2c"; 1962 reg = <0x0 0xa98000 0x0 0x4000>; 1963 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1964 clock-names = "se"; 1965 pinctrl-0 = <&qup_i2c14_data_clk>; 1966 pinctrl-names = "default"; 1967 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1968 #address-cells = <1>; 1969 #size-cells = <0>; 1970 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1971 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1972 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 1973 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 1974 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1975 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1976 interconnect-names = "qup-core", 1977 "qup-config", 1978 "qup-memory"; 1979 power-domains = <&rpmhpd RPMHPD_CX>; 1980 required-opps = <&rpmhpd_opp_low_svs>; 1981 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1982 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1983 dma-names = "tx", 1984 "rx"; 1985 status = "disabled"; 1986 }; 1987 1988 spi14: spi@a98000 { 1989 compatible = "qcom,geni-spi"; 1990 reg = <0x0 0xa98000 0x0 0x4000>; 1991 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1992 clock-names = "se"; 1993 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1994 pinctrl-names = "default"; 1995 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1999 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2000 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2001 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2002 interconnect-names = "qup-core", 2003 "qup-config"; 2004 power-domains = <&rpmhpd RPMHPD_CX>; 2005 operating-points-v2 = <&qup_opp_table>; 2006 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2007 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2008 dma-names = "tx", 2009 "rx"; 2010 status = "disabled"; 2011 }; 2012 2013 uart14: serial@a98000 { 2014 compatible = "qcom,geni-uart"; 2015 reg = <0x0 0xa98000 0x0 0x4000>; 2016 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2017 clock-names = "se"; 2018 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, 2019 <&qup_uart14_tx>, <&qup_uart14_rx>; 2020 pinctrl-names = "default"; 2021 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 2022 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2023 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2024 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2025 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2026 interconnect-names = "qup-core", 2027 "qup-config"; 2028 power-domains = <&rpmhpd RPMHPD_CX>; 2029 operating-points-v2 = <&qup_opp_table>; 2030 status = "disabled"; 2031 }; 2032 2033 i2c15: i2c@a9c000 { 2034 compatible = "qcom,geni-i2c"; 2035 reg = <0x0 0xa9c000 0x0 0x4000>; 2036 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2037 clock-names = "se"; 2038 pinctrl-0 = <&qup_i2c15_data_clk>; 2039 pinctrl-names = "default"; 2040 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2041 #address-cells = <1>; 2042 #size-cells = <0>; 2043 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2044 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2045 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2046 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, 2047 <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 2048 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2049 interconnect-names = "qup-core", 2050 "qup-config", 2051 "qup-memory"; 2052 power-domains = <&rpmhpd RPMHPD_CX>; 2053 required-opps = <&rpmhpd_opp_low_svs>; 2054 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2055 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2056 dma-names = "tx", 2057 "rx"; 2058 status = "disabled"; 2059 }; 2060 2061 spi15: spi@a9c000 { 2062 compatible = "qcom,geni-spi"; 2063 reg = <0x0 0xa9c000 0x0 0x4000>; 2064 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2065 clock-names = "se"; 2066 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2067 pinctrl-names = "default"; 2068 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2069 #address-cells = <1>; 2070 #size-cells = <0>; 2071 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2072 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2073 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2074 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2075 interconnect-names = "qup-core", 2076 "qup-config"; 2077 power-domains = <&rpmhpd RPMHPD_CX>; 2078 operating-points-v2 = <&qup_opp_table>; 2079 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2080 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2081 dma-names = "tx", 2082 "rx"; 2083 status = "disabled"; 2084 }; 2085 2086 uart15: serial@a9c000 { 2087 compatible = "qcom,geni-uart"; 2088 reg = <0x0 0xa9c000 0x0 0x4000>; 2089 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2090 clock-names = "se"; 2091 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, 2092 <&qup_uart15_tx>, <&qup_uart15_rx>; 2093 pinctrl-names = "default"; 2094 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 2095 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 2096 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 2097 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2098 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; 2099 interconnect-names = "qup-core", 2100 "qup-config"; 2101 power-domains = <&rpmhpd RPMHPD_CX>; 2102 operating-points-v2 = <&qup_opp_table>; 2103 status = "disabled"; 2104 }; 2105 }; 2106 2107 gpi_dma3: dma-controller@b00000 { 2108 compatible = "qcom,qcs8300-gpi-dma", "qcom,sm6350-gpi-dma"; 2109 reg = <0x0 0xb00000 0x0 0x60000>; 2110 #dma-cells = <3>; 2111 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2112 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 2113 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, 2114 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>; 2115 iommus = <&apps_smmu 0x56 0x0>; 2116 dma-channels = <4>; 2117 dma-channel-mask = <0xf>; 2118 dma-coherent; 2119 status = "disabled"; 2120 }; 2121 2122 qupv3_id_3: geniqup@bc0000 { 2123 compatible = "qcom,geni-se-qup"; 2124 reg = <0x0 0xbc0000 0x0 0x2000>; 2125 ranges; 2126 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 2127 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 2128 clock-names = "m-ahb", 2129 "s-ahb"; 2130 #address-cells = <2>; 2131 #size-cells = <2>; 2132 iommus = <&apps_smmu 0x43 0x0>; 2133 dma-coherent; 2134 status = "disabled"; 2135 2136 i2c16: i2c@b80000 { 2137 compatible = "qcom,geni-i2c"; 2138 reg = <0x0 0xb80000 0x0 0x4000>; 2139 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2140 clock-names = "se"; 2141 pinctrl-0 = <&qup_i2c16_data_clk>; 2142 pinctrl-names = "default"; 2143 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2144 #address-cells = <1>; 2145 #size-cells = <0>; 2146 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2147 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2148 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2149 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, 2150 <&aggre2_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 2151 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2152 interconnect-names = "qup-core", 2153 "qup-config", 2154 "qup-memory"; 2155 power-domains = <&rpmhpd RPMHPD_CX>; 2156 required-opps = <&rpmhpd_opp_low_svs>; 2157 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 2158 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 2159 dma-names = "tx", 2160 "rx"; 2161 status = "disabled"; 2162 }; 2163 2164 spi16: spi@b80000 { 2165 compatible = "qcom,geni-spi"; 2166 reg = <0x0 0xb80000 0x0 0x4000>; 2167 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2168 clock-names = "se"; 2169 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 2170 pinctrl-names = "default"; 2171 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2172 #address-cells = <1>; 2173 #size-cells = <0>; 2174 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2175 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2176 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2177 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2178 interconnect-names = "qup-core", 2179 "qup-config"; 2180 power-domains = <&rpmhpd RPMHPD_CX>; 2181 operating-points-v2 = <&qup_opp_table>; 2182 dmas = <&gpi_dma3 0 0 QCOM_GPI_SPI>, 2183 <&gpi_dma3 1 0 QCOM_GPI_SPI>; 2184 dma-names = "tx", 2185 "rx"; 2186 status = "disabled"; 2187 }; 2188 2189 uart16: serial@b80000 { 2190 compatible = "qcom,geni-uart"; 2191 reg = <0x0 0xb80000 0x0 0x4000>; 2192 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 2193 clock-names = "se"; 2194 pinctrl-0 = <&qup_uart16_cts>, <&qup_uart16_rts>, 2195 <&qup_uart16_tx>, <&qup_uart16_rx>; 2196 pinctrl-names = "default"; 2197 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 2198 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 2199 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 2200 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2201 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; 2202 interconnect-names = "qup-core", 2203 "qup-config"; 2204 power-domains = <&rpmhpd RPMHPD_CX>; 2205 operating-points-v2 = <&qup_opp_table>; 2206 status = "disabled"; 2207 }; 2208 }; 2209 2210 rng: rng@10d2000 { 2211 compatible = "qcom,qcs8300-trng", "qcom,trng"; 2212 reg = <0x0 0x010d2000 0x0 0x1000>; 2213 }; 2214 2215 config_noc: interconnect@14c0000 { 2216 compatible = "qcom,qcs8300-config-noc"; 2217 reg = <0x0 0x014c0000 0x0 0x13080>; 2218 #interconnect-cells = <2>; 2219 qcom,bcm-voters = <&apps_bcm_voter>; 2220 }; 2221 2222 system_noc: interconnect@1680000 { 2223 compatible = "qcom,qcs8300-system-noc"; 2224 reg = <0x0 0x01680000 0x0 0x15080>; 2225 #interconnect-cells = <2>; 2226 qcom,bcm-voters = <&apps_bcm_voter>; 2227 }; 2228 2229 aggre1_noc: interconnect@16c0000 { 2230 compatible = "qcom,qcs8300-aggre1-noc"; 2231 reg = <0x0 0x016c0000 0x0 0x17080>; 2232 #interconnect-cells = <2>; 2233 qcom,bcm-voters = <&apps_bcm_voter>; 2234 }; 2235 2236 aggre2_noc: interconnect@1700000 { 2237 compatible = "qcom,qcs8300-aggre2-noc"; 2238 reg = <0x0 0x01700000 0x0 0x1a080>; 2239 #interconnect-cells = <2>; 2240 qcom,bcm-voters = <&apps_bcm_voter>; 2241 }; 2242 2243 pcie_anoc: interconnect@1760000 { 2244 compatible = "qcom,qcs8300-pcie-anoc"; 2245 reg = <0x0 0x01760000 0x0 0xc080>; 2246 #interconnect-cells = <2>; 2247 qcom,bcm-voters = <&apps_bcm_voter>; 2248 }; 2249 2250 gpdsp_anoc: interconnect@1780000 { 2251 compatible = "qcom,qcs8300-gpdsp-anoc"; 2252 reg = <0x0 0x01780000 0x0 0xd080>; 2253 #interconnect-cells = <2>; 2254 qcom,bcm-voters = <&apps_bcm_voter>; 2255 }; 2256 2257 mmss_noc: interconnect@17a0000 { 2258 compatible = "qcom,qcs8300-mmss-noc"; 2259 reg = <0x0 0x017a0000 0x0 0x40000>; 2260 #interconnect-cells = <2>; 2261 qcom,bcm-voters = <&apps_bcm_voter>; 2262 }; 2263 2264 ufs_mem_hc: ufs@1d84000 { 2265 compatible = "qcom,qcs8300-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; 2266 reg = <0x0 0x01d84000 0x0 0x3000>; 2267 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2268 phys = <&ufs_mem_phy>; 2269 phy-names = "ufsphy"; 2270 lanes-per-direction = <2>; 2271 #reset-cells = <1>; 2272 resets = <&gcc GCC_UFS_PHY_BCR>; 2273 reset-names = "rst"; 2274 2275 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2276 required-opps = <&rpmhpd_opp_nom>; 2277 2278 iommus = <&apps_smmu 0x100 0x0>; 2279 dma-coherent; 2280 2281 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2282 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2283 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2284 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2285 interconnect-names = "ufs-ddr", 2286 "cpu-ufs"; 2287 2288 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2289 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2290 <&gcc GCC_UFS_PHY_AHB_CLK>, 2291 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2292 <&rpmhcc RPMH_CXO_CLK>, 2293 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2294 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2295 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2296 clock-names = "core_clk", 2297 "bus_aggr_clk", 2298 "iface_clk", 2299 "core_clk_unipro", 2300 "ref_clk", 2301 "tx_lane0_sync_clk", 2302 "rx_lane0_sync_clk", 2303 "rx_lane1_sync_clk"; 2304 freq-table-hz = <75000000 300000000>, 2305 <0 0>, 2306 <0 0>, 2307 <75000000 300000000>, 2308 <0 0>, 2309 <0 0>, 2310 <0 0>, 2311 <0 0>; 2312 qcom,ice = <&ice>; 2313 status = "disabled"; 2314 }; 2315 2316 ufs_mem_phy: phy@1d87000 { 2317 compatible = "qcom,qcs8300-qmp-ufs-phy", "qcom,sa8775p-qmp-ufs-phy"; 2318 reg = <0x0 0x01d87000 0x0 0xe10>; 2319 /* 2320 * Yes, GCC_EDP_REF_CLKREF_EN is correct in qref. It 2321 * enables the CXO clock to eDP *and* UFS PHY. 2322 */ 2323 clocks = <&rpmhcc RPMH_CXO_CLK>, 2324 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2325 <&gcc GCC_EDP_REF_CLKREF_EN>; 2326 clock-names = "ref", 2327 "ref_aux", 2328 "qref"; 2329 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2330 2331 resets = <&ufs_mem_hc 0>; 2332 reset-names = "ufsphy"; 2333 2334 #phy-cells = <0>; 2335 status = "disabled"; 2336 }; 2337 2338 cryptobam: dma-controller@1dc4000 { 2339 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2340 reg = <0x0 0x01dc4000 0x0 0x28000>; 2341 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2342 #dma-cells = <1>; 2343 qcom,ee = <0>; 2344 qcom,controlled-remotely; 2345 num-channels = <20>; 2346 qcom,num-ees = <4>; 2347 iommus = <&apps_smmu 0x480 0x00>, 2348 <&apps_smmu 0x481 0x00>; 2349 }; 2350 2351 ice: crypto@1d88000 { 2352 compatible = "qcom,qcs8300-inline-crypto-engine", 2353 "qcom,inline-crypto-engine"; 2354 reg = <0x0 0x01d88000 0x0 0x18000>; 2355 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2356 }; 2357 2358 tcsr_mutex: hwlock@1f40000 { 2359 compatible = "qcom,tcsr-mutex"; 2360 reg = <0x0 0x01f40000 0x0 0x20000>; 2361 #hwlock-cells = <1>; 2362 }; 2363 2364 tcsr: syscon@1fc0000 { 2365 compatible = "qcom,qcs8300-tcsr", "syscon"; 2366 reg = <0x0 0x1fc0000 0x0 0x30000>; 2367 }; 2368 2369 remoteproc_adsp: remoteproc@3000000 { 2370 compatible = "qcom,qcs8300-adsp-pas", "qcom,sa8775p-adsp-pas"; 2371 reg = <0x0 0x3000000 0x0 0x00100>; 2372 2373 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2374 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2375 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2376 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2377 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; 2378 interrupt-names = "wdog", 2379 "fatal", 2380 "ready", 2381 "handover", 2382 "stop-ack"; 2383 2384 clocks = <&rpmhcc RPMH_CXO_CLK>; 2385 clock-names = "xo"; 2386 2387 power-domains = <&rpmhpd RPMHPD_LCX>, 2388 <&rpmhpd RPMHPD_LMX>; 2389 power-domain-names = "lcx", 2390 "lmx"; 2391 2392 memory-region = <&adsp_mem>; 2393 2394 qcom,qmp = <&aoss_qmp>; 2395 2396 qcom,smem-states = <&smp2p_adsp_out 0>; 2397 qcom,smem-state-names = "stop"; 2398 2399 status = "disabled"; 2400 2401 remoteproc_adsp_glink: glink-edge { 2402 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 2403 IPCC_MPROC_SIGNAL_GLINK_QMP 2404 IRQ_TYPE_EDGE_RISING>; 2405 mboxes = <&ipcc IPCC_CLIENT_LPASS 2406 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2407 2408 label = "lpass"; 2409 qcom,remote-pid = <2>; 2410 2411 fastrpc { 2412 compatible = "qcom,fastrpc"; 2413 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2414 label = "adsp"; 2415 memory-region = <&adsp_rpc_remote_heap_mem>; 2416 qcom,vmids = <QCOM_SCM_VMID_LPASS 2417 QCOM_SCM_VMID_ADSP_HEAP>; 2418 #address-cells = <1>; 2419 #size-cells = <0>; 2420 2421 compute-cb@3 { 2422 compatible = "qcom,fastrpc-compute-cb"; 2423 reg = <3>; 2424 iommus = <&apps_smmu 0x2003 0x0>; 2425 dma-coherent; 2426 }; 2427 2428 compute-cb@4 { 2429 compatible = "qcom,fastrpc-compute-cb"; 2430 reg = <4>; 2431 iommus = <&apps_smmu 0x2004 0x0>; 2432 dma-coherent; 2433 }; 2434 2435 compute-cb@5 { 2436 compatible = "qcom,fastrpc-compute-cb"; 2437 reg = <5>; 2438 iommus = <&apps_smmu 0x2005 0x0>; 2439 dma-coherent; 2440 }; 2441 }; 2442 2443 gpr { 2444 compatible = "qcom,gpr"; 2445 qcom,glink-channels = "adsp_apps"; 2446 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2447 qcom,intents = <512 20>; 2448 #address-cells = <1>; 2449 #size-cells = <0>; 2450 2451 q6apm: service@1 { 2452 compatible = "qcom,q6apm"; 2453 reg = <GPR_APM_MODULE_IID>; 2454 #sound-dai-cells = <0>; 2455 qcom,protection-domain = "avs/audio", 2456 "msm/adsp/audio_pd"; 2457 2458 q6apmbedai: bedais { 2459 compatible = "qcom,q6apm-lpass-dais"; 2460 #sound-dai-cells = <1>; 2461 }; 2462 2463 q6apmdai: dais { 2464 compatible = "qcom,q6apm-dais"; 2465 iommus = <&apps_smmu 0x2001 0x0>; 2466 }; 2467 }; 2468 2469 q6prm: service@2 { 2470 compatible = "qcom,q6prm"; 2471 reg = <GPR_PRM_MODULE_IID>; 2472 qcom,protection-domain = "avs/audio", 2473 "msm/adsp/audio_pd"; 2474 2475 q6prmcc: clock-controller { 2476 compatible = "qcom,q6prm-lpass-clocks"; 2477 #clock-cells = <2>; 2478 }; 2479 }; 2480 }; 2481 }; 2482 }; 2483 2484 lpass_ag_noc: interconnect@3c40000 { 2485 compatible = "qcom,qcs8300-lpass-ag-noc"; 2486 reg = <0x0 0x03c40000 0x0 0x17200>; 2487 #interconnect-cells = <2>; 2488 qcom,bcm-voters = <&apps_bcm_voter>; 2489 }; 2490 2491 stm@4002000 { 2492 compatible = "arm,coresight-stm", "arm,primecell"; 2493 reg = <0x0 0x04002000 0x0 0x1000>, 2494 <0x0 0x16280000 0x0 0x180000>; 2495 reg-names = "stm-base", 2496 "stm-stimulus-base"; 2497 2498 clocks = <&aoss_qmp>; 2499 clock-names = "apb_pclk"; 2500 2501 out-ports { 2502 port { 2503 stm_out: endpoint { 2504 remote-endpoint = <&funnel0_in7>; 2505 }; 2506 }; 2507 }; 2508 }; 2509 2510 tpda@4004000 { 2511 compatible = "qcom,coresight-tpda", "arm,primecell"; 2512 reg = <0x0 0x04004000 0x0 0x1000>; 2513 2514 clocks = <&aoss_qmp>; 2515 clock-names = "apb_pclk"; 2516 2517 in-ports { 2518 #address-cells = <1>; 2519 #size-cells = <0>; 2520 2521 port@1 { 2522 reg = <1>; 2523 2524 qdss_tpda_in1: endpoint { 2525 remote-endpoint = <&qdss_tpdm1_out>; 2526 }; 2527 }; 2528 }; 2529 2530 out-ports { 2531 port { 2532 qdss_tpda_out: endpoint { 2533 remote-endpoint = <&funnel0_in6>; 2534 }; 2535 }; 2536 }; 2537 }; 2538 2539 tpdm@400f000 { 2540 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2541 reg = <0x0 0x0400f000 0x0 0x1000>; 2542 2543 clocks = <&aoss_qmp>; 2544 clock-names = "apb_pclk"; 2545 2546 qcom,cmb-element-bits = <32>; 2547 qcom,cmb-msrs-num = <32>; 2548 2549 out-ports { 2550 port { 2551 qdss_tpdm1_out: endpoint { 2552 remote-endpoint = <&qdss_tpda_in1>; 2553 }; 2554 }; 2555 }; 2556 }; 2557 2558 funnel@4041000 { 2559 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2560 reg = <0x0 0x04041000 0x0 0x1000>; 2561 2562 clocks = <&aoss_qmp>; 2563 clock-names = "apb_pclk"; 2564 2565 in-ports { 2566 #address-cells = <1>; 2567 #size-cells = <0>; 2568 2569 port@6 { 2570 reg = <6>; 2571 2572 funnel0_in6: endpoint { 2573 remote-endpoint = <&qdss_tpda_out>; 2574 }; 2575 }; 2576 2577 port@7 { 2578 reg = <7>; 2579 2580 funnel0_in7: endpoint { 2581 remote-endpoint = <&stm_out>; 2582 }; 2583 }; 2584 }; 2585 2586 out-ports { 2587 port { 2588 funnel0_out: endpoint { 2589 remote-endpoint = <&qdss_funnel_in0>; 2590 }; 2591 }; 2592 }; 2593 }; 2594 2595 funnel@4042000 { 2596 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2597 reg = <0x0 0x04042000 0x0 0x1000>; 2598 2599 clocks = <&aoss_qmp>; 2600 clock-names = "apb_pclk"; 2601 2602 in-ports { 2603 #address-cells = <1>; 2604 #size-cells = <0>; 2605 2606 port@4 { 2607 reg = <4>; 2608 2609 funnel1_in4: endpoint { 2610 remote-endpoint = <&apss_funnel1_out>; 2611 }; 2612 }; 2613 2614 port@5 { 2615 reg = <5>; 2616 2617 funnel1_in5: endpoint { 2618 remote-endpoint = <&dlct0_funnel_out>; 2619 }; 2620 }; 2621 2622 port@6 { 2623 reg = <6>; 2624 2625 funnel1_in6: endpoint { 2626 remote-endpoint = <&dlmm_funnel_out>; 2627 }; 2628 }; 2629 2630 port@7 { 2631 reg = <7>; 2632 2633 funnel1_in7: endpoint { 2634 remote-endpoint = <&dlst_ch_funnel_out>; 2635 }; 2636 }; 2637 }; 2638 2639 out-ports { 2640 port { 2641 funnel1_out: endpoint { 2642 remote-endpoint = <&qdss_funnel_in1>; 2643 }; 2644 }; 2645 }; 2646 }; 2647 2648 funnel@4045000 { 2649 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2650 reg = <0x0 0x04045000 0x0 0x1000>; 2651 2652 clocks = <&aoss_qmp>; 2653 clock-names = "apb_pclk"; 2654 2655 in-ports { 2656 #address-cells = <1>; 2657 #size-cells = <0>; 2658 2659 port@0 { 2660 reg = <0>; 2661 2662 qdss_funnel_in0: endpoint { 2663 remote-endpoint = <&funnel0_out>; 2664 }; 2665 }; 2666 2667 port@1 { 2668 reg = <1>; 2669 2670 qdss_funnel_in1: endpoint { 2671 remote-endpoint = <&funnel1_out>; 2672 }; 2673 }; 2674 }; 2675 2676 out-ports { 2677 port { 2678 qdss_funnel_out: endpoint { 2679 remote-endpoint = <&aoss_funnel_in7>; 2680 }; 2681 }; 2682 }; 2683 }; 2684 2685 tpdm@4841000 { 2686 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2687 reg = <0x0 0x04841000 0x0 0x1000>; 2688 2689 clocks = <&aoss_qmp>; 2690 clock-names = "apb_pclk"; 2691 2692 qcom,cmb-element-bits = <32>; 2693 qcom,cmb-msrs-num = <32>; 2694 2695 out-ports { 2696 port { 2697 prng_tpdm_out: endpoint { 2698 remote-endpoint = <&dlct0_tpda_in19>; 2699 }; 2700 }; 2701 }; 2702 }; 2703 2704 tpdm@4850000 { 2705 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2706 reg = <0x0 0x04850000 0x0 0x1000>; 2707 2708 clocks = <&aoss_qmp>; 2709 clock-names = "apb_pclk"; 2710 2711 qcom,cmb-element-bits = <64>; 2712 qcom,cmb-msrs-num = <32>; 2713 qcom,dsb-element-bits = <32>; 2714 qcom,dsb-msrs-num = <32>; 2715 2716 out-ports { 2717 port { 2718 pimem_tpdm_out: endpoint { 2719 remote-endpoint = <&dlct0_tpda_in25>; 2720 }; 2721 }; 2722 }; 2723 }; 2724 2725 tpdm@4860000 { 2726 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2727 reg = <0x0 0x04860000 0x0 0x1000>; 2728 2729 clocks = <&aoss_qmp>; 2730 clock-names = "apb_pclk"; 2731 2732 qcom,dsb-element-bits = <32>; 2733 qcom,dsb-msrs-num = <32>; 2734 2735 out-ports { 2736 port { 2737 dlst_ch_tpdm0_out: endpoint { 2738 remote-endpoint = <&dlst_ch_tpda_in8>; 2739 }; 2740 }; 2741 }; 2742 }; 2743 2744 tpda@4864000 { 2745 compatible = "qcom,coresight-tpda", "arm,primecell"; 2746 reg = <0x0 0x04864000 0x0 0x1000>; 2747 2748 clocks = <&aoss_qmp>; 2749 clock-names = "apb_pclk"; 2750 2751 in-ports { 2752 #address-cells = <1>; 2753 #size-cells = <0>; 2754 2755 port@8 { 2756 reg = <8>; 2757 2758 dlst_ch_tpda_in8: endpoint { 2759 remote-endpoint = <&dlst_ch_tpdm0_out>; 2760 }; 2761 }; 2762 }; 2763 2764 out-ports { 2765 port { 2766 dlst_ch_tpda_out: endpoint { 2767 remote-endpoint = <&dlst_ch_funnel_in0>; 2768 }; 2769 }; 2770 }; 2771 }; 2772 2773 funnel@4865000 { 2774 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2775 reg = <0x0 0x04865000 0x0 0x1000>; 2776 2777 clocks = <&aoss_qmp>; 2778 clock-names = "apb_pclk"; 2779 2780 in-ports { 2781 #address-cells = <1>; 2782 #size-cells = <0>; 2783 2784 port@0 { 2785 reg = <0>; 2786 2787 dlst_ch_funnel_in0: endpoint { 2788 remote-endpoint = <&dlst_ch_tpda_out>; 2789 }; 2790 }; 2791 2792 port@4 { 2793 reg = <4>; 2794 2795 dlst_ch_funnel_in4: endpoint { 2796 remote-endpoint = <&dlst_funnel_out>; 2797 }; 2798 }; 2799 2800 port@6 { 2801 reg = <6>; 2802 2803 dlst_ch_funnel_in6: endpoint { 2804 remote-endpoint = <&gdsp_funnel_out>; 2805 }; 2806 }; 2807 }; 2808 2809 out-ports { 2810 port { 2811 dlst_ch_funnel_out: endpoint { 2812 remote-endpoint = <&funnel1_in7>; 2813 }; 2814 }; 2815 }; 2816 }; 2817 2818 tpdm@4980000 { 2819 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2820 reg = <0x0 0x04980000 0x0 0x1000>; 2821 2822 clocks = <&aoss_qmp>; 2823 clock-names = "apb_pclk"; 2824 2825 qcom,dsb-element-bits = <32>; 2826 qcom,dsb-msrs-num = <32>; 2827 2828 out-ports { 2829 port { 2830 turing2_tpdm_out: endpoint { 2831 remote-endpoint = <&turing2_funnel_in0>; 2832 }; 2833 }; 2834 }; 2835 }; 2836 2837 funnel@4983000 { 2838 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2839 reg = <0x0 0x04983000 0x0 0x1000>; 2840 2841 clocks = <&aoss_qmp>; 2842 clock-names = "apb_pclk"; 2843 2844 in-ports { 2845 port { 2846 turing2_funnel_in0: endpoint { 2847 remote-endpoint = <&turing2_tpdm_out>; 2848 }; 2849 }; 2850 }; 2851 2852 out-ports { 2853 port { 2854 turing2_funnel_out0: endpoint { 2855 remote-endpoint = <&gdsp_tpda_in5>; 2856 }; 2857 }; 2858 }; 2859 }; 2860 2861 tpdm@4ac0000 { 2862 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2863 reg = <0x0 0x04ac0000 0x0 0x1000>; 2864 2865 clocks = <&aoss_qmp>; 2866 clock-names = "apb_pclk"; 2867 2868 qcom,dsb-element-bits = <32>; 2869 qcom,dsb-msrs-num = <32>; 2870 2871 out-ports { 2872 port { 2873 dlmm_tpdm0_out: endpoint { 2874 remote-endpoint = <&dlmm_tpda_in27>; 2875 }; 2876 }; 2877 }; 2878 }; 2879 2880 tpda@4ac4000 { 2881 compatible = "qcom,coresight-tpda", "arm,primecell"; 2882 reg = <0x0 0x04ac4000 0x0 0x1000>; 2883 2884 clocks = <&aoss_qmp>; 2885 clock-names = "apb_pclk"; 2886 2887 in-ports { 2888 #address-cells = <1>; 2889 #size-cells = <0>; 2890 2891 port@1b { 2892 reg = <27>; 2893 2894 dlmm_tpda_in27: endpoint { 2895 remote-endpoint = <&dlmm_tpdm0_out>; 2896 }; 2897 }; 2898 }; 2899 2900 out-ports { 2901 port { 2902 dlmm_tpda_out: endpoint { 2903 remote-endpoint = <&dlmm_funnel_in0>; 2904 }; 2905 }; 2906 }; 2907 }; 2908 2909 funnel@4ac5000 { 2910 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2911 reg = <0x0 0x04ac5000 0x0 0x1000>; 2912 2913 clocks = <&aoss_qmp>; 2914 clock-names = "apb_pclk"; 2915 2916 in-ports { 2917 port { 2918 dlmm_funnel_in0: endpoint { 2919 remote-endpoint = <&dlmm_tpda_out>; 2920 }; 2921 }; 2922 }; 2923 2924 out-ports { 2925 port { 2926 dlmm_funnel_out: endpoint { 2927 remote-endpoint = <&funnel1_in6>; 2928 }; 2929 }; 2930 }; 2931 }; 2932 2933 tpdm@4ad0000 { 2934 compatible = "qcom,coresight-tpdm", "arm,primecell"; 2935 reg = <0x0 0x04ad0000 0x0 0x1000>; 2936 2937 clocks = <&aoss_qmp>; 2938 clock-names = "apb_pclk"; 2939 2940 qcom,dsb-element-bits = <32>; 2941 qcom,dsb-msrs-num = <32>; 2942 2943 out-ports { 2944 port { 2945 dlct0_tpdm0_out: endpoint { 2946 remote-endpoint = <&dlct0_tpda_in26>; 2947 }; 2948 }; 2949 }; 2950 }; 2951 2952 tpda@4ad3000 { 2953 compatible = "qcom,coresight-tpda", "arm,primecell"; 2954 reg = <0x0 0x04ad3000 0x0 0x1000>; 2955 2956 clocks = <&aoss_qmp>; 2957 clock-names = "apb_pclk"; 2958 2959 in-ports { 2960 #address-cells = <1>; 2961 #size-cells = <0>; 2962 2963 port@13 { 2964 reg = <19>; 2965 2966 dlct0_tpda_in19: endpoint { 2967 remote-endpoint = <&prng_tpdm_out>; 2968 }; 2969 }; 2970 2971 port@19 { 2972 reg = <25>; 2973 2974 dlct0_tpda_in25: endpoint { 2975 remote-endpoint = <&pimem_tpdm_out>; 2976 }; 2977 }; 2978 2979 port@1a { 2980 reg = <26>; 2981 2982 dlct0_tpda_in26: endpoint { 2983 remote-endpoint = <&dlct0_tpdm0_out>; 2984 }; 2985 }; 2986 }; 2987 2988 out-ports { 2989 port { 2990 dlct0_tpda_out: endpoint { 2991 remote-endpoint = <&dlct0_funnel_in0>; 2992 }; 2993 }; 2994 }; 2995 }; 2996 2997 funnel@4ad4000 { 2998 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 2999 reg = <0x0 0x04ad4000 0x0 0x1000>; 3000 3001 clocks = <&aoss_qmp>; 3002 clock-names = "apb_pclk"; 3003 3004 in-ports { 3005 #address-cells = <1>; 3006 #size-cells = <0>; 3007 3008 port@0 { 3009 reg = <0>; 3010 3011 dlct0_funnel_in0: endpoint { 3012 remote-endpoint = <&dlct0_tpda_out>; 3013 }; 3014 }; 3015 3016 port@4 { 3017 reg = <4>; 3018 3019 dlct0_funnel_in4: endpoint { 3020 remote-endpoint = <&ddr_funnel5_out>; 3021 }; 3022 }; 3023 }; 3024 3025 out-ports { 3026 port { 3027 dlct0_funnel_out: endpoint { 3028 remote-endpoint = <&funnel1_in5>; 3029 }; 3030 }; 3031 }; 3032 }; 3033 3034 funnel@4b04000 { 3035 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3036 reg = <0x0 0x04b04000 0x0 0x1000>; 3037 3038 clocks = <&aoss_qmp>; 3039 clock-names = "apb_pclk"; 3040 3041 in-ports { 3042 #address-cells = <1>; 3043 #size-cells = <0>; 3044 3045 port@6 { 3046 reg = <6>; 3047 3048 aoss_funnel_in6: endpoint { 3049 remote-endpoint = <&aoss_tpda_out>; 3050 }; 3051 }; 3052 3053 port@7 { 3054 reg = <7>; 3055 3056 aoss_funnel_in7: endpoint { 3057 remote-endpoint = <&qdss_funnel_out>; 3058 }; 3059 }; 3060 }; 3061 3062 out-ports { 3063 port { 3064 aoss_funnel_out: endpoint { 3065 remote-endpoint = <&etf0_in>; 3066 }; 3067 }; 3068 }; 3069 }; 3070 3071 tmc_etf: tmc@4b05000 { 3072 compatible = "arm,coresight-tmc", "arm,primecell"; 3073 reg = <0x0 0x04b05000 0x0 0x1000>; 3074 3075 clocks = <&aoss_qmp>; 3076 clock-names = "apb_pclk"; 3077 3078 in-ports { 3079 port { 3080 etf0_in: endpoint { 3081 remote-endpoint = <&aoss_funnel_out>; 3082 }; 3083 }; 3084 }; 3085 3086 out-ports { 3087 port { 3088 etf0_out: endpoint { 3089 remote-endpoint = <&swao_rep_in>; 3090 }; 3091 }; 3092 }; 3093 }; 3094 3095 replicator@4b06000 { 3096 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3097 reg = <0x0 0x04b06000 0x0 0x1000>; 3098 3099 clocks = <&aoss_qmp>; 3100 clock-names = "apb_pclk"; 3101 3102 in-ports { 3103 port { 3104 swao_rep_in: endpoint { 3105 remote-endpoint = <&etf0_out>; 3106 }; 3107 }; 3108 }; 3109 3110 out-ports { 3111 #address-cells = <1>; 3112 #size-cells = <0>; 3113 3114 port@1 { 3115 reg = <1>; 3116 3117 swao_rep_out1: endpoint { 3118 remote-endpoint = <&eud_in>; 3119 }; 3120 }; 3121 }; 3122 }; 3123 3124 tpda@4b08000 { 3125 compatible = "qcom,coresight-tpda", "arm,primecell"; 3126 reg = <0x0 0x04b08000 0x0 0x1000>; 3127 3128 clocks = <&aoss_qmp>; 3129 clock-names = "apb_pclk"; 3130 3131 in-ports { 3132 #address-cells = <1>; 3133 #size-cells = <0>; 3134 3135 port@0 { 3136 reg = <0>; 3137 3138 aoss_tpda_in0: endpoint { 3139 remote-endpoint = <&aoss_tpdm0_out>; 3140 }; 3141 }; 3142 3143 port@1 { 3144 reg = <1>; 3145 3146 aoss_tpda_in1: endpoint { 3147 remote-endpoint = <&aoss_tpdm1_out>; 3148 }; 3149 }; 3150 3151 port@2 { 3152 reg = <2>; 3153 3154 aoss_tpda_in2: endpoint { 3155 remote-endpoint = <&aoss_tpdm2_out>; 3156 }; 3157 }; 3158 3159 port@3 { 3160 reg = <3>; 3161 3162 aoss_tpda_in3: endpoint { 3163 remote-endpoint = <&aoss_tpdm3_out>; 3164 }; 3165 }; 3166 3167 port@4 { 3168 reg = <4>; 3169 3170 aoss_tpda_in4: endpoint { 3171 remote-endpoint = <&aoss_tpdm4_out>; 3172 }; 3173 }; 3174 }; 3175 3176 out-ports { 3177 port { 3178 aoss_tpda_out: endpoint { 3179 remote-endpoint = <&aoss_funnel_in6>; 3180 }; 3181 }; 3182 }; 3183 }; 3184 3185 tpdm@4b09000 { 3186 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3187 reg = <0x0 0x04b09000 0x0 0x1000>; 3188 3189 clocks = <&aoss_qmp>; 3190 clock-names = "apb_pclk"; 3191 3192 qcom,cmb-element-bits = <64>; 3193 qcom,cmb-msrs-num = <32>; 3194 3195 out-ports { 3196 port { 3197 aoss_tpdm0_out: endpoint { 3198 remote-endpoint = <&aoss_tpda_in0>; 3199 }; 3200 }; 3201 }; 3202 }; 3203 3204 tpdm@4b0a000 { 3205 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3206 reg = <0x0 0x04b0a000 0x0 0x1000>; 3207 3208 clocks = <&aoss_qmp>; 3209 clock-names = "apb_pclk"; 3210 3211 qcom,cmb-element-bits = <64>; 3212 qcom,cmb-msrs-num = <32>; 3213 3214 out-ports { 3215 port { 3216 aoss_tpdm1_out: endpoint { 3217 remote-endpoint = <&aoss_tpda_in1>; 3218 }; 3219 }; 3220 }; 3221 }; 3222 3223 tpdm@4b0b000 { 3224 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3225 reg = <0x0 0x04b0b000 0x0 0x1000>; 3226 3227 clocks = <&aoss_qmp>; 3228 clock-names = "apb_pclk"; 3229 3230 qcom,cmb-element-bits = <64>; 3231 qcom,cmb-msrs-num = <32>; 3232 3233 out-ports { 3234 port { 3235 aoss_tpdm2_out: endpoint { 3236 remote-endpoint = <&aoss_tpda_in2>; 3237 }; 3238 }; 3239 }; 3240 }; 3241 3242 tpdm@4b0c000 { 3243 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3244 reg = <0x0 0x04b0c000 0x0 0x1000>; 3245 3246 clocks = <&aoss_qmp>; 3247 clock-names = "apb_pclk"; 3248 3249 qcom,cmb-element-bits = <64>; 3250 qcom,cmb-msrs-num = <32>; 3251 3252 out-ports { 3253 port { 3254 aoss_tpdm3_out: endpoint { 3255 remote-endpoint = <&aoss_tpda_in3>; 3256 }; 3257 }; 3258 }; 3259 }; 3260 3261 tpdm@4b0d000 { 3262 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3263 reg = <0x0 0x04b0d000 0x0 0x1000>; 3264 3265 clocks = <&aoss_qmp>; 3266 clock-names = "apb_pclk"; 3267 3268 qcom,dsb-element-bits = <32>; 3269 qcom,dsb-msrs-num = <32>; 3270 3271 out-ports { 3272 port { 3273 aoss_tpdm4_out: endpoint { 3274 remote-endpoint = <&aoss_tpda_in4>; 3275 }; 3276 }; 3277 }; 3278 }; 3279 3280 cti@4b13000 { 3281 compatible = "arm,coresight-cti", "arm,primecell"; 3282 reg = <0x0 0x04b13000 0x0 0x1000>; 3283 3284 clocks = <&aoss_qmp>; 3285 clock-names = "apb_pclk"; 3286 }; 3287 3288 tpdm@4b80000 { 3289 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3290 reg = <0x0 0x04b80000 0x0 0x1000>; 3291 3292 clocks = <&aoss_qmp>; 3293 clock-names = "apb_pclk"; 3294 3295 qcom,dsb-element-bits = <32>; 3296 qcom,dsb-msrs-num = <32>; 3297 3298 out-ports { 3299 port { 3300 turing0_tpdm0_out: endpoint { 3301 remote-endpoint = <&turing0_tpda_in0>; 3302 }; 3303 }; 3304 }; 3305 }; 3306 3307 tpda@4b86000 { 3308 compatible = "qcom,coresight-tpda", "arm,primecell"; 3309 reg = <0x0 0x04b86000 0x0 0x1000>; 3310 3311 clocks = <&aoss_qmp>; 3312 clock-names = "apb_pclk"; 3313 3314 in-ports { 3315 port { 3316 turing0_tpda_in0: endpoint { 3317 remote-endpoint = <&turing0_tpdm0_out>; 3318 }; 3319 }; 3320 }; 3321 3322 out-ports { 3323 port { 3324 turing0_tpda_out: endpoint { 3325 remote-endpoint = <&turing0_funnel_in0>; 3326 }; 3327 }; 3328 }; 3329 }; 3330 3331 funnel@4b87000 { 3332 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3333 reg = <0x0 0x04b87000 0x0 0x1000>; 3334 3335 clocks = <&aoss_qmp>; 3336 clock-names = "apb_pclk"; 3337 3338 in-ports { 3339 port { 3340 turing0_funnel_in0: endpoint { 3341 remote-endpoint = <&turing0_tpda_out>; 3342 }; 3343 }; 3344 }; 3345 3346 out-ports { 3347 port { 3348 turing0_funnel_out: endpoint { 3349 remote-endpoint = <&gdsp_funnel_in4>; 3350 }; 3351 }; 3352 }; 3353 }; 3354 3355 cti@4b8b000 { 3356 compatible = "arm,coresight-cti", "arm,primecell"; 3357 reg = <0x0 0x04b8b000 0x0 0x1000>; 3358 3359 clocks = <&aoss_qmp>; 3360 clock-names = "apb_pclk"; 3361 }; 3362 3363 tpdm@4c40000 { 3364 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3365 reg = <0x0 0x04c40000 0x0 0x1000>; 3366 3367 clocks = <&aoss_qmp>; 3368 clock-names = "apb_pclk"; 3369 3370 qcom,dsb-element-bits = <32>; 3371 qcom,dsb-msrs-num = <32>; 3372 3373 out-ports { 3374 port { 3375 gdsp_tpdm0_out: endpoint { 3376 remote-endpoint = <&gdsp_tpda_in8>; 3377 }; 3378 }; 3379 }; 3380 }; 3381 3382 tpda@4c44000 { 3383 compatible = "qcom,coresight-tpda", "arm,primecell"; 3384 reg = <0x0 0x04c44000 0x0 0x1000>; 3385 3386 clocks = <&aoss_qmp>; 3387 clock-names = "apb_pclk"; 3388 3389 in-ports { 3390 #address-cells = <1>; 3391 #size-cells = <0>; 3392 3393 port@5 { 3394 reg = <5>; 3395 3396 gdsp_tpda_in5: endpoint { 3397 remote-endpoint = <&turing2_funnel_out0>; 3398 }; 3399 }; 3400 3401 port@8 { 3402 reg = <8>; 3403 3404 gdsp_tpda_in8: endpoint { 3405 remote-endpoint = <&gdsp_tpdm0_out>; 3406 }; 3407 }; 3408 }; 3409 3410 out-ports { 3411 port { 3412 gdsp_tpda_out: endpoint { 3413 remote-endpoint = <&gdsp_funnel_in0>; 3414 }; 3415 }; 3416 }; 3417 }; 3418 3419 funnel@4c45000 { 3420 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3421 reg = <0x0 0x04c45000 0x0 0x1000>; 3422 3423 clocks = <&aoss_qmp>; 3424 clock-names = "apb_pclk"; 3425 3426 in-ports { 3427 #address-cells = <1>; 3428 #size-cells = <0>; 3429 3430 port@0 { 3431 reg = <0>; 3432 3433 gdsp_funnel_in0: endpoint { 3434 remote-endpoint = <&gdsp_tpda_out>; 3435 }; 3436 }; 3437 3438 port@4 { 3439 reg = <4>; 3440 3441 gdsp_funnel_in4: endpoint { 3442 remote-endpoint = <&turing0_funnel_out>; 3443 }; 3444 }; 3445 }; 3446 3447 out-ports { 3448 port { 3449 gdsp_funnel_out: endpoint { 3450 remote-endpoint = <&dlst_ch_funnel_in6>; 3451 }; 3452 }; 3453 }; 3454 }; 3455 3456 tpdm@4c50000 { 3457 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3458 reg = <0x0 0x04c50000 0x0 0x1000>; 3459 3460 clocks = <&aoss_qmp>; 3461 clock-names = "apb_pclk"; 3462 3463 qcom,dsb-element-bits = <32>; 3464 qcom,dsb-msrs-num = <32>; 3465 3466 out-ports { 3467 port { 3468 dlst_tpdm0_out: endpoint { 3469 remote-endpoint = <&dlst_tpda_in8>; 3470 }; 3471 }; 3472 }; 3473 }; 3474 3475 tpda@4c54000 { 3476 compatible = "qcom,coresight-tpda", "arm,primecell"; 3477 reg = <0x0 0x04c54000 0x0 0x1000>; 3478 3479 clocks = <&aoss_qmp>; 3480 clock-names = "apb_pclk"; 3481 3482 in-ports { 3483 #address-cells = <1>; 3484 #size-cells = <0>; 3485 3486 port@8 { 3487 reg = <8>; 3488 3489 dlst_tpda_in8: endpoint { 3490 remote-endpoint = <&dlst_tpdm0_out>; 3491 }; 3492 }; 3493 }; 3494 3495 out-ports { 3496 port { 3497 dlst_tpda_out: endpoint { 3498 remote-endpoint = <&dlst_funnel_in0>; 3499 }; 3500 }; 3501 }; 3502 }; 3503 3504 funnel@4c55000 { 3505 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3506 reg = <0x0 0x04c55000 0x0 0x1000>; 3507 3508 clocks = <&aoss_qmp>; 3509 clock-names = "apb_pclk"; 3510 3511 in-ports { 3512 port { 3513 dlst_funnel_in0: endpoint { 3514 remote-endpoint = <&dlst_tpda_out>; 3515 }; 3516 }; 3517 }; 3518 3519 out-ports { 3520 port { 3521 dlst_funnel_out: endpoint { 3522 remote-endpoint = <&dlst_ch_funnel_in4>; 3523 }; 3524 }; 3525 }; 3526 }; 3527 3528 tpdm@4e00000 { 3529 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3530 reg = <0x0 0x04e00000 0x0 0x1000>; 3531 3532 clocks = <&aoss_qmp>; 3533 clock-names = "apb_pclk"; 3534 3535 qcom,dsb-element-bits = <32>; 3536 qcom,dsb-msrs-num = <32>; 3537 qcom,cmb-element-bits = <32>; 3538 qcom,cmb-msrs-num = <32>; 3539 3540 out-ports { 3541 port { 3542 ddr_tpdm3_out: endpoint { 3543 remote-endpoint = <&ddr_tpda_in4>; 3544 }; 3545 }; 3546 }; 3547 }; 3548 3549 tpda@4e03000 { 3550 compatible = "qcom,coresight-tpda", "arm,primecell"; 3551 reg = <0x0 0x04e03000 0x0 0x1000>; 3552 3553 clocks = <&aoss_qmp>; 3554 clock-names = "apb_pclk"; 3555 3556 in-ports { 3557 #address-cells = <1>; 3558 #size-cells = <0>; 3559 3560 port@0 { 3561 reg = <0>; 3562 3563 ddr_tpda_in0: endpoint { 3564 remote-endpoint = <&ddr_funnel0_out0>; 3565 }; 3566 }; 3567 3568 port@1 { 3569 reg = <1>; 3570 3571 ddr_tpda_in1: endpoint { 3572 remote-endpoint = <&ddr_funnel1_out0>; 3573 }; 3574 }; 3575 3576 port@4 { 3577 reg = <4>; 3578 3579 ddr_tpda_in4: endpoint { 3580 remote-endpoint = <&ddr_tpdm3_out>; 3581 }; 3582 }; 3583 }; 3584 3585 out-ports { 3586 port { 3587 ddr_tpda_out: endpoint { 3588 remote-endpoint = <&ddr_funnel5_in0>; 3589 }; 3590 }; 3591 }; 3592 }; 3593 3594 funnel@4e04000 { 3595 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3596 reg = <0x0 0x04e04000 0x0 0x1000>; 3597 3598 clocks = <&aoss_qmp>; 3599 clock-names = "apb_pclk"; 3600 3601 in-ports { 3602 port { 3603 ddr_funnel5_in0: endpoint { 3604 remote-endpoint = <&ddr_tpda_out>; 3605 }; 3606 }; 3607 }; 3608 3609 out-ports { 3610 port { 3611 ddr_funnel5_out: endpoint { 3612 remote-endpoint = <&dlct0_funnel_in4>; 3613 }; 3614 }; 3615 }; 3616 }; 3617 3618 tpdm@4e10000 { 3619 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3620 reg = <0x0 0x04e10000 0x0 0x1000>; 3621 3622 clocks = <&aoss_qmp>; 3623 clock-names = "apb_pclk"; 3624 3625 qcom,dsb-element-bits = <32>; 3626 qcom,dsb-msrs-num = <32>; 3627 3628 out-ports { 3629 port { 3630 ddr_tpdm0_out: endpoint { 3631 remote-endpoint = <&ddr_funnel0_in0>; 3632 }; 3633 }; 3634 }; 3635 }; 3636 3637 funnel@4e12000 { 3638 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3639 reg = <0x0 0x04e12000 0x0 0x1000>; 3640 3641 clocks = <&aoss_qmp>; 3642 clock-names = "apb_pclk"; 3643 3644 in-ports { 3645 port { 3646 ddr_funnel0_in0: endpoint { 3647 remote-endpoint = <&ddr_tpdm0_out>; 3648 }; 3649 }; 3650 }; 3651 3652 out-ports { 3653 port { 3654 ddr_funnel0_out0: endpoint { 3655 remote-endpoint = <&ddr_tpda_in0>; 3656 }; 3657 }; 3658 }; 3659 }; 3660 3661 tpdm@4e20000 { 3662 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3663 reg = <0x0 0x04e20000 0x0 0x1000>; 3664 3665 clocks = <&aoss_qmp>; 3666 clock-names = "apb_pclk"; 3667 3668 qcom,dsb-element-bits = <32>; 3669 qcom,dsb-msrs-num = <32>; 3670 3671 out-ports { 3672 port { 3673 ddr_tpdm1_out: endpoint { 3674 remote-endpoint = <&ddr_funnel1_in0>; 3675 }; 3676 }; 3677 }; 3678 }; 3679 3680 funnel@4e22000 { 3681 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3682 reg = <0x0 0x04e22000 0x0 0x1000>; 3683 3684 clocks = <&aoss_qmp>; 3685 clock-names = "apb_pclk"; 3686 3687 in-ports { 3688 port { 3689 ddr_funnel1_in0: endpoint { 3690 remote-endpoint = <&ddr_tpdm1_out>; 3691 }; 3692 }; 3693 }; 3694 3695 out-ports { 3696 port { 3697 ddr_funnel1_out0: endpoint { 3698 remote-endpoint = <&ddr_tpda_in1>; 3699 }; 3700 }; 3701 }; 3702 }; 3703 3704 etm@6040000 { 3705 compatible = "arm,primecell"; 3706 reg = <0x0 0x06040000 0x0 0x1000>; 3707 cpu = <&cpu0>; 3708 3709 clocks = <&aoss_qmp>; 3710 clock-names = "apb_pclk"; 3711 3712 arm,coresight-loses-context-with-cpu; 3713 qcom,skip-power-up; 3714 3715 out-ports { 3716 port { 3717 etm0_out: endpoint { 3718 remote-endpoint = <&apss_funnel0_in0>; 3719 }; 3720 }; 3721 }; 3722 }; 3723 3724 etm@6140000 { 3725 compatible = "arm,primecell"; 3726 reg = <0x0 0x06140000 0x0 0x1000>; 3727 cpu = <&cpu1>; 3728 3729 clocks = <&aoss_qmp>; 3730 clock-names = "apb_pclk"; 3731 3732 arm,coresight-loses-context-with-cpu; 3733 qcom,skip-power-up; 3734 3735 out-ports { 3736 port { 3737 etm1_out: endpoint { 3738 remote-endpoint = <&apss_funnel0_in1>; 3739 }; 3740 }; 3741 }; 3742 }; 3743 3744 etm@6240000 { 3745 compatible = "arm,primecell"; 3746 reg = <0x0 0x06240000 0x0 0x1000>; 3747 cpu = <&cpu2>; 3748 3749 clocks = <&aoss_qmp>; 3750 clock-names = "apb_pclk"; 3751 3752 arm,coresight-loses-context-with-cpu; 3753 qcom,skip-power-up; 3754 3755 out-ports { 3756 port { 3757 etm2_out: endpoint { 3758 remote-endpoint = <&apss_funnel0_in2>; 3759 }; 3760 }; 3761 }; 3762 }; 3763 3764 etm@6340000 { 3765 compatible = "arm,primecell"; 3766 reg = <0x0 0x06340000 0x0 0x1000>; 3767 cpu = <&cpu3>; 3768 3769 clocks = <&aoss_qmp>; 3770 clock-names = "apb_pclk"; 3771 3772 arm,coresight-loses-context-with-cpu; 3773 qcom,skip-power-up; 3774 3775 out-ports { 3776 port { 3777 etm3_out: endpoint { 3778 remote-endpoint = <&apss_funnel0_in3>; 3779 }; 3780 }; 3781 }; 3782 }; 3783 3784 etm@6440000 { 3785 compatible = "arm,primecell"; 3786 reg = <0x0 0x06440000 0x0 0x1000>; 3787 cpu = <&cpu4>; 3788 3789 clocks = <&aoss_qmp>; 3790 clock-names = "apb_pclk"; 3791 3792 arm,coresight-loses-context-with-cpu; 3793 qcom,skip-power-up; 3794 3795 out-ports { 3796 port { 3797 etm4_out: endpoint { 3798 remote-endpoint = <&apss_funnel0_in4>; 3799 }; 3800 }; 3801 }; 3802 }; 3803 3804 etm@6540000 { 3805 compatible = "arm,primecell"; 3806 reg = <0x0 0x06540000 0x0 0x1000>; 3807 cpu = <&cpu5>; 3808 3809 clocks = <&aoss_qmp>; 3810 clock-names = "apb_pclk"; 3811 3812 arm,coresight-loses-context-with-cpu; 3813 qcom,skip-power-up; 3814 3815 out-ports { 3816 port { 3817 etm5_out: endpoint { 3818 remote-endpoint = <&apss_funnel0_in5>; 3819 }; 3820 }; 3821 }; 3822 }; 3823 3824 etm@6640000 { 3825 compatible = "arm,primecell"; 3826 reg = <0x0 0x06640000 0x0 0x1000>; 3827 cpu = <&cpu6>; 3828 3829 clocks = <&aoss_qmp>; 3830 clock-names = "apb_pclk"; 3831 3832 arm,coresight-loses-context-with-cpu; 3833 qcom,skip-power-up; 3834 3835 out-ports { 3836 port { 3837 etm6_out: endpoint { 3838 remote-endpoint = <&apss_funnel0_in6>; 3839 }; 3840 }; 3841 }; 3842 }; 3843 3844 etm@6740000 { 3845 compatible = "arm,primecell"; 3846 reg = <0x0 0x06740000 0x0 0x1000>; 3847 cpu = <&cpu7>; 3848 3849 clocks = <&aoss_qmp>; 3850 clock-names = "apb_pclk"; 3851 3852 arm,coresight-loses-context-with-cpu; 3853 qcom,skip-power-up; 3854 3855 out-ports { 3856 port { 3857 etm7_out: endpoint { 3858 remote-endpoint = <&apss_funnel0_in7>; 3859 }; 3860 }; 3861 }; 3862 }; 3863 3864 funnel@6800000 { 3865 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3866 reg = <0x0 0x06800000 0x0 0x1000>; 3867 3868 clocks = <&aoss_qmp>; 3869 clock-names = "apb_pclk"; 3870 3871 in-ports { 3872 #address-cells = <1>; 3873 #size-cells = <0>; 3874 3875 port@0 { 3876 reg = <0>; 3877 3878 apss_funnel0_in0: endpoint { 3879 remote-endpoint = <&etm0_out>; 3880 }; 3881 }; 3882 3883 port@1 { 3884 reg = <1>; 3885 3886 apss_funnel0_in1: endpoint { 3887 remote-endpoint = <&etm1_out>; 3888 }; 3889 }; 3890 3891 port@2 { 3892 reg = <2>; 3893 3894 apss_funnel0_in2: endpoint { 3895 remote-endpoint = <&etm2_out>; 3896 }; 3897 }; 3898 3899 port@3 { 3900 reg = <3>; 3901 3902 apss_funnel0_in3: endpoint { 3903 remote-endpoint = <&etm3_out>; 3904 }; 3905 }; 3906 3907 port@4 { 3908 reg = <4>; 3909 3910 apss_funnel0_in4: endpoint { 3911 remote-endpoint = <&etm4_out>; 3912 }; 3913 }; 3914 3915 port@5 { 3916 reg = <5>; 3917 3918 apss_funnel0_in5: endpoint { 3919 remote-endpoint = <&etm5_out>; 3920 }; 3921 }; 3922 3923 port@6 { 3924 reg = <6>; 3925 3926 apss_funnel0_in6: endpoint { 3927 remote-endpoint = <&etm6_out>; 3928 }; 3929 }; 3930 3931 port@7 { 3932 reg = <7>; 3933 3934 apss_funnel0_in7: endpoint { 3935 remote-endpoint = <&etm7_out>; 3936 }; 3937 }; 3938 }; 3939 3940 out-ports { 3941 port { 3942 apss_funnel0_out: endpoint { 3943 remote-endpoint = <&apss_funnel1_in0>; 3944 }; 3945 }; 3946 }; 3947 }; 3948 3949 funnel@6810000 { 3950 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3951 reg = <0x0 0x06810000 0x0 0x1000>; 3952 3953 clocks = <&aoss_qmp>; 3954 clock-names = "apb_pclk"; 3955 3956 in-ports { 3957 #address-cells = <1>; 3958 #size-cells = <0>; 3959 3960 port@0 { 3961 reg = <0>; 3962 3963 apss_funnel1_in0: endpoint { 3964 remote-endpoint = <&apss_funnel0_out>; 3965 }; 3966 }; 3967 3968 port@3 { 3969 reg = <3>; 3970 3971 apss_funnel1_in3: endpoint { 3972 remote-endpoint = <&apss_tpda_out>; 3973 }; 3974 }; 3975 }; 3976 3977 out-ports { 3978 port { 3979 apss_funnel1_out: endpoint { 3980 remote-endpoint = <&funnel1_in4>; 3981 }; 3982 }; 3983 }; 3984 }; 3985 3986 cti@682b000 { 3987 compatible = "arm,coresight-cti", "arm,primecell"; 3988 reg = <0x0 0x0682b000 0x0 0x1000>; 3989 3990 clocks = <&aoss_qmp>; 3991 clock-names = "apb_pclk"; 3992 }; 3993 3994 tpdm@6860000 { 3995 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3996 reg = <0x0 0x06860000 0x0 0x1000>; 3997 3998 clocks = <&aoss_qmp>; 3999 clock-names = "apb_pclk"; 4000 4001 qcom,cmb-element-bits = <64>; 4002 qcom,cmb-msrs-num = <32>; 4003 4004 out-ports { 4005 port { 4006 apss_tpdm3_out: endpoint { 4007 remote-endpoint = <&apss_tpda_in3>; 4008 }; 4009 }; 4010 }; 4011 }; 4012 4013 tpdm@6861000 { 4014 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4015 reg = <0x0 0x06861000 0x0 0x1000>; 4016 4017 clocks = <&aoss_qmp>; 4018 clock-names = "apb_pclk"; 4019 4020 qcom,dsb-element-bits = <32>; 4021 qcom,dsb-msrs-num = <32>; 4022 4023 out-ports { 4024 port { 4025 apss_tpdm4_out: endpoint { 4026 remote-endpoint = <&apss_tpda_in4>; 4027 }; 4028 }; 4029 }; 4030 }; 4031 4032 tpda@6863000 { 4033 compatible = "qcom,coresight-tpda", "arm,primecell"; 4034 reg = <0x0 0x06863000 0x0 0x1000>; 4035 4036 clocks = <&aoss_qmp>; 4037 clock-names = "apb_pclk"; 4038 4039 in-ports { 4040 #address-cells = <1>; 4041 #size-cells = <0>; 4042 4043 port@0 { 4044 reg = <0>; 4045 4046 apss_tpda_in0: endpoint { 4047 remote-endpoint = <&apss_tpdm0_out>; 4048 }; 4049 }; 4050 4051 port@1 { 4052 reg = <1>; 4053 4054 apss_tpda_in1: endpoint { 4055 remote-endpoint = <&apss_tpdm1_out>; 4056 }; 4057 }; 4058 4059 port@2 { 4060 reg = <2>; 4061 4062 apss_tpda_in2: endpoint { 4063 remote-endpoint = <&apss_tpdm2_out>; 4064 }; 4065 }; 4066 4067 port@3 { 4068 reg = <3>; 4069 4070 apss_tpda_in3: endpoint { 4071 remote-endpoint = <&apss_tpdm3_out>; 4072 }; 4073 }; 4074 4075 port@4 { 4076 reg = <4>; 4077 4078 apss_tpda_in4: endpoint { 4079 remote-endpoint = <&apss_tpdm4_out>; 4080 }; 4081 }; 4082 }; 4083 4084 out-ports { 4085 port { 4086 apss_tpda_out: endpoint { 4087 remote-endpoint = <&apss_funnel1_in3>; 4088 }; 4089 }; 4090 }; 4091 }; 4092 4093 tpdm@68a0000 { 4094 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4095 reg = <0x0 0x068a0000 0x0 0x1000>; 4096 4097 clocks = <&aoss_qmp>; 4098 clock-names = "apb_pclk"; 4099 4100 qcom,cmb-element-bits = <32>; 4101 qcom,cmb-msrs-num = <32>; 4102 4103 out-ports { 4104 port { 4105 apss_tpdm1_out: endpoint { 4106 remote-endpoint = <&apss_tpda_in1>; 4107 }; 4108 }; 4109 }; 4110 }; 4111 4112 tpdm@68b0000 { 4113 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4114 reg = <0x0 0x068b0000 0x0 0x1000>; 4115 4116 clocks = <&aoss_qmp>; 4117 clock-names = "apb_pclk"; 4118 4119 qcom,cmb-element-bits = <32>; 4120 qcom,cmb-msrs-num = <32>; 4121 4122 out-ports { 4123 port { 4124 apss_tpdm0_out: endpoint { 4125 remote-endpoint = <&apss_tpda_in0>; 4126 }; 4127 }; 4128 }; 4129 }; 4130 4131 tpdm@68c0000 { 4132 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4133 reg = <0x0 0x068c0000 0x0 0x1000>; 4134 4135 clocks = <&aoss_qmp>; 4136 clock-names = "apb_pclk"; 4137 4138 qcom,dsb-element-bits = <32>; 4139 qcom,dsb-msrs-num = <32>; 4140 4141 out-ports { 4142 port { 4143 apss_tpdm2_out: endpoint { 4144 remote-endpoint = <&apss_tpda_in2>; 4145 }; 4146 }; 4147 }; 4148 }; 4149 4150 cti@68e0000 { 4151 compatible = "arm,coresight-cti", "arm,primecell"; 4152 reg = <0x0 0x068e0000 0x0 0x1000>; 4153 4154 clocks = <&aoss_qmp>; 4155 clock-names = "apb_pclk"; 4156 }; 4157 4158 cti@68f0000 { 4159 compatible = "arm,coresight-cti", "arm,primecell"; 4160 reg = <0x0 0x068f0000 0x0 0x1000>; 4161 4162 clocks = <&aoss_qmp>; 4163 clock-names = "apb_pclk"; 4164 }; 4165 4166 cti@6900000 { 4167 compatible = "arm,coresight-cti", "arm,primecell"; 4168 reg = <0x0 0x06900000 0x0 0x1000>; 4169 4170 clocks = <&aoss_qmp>; 4171 clock-names = "apb_pclk"; 4172 }; 4173 4174 sdhc_1: mmc@87c4000 { 4175 compatible = "qcom,qcs8300-sdhci", "qcom,sdhci-msm-v5"; 4176 reg = <0x0 0x087c4000 0x0 0x1000>, 4177 <0x0 0x087c5000 0x0 0x1000>; 4178 reg-names = "hc", 4179 "cqhci"; 4180 4181 interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 4182 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>; 4183 interrupt-names = "hc_irq", 4184 "pwr_irq"; 4185 4186 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 4187 <&gcc GCC_SDCC1_APPS_CLK>, 4188 <&rpmhcc RPMH_CXO_CLK>; 4189 clock-names = "iface", 4190 "core", 4191 "xo"; 4192 4193 resets = <&gcc GCC_SDCC1_BCR>; 4194 4195 power-domains = <&rpmhpd RPMHPD_CX>; 4196 operating-points-v2 = <&sdhc1_opp_table>; 4197 iommus = <&apps_smmu 0x0 0x0>; 4198 interconnects = <&aggre1_noc MASTER_SDC QCOM_ICC_TAG_ALWAYS 4199 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4200 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4201 &config_noc SLAVE_SDC1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4202 interconnect-names = "sdhc-ddr", 4203 "cpu-sdhc"; 4204 4205 qcom,dll-config = <0x000f64ee>; 4206 qcom,ddr-config = <0x80040868>; 4207 supports-cqe; 4208 dma-coherent; 4209 4210 status = "disabled"; 4211 4212 sdhc1_opp_table: opp-table { 4213 compatible = "operating-points-v2"; 4214 4215 opp-50000000 { 4216 opp-hz = /bits/ 64 <50000000>; 4217 required-opps = <&rpmhpd_opp_low_svs>; 4218 }; 4219 4220 opp-100000000 { 4221 opp-hz = /bits/ 64 <100000000>; 4222 required-opps = <&rpmhpd_opp_svs>; 4223 }; 4224 4225 opp-200000000 { 4226 opp-hz = /bits/ 64 <200000000>; 4227 required-opps = <&rpmhpd_opp_svs_l1>; 4228 }; 4229 4230 opp-384000000 { 4231 opp-hz = /bits/ 64 <384000000>; 4232 required-opps = <&rpmhpd_opp_nom>; 4233 }; 4234 }; 4235 }; 4236 4237 usb_1_hsphy: phy@8904000 { 4238 compatible = "qcom,qcs8300-usb-hs-phy", 4239 "qcom,usb-snps-hs-7nm-phy"; 4240 reg = <0x0 0x08904000 0x0 0x400>; 4241 4242 clocks = <&rpmhcc RPMH_CXO_CLK>; 4243 clock-names = "ref"; 4244 4245 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>; 4246 4247 #phy-cells = <0>; 4248 4249 status = "disabled"; 4250 }; 4251 4252 usb_2_hsphy: phy@8906000 { 4253 compatible = "qcom,qcs8300-usb-hs-phy", 4254 "qcom,usb-snps-hs-7nm-phy"; 4255 reg = <0x0 0x08906000 0x0 0x400>; 4256 4257 clocks = <&rpmhcc RPMH_CXO_CLK>; 4258 clock-names = "ref"; 4259 4260 resets = <&gcc GCC_USB2_PHY_SEC_BCR>; 4261 4262 #phy-cells = <0>; 4263 4264 status = "disabled"; 4265 }; 4266 4267 usb_qmpphy: phy@8907000 { 4268 compatible = "qcom,qcs8300-qmp-usb3-uni-phy"; 4269 reg = <0x0 0x08907000 0x0 0x2000>; 4270 4271 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4272 <&gcc GCC_USB_CLKREF_EN>, 4273 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4274 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4275 clock-names = "aux", 4276 "ref", 4277 "com_aux", 4278 "pipe"; 4279 4280 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, 4281 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>; 4282 reset-names = "phy", "phy_phy"; 4283 4284 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4285 4286 #clock-cells = <0>; 4287 clock-output-names = "usb3_prim_phy_pipe_clk_src"; 4288 4289 #phy-cells = <0>; 4290 4291 status = "disabled"; 4292 }; 4293 4294 serdes0: phy@8909000 { 4295 compatible = "qcom,qcs8300-dwmac-sgmii-phy", "qcom,sa8775p-dwmac-sgmii-phy"; 4296 reg = <0x0 0x08909000 0x0 0x00000e10>; 4297 clocks = <&gcc GCC_SGMI_CLKREF_EN>; 4298 clock-names = "sgmi_ref"; 4299 #phy-cells = <0>; 4300 status = "disabled"; 4301 }; 4302 4303 refgen: regulator@891c000 { 4304 compatible = "qcom,qcs8300-refgen-regulator", 4305 "qcom,sm8250-refgen-regulator"; 4306 reg = <0x0 0x0891c000 0x0 0x84>; 4307 }; 4308 4309 gpu: gpu@3d00000 { 4310 compatible = "qcom,adreno-623.0", "qcom,adreno"; 4311 reg = <0x0 0x03d00000 0x0 0x40000>, 4312 <0x0 0x03d9e000 0x0 0x1000>, 4313 <0x0 0x03d61000 0x0 0x800>; 4314 reg-names = "kgsl_3d0_reg_memory", 4315 "cx_mem", 4316 "cx_dbgc"; 4317 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 4318 iommus = <&adreno_smmu 0 0xc00>, 4319 <&adreno_smmu 1 0xc00>; 4320 operating-points-v2 = <&gpu_opp_table>; 4321 qcom,gmu = <&gmu>; 4322 interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS 4323 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4324 interconnect-names = "gfx-mem"; 4325 #cooling-cells = <2>; 4326 4327 nvmem-cells = <&gpu_speed_bin>; 4328 nvmem-cell-names = "speed_bin"; 4329 4330 status = "disabled"; 4331 4332 gpu_zap_shader: zap-shader { 4333 memory-region = <&gpu_microcode_mem>; 4334 }; 4335 4336 gpu_opp_table: opp-table { 4337 compatible = "operating-points-v2"; 4338 4339 opp-877000000 { 4340 opp-hz = /bits/ 64 <877000000>; 4341 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 4342 opp-peak-kBps = <12484375>; 4343 opp-supported-hw = <0x1>; 4344 }; 4345 4346 opp-780000000 { 4347 opp-hz = /bits/ 64 <780000000>; 4348 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 4349 opp-peak-kBps = <10687500>; 4350 opp-supported-hw = <0x1>; 4351 }; 4352 4353 opp-599000000 { 4354 opp-hz = /bits/ 64 <599000000>; 4355 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 4356 opp-peak-kBps = <8171875>; 4357 opp-supported-hw = <0x3>; 4358 }; 4359 4360 opp-479000000 { 4361 opp-hz = /bits/ 64 <479000000>; 4362 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 4363 opp-peak-kBps = <5285156>; 4364 opp-supported-hw = <0x3>; 4365 }; 4366 }; 4367 }; 4368 4369 gmu: gmu@3d6a000 { 4370 compatible = "qcom,adreno-gmu-623.0", "qcom,adreno-gmu"; 4371 reg = <0x0 0x03d6a000 0x0 0x34000>, 4372 <0x0 0x03de0000 0x0 0x10000>, 4373 <0x0 0x0b290000 0x0 0x10000>; 4374 reg-names = "gmu", "rscc", "gmu_pdc"; 4375 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 4376 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 4377 interrupt-names = "hfi", "gmu"; 4378 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 4379 <&gpucc GPU_CC_CXO_CLK>, 4380 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 4381 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4382 <&gpucc GPU_CC_AHB_CLK>, 4383 <&gpucc GPU_CC_HUB_CX_INT_CLK>; 4384 clock-names = "gmu", 4385 "cxo", 4386 "axi", 4387 "memnoc", 4388 "ahb", 4389 "hub"; 4390 power-domains = <&gpucc GPU_CC_CX_GDSC>, 4391 <&gpucc GPU_CC_GX_GDSC>; 4392 power-domain-names = "cx", 4393 "gx"; 4394 iommus = <&adreno_smmu 5 0xc00>; 4395 operating-points-v2 = <&gmu_opp_table>; 4396 4397 gmu_opp_table: opp-table { 4398 compatible = "operating-points-v2"; 4399 4400 opp-500000000 { 4401 opp-hz = /bits/ 64 <500000000>; 4402 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 4403 }; 4404 }; 4405 }; 4406 4407 gpucc: clock-controller@3d90000 { 4408 compatible = "qcom,qcs8300-gpucc"; 4409 reg = <0x0 0x03d90000 0x0 0xa000>; 4410 clocks = <&rpmhcc RPMH_CXO_CLK>, 4411 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 4412 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 4413 clock-names = "bi_tcxo", 4414 "gcc_gpu_gpll0_clk_src", 4415 "gcc_gpu_gpll0_div_clk_src"; 4416 #clock-cells = <1>; 4417 #reset-cells = <1>; 4418 #power-domain-cells = <1>; 4419 }; 4420 4421 adreno_smmu: iommu@3da0000 { 4422 compatible = "qcom,qcs8300-smmu-500", "qcom,adreno-smmu", 4423 "qcom,smmu-500", "arm,mmu-500"; 4424 reg = <0x0 0x3da0000 0x0 0x20000>; 4425 #iommu-cells = <2>; 4426 #global-interrupts = <2>; 4427 4428 interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, 4429 <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 4430 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 4431 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 4432 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 4433 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 4434 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 4435 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 4436 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 4437 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 4438 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 4439 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 4440 4441 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 4442 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 4443 <&gpucc GPU_CC_AHB_CLK>, 4444 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 4445 <&gpucc GPU_CC_CX_GMU_CLK>, 4446 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 4447 <&gpucc GPU_CC_HUB_AON_CLK>; 4448 4449 clock-names = "gcc_gpu_memnoc_gfx_clk", 4450 "gcc_gpu_snoc_dvm_gfx_clk", 4451 "gpu_cc_ahb_clk", 4452 "gpu_cc_hlos1_vote_gpu_smmu_clk", 4453 "gpu_cc_cx_gmu_clk", 4454 "gpu_cc_hub_cx_int_clk", 4455 "gpu_cc_hub_aon_clk"; 4456 power-domains = <&gpucc GPU_CC_CX_GDSC>; 4457 dma-coherent; 4458 }; 4459 4460 pmu@9091000 { 4461 compatible = "qcom,qcs8300-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; 4462 reg = <0x0 0x9091000 0x0 0x1000>; 4463 4464 interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>; 4465 4466 interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY 4467 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 4468 4469 operating-points-v2 = <&llcc_bwmon_opp_table>; 4470 4471 llcc_bwmon_opp_table: opp-table { 4472 compatible = "operating-points-v2"; 4473 4474 opp-0 { 4475 opp-peak-kBps = <762000>; 4476 }; 4477 4478 opp-1 { 4479 opp-peak-kBps = <1720000>; 4480 }; 4481 4482 opp-2 { 4483 opp-peak-kBps = <2086000>; 4484 }; 4485 4486 opp-3 { 4487 opp-peak-kBps = <2601000>; 4488 }; 4489 4490 opp-4 { 4491 opp-peak-kBps = <2929000>; 4492 }; 4493 4494 opp-5 { 4495 opp-peak-kBps = <5931000>; 4496 }; 4497 4498 opp-6 { 4499 opp-peak-kBps = <6515000>; 4500 }; 4501 4502 opp-7 { 4503 opp-peak-kBps = <7984000>; 4504 }; 4505 4506 opp-8 { 4507 opp-peak-kBps = <10437000>; 4508 }; 4509 4510 opp-9 { 4511 opp-peak-kBps = <12195000>; 4512 }; 4513 }; 4514 }; 4515 4516 pmu@90b5400 { 4517 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 4518 reg = <0x0 0x90b5400 0x0 0x600>; 4519 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4520 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4521 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4522 4523 operating-points-v2 = <&cpu_bwmon_opp_table>; 4524 4525 cpu_bwmon_opp_table: opp-table { 4526 compatible = "operating-points-v2"; 4527 4528 opp-0 { 4529 opp-peak-kBps = <9155000>; 4530 }; 4531 4532 opp-1 { 4533 opp-peak-kBps = <12298000>; 4534 }; 4535 4536 opp-2 { 4537 opp-peak-kBps = <14236000>; 4538 }; 4539 4540 opp-3 { 4541 opp-peak-kBps = <16265000>; 4542 }; 4543 }; 4544 }; 4545 4546 pmu@90b6400 { 4547 compatible = "qcom,qcs8300-cpu-bwmon", "qcom,sdm845-bwmon"; 4548 reg = <0x0 0x90b6400 0x0 0x600>; 4549 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4550 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4551 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; 4552 4553 operating-points-v2 = <&cpu_bwmon_opp_table>; 4554 }; 4555 4556 dc_noc: interconnect@90e0000 { 4557 compatible = "qcom,qcs8300-dc-noc"; 4558 reg = <0x0 0x090e0000 0x0 0x5080>; 4559 #interconnect-cells = <2>; 4560 qcom,bcm-voters = <&apps_bcm_voter>; 4561 }; 4562 4563 gem_noc: interconnect@9100000 { 4564 compatible = "qcom,qcs8300-gem-noc"; 4565 reg = <0x0 0x9100000 0x0 0xf7080>; 4566 #interconnect-cells = <2>; 4567 qcom,bcm-voters = <&apps_bcm_voter>; 4568 }; 4569 4570 llcc: system-cache-controller@9200000 { 4571 compatible = "qcom,qcs8300-llcc"; 4572 reg = <0x0 0x09200000 0x0 0x80000>, 4573 <0x0 0x09300000 0x0 0x80000>, 4574 <0x0 0x09400000 0x0 0x80000>, 4575 <0x0 0x09500000 0x0 0x80000>, 4576 <0x0 0x09a00000 0x0 0x80000>; 4577 reg-names = "llcc0_base", 4578 "llcc1_base", 4579 "llcc2_base", 4580 "llcc3_base", 4581 "llcc_broadcast_base"; 4582 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4583 }; 4584 4585 usb_1: usb@a600000 { 4586 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 4587 reg = <0x0 0x0a600000 0x0 0xfc100>; 4588 4589 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4590 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4591 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4592 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4593 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4594 clock-names = "cfg_noc", 4595 "core", 4596 "iface", 4597 "sleep", 4598 "mock_utmi"; 4599 4600 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4601 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4602 assigned-clock-rates = <19200000>, <200000000>; 4603 4604 interrupts-extended = <&intc GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 4605 <&intc GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 4606 <&intc GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 4607 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4608 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4609 <&pdc 12 IRQ_TYPE_LEVEL_HIGH>; 4610 interrupt-names = "dwc_usb3", 4611 "pwr_event", 4612 "hs_phy_irq", 4613 "dp_hs_phy_irq", 4614 "dm_hs_phy_irq", 4615 "ss_phy_irq"; 4616 4617 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4618 required-opps = <&rpmhpd_opp_nom>; 4619 4620 resets = <&gcc GCC_USB30_PRIM_BCR>; 4621 interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS 4622 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4623 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4624 &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ALWAYS>; 4625 interconnect-names = "usb-ddr", "apps-usb"; 4626 4627 iommus = <&apps_smmu 0x80 0x0>; 4628 phys = <&usb_1_hsphy>, <&usb_qmpphy>; 4629 phy-names = "usb2-phy", "usb3-phy"; 4630 snps,dis_enblslpm_quirk; 4631 snps,dis-u1-entry-quirk; 4632 snps,dis-u2-entry-quirk; 4633 snps,dis_u2_susphy_quirk; 4634 snps,dis_u3_susphy_quirk; 4635 4636 wakeup-source; 4637 4638 status = "disabled"; 4639 }; 4640 4641 usb_2: usb@a400000 { 4642 compatible = "qcom,qcs8300-dwc3", "qcom,snps-dwc3"; 4643 reg = <0x0 0x0a400000 0x0 0xfc100>; 4644 4645 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>, 4646 <&gcc GCC_USB20_MASTER_CLK>, 4647 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>, 4648 <&gcc GCC_USB20_SLEEP_CLK>, 4649 <&gcc GCC_USB20_MOCK_UTMI_CLK>; 4650 clock-names = "cfg_noc", 4651 "core", 4652 "iface", 4653 "sleep", 4654 "mock_utmi"; 4655 4656 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>, 4657 <&gcc GCC_USB20_MASTER_CLK>; 4658 assigned-clock-rates = <19200000>, <120000000>; 4659 4660 interrupts-extended = <&intc GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, 4661 <&intc GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>, 4662 <&intc GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, 4663 <&pdc 10 IRQ_TYPE_EDGE_BOTH>, 4664 <&pdc 9 IRQ_TYPE_EDGE_BOTH>; 4665 interrupt-names = "dwc_usb3", 4666 "pwr_event", 4667 "hs_phy_irq", 4668 "dp_hs_phy_irq", 4669 "dm_hs_phy_irq"; 4670 4671 power-domains = <&gcc GCC_USB20_PRIM_GDSC>; 4672 required-opps = <&rpmhpd_opp_nom>; 4673 4674 resets = <&gcc GCC_USB20_PRIM_BCR>; 4675 4676 interconnects = <&aggre1_noc MASTER_USB2 QCOM_ICC_TAG_ALWAYS 4677 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 4678 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 4679 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>; 4680 interconnect-names = "usb-ddr", "apps-usb"; 4681 4682 iommus = <&apps_smmu 0x20 0x0>; 4683 4684 phys = <&usb_2_hsphy>; 4685 phy-names = "usb2-phy"; 4686 maximum-speed = "high-speed"; 4687 4688 snps,dis-u1-entry-quirk; 4689 snps,dis-u2-entry-quirk; 4690 snps,dis_u2_susphy_quirk; 4691 snps,dis_u3_susphy_quirk; 4692 snps,dis_enblslpm_quirk; 4693 4694 qcom,select-utmi-as-pipe-clk; 4695 wakeup-source; 4696 4697 status = "disabled"; 4698 }; 4699 4700 iris: video-codec@aa00000 { 4701 compatible = "qcom,qcs8300-iris"; 4702 4703 reg = <0x0 0x0aa00000 0x0 0xf0000>; 4704 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4705 4706 power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>, 4707 <&videocc VIDEO_CC_MVS0_GDSC>, 4708 <&rpmhpd RPMHPD_MX>, 4709 <&rpmhpd RPMHPD_MMCX>; 4710 power-domain-names = "venus", 4711 "vcodec0", 4712 "mxc", 4713 "mmcx"; 4714 4715 operating-points-v2 = <&iris_opp_table>; 4716 4717 clocks = <&gcc GCC_VIDEO_AXI0_CLK>, 4718 <&videocc VIDEO_CC_MVS0C_CLK>, 4719 <&videocc VIDEO_CC_MVS0_CLK>; 4720 clock-names = "iface", 4721 "core", 4722 "vcodec0_core"; 4723 4724 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 4725 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 4726 <&mmss_noc MASTER_VIDEO_P0 QCOM_ICC_TAG_ALWAYS 4727 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 4728 interconnect-names = "cpu-cfg", 4729 "video-mem"; 4730 4731 memory-region = <&video_mem>; 4732 4733 resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>; 4734 reset-names = "bus"; 4735 4736 iommus = <&apps_smmu 0x0880 0x0400>, 4737 <&apps_smmu 0x0887 0x0400>; 4738 dma-coherent; 4739 4740 status = "disabled"; 4741 4742 iris_opp_table: opp-table { 4743 compatible = "operating-points-v2"; 4744 4745 opp-366000000 { 4746 opp-hz = /bits/ 64 <366000000>; 4747 required-opps = <&rpmhpd_opp_svs_l1>, 4748 <&rpmhpd_opp_svs_l1>; 4749 }; 4750 4751 opp-444000000 { 4752 opp-hz = /bits/ 64 <444000000>; 4753 required-opps = <&rpmhpd_opp_nom>, 4754 <&rpmhpd_opp_nom>; 4755 }; 4756 4757 opp-533000000 { 4758 opp-hz = /bits/ 64 <533000000>; 4759 required-opps = <&rpmhpd_opp_turbo>, 4760 <&rpmhpd_opp_turbo>; 4761 }; 4762 4763 opp-560000000 { 4764 opp-hz = /bits/ 64 <560000000>; 4765 required-opps = <&rpmhpd_opp_turbo_l1>, 4766 <&rpmhpd_opp_turbo_l1>; 4767 }; 4768 }; 4769 }; 4770 4771 videocc: clock-controller@abf0000 { 4772 compatible = "qcom,qcs8300-videocc"; 4773 reg = <0x0 0x0abf0000 0x0 0x10000>; 4774 clocks = <&gcc GCC_VIDEO_AHB_CLK>, 4775 <&rpmhcc RPMH_CXO_CLK>, 4776 <&rpmhcc RPMH_CXO_CLK_A>, 4777 <&sleep_clk>; 4778 power-domains = <&rpmhpd RPMHPD_MMCX>; 4779 #clock-cells = <1>; 4780 #reset-cells = <1>; 4781 #power-domain-cells = <1>; 4782 }; 4783 4784 camcc: clock-controller@ade0000 { 4785 compatible = "qcom,qcs8300-camcc"; 4786 reg = <0x0 0x0ade0000 0x0 0x20000>; 4787 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 4788 <&rpmhcc RPMH_CXO_CLK>, 4789 <&rpmhcc RPMH_CXO_CLK_A>, 4790 <&sleep_clk>; 4791 power-domains = <&rpmhpd RPMHPD_MMCX>; 4792 #clock-cells = <1>; 4793 #reset-cells = <1>; 4794 #power-domain-cells = <1>; 4795 }; 4796 4797 dispcc: clock-controller@af00000 { 4798 compatible = "qcom,sa8775p-dispcc0"; 4799 reg = <0x0 0x0af00000 0x0 0x20000>; 4800 clocks = <&gcc GCC_DISP_AHB_CLK>, 4801 <&rpmhcc RPMH_CXO_CLK>, 4802 <&rpmhcc RPMH_CXO_CLK_A>, 4803 <&sleep_clk>, 4804 <0>, <0>, <0>, <0>, 4805 <0>, <0>, <0>, <0>; 4806 power-domains = <&rpmhpd RPMHPD_MMCX>; 4807 #clock-cells = <1>; 4808 #reset-cells = <1>; 4809 #power-domain-cells = <1>; 4810 }; 4811 4812 pdc: interrupt-controller@b220000 { 4813 compatible = "qcom,qcs8300-pdc", "qcom,pdc"; 4814 reg = <0x0 0xb220000 0x0 0x30000>, 4815 <0x0 0x17c000f0 0x0 0x64>; 4816 interrupt-parent = <&intc>; 4817 #interrupt-cells = <2>; 4818 interrupt-controller; 4819 qcom,pdc-ranges = <0 480 40>, 4820 <40 140 14>, 4821 <54 263 1>, 4822 <55 306 4>, 4823 <59 312 3>, 4824 <62 374 2>, 4825 <64 434 2>, 4826 <66 438 2>, 4827 <70 520 1>, 4828 <73 523 1>, 4829 <118 568 6>, 4830 <124 609 3>, 4831 <159 638 1>, 4832 <160 720 3>, 4833 <169 728 30>, 4834 <199 416 2>, 4835 <201 449 1>, 4836 <202 89 1>, 4837 <203 451 1>, 4838 <204 462 1>, 4839 <205 264 1>, 4840 <206 579 1>, 4841 <207 653 1>, 4842 <208 656 1>, 4843 <209 659 1>, 4844 <210 122 1>, 4845 <211 699 1>, 4846 <212 705 1>, 4847 <213 450 1>, 4848 <214 643 2>, 4849 <216 646 5>, 4850 <221 390 5>, 4851 <226 700 2>, 4852 <228 440 1>, 4853 <229 663 1>, 4854 <230 524 2>, 4855 <232 612 3>, 4856 <235 723 5>; 4857 }; 4858 4859 aoss_qmp: power-management@c300000 { 4860 compatible = "qcom,qcs8300-aoss-qmp", "qcom,aoss-qmp"; 4861 reg = <0x0 0x0c300000 0x0 0x400>; 4862 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 4863 IPCC_MPROC_SIGNAL_GLINK_QMP 4864 IRQ_TYPE_EDGE_RISING>; 4865 mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; 4866 #clock-cells = <0>; 4867 }; 4868 4869 sram@c3f0000 { 4870 compatible = "qcom,rpmh-stats"; 4871 reg = <0x0 0x0c3f0000 0x0 0x400>; 4872 }; 4873 4874 spmi_bus: spmi@c440000 { 4875 compatible = "qcom,spmi-pmic-arb"; 4876 reg = <0x0 0x0c440000 0x0 0x1100>, 4877 <0x0 0x0c600000 0x0 0x2000000>, 4878 <0x0 0x0e600000 0x0 0x100000>, 4879 <0x0 0x0e700000 0x0 0xa0000>, 4880 <0x0 0x0c40a000 0x0 0x26000>; 4881 reg-names = "core", 4882 "chnls", 4883 "obsrvr", 4884 "intr", 4885 "cnfg"; 4886 qcom,channel = <0>; 4887 qcom,ee = <0>; 4888 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 4889 interrupt-names = "periph_irq"; 4890 interrupt-controller; 4891 #interrupt-cells = <4>; 4892 #address-cells = <2>; 4893 #size-cells = <0>; 4894 }; 4895 4896 tlmm: pinctrl@f100000 { 4897 compatible = "qcom,qcs8300-tlmm"; 4898 reg = <0x0 0x0f100000 0x0 0x300000>; 4899 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 4900 gpio-controller; 4901 #gpio-cells = <2>; 4902 gpio-ranges = <&tlmm 0 0 134>; 4903 interrupt-controller; 4904 #interrupt-cells = <2>; 4905 wakeup-parent = <&pdc>; 4906 4907 hs0_mi2s_active: hs0-mi2s-active-state { 4908 pins = "gpio106", "gpio107", "gpio108", "gpio109"; 4909 function = "hs0_mi2s"; 4910 drive-strength = <8>; 4911 bias-disable; 4912 }; 4913 4914 mi2s1_active: mi2s1-active-state { 4915 data0-pins { 4916 pins = "gpio100"; 4917 function = "mi2s1_data0"; 4918 drive-strength = <8>; 4919 bias-disable; 4920 }; 4921 4922 data1-pins { 4923 pins = "gpio101"; 4924 function = "mi2s1_data1"; 4925 drive-strength = <8>; 4926 bias-disable; 4927 }; 4928 4929 sclk-pins { 4930 pins = "gpio98"; 4931 function = "mi2s1_sck"; 4932 drive-strength = <8>; 4933 bias-disable; 4934 }; 4935 4936 ws-pins { 4937 pins = "gpio99"; 4938 function = "mi2s1_ws"; 4939 drive-strength = <8>; 4940 bias-disable; 4941 }; 4942 }; 4943 4944 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 4945 pins = "gpio17", "gpio18"; 4946 function = "qup0_se0"; 4947 }; 4948 4949 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 4950 pins = "gpio19", "gpio20"; 4951 function = "qup0_se1"; 4952 }; 4953 4954 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 4955 pins = "gpio33", "gpio34"; 4956 function = "qup0_se2"; 4957 }; 4958 4959 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 4960 pins = "gpio25", "gpio26"; 4961 function = "qup0_se3"; 4962 }; 4963 4964 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 4965 pins = "gpio29", "gpio30"; 4966 function = "qup0_se4"; 4967 }; 4968 4969 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 4970 pins = "gpio21", "gpio22"; 4971 function = "qup0_se5"; 4972 }; 4973 4974 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 4975 pins = "gpio80", "gpio81"; 4976 function = "qup0_se6"; 4977 }; 4978 4979 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 4980 pins = "gpio37", "gpio38"; 4981 function = "qup1_se0"; 4982 }; 4983 4984 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 4985 pins = "gpio39", "gpio40"; 4986 function = "qup1_se1"; 4987 }; 4988 4989 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 4990 pins = "gpio84", "gpio85"; 4991 function = "qup1_se2"; 4992 }; 4993 4994 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 4995 pins = "gpio41", "gpio42"; 4996 function = "qup1_se3"; 4997 }; 4998 4999 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 5000 pins = "gpio45", "gpio46"; 5001 function = "qup1_se4"; 5002 }; 5003 5004 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 5005 pins = "gpio49", "gpio50"; 5006 function = "qup1_se5"; 5007 }; 5008 5009 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 5010 pins = "gpio89", "gpio90"; 5011 function = "qup1_se6"; 5012 }; 5013 5014 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 5015 pins = "gpio91", "gpio92"; 5016 function = "qup1_se7"; 5017 }; 5018 5019 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 5020 pins = "gpio10", "gpio11"; 5021 function = "qup2_se0"; 5022 }; 5023 5024 qup_spi0_data_clk: qup-spi0-data-clk-state { 5025 pins = "gpio17", "gpio18", "gpio19"; 5026 function = "qup0_se0"; 5027 }; 5028 5029 qup_spi0_cs: qup-spi0-cs-state { 5030 pins = "gpio20"; 5031 function = "qup0_se0"; 5032 }; 5033 5034 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 5035 pins = "gpio20"; 5036 function = "gpio"; 5037 }; 5038 5039 qup_spi1_data_clk: qup-spi1-data-clk-state { 5040 pins = "gpio19", "gpio20", "gpio17"; 5041 function = "qup0_se1"; 5042 }; 5043 5044 qup_spi1_cs: qup-spi1-cs-state { 5045 pins = "gpio18"; 5046 function = "qup0_se1"; 5047 }; 5048 5049 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 5050 pins = "gpio18"; 5051 function = "gpio"; 5052 }; 5053 5054 qup_spi2_data_clk: qup-spi2-data-clk-state { 5055 pins = "gpio33", "gpio34", "gpio35"; 5056 function = "qup0_se2"; 5057 }; 5058 5059 qup_spi2_cs: qup-spi2-cs-state { 5060 pins = "gpio36"; 5061 function = "qup0_se2"; 5062 }; 5063 5064 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 5065 pins = "gpio36"; 5066 function = "gpio"; 5067 }; 5068 5069 qup_spi3_data_clk: qup-spi3-data-clk-state { 5070 pins = "gpio25", "gpio26", "gpio27"; 5071 function = "qup0_se3"; 5072 }; 5073 5074 qup_spi3_cs: qup-spi3-cs-state { 5075 pins = "gpio28"; 5076 function = "qup0_se3"; 5077 }; 5078 5079 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 5080 pins = "gpio28"; 5081 function = "gpio"; 5082 }; 5083 5084 qup_spi4_data_clk: qup-spi4-data-clk-state { 5085 pins = "gpio29", "gpio30", "gpio31"; 5086 function = "qup0_se4"; 5087 }; 5088 5089 qup_spi4_cs: qup-spi4-cs-state { 5090 pins = "gpio32"; 5091 function = "qup0_se4"; 5092 }; 5093 5094 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 5095 pins = "gpio32"; 5096 function = "gpio"; 5097 }; 5098 5099 qup_spi5_data_clk: qup-spi5-data-clk-state { 5100 pins = "gpio21", "gpio22", "gpio23"; 5101 function = "qup0_se5"; 5102 }; 5103 5104 qup_spi5_cs: qup-spi5-cs-state { 5105 pins = "gpio24"; 5106 function = "qup0_se5"; 5107 }; 5108 5109 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 5110 pins = "gpio24"; 5111 function = "gpio"; 5112 }; 5113 5114 qup_spi6_data_clk: qup-spi6-data-clk-state { 5115 pins = "gpio80", "gpio81", "gpio82"; 5116 function = "qup0_se6"; 5117 }; 5118 5119 qup_spi6_cs: qup-spi6-cs-state { 5120 pins = "gpio83"; 5121 function = "qup0_se6"; 5122 }; 5123 5124 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 5125 pins = "gpio83"; 5126 function = "gpio"; 5127 }; 5128 5129 qup_spi8_data_clk: qup-spi8-data-clk-state { 5130 pins = "gpio37", "gpio38", "gpio39"; 5131 function = "qup1_se0"; 5132 }; 5133 5134 qup_spi8_cs: qup-spi8-cs-state { 5135 pins = "gpio40"; 5136 function = "qup1_se0"; 5137 }; 5138 5139 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 5140 pins = "gpio40"; 5141 function = "gpio"; 5142 }; 5143 5144 qup_spi9_data_clk: qup-spi9-data-clk-state { 5145 pins = "gpio39", "gpio40", "gpio37"; 5146 function = "qup1_se1"; 5147 }; 5148 5149 qup_spi9_cs: qup-spi9-cs-state { 5150 pins = "gpio38"; 5151 function = "qup1_se1"; 5152 }; 5153 5154 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 5155 pins = "gpio38"; 5156 function = "gpio"; 5157 }; 5158 5159 qup_spi10_data_clk: qup-spi10-data-clk-state { 5160 pins = "gpio84", "gpio85", "gpio86"; 5161 function = "qup1_se2"; 5162 }; 5163 5164 qup_spi10_cs: qup-spi10-cs-state { 5165 pins = "gpio87"; 5166 function = "qup1_se2"; 5167 }; 5168 5169 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 5170 pins = "gpio87"; 5171 function = "gpio"; 5172 }; 5173 5174 qup_spi12_data_clk: qup-spi12-data-clk-state { 5175 pins = "gpio45", "gpio46", "gpio47"; 5176 function = "qup1_se4"; 5177 }; 5178 5179 qup_spi12_cs: qup-spi12-cs-state { 5180 pins = "gpio48"; 5181 function = "qup1_se4"; 5182 }; 5183 5184 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 5185 pins = "gpio48"; 5186 function = "gpio"; 5187 }; 5188 5189 qup_spi13_data_clk: qup-spi13-data-clk-state { 5190 pins = "gpio49", "gpio50", "gpio51"; 5191 function = "qup1_se5"; 5192 }; 5193 5194 qup_spi13_cs: qup-spi13-cs-state { 5195 pins = "gpio52"; 5196 function = "qup1_se5"; 5197 }; 5198 5199 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 5200 pins = "gpio52"; 5201 function = "gpio"; 5202 }; 5203 5204 qup_spi14_data_clk: qup-spi14-data-clk-state { 5205 pins = "gpio89", "gpio90", "gpio91"; 5206 function = "qup1_se6"; 5207 }; 5208 5209 qup_spi14_cs: qup-spi14-cs-state { 5210 pins = "gpio92"; 5211 function = "qup1_se6"; 5212 }; 5213 5214 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 5215 pins = "gpio92"; 5216 function = "gpio"; 5217 }; 5218 5219 qup_spi15_data_clk: qup-spi15-data-clk-state { 5220 pins = "gpio91", "gpio92", "gpio89"; 5221 function = "qup1_se7"; 5222 }; 5223 5224 qup_spi15_cs: qup-spi15-cs-state { 5225 pins = "gpio90"; 5226 function = "qup1_se7"; 5227 }; 5228 5229 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 5230 pins = "gpio90"; 5231 function = "gpio"; 5232 }; 5233 5234 qup_spi16_data_clk: qup-spi16-data-clk-state { 5235 pins = "gpio10", "gpio11", "gpio12"; 5236 function = "qup2_se0"; 5237 }; 5238 5239 qup_spi16_cs: qup-spi16-cs-state { 5240 pins = "gpio13"; 5241 function = "qup2_se0"; 5242 }; 5243 5244 qup_spi16_cs_gpio: qup-spi16-cs-gpio-state { 5245 pins = "gpio13"; 5246 function = "gpio"; 5247 }; 5248 5249 qup_uart0_cts: qup-uart0-cts-state { 5250 pins = "gpio17"; 5251 function = "qup0_se0"; 5252 }; 5253 5254 qup_uart0_rts: qup-uart0-rts-state { 5255 pins = "gpio18"; 5256 function = "qup0_se0"; 5257 }; 5258 5259 qup_uart0_tx: qup-uart0-tx-state { 5260 pins = "gpio19"; 5261 function = "qup0_se0"; 5262 }; 5263 5264 qup_uart0_rx: qup-uart0-rx-state { 5265 pins = "gpio20"; 5266 function = "qup0_se0"; 5267 }; 5268 5269 qup_uart1_cts: qup-uart1-cts-state { 5270 pins = "gpio19"; 5271 function = "qup0_se1"; 5272 }; 5273 5274 qup_uart1_rts: qup-uart1-rts-state { 5275 pins = "gpio20"; 5276 function = "qup0_se1"; 5277 }; 5278 5279 qup_uart1_tx: qup-uart1-tx-state { 5280 pins = "gpio17"; 5281 function = "qup0_se1"; 5282 }; 5283 5284 qup_uart1_rx: qup-uart1-rx-state { 5285 pins = "gpio18"; 5286 function = "qup0_se1"; 5287 }; 5288 5289 qup_uart2_cts: qup-uart2-cts-state { 5290 pins = "gpio33"; 5291 function = "qup0_se2"; 5292 }; 5293 5294 qup_uart2_rts: qup-uart2-rts-state { 5295 pins = "gpio34"; 5296 function = "qup0_se2"; 5297 }; 5298 5299 qup_uart2_tx: qup-uart2-tx-state { 5300 pins = "gpio35"; 5301 function = "qup0_se2"; 5302 }; 5303 5304 qup_uart2_rx: qup-uart2-rx-state { 5305 pins = "gpio36"; 5306 function = "qup0_se2"; 5307 }; 5308 5309 qup_uart3_cts: qup-uart3-cts-state { 5310 pins = "gpio25"; 5311 function = "qup0_se3"; 5312 }; 5313 5314 qup_uart3_rts: qup-uart3-rts-state { 5315 pins = "gpio26"; 5316 function = "qup0_se3"; 5317 }; 5318 5319 qup_uart3_tx: qup-uart3-tx-state { 5320 pins = "gpio27"; 5321 function = "qup0_se3"; 5322 }; 5323 5324 qup_uart3_rx: qup-uart3-rx-state { 5325 pins = "gpio28"; 5326 function = "qup0_se3"; 5327 }; 5328 5329 qup_uart4_cts: qup-uart4-cts-state { 5330 pins = "gpio29"; 5331 function = "qup0_se4"; 5332 }; 5333 5334 qup_uart4_rts: qup-uart4-rts-state { 5335 pins = "gpio30"; 5336 function = "qup0_se4"; 5337 }; 5338 5339 qup_uart4_tx: qup-uart4-tx-state { 5340 pins = "gpio31"; 5341 function = "qup0_se4"; 5342 }; 5343 5344 qup_uart4_rx: qup-uart4-rx-state { 5345 pins = "gpio32"; 5346 function = "qup0_se4"; 5347 }; 5348 5349 qup_uart5_cts: qup-uart5-cts-state { 5350 pins = "gpio21"; 5351 function = "qup0_se5"; 5352 }; 5353 5354 qup_uart5_rts: qup-uart5-rts-state { 5355 pins = "gpio22"; 5356 function = "qup0_se5"; 5357 }; 5358 5359 qup_uart5_tx: qup-uart5-tx-state { 5360 pins = "gpio23"; 5361 function = "qup0_se5"; 5362 }; 5363 5364 qup_uart5_rx: qup-uart5-rx-state { 5365 pins = "gpio23"; 5366 function = "qup0_se5"; 5367 }; 5368 5369 qup_uart6_cts: qup-uart6-cts-state { 5370 pins = "gpio80"; 5371 function = "qup0_se6"; 5372 }; 5373 5374 qup_uart6_rts: qup-uart6-rts-state { 5375 pins = "gpio81"; 5376 function = "qup0_se6"; 5377 }; 5378 5379 qup_uart6_tx: qup-uart6-tx-state { 5380 pins = "gpio82"; 5381 function = "qup0_se6"; 5382 }; 5383 5384 qup_uart6_rx: qup-uart6-rx-state { 5385 pins = "gpio83"; 5386 function = "qup0_se6"; 5387 }; 5388 5389 qup_uart7_tx: qup-uart7-tx-state { 5390 pins = "gpio43"; 5391 function = "qup0_se7"; 5392 }; 5393 5394 qup_uart7_rx: qup-uart7-rx-state { 5395 pins = "gpio44"; 5396 function = "qup0_se7"; 5397 }; 5398 5399 qup_uart8_cts: qup-uart8-cts-state { 5400 pins = "gpio37"; 5401 function = "qup1_se0"; 5402 }; 5403 5404 qup_uart8_rts: qup-uart8-rts-state { 5405 pins = "gpio38"; 5406 function = "qup1_se0"; 5407 }; 5408 5409 qup_uart8_tx: qup-uart8-tx-state { 5410 pins = "gpio39"; 5411 function = "qup1_se0"; 5412 }; 5413 5414 qup_uart8_rx: qup-uart8-rx-state { 5415 pins = "gpio40"; 5416 function = "qup1_se0"; 5417 }; 5418 5419 qup_uart9_cts: qup-uart9-cts-state { 5420 pins = "gpio39"; 5421 function = "qup1_se1"; 5422 }; 5423 5424 qup_uart9_rts: qup-uart9-rts-state { 5425 pins = "gpio40"; 5426 function = "qup1_se1"; 5427 }; 5428 5429 qup_uart9_tx: qup-uart9-tx-state { 5430 pins = "gpio37"; 5431 function = "qup1_se1"; 5432 }; 5433 5434 qup_uart9_rx: qup-uart9-rx-state { 5435 pins = "gpio38"; 5436 function = "qup1_se1"; 5437 }; 5438 5439 qup_uart10_cts: qup-uart10-cts-state { 5440 pins = "gpio84"; 5441 function = "qup1_se2"; 5442 }; 5443 5444 qup_uart10_rts: qup-uart10-rts-state { 5445 pins = "gpio85"; 5446 function = "qup1_se2"; 5447 }; 5448 5449 qup_uart10_tx: qup-uart10-tx-state { 5450 pins = "gpio86"; 5451 function = "qup1_se2"; 5452 }; 5453 5454 qup_uart10_rx: qup-uart10-rx-state { 5455 pins = "gpio87"; 5456 function = "qup1_se2"; 5457 }; 5458 5459 qup_uart11_tx: qup-uart11-tx-state { 5460 pins = "gpio41"; 5461 function = "qup1_se3"; 5462 }; 5463 5464 qup_uart11_rx: qup-uart11-rx-state { 5465 pins = "gpio42"; 5466 function = "qup1_se3"; 5467 }; 5468 5469 qup_uart12_cts: qup-uart12-cts-state { 5470 pins = "gpio45"; 5471 function = "qup1_se4"; 5472 }; 5473 5474 qup_uart12_rts: qup-uart12-rts-state { 5475 pins = "gpio46"; 5476 function = "qup1_se4"; 5477 }; 5478 5479 qup_uart12_tx: qup-uart12-tx-state { 5480 pins = "gpio47"; 5481 function = "qup1_se4"; 5482 }; 5483 5484 qup_uart12_rx: qup-uart12-rx-state { 5485 pins = "gpio48"; 5486 function = "qup1_se4"; 5487 }; 5488 5489 qup_uart13_cts: qup-uart13-cts-state { 5490 pins = "gpio49"; 5491 function = "qup1_se5"; 5492 }; 5493 5494 qup_uart13_rts: qup-uart13-rts-state { 5495 pins = "gpio50"; 5496 function = "qup1_se5"; 5497 }; 5498 5499 qup_uart13_tx: qup-uart13-tx-state { 5500 pins = "gpio51"; 5501 function = "qup1_se5"; 5502 }; 5503 5504 qup_uart13_rx: qup-uart13-rx-state { 5505 pins = "gpio52"; 5506 function = "qup1_se5"; 5507 }; 5508 5509 qup_uart14_cts: qup-uart14-cts-state { 5510 pins = "gpio89"; 5511 function = "qup1_se6"; 5512 }; 5513 5514 qup_uart14_rts: qup-uart14-rts-state { 5515 pins = "gpio90"; 5516 function = "qup1_se6"; 5517 }; 5518 5519 qup_uart14_tx: qup-uart14-tx-state { 5520 pins = "gpio91"; 5521 function = "qup1_se6"; 5522 }; 5523 5524 qup_uart14_rx: qup-uart14-rx-state { 5525 pins = "gpio92"; 5526 function = "qup1_se6"; 5527 }; 5528 5529 qup_uart15_cts: qup-uart15-cts-state { 5530 pins = "gpio91"; 5531 function = "qup1_se7"; 5532 }; 5533 5534 qup_uart15_rts: qup-uart15-rts-state { 5535 pins = "gpio92"; 5536 function = "qup1_se7"; 5537 }; 5538 5539 qup_uart15_tx: qup-uart15-tx-state { 5540 pins = "gpio89"; 5541 function = "qup1_se7"; 5542 }; 5543 5544 qup_uart15_rx: qup-uart15-rx-state { 5545 pins = "gpio90"; 5546 function = "qup1_se7"; 5547 }; 5548 5549 qup_uart16_cts: qup-uart16-cts-state { 5550 pins = "gpio10"; 5551 function = "qup2_se0"; 5552 }; 5553 5554 qup_uart16_rts: qup-uart16-rts-state { 5555 pins = "gpio11"; 5556 function = "qup2_se0"; 5557 }; 5558 5559 qup_uart16_tx: qup-uart16-tx-state { 5560 pins = "gpio12"; 5561 function = "qup2_se0"; 5562 }; 5563 5564 qup_uart16_rx: qup-uart16-rx-state { 5565 pins = "gpio13"; 5566 function = "qup2_se0"; 5567 }; 5568 5569 sdc1_state_on: sdc1-on-state { 5570 clk-pins { 5571 pins = "sdc1_clk"; 5572 drive-strength = <16>; 5573 bias-disable; 5574 }; 5575 5576 cmd-pins { 5577 pins = "sdc1_cmd"; 5578 drive-strength = <10>; 5579 bias-pull-up; 5580 }; 5581 5582 data-pins { 5583 pins = "sdc1_data"; 5584 drive-strength = <10>; 5585 bias-pull-up; 5586 }; 5587 5588 rclk-pins { 5589 pins = "sdc1_rclk"; 5590 bias-pull-down; 5591 }; 5592 }; 5593 5594 sdc1_state_off: sdc1-off-state { 5595 clk-pins { 5596 pins = "sdc1_clk"; 5597 drive-strength = <2>; 5598 bias-bus-hold; 5599 }; 5600 5601 cmd-pins { 5602 pins = "sdc1_cmd"; 5603 drive-strength = <2>; 5604 bias-bus-hold; 5605 }; 5606 5607 data-pins { 5608 pins = "sdc1_data"; 5609 drive-strength = <2>; 5610 bias-bus-hold; 5611 }; 5612 5613 rclk-pins { 5614 pins = "sdc1_rclk"; 5615 bias-bus-hold; 5616 }; 5617 }; 5618 }; 5619 5620 sram: sram@146d8000 { 5621 compatible = "qcom,qcs8300-imem", "syscon", "simple-mfd"; 5622 reg = <0x0 0x146d8000 0x0 0x1000>; 5623 ranges = <0x0 0x0 0x146d8000 0x1000>; 5624 5625 #address-cells = <1>; 5626 #size-cells = <1>; 5627 5628 pil-reloc@94c { 5629 compatible = "qcom,pil-reloc-info"; 5630 reg = <0x94c 0xc8>; 5631 }; 5632 }; 5633 5634 apps_smmu: iommu@15000000 { 5635 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5636 5637 reg = <0x0 0x15000000 0x0 0x100000>; 5638 #iommu-cells = <2>; 5639 #global-interrupts = <2>; 5640 dma-coherent; 5641 5642 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 5643 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 5644 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5645 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5646 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5647 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5648 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5649 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5650 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5651 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5652 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5653 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5654 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5655 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5656 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5657 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5658 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5659 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5660 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5661 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5662 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5663 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5664 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5665 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5666 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5667 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5668 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5669 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5670 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5671 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5672 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5673 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5674 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5675 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5676 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5677 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5678 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5679 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5680 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5681 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5682 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5683 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5684 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5685 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5686 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5687 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5688 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5689 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5690 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5691 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5692 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5693 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5694 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5695 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5696 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5697 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5698 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5699 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5700 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5701 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5702 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5703 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5704 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5705 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5706 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5707 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5708 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5709 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5710 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5711 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5712 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5713 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5714 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5715 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5716 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5717 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5718 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5719 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5720 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5721 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5722 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5723 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5724 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5725 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5726 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5727 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 5728 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5729 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5730 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5731 <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, 5732 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5733 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5734 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5735 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5736 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5737 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5738 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5739 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5740 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>, 5741 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, 5742 <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>, 5743 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, 5744 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5745 <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>, 5746 <GIC_SPI 709 IRQ_TYPE_LEVEL_HIGH>, 5747 <GIC_SPI 710 IRQ_TYPE_LEVEL_HIGH>, 5748 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 5749 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>, 5750 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 5751 <GIC_SPI 713 IRQ_TYPE_LEVEL_HIGH>, 5752 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>, 5753 <GIC_SPI 715 IRQ_TYPE_LEVEL_HIGH>, 5754 <GIC_SPI 912 IRQ_TYPE_LEVEL_HIGH>, 5755 <GIC_SPI 911 IRQ_TYPE_LEVEL_HIGH>, 5756 <GIC_SPI 910 IRQ_TYPE_LEVEL_HIGH>, 5757 <GIC_SPI 909 IRQ_TYPE_LEVEL_HIGH>, 5758 <GIC_SPI 908 IRQ_TYPE_LEVEL_HIGH>, 5759 <GIC_SPI 907 IRQ_TYPE_LEVEL_HIGH>, 5760 <GIC_SPI 906 IRQ_TYPE_LEVEL_HIGH>, 5761 <GIC_SPI 905 IRQ_TYPE_LEVEL_HIGH>, 5762 <GIC_SPI 904 IRQ_TYPE_LEVEL_HIGH>, 5763 <GIC_SPI 903 IRQ_TYPE_LEVEL_HIGH>, 5764 <GIC_SPI 902 IRQ_TYPE_LEVEL_HIGH>, 5765 <GIC_SPI 901 IRQ_TYPE_LEVEL_HIGH>, 5766 <GIC_SPI 900 IRQ_TYPE_LEVEL_HIGH>, 5767 <GIC_SPI 899 IRQ_TYPE_LEVEL_HIGH>, 5768 <GIC_SPI 898 IRQ_TYPE_LEVEL_HIGH>, 5769 <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>, 5770 <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>, 5771 <GIC_SPI 895 IRQ_TYPE_LEVEL_HIGH>; 5772 }; 5773 5774 pcie_smmu: iommu@15200000 { 5775 compatible = "qcom,qcs8300-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5776 reg = <0x0 0x15200000 0x0 0x80000>; 5777 #iommu-cells = <2>; 5778 #global-interrupts = <2>; 5779 dma-coherent; 5780 5781 interrupts = <GIC_SPI 920 IRQ_TYPE_LEVEL_HIGH>, 5782 <GIC_SPI 921 IRQ_TYPE_LEVEL_HIGH>, 5783 <GIC_SPI 925 IRQ_TYPE_LEVEL_HIGH>, 5784 <GIC_SPI 926 IRQ_TYPE_LEVEL_HIGH>, 5785 <GIC_SPI 927 IRQ_TYPE_LEVEL_HIGH>, 5786 <GIC_SPI 928 IRQ_TYPE_LEVEL_HIGH>, 5787 <GIC_SPI 950 IRQ_TYPE_LEVEL_HIGH>, 5788 <GIC_SPI 951 IRQ_TYPE_LEVEL_HIGH>, 5789 <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>, 5790 <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>, 5791 <GIC_SPI 954 IRQ_TYPE_LEVEL_HIGH>, 5792 <GIC_SPI 955 IRQ_TYPE_LEVEL_HIGH>, 5793 <GIC_SPI 956 IRQ_TYPE_LEVEL_HIGH>, 5794 <GIC_SPI 957 IRQ_TYPE_LEVEL_HIGH>, 5795 <GIC_SPI 958 IRQ_TYPE_LEVEL_HIGH>, 5796 <GIC_SPI 885 IRQ_TYPE_LEVEL_HIGH>, 5797 <GIC_SPI 886 IRQ_TYPE_LEVEL_HIGH>, 5798 <GIC_SPI 887 IRQ_TYPE_LEVEL_HIGH>, 5799 <GIC_SPI 888 IRQ_TYPE_LEVEL_HIGH>, 5800 <GIC_SPI 820 IRQ_TYPE_LEVEL_HIGH>, 5801 <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH>, 5802 <GIC_SPI 823 IRQ_TYPE_LEVEL_HIGH>, 5803 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 5804 <GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, 5805 <GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, 5806 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 5807 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 5808 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 5809 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 5810 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 5811 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 5812 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 5813 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 5814 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>, 5815 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 5816 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 5817 <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>, 5818 <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>, 5819 <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, 5820 <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, 5821 <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>, 5822 <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>, 5823 <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>, 5824 <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>, 5825 <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>, 5826 <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, 5827 <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>, 5828 <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>, 5829 <GIC_SPI 814 IRQ_TYPE_LEVEL_HIGH>, 5830 <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 5831 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 5832 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 5833 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 5834 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>, 5835 <GIC_SPI 855 IRQ_TYPE_LEVEL_HIGH>, 5836 <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, 5837 <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, 5838 <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>, 5839 <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>, 5840 <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>, 5841 <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>, 5842 <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>, 5843 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>, 5844 <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH>, 5845 <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, 5846 <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; 5847 }; 5848 5849 intc: interrupt-controller@17a00000 { 5850 compatible = "arm,gic-v3"; 5851 reg = <0x0 0x17a00000 0x0 0x10000>, 5852 <0x0 0x17a60000 0x0 0x100000>; 5853 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5854 #interrupt-cells = <3>; 5855 interrupt-controller; 5856 #redistributor-regions = <1>; 5857 redistributor-stride = <0x0 0x20000>; 5858 }; 5859 5860 watchdog@17c10000 { 5861 compatible = "qcom,apss-wdt-qcs8300", "qcom,kpss-wdt"; 5862 reg = <0x0 0x17c10000 0x0 0x1000>; 5863 clocks = <&sleep_clk>; 5864 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5865 }; 5866 5867 timer@17c20000 { 5868 compatible = "arm,armv7-timer-mem"; 5869 reg = <0x0 0x17c20000 0x0 0x1000>; 5870 ranges = <0x0 0x0 0x0 0x20000000>; 5871 #address-cells = <1>; 5872 #size-cells = <1>; 5873 5874 frame@17c21000 { 5875 reg = <0x17c21000 0x1000>, 5876 <0x17c22000 0x1000>; 5877 frame-number = <0>; 5878 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5879 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5880 }; 5881 5882 frame@17c23000 { 5883 reg = <0x17c23000 0x1000>; 5884 frame-number = <1>; 5885 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5886 status = "disabled"; 5887 }; 5888 5889 frame@17c25000 { 5890 reg = <0x17c25000 0x1000>; 5891 frame-number = <2>; 5892 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5893 status = "disabled"; 5894 }; 5895 5896 frame@17c27000 { 5897 reg = <0x17c27000 0x1000>; 5898 frame-number = <3>; 5899 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5900 status = "disabled"; 5901 }; 5902 5903 frame@17c29000 { 5904 reg = <0x17c29000 0x1000>; 5905 frame-number = <4>; 5906 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5907 status = "disabled"; 5908 }; 5909 5910 frame@17c2b000 { 5911 reg = <0x17c2b000 0x1000>; 5912 frame-number = <5>; 5913 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5914 status = "disabled"; 5915 }; 5916 5917 frame@17c2d000 { 5918 reg = <0x17c2d000 0x1000>; 5919 frame-number = <6>; 5920 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5921 status = "disabled"; 5922 }; 5923 }; 5924 5925 apps_rsc: rsc@18200000 { 5926 compatible = "qcom,rpmh-rsc"; 5927 reg = <0x0 0x18200000 0x0 0x10000>, 5928 <0x0 0x18210000 0x0 0x10000>, 5929 <0x0 0x18220000 0x0 0x10000>; 5930 reg-names = "drv-0", 5931 "drv-1", 5932 "drv-2"; 5933 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5934 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5935 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5936 5937 power-domains = <&system_pd>; 5938 label = "apps_rsc"; 5939 5940 qcom,tcs-offset = <0xd00>; 5941 qcom,drv-id = <2>; 5942 qcom,tcs-config = <ACTIVE_TCS 2>, 5943 <SLEEP_TCS 3>, 5944 <WAKE_TCS 3>, 5945 <CONTROL_TCS 0>; 5946 5947 apps_bcm_voter: bcm-voter { 5948 compatible = "qcom,bcm-voter"; 5949 }; 5950 5951 rpmhcc: clock-controller { 5952 compatible = "qcom,sa8775p-rpmh-clk"; 5953 #clock-cells = <1>; 5954 clocks = <&xo_board_clk>; 5955 clock-names = "xo"; 5956 }; 5957 5958 rpmhpd: power-controller { 5959 compatible = "qcom,qcs8300-rpmhpd"; 5960 #power-domain-cells = <1>; 5961 operating-points-v2 = <&rpmhpd_opp_table>; 5962 5963 rpmhpd_opp_table: opp-table { 5964 compatible = "operating-points-v2"; 5965 5966 rpmhpd_opp_ret: opp-0 { 5967 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5968 }; 5969 5970 rpmhpd_opp_min_svs: opp-1 { 5971 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 5972 }; 5973 5974 rpmhpd_opp_low_svs: opp-2 { 5975 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5976 }; 5977 5978 rpmhpd_opp_svs: opp-3 { 5979 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5980 }; 5981 5982 rpmhpd_opp_svs_l1: opp-4 { 5983 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5984 }; 5985 5986 rpmhpd_opp_nom: opp-5 { 5987 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5988 }; 5989 5990 rpmhpd_opp_nom_l1: opp-6 { 5991 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5992 }; 5993 5994 rpmhpd_opp_nom_l2: opp-7 { 5995 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5996 }; 5997 5998 rpmhpd_opp_turbo: opp-8 { 5999 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 6000 }; 6001 6002 rpmhpd_opp_turbo_l1: opp-9 { 6003 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 6004 }; 6005 }; 6006 }; 6007 }; 6008 6009 epss_l3_cl0: interconnect@18590000 { 6010 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 6011 "qcom,epss-l3"; 6012 reg = <0x0 0x18590000 0x0 0x1000>; 6013 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6014 clock-names = "xo", "alternate"; 6015 #interconnect-cells = <1>; 6016 }; 6017 6018 cpufreq_hw: cpufreq@18591000 { 6019 compatible = "qcom,qcs8300-cpufreq-epss", "qcom,cpufreq-epss"; 6020 reg = <0x0 0x18591000 0x0 0x1000>, 6021 <0x0 0x18593000 0x0 0x1000>, 6022 <0x0 0x18594000 0x0 0x1000>; 6023 reg-names = "freq-domain0", 6024 "freq-domain1", 6025 "freq-domain2"; 6026 6027 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 6028 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 6029 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 6030 interrupt-names = "dcvsh-irq-0", 6031 "dcvsh-irq-1", 6032 "dcvsh-irq-2"; 6033 6034 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6035 clock-names = "xo", "alternate"; 6036 6037 #freq-domain-cells = <1>; 6038 }; 6039 6040 epss_l3_cl1: interconnect@18592000 { 6041 compatible = "qcom,qcs8300-epss-l3", "qcom,sa8775p-epss-l3", 6042 "qcom,epss-l3"; 6043 reg = <0x0 0x18592000 0x0 0x1000>; 6044 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 6045 clock-names = "xo", "alternate"; 6046 #interconnect-cells = <1>; 6047 }; 6048 6049 remoteproc_gpdsp: remoteproc@20c00000 { 6050 compatible = "qcom,qcs8300-gpdsp-pas", "qcom,sa8775p-gpdsp0-pas"; 6051 reg = <0x0 0x20c00000 0x0 0x10000>; 6052 6053 interrupts-extended = <&intc GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 6054 <&smp2p_gpdsp_in 0 0>, 6055 <&smp2p_gpdsp_in 1 0>, 6056 <&smp2p_gpdsp_in 2 0>, 6057 <&smp2p_gpdsp_in 3 0>; 6058 interrupt-names = "wdog", 6059 "fatal", 6060 "ready", 6061 "handover", 6062 "stop-ack"; 6063 6064 clocks = <&rpmhcc RPMH_CXO_CLK>; 6065 clock-names = "xo"; 6066 6067 power-domains = <&rpmhpd RPMHPD_CX>, 6068 <&rpmhpd RPMHPD_MXC>; 6069 power-domain-names = "cx", 6070 "mxc"; 6071 6072 interconnects = <&gpdsp_anoc MASTER_DSP0 QCOM_ICC_TAG_ALWAYS 6073 &config_noc SLAVE_CLK_CTL QCOM_ICC_TAG_ALWAYS>; 6074 6075 memory-region = <&gpdsp_mem>; 6076 6077 qcom,qmp = <&aoss_qmp>; 6078 6079 qcom,smem-states = <&smp2p_gpdsp_out 0>; 6080 qcom,smem-state-names = "stop"; 6081 6082 status = "disabled"; 6083 6084 glink-edge { 6085 interrupts-extended = <&ipcc IPCC_CLIENT_GPDSP0 6086 IPCC_MPROC_SIGNAL_GLINK_QMP 6087 IRQ_TYPE_EDGE_RISING>; 6088 mboxes = <&ipcc IPCC_CLIENT_GPDSP0 6089 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6090 6091 label = "gpdsp"; 6092 qcom,remote-pid = <17>; 6093 }; 6094 }; 6095 6096 ethernet0: ethernet@23040000 { 6097 compatible = "qcom,qcs8300-ethqos", "qcom,sa8775p-ethqos"; 6098 reg = <0x0 0x23040000 0x0 0x00010000>, 6099 <0x0 0x23056000 0x0 0x00000100>; 6100 reg-names = "stmmaceth", "rgmii"; 6101 6102 interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, 6103 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 6104 interrupt-names = "macirq", "sfty"; 6105 6106 clocks = <&gcc GCC_EMAC0_AXI_CLK>, 6107 <&gcc GCC_EMAC0_SLV_AHB_CLK>, 6108 <&gcc GCC_EMAC0_PTP_CLK>, 6109 <&gcc GCC_EMAC0_PHY_AUX_CLK>; 6110 clock-names = "stmmaceth", 6111 "pclk", 6112 "ptp_ref", 6113 "phyaux"; 6114 power-domains = <&gcc GCC_EMAC0_GDSC>; 6115 6116 phys = <&serdes0>; 6117 phy-names = "serdes"; 6118 6119 iommus = <&apps_smmu 0x120 0xf>; 6120 dma-coherent; 6121 6122 snps,tso; 6123 snps,pbl = <32>; 6124 rx-fifo-depth = <16384>; 6125 tx-fifo-depth = <20480>; 6126 6127 status = "disabled"; 6128 }; 6129 6130 nspa_noc: interconnect@260c0000 { 6131 compatible = "qcom,qcs8300-nspa-noc"; 6132 reg = <0x0 0x260c0000 0x0 0x16080>; 6133 #interconnect-cells = <2>; 6134 qcom,bcm-voters = <&apps_bcm_voter>; 6135 }; 6136 6137 remoteproc_cdsp: remoteproc@26300000 { 6138 compatible = "qcom,qcs8300-cdsp-pas", "qcom,sa8775p-cdsp0-pas"; 6139 reg = <0x0 0x26300000 0x0 0x10000>; 6140 6141 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 6142 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 6143 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 6144 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 6145 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; 6146 interrupt-names = "wdog", 6147 "fatal", 6148 "ready", 6149 "handover", 6150 "stop-ack"; 6151 6152 clocks = <&rpmhcc RPMH_CXO_CLK>; 6153 clock-names = "xo"; 6154 6155 power-domains = <&rpmhpd RPMHPD_CX>, 6156 <&rpmhpd RPMHPD_MXC>, 6157 <&rpmhpd RPMHPD_NSP0>; 6158 6159 power-domain-names = "cx", 6160 "mxc", 6161 "nsp"; 6162 6163 interconnects = <&nspa_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 6164 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 6165 6166 memory-region = <&cdsp_mem>; 6167 6168 qcom,qmp = <&aoss_qmp>; 6169 6170 qcom,smem-states = <&smp2p_cdsp_out 0>; 6171 qcom,smem-state-names = "stop"; 6172 6173 status = "disabled"; 6174 6175 glink-edge { 6176 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 6177 IPCC_MPROC_SIGNAL_GLINK_QMP 6178 IRQ_TYPE_EDGE_RISING>; 6179 mboxes = <&ipcc IPCC_CLIENT_CDSP 6180 IPCC_MPROC_SIGNAL_GLINK_QMP>; 6181 6182 label = "cdsp"; 6183 qcom,remote-pid = <5>; 6184 6185 fastrpc { 6186 compatible = "qcom,fastrpc"; 6187 qcom,glink-channels = "fastrpcglink-apps-dsp"; 6188 label = "cdsp"; 6189 #address-cells = <1>; 6190 #size-cells = <0>; 6191 6192 compute-cb@1 { 6193 compatible = "qcom,fastrpc-compute-cb"; 6194 reg = <1>; 6195 iommus = <&apps_smmu 0x19c1 0x0440>, 6196 <&apps_smmu 0x1961 0x0400>; 6197 dma-coherent; 6198 }; 6199 6200 compute-cb@2 { 6201 compatible = "qcom,fastrpc-compute-cb"; 6202 reg = <2>; 6203 iommus = <&apps_smmu 0x19c2 0x0440>, 6204 <&apps_smmu 0x1962 0x0400>; 6205 dma-coherent; 6206 }; 6207 6208 compute-cb@3 { 6209 compatible = "qcom,fastrpc-compute-cb"; 6210 reg = <3>; 6211 iommus = <&apps_smmu 0x19c3 0x0440>, 6212 <&apps_smmu 0x1963 0x0400>; 6213 dma-coherent; 6214 }; 6215 6216 compute-cb@4 { 6217 compatible = "qcom,fastrpc-compute-cb"; 6218 reg = <4>; 6219 iommus = <&apps_smmu 0x19c4 0x0440>, 6220 <&apps_smmu 0x1964 0x0400>; 6221 dma-coherent; 6222 }; 6223 }; 6224 }; 6225 }; 6226 }; 6227 6228 timer { 6229 compatible = "arm,armv8-timer"; 6230 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6231 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6232 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 6233 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 6234 }; 6235};
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