FILE
ipq6018.dtsi
File preview with syntax highlighting.
linux-6.19.14/arch/arm64/boot/dts/qcom/ipq6018.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * IPQ6018 SoC device tree source 4 * 5 * Copyright (c) 2019, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/clock/qcom,gcc-ipq6018.h> 10#include <dt-bindings/reset/qcom,gcc-ipq6018.h> 11#include <dt-bindings/clock/qcom,apss-ipq.h> 12#include <dt-bindings/thermal/thermal.h> 13 14/ { 15 #address-cells = <2>; 16 #size-cells = <2>; 17 interrupt-parent = <&intc>; 18 19 clocks { 20 sleep_clk: sleep-clk { 21 compatible = "fixed-clock"; 22 clock-frequency = <32000>; 23 #clock-cells = <0>; 24 }; 25 26 xo: xo { 27 compatible = "fixed-clock"; 28 clock-frequency = <24000000>; 29 #clock-cells = <0>; 30 }; 31 }; 32 33 cpus: cpus { 34 #address-cells = <1>; 35 #size-cells = <0>; 36 37 cpu0: cpu@0 { 38 device_type = "cpu"; 39 compatible = "arm,cortex-a53"; 40 reg = <0x0>; 41 enable-method = "psci"; 42 next-level-cache = <&l2_0>; 43 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 44 clock-names = "cpu"; 45 operating-points-v2 = <&cpu_opp_table>; 46 #cooling-cells = <2>; 47 }; 48 49 cpu1: cpu@1 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 enable-method = "psci"; 53 reg = <0x1>; 54 next-level-cache = <&l2_0>; 55 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 56 clock-names = "cpu"; 57 operating-points-v2 = <&cpu_opp_table>; 58 #cooling-cells = <2>; 59 }; 60 61 cpu2: cpu@2 { 62 device_type = "cpu"; 63 compatible = "arm,cortex-a53"; 64 enable-method = "psci"; 65 reg = <0x2>; 66 next-level-cache = <&l2_0>; 67 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 68 clock-names = "cpu"; 69 operating-points-v2 = <&cpu_opp_table>; 70 #cooling-cells = <2>; 71 }; 72 73 cpu3: cpu@3 { 74 device_type = "cpu"; 75 compatible = "arm,cortex-a53"; 76 enable-method = "psci"; 77 reg = <0x3>; 78 next-level-cache = <&l2_0>; 79 clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; 80 clock-names = "cpu"; 81 operating-points-v2 = <&cpu_opp_table>; 82 #cooling-cells = <2>; 83 }; 84 85 l2_0: l2-cache { 86 compatible = "cache"; 87 cache-level = <2>; 88 cache-unified; 89 }; 90 }; 91 92 firmware { 93 scm { 94 compatible = "qcom,scm-ipq6018", "qcom,scm"; 95 qcom,dload-mode = <&tcsr 0x6100>; 96 }; 97 }; 98 99 cpu_opp_table: opp-table-cpu { 100 compatible = "operating-points-v2-kryo-cpu"; 101 nvmem-cells = <&cpu_speed_bin>; 102 opp-shared; 103 104 opp-864000000 { 105 opp-hz = /bits/ 64 <864000000>; 106 opp-microvolt = <725000>; 107 opp-supported-hw = <0xf>; 108 clock-latency-ns = <200000>; 109 }; 110 111 opp-1056000000 { 112 opp-hz = /bits/ 64 <1056000000>; 113 opp-microvolt = <787500>; 114 opp-supported-hw = <0xf>; 115 clock-latency-ns = <200000>; 116 }; 117 118 opp-1200000000 { 119 opp-hz = /bits/ 64 <1200000000>; 120 opp-microvolt = <850000>; 121 opp-supported-hw = <0x4>; 122 clock-latency-ns = <200000>; 123 }; 124 125 opp-1320000000 { 126 opp-hz = /bits/ 64 <1320000000>; 127 opp-microvolt = <862500>; 128 opp-supported-hw = <0x3>; 129 clock-latency-ns = <200000>; 130 }; 131 132 opp-1440000000 { 133 opp-hz = /bits/ 64 <1440000000>; 134 opp-microvolt = <925000>; 135 opp-supported-hw = <0x3>; 136 clock-latency-ns = <200000>; 137 }; 138 139 opp-1512000000 { 140 opp-hz = /bits/ 64 <1512000000>; 141 opp-microvolt = <937500>; 142 opp-supported-hw = <0x2>; 143 clock-latency-ns = <200000>; 144 }; 145 146 opp-1608000000 { 147 opp-hz = /bits/ 64 <1608000000>; 148 opp-microvolt = <987500>; 149 opp-supported-hw = <0x1>; 150 clock-latency-ns = <200000>; 151 }; 152 153 opp-1800000000 { 154 opp-hz = /bits/ 64 <1800000000>; 155 opp-microvolt = <1062500>; 156 opp-supported-hw = <0x1>; 157 clock-latency-ns = <200000>; 158 }; 159 }; 160 161 pmuv8: pmu { 162 compatible = "arm,cortex-a53-pmu"; 163 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 164 }; 165 166 psci: psci { 167 compatible = "arm,psci-1.0"; 168 method = "smc"; 169 }; 170 171 rpm: remoteproc { 172 compatible = "qcom,ipq6018-rpm-proc", "qcom,rpm-proc"; 173 174 glink-edge { 175 compatible = "qcom,glink-rpm"; 176 interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>; 177 qcom,rpm-msg-ram = <&rpm_msg_ram>; 178 mboxes = <&apcs_glb 0>; 179 180 rpm_requests: rpm-requests { 181 compatible = "qcom,rpm-ipq6018", "qcom,glink-smd-rpm"; 182 qcom,glink-channels = "rpm_requests"; 183 }; 184 }; 185 }; 186 187 reserved-memory { 188 #address-cells = <2>; 189 #size-cells = <2>; 190 ranges; 191 192 rpm_msg_ram: memory@60000 { 193 reg = <0x0 0x00060000 0x0 0x6000>; 194 no-map; 195 }; 196 197 bootloader@4a100000 { 198 reg = <0x0 0x4a100000 0x0 0x400000>; 199 no-map; 200 }; 201 202 sbl@4a500000 { 203 reg = <0x0 0x4a500000 0x0 0x100000>; 204 no-map; 205 }; 206 207 tz: memory@4a600000 { 208 reg = <0x0 0x4a600000 0x0 0x400000>; 209 no-map; 210 }; 211 212 smem_region: memory@4aa00000 { 213 compatible = "qcom,smem"; 214 reg = <0x0 0x4aa00000 0x0 0x100000>; 215 no-map; 216 217 hwlocks = <&tcsr_mutex 3>; 218 }; 219 220 q6_region: memory@4ab00000 { 221 reg = <0x0 0x4ab00000 0x0 0x5500000>; 222 no-map; 223 }; 224 }; 225 226 soc: soc@0 { 227 #address-cells = <2>; 228 #size-cells = <2>; 229 ranges = <0 0 0 0 0x0 0xffffffff>; 230 dma-ranges; 231 compatible = "simple-bus"; 232 233 qusb_phy_1: qusb@59000 { 234 compatible = "qcom,ipq6018-qusb2-phy"; 235 reg = <0x0 0x00059000 0x0 0x180>; 236 #phy-cells = <0>; 237 238 clocks = <&gcc GCC_USB1_PHY_CFG_AHB_CLK>, 239 <&xo>; 240 clock-names = "cfg_ahb", "ref"; 241 242 resets = <&gcc GCC_QUSB2_1_PHY_BCR>; 243 status = "disabled"; 244 }; 245 246 ssphy_0: ssphy@78000 { 247 compatible = "qcom,ipq6018-qmp-usb3-phy"; 248 reg = <0x0 0x00078000 0x0 0x1000>; 249 250 clocks = <&gcc GCC_USB0_AUX_CLK>, 251 <&xo>, 252 <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 253 <&gcc GCC_USB0_PIPE_CLK>; 254 clock-names = "aux", 255 "ref", 256 "cfg_ahb", 257 "pipe"; 258 clock-output-names = "gcc_usb0_pipe_clk_src"; 259 #clock-cells = <0>; 260 #phy-cells = <0>; 261 262 resets = <&gcc GCC_USB0_PHY_BCR>, 263 <&gcc GCC_USB3PHY_0_PHY_BCR>; 264 reset-names = "phy", 265 "phy_phy"; 266 267 status = "disabled"; 268 }; 269 270 qusb_phy_0: qusb@79000 { 271 compatible = "qcom,ipq6018-qusb2-phy"; 272 reg = <0x0 0x00079000 0x0 0x180>; 273 #phy-cells = <0>; 274 275 clocks = <&gcc GCC_USB0_PHY_CFG_AHB_CLK>, 276 <&xo>; 277 clock-names = "cfg_ahb", "ref"; 278 279 resets = <&gcc GCC_QUSB2_0_PHY_BCR>; 280 status = "disabled"; 281 }; 282 283 pcie_phy: phy@84000 { 284 compatible = "qcom,ipq6018-qmp-pcie-phy"; 285 reg = <0x0 0x00084000 0x0 0x1000>; 286 status = "disabled"; 287 288 clocks = <&gcc GCC_PCIE0_AUX_CLK>, 289 <&gcc GCC_PCIE0_AHB_CLK>, 290 <&gcc GCC_PCIE0_PIPE_CLK>; 291 clock-names = "aux", 292 "cfg_ahb", 293 "pipe"; 294 295 clock-output-names = "gcc_pcie0_pipe_clk_src"; 296 #clock-cells = <0>; 297 298 #phy-cells = <0>; 299 300 resets = <&gcc GCC_PCIE0_PHY_BCR>, 301 <&gcc GCC_PCIE0PHY_PHY_BCR>; 302 reset-names = "phy", 303 "common"; 304 }; 305 306 mdio: mdio@90000 { 307 #address-cells = <1>; 308 #size-cells = <0>; 309 compatible = "qcom,ipq6018-mdio", "qcom,ipq4019-mdio"; 310 reg = <0x0 0x00090000 0x0 0x64>; 311 clocks = <&gcc GCC_MDIO_AHB_CLK>; 312 clock-names = "gcc_mdio_ahb_clk"; 313 status = "disabled"; 314 }; 315 316 qfprom: efuse@a4000 { 317 compatible = "qcom,ipq6018-qfprom", "qcom,qfprom"; 318 reg = <0x0 0x000a4000 0x0 0x2000>; 319 #address-cells = <1>; 320 #size-cells = <1>; 321 322 cpu_speed_bin: cpu-speed-bin@135 { 323 reg = <0x135 0x1>; 324 bits = <7 1>; 325 }; 326 }; 327 328 prng: qrng@e3000 { 329 compatible = "qcom,prng-ee"; 330 reg = <0x0 0x000e3000 0x0 0x1000>; 331 clocks = <&gcc GCC_PRNG_AHB_CLK>; 332 clock-names = "core"; 333 }; 334 335 tsens: thermal-sensor@4a9000 { 336 compatible = "qcom,ipq6018-tsens", "qcom,ipq8074-tsens"; 337 reg = <0x0 0x004a9000 0x0 0x1000>, 338 <0x0 0x004a8000 0x0 0x1000>; 339 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 340 interrupt-names = "combined"; 341 #qcom,sensors = <16>; 342 #thermal-sensor-cells = <1>; 343 }; 344 345 cryptobam: dma-controller@704000 { 346 compatible = "qcom,bam-v1.7.0"; 347 reg = <0x0 0x00704000 0x0 0x20000>; 348 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&gcc GCC_CRYPTO_AHB_CLK>; 350 clock-names = "bam_clk"; 351 #dma-cells = <1>; 352 qcom,ee = <1>; 353 qcom,controlled-remotely; 354 }; 355 356 crypto: crypto@73a000 { 357 compatible = "qcom,crypto-v5.1"; 358 reg = <0x0 0x0073a000 0x0 0x6000>; 359 clocks = <&gcc GCC_CRYPTO_AHB_CLK>, 360 <&gcc GCC_CRYPTO_AXI_CLK>, 361 <&gcc GCC_CRYPTO_CLK>; 362 clock-names = "iface", "bus", "core"; 363 dmas = <&cryptobam 2>, <&cryptobam 3>; 364 dma-names = "rx", "tx"; 365 }; 366 367 tlmm: pinctrl@1000000 { 368 compatible = "qcom,ipq6018-pinctrl"; 369 reg = <0x0 0x01000000 0x0 0x300000>; 370 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 371 gpio-controller; 372 #gpio-cells = <2>; 373 gpio-ranges = <&tlmm 0 0 80>; 374 interrupt-controller; 375 #interrupt-cells = <2>; 376 377 serial_3_pins: serial3-state { 378 pins = "gpio44", "gpio45"; 379 function = "blsp2_uart"; 380 drive-strength = <8>; 381 bias-pull-down; 382 }; 383 384 qpic_pins: qpic-state { 385 pins = "gpio1", "gpio3", "gpio4", 386 "gpio5", "gpio6", "gpio7", 387 "gpio8", "gpio10", "gpio11", 388 "gpio12", "gpio13", "gpio14", 389 "gpio15", "gpio17"; 390 function = "qpic_pad"; 391 drive-strength = <8>; 392 bias-disable; 393 }; 394 }; 395 396 gcc: clock-controller@1800000 { 397 compatible = "qcom,gcc-ipq6018"; 398 reg = <0x0 0x01800000 0x0 0x80000>; 399 clocks = <&xo>, <&sleep_clk>; 400 clock-names = "xo", "sleep_clk"; 401 #clock-cells = <1>; 402 #reset-cells = <1>; 403 }; 404 405 tcsr_mutex: hwlock@1905000 { 406 compatible = "qcom,ipq6018-tcsr-mutex", "qcom,tcsr-mutex"; 407 reg = <0x0 0x01905000 0x0 0x20000>; 408 #hwlock-cells = <1>; 409 }; 410 411 tcsr: syscon@1937000 { 412 compatible = "qcom,tcsr-ipq6018", "syscon"; 413 reg = <0x0 0x01937000 0x0 0x21000>; 414 }; 415 416 usb2: usb@70f8800 { 417 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 418 reg = <0x0 0x070f8800 0x0 0x400>; 419 #address-cells = <2>; 420 #size-cells = <2>; 421 ranges; 422 clocks = <&gcc GCC_USB1_MASTER_CLK>, 423 <&gcc GCC_USB1_SLEEP_CLK>, 424 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 425 clock-names = "core", 426 "sleep", 427 "mock_utmi"; 428 429 assigned-clocks = <&gcc GCC_USB1_MASTER_CLK>, 430 <&gcc GCC_USB1_MOCK_UTMI_CLK>; 431 assigned-clock-rates = <133330000>, 432 <24000000>; 433 434 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 435 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 436 interrupt-names = "pwr_event", 437 "qusb2_phy"; 438 439 resets = <&gcc GCC_USB1_BCR>; 440 status = "disabled"; 441 442 dwc_1: usb@7000000 { 443 compatible = "snps,dwc3"; 444 reg = <0x0 0x07000000 0x0 0xcd00>; 445 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 446 phys = <&qusb_phy_1>; 447 phy-names = "usb2-phy"; 448 tx-fifo-resize; 449 snps,is-utmi-l1-suspend; 450 snps,hird-threshold = /bits/ 8 <0x0>; 451 snps,dis_u2_susphy_quirk; 452 snps,dis_u3_susphy_quirk; 453 dr_mode = "host"; 454 }; 455 }; 456 457 sdhc: mmc@7804000 { 458 compatible = "qcom,ipq6018-sdhci", "qcom,sdhci-msm-v5"; 459 reg = <0x0 0x07804000 0x0 0x1000>, 460 <0x0 0x07805000 0x0 0x1000>; 461 reg-names = "hc", "cqhci"; 462 463 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 465 interrupt-names = "hc_irq", "pwr_irq"; 466 467 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 468 <&gcc GCC_SDCC1_APPS_CLK>, 469 <&xo>; 470 clock-names = "iface", "core", "xo"; 471 resets = <&gcc GCC_SDCC1_BCR>; 472 max-frequency = <192000000>; 473 status = "disabled"; 474 }; 475 476 blsp_dma: dma-controller@7884000 { 477 compatible = "qcom,bam-v1.7.0"; 478 reg = <0x0 0x07884000 0x0 0x2b000>; 479 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 480 clocks = <&gcc GCC_BLSP1_AHB_CLK>; 481 clock-names = "bam_clk"; 482 #dma-cells = <1>; 483 qcom,ee = <0>; 484 }; 485 486 blsp1_uart1: serial@78af000 { 487 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 488 reg = <0x0 0x78af000 0x0 0x200>; 489 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 490 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, 491 <&gcc GCC_BLSP1_AHB_CLK>; 492 clock-names = "core", "iface"; 493 status = "disabled"; 494 }; 495 496 blsp1_uart2: serial@78b0000 { 497 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 498 reg = <0x0 0x78b0000 0x0 0x200>; 499 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 500 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, 501 <&gcc GCC_BLSP1_AHB_CLK>; 502 clock-names = "core", "iface"; 503 status = "disabled"; 504 }; 505 506 blsp1_uart3: serial@78b1000 { 507 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 508 reg = <0x0 0x078b1000 0x0 0x200>; 509 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 510 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, 511 <&gcc GCC_BLSP1_AHB_CLK>; 512 clock-names = "core", "iface"; 513 status = "disabled"; 514 }; 515 516 blsp1_uart4: serial@78b2000 { 517 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 518 reg = <0x0 0x078b2000 0x0 0x200>; 519 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; 520 clocks = <&gcc GCC_BLSP1_UART4_APPS_CLK>, 521 <&gcc GCC_BLSP1_AHB_CLK>; 522 clock-names = "core", "iface"; 523 status = "disabled"; 524 }; 525 526 blsp1_uart5: serial@78b3000 { 527 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 528 reg = <0x0 0x78b3000 0x0 0x200>; 529 interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; 530 clocks = <&gcc GCC_BLSP1_UART5_APPS_CLK>, 531 <&gcc GCC_BLSP1_AHB_CLK>; 532 clock-names = "core", "iface"; 533 status = "disabled"; 534 }; 535 536 blsp1_uart6: serial@78b4000 { 537 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; 538 reg = <0x0 0x078b4000 0x0 0x200>; 539 interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 540 clocks = <&gcc GCC_BLSP1_UART6_APPS_CLK>, 541 <&gcc GCC_BLSP1_AHB_CLK>; 542 clock-names = "core", "iface"; 543 status = "disabled"; 544 }; 545 546 blsp1_spi1: spi@78b5000 { 547 compatible = "qcom,spi-qup-v2.2.1"; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 reg = <0x0 0x078b5000 0x0 0x600>; 551 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 552 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>, 553 <&gcc GCC_BLSP1_AHB_CLK>; 554 clock-names = "core", "iface"; 555 dmas = <&blsp_dma 12>, <&blsp_dma 13>; 556 dma-names = "tx", "rx"; 557 status = "disabled"; 558 }; 559 560 blsp1_spi2: spi@78b6000 { 561 compatible = "qcom,spi-qup-v2.2.1"; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 reg = <0x0 0x078b6000 0x0 0x600>; 565 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 566 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>, 567 <&gcc GCC_BLSP1_AHB_CLK>; 568 clock-names = "core", "iface"; 569 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 570 dma-names = "tx", "rx"; 571 status = "disabled"; 572 }; 573 574 blsp1_spi5: spi@78b9000 { 575 compatible = "qcom,spi-qup-v2.2.1"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 reg = <0x0 0x078b9000 0x0 0x600>; 579 interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>, 581 <&gcc GCC_BLSP1_AHB_CLK>; 582 clock-names = "core", "iface"; 583 dmas = <&blsp_dma 20>, <&blsp_dma 21>; 584 dma-names = "tx", "rx"; 585 status = "disabled"; 586 }; 587 588 blsp1_i2c2: i2c@78b6000 { 589 compatible = "qcom,i2c-qup-v2.2.1"; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 reg = <0x0 0x078b6000 0x0 0x600>; 593 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 594 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, 595 <&gcc GCC_BLSP1_AHB_CLK>; 596 clock-names = "core", "iface"; 597 clock-frequency = <400000>; 598 dmas = <&blsp_dma 14>, <&blsp_dma 15>; 599 dma-names = "tx", "rx"; 600 status = "disabled"; 601 }; 602 603 blsp1_i2c3: i2c@78b7000 { 604 compatible = "qcom,i2c-qup-v2.2.1"; 605 #address-cells = <1>; 606 #size-cells = <0>; 607 reg = <0x0 0x078b7000 0x0 0x600>; 608 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 609 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, 610 <&gcc GCC_BLSP1_AHB_CLK>; 611 clock-names = "core", "iface"; 612 clock-frequency = <400000>; 613 dmas = <&blsp_dma 16>, <&blsp_dma 17>; 614 dma-names = "tx", "rx"; 615 status = "disabled"; 616 }; 617 618 blsp1_i2c6: i2c@78ba000 { 619 compatible = "qcom,i2c-qup-v2.2.1"; 620 #address-cells = <1>; 621 #size-cells = <0>; 622 reg = <0x0 0x078ba000 0x0 0x600>; 623 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 624 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>, 625 <&gcc GCC_BLSP1_AHB_CLK>; 626 clock-names = "core", "iface"; 627 clock-frequency = <400000>; 628 dmas = <&blsp_dma 22>, <&blsp_dma 23>; 629 dma-names = "tx", "rx"; 630 status = "disabled"; 631 }; 632 633 qpic_bam: dma-controller@7984000 { 634 compatible = "qcom,bam-v1.7.0"; 635 reg = <0x0 0x07984000 0x0 0x1a000>; 636 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 637 clocks = <&gcc GCC_QPIC_AHB_CLK>; 638 clock-names = "bam_clk"; 639 #dma-cells = <1>; 640 qcom,ee = <0>; 641 status = "disabled"; 642 }; 643 644 qpic_nand: nand-controller@79b0000 { 645 compatible = "qcom,ipq6018-nand"; 646 reg = <0x0 0x079b0000 0x0 0x10000>; 647 #address-cells = <1>; 648 #size-cells = <0>; 649 clocks = <&gcc GCC_QPIC_CLK>, 650 <&gcc GCC_QPIC_AHB_CLK>; 651 clock-names = "core", "aon"; 652 653 dmas = <&qpic_bam 0>, 654 <&qpic_bam 1>, 655 <&qpic_bam 2>; 656 dma-names = "tx", "rx", "cmd"; 657 pinctrl-0 = <&qpic_pins>; 658 pinctrl-names = "default"; 659 status = "disabled"; 660 }; 661 662 usb3: usb@8af8800 { 663 compatible = "qcom,ipq6018-dwc3", "qcom,dwc3"; 664 reg = <0x0 0x08af8800 0x0 0x400>; 665 #address-cells = <2>; 666 #size-cells = <2>; 667 ranges; 668 669 clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 670 <&gcc GCC_USB0_MASTER_CLK>, 671 <&gcc GCC_USB0_SLEEP_CLK>, 672 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 673 clock-names = "cfg_noc", 674 "core", 675 "sleep", 676 "mock_utmi"; 677 678 assigned-clocks = <&gcc GCC_SYS_NOC_USB0_AXI_CLK>, 679 <&gcc GCC_USB0_MASTER_CLK>, 680 <&gcc GCC_USB0_MOCK_UTMI_CLK>; 681 assigned-clock-rates = <133330000>, 682 <133330000>, 683 <24000000>; 684 685 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 688 interrupt-names = "pwr_event", 689 "qusb2_phy", 690 "ss_phy_irq"; 691 692 resets = <&gcc GCC_USB0_BCR>; 693 status = "disabled"; 694 695 dwc_0: usb@8a00000 { 696 compatible = "snps,dwc3"; 697 reg = <0x0 0x08a00000 0x0 0xcd00>; 698 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 699 phys = <&qusb_phy_0>, <&ssphy_0>; 700 phy-names = "usb2-phy", "usb3-phy"; 701 clocks = <&xo>; 702 clock-names = "ref"; 703 tx-fifo-resize; 704 snps,parkmode-disable-ss-quirk; 705 snps,is-utmi-l1-suspend; 706 snps,hird-threshold = /bits/ 8 <0x0>; 707 snps,dis_u2_susphy_quirk; 708 snps,dis_u3_susphy_quirk; 709 dr_mode = "host"; 710 }; 711 }; 712 713 intc: interrupt-controller@b000000 { 714 compatible = "qcom,msm-qgic2"; 715 #address-cells = <2>; 716 #size-cells = <2>; 717 interrupt-controller; 718 #interrupt-cells = <3>; 719 reg = <0x0 0x0b000000 0x0 0x1000>, /*GICD*/ 720 <0x0 0x0b002000 0x0 0x1000>, /*GICC*/ 721 <0x0 0x0b001000 0x0 0x1000>, /*GICH*/ 722 <0x0 0x0b004000 0x0 0x1000>; /*GICV*/ 723 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 724 ranges = <0 0 0 0xb00a000 0 0xffd>; 725 726 v2m@0 { 727 compatible = "arm,gic-v2m-frame"; 728 msi-controller; 729 reg = <0x0 0x0 0x0 0xffd>; 730 }; 731 }; 732 733 watchdog@b017000 { 734 compatible = "qcom,kpss-wdt"; 735 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>; 736 reg = <0x0 0x0b017000 0x0 0x40>; 737 clocks = <&sleep_clk>; 738 timeout-sec = <10>; 739 }; 740 741 apcs_glb: mailbox@b111000 { 742 compatible = "qcom,ipq6018-apcs-apps-global"; 743 reg = <0x0 0x0b111000 0x0 0x1000>; 744 #clock-cells = <1>; 745 clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; 746 clock-names = "pll", "xo", "gpll0"; 747 #mbox-cells = <1>; 748 }; 749 750 a53pll: clock@b116000 { 751 compatible = "qcom,ipq6018-a53pll"; 752 reg = <0x0 0x0b116000 0x0 0x40>; 753 #clock-cells = <0>; 754 clocks = <&xo>; 755 clock-names = "xo"; 756 }; 757 758 timer@b120000 { 759 #address-cells = <1>; 760 #size-cells = <1>; 761 ranges = <0 0 0 0x10000000>; 762 compatible = "arm,armv7-timer-mem"; 763 reg = <0x0 0x0b120000 0x0 0x1000>; 764 765 frame@b120000 { 766 frame-number = <0>; 767 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 769 reg = <0x0b121000 0x1000>, 770 <0x0b122000 0x1000>; 771 }; 772 773 frame@b123000 { 774 frame-number = <1>; 775 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 776 reg = <0x0b123000 0x1000>; 777 status = "disabled"; 778 }; 779 780 frame@b124000 { 781 frame-number = <2>; 782 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 783 reg = <0x0b124000 0x1000>; 784 status = "disabled"; 785 }; 786 787 frame@b125000 { 788 frame-number = <3>; 789 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 790 reg = <0x0b125000 0x1000>; 791 status = "disabled"; 792 }; 793 794 frame@b126000 { 795 frame-number = <4>; 796 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 797 reg = <0x0b126000 0x1000>; 798 status = "disabled"; 799 }; 800 801 frame@b127000 { 802 frame-number = <5>; 803 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 804 reg = <0x0b127000 0x1000>; 805 status = "disabled"; 806 }; 807 808 frame@b128000 { 809 frame-number = <6>; 810 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 811 reg = <0x0b128000 0x1000>; 812 status = "disabled"; 813 }; 814 }; 815 816 q6v5_wcss: remoteproc@cd00000 { 817 compatible = "qcom,ipq6018-wcss-pil"; 818 reg = <0x0 0x0cd00000 0x0 0x4040>, 819 <0x0 0x004ab000 0x0 0x20>; 820 reg-names = "qdsp6", 821 "rmb"; 822 interrupts-extended = <&intc GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 823 <&wcss_smp2p_in 0 0>, 824 <&wcss_smp2p_in 1 0>, 825 <&wcss_smp2p_in 2 0>, 826 <&wcss_smp2p_in 3 0>; 827 interrupt-names = "wdog", 828 "fatal", 829 "ready", 830 "handover", 831 "stop-ack"; 832 833 resets = <&gcc GCC_WCSSAON_RESET>, 834 <&gcc GCC_WCSS_BCR>, 835 <&gcc GCC_WCSS_Q6_BCR>; 836 837 reset-names = "wcss_aon_reset", 838 "wcss_reset", 839 "wcss_q6_reset"; 840 841 clocks = <&gcc GCC_PRNG_AHB_CLK>; 842 clock-names = "prng"; 843 844 qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>; 845 846 qcom,smem-states = <&wcss_smp2p_out 0>, 847 <&wcss_smp2p_out 1>; 848 qcom,smem-state-names = "shutdown", 849 "stop"; 850 851 memory-region = <&q6_region>; 852 853 glink-edge { 854 interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>; 855 label = "rtr"; 856 qcom,remote-pid = <1>; 857 mboxes = <&apcs_glb 8>; 858 859 qrtr_requests { 860 qcom,glink-channels = "IPCRTR"; 861 }; 862 }; 863 }; 864 865 pcie0: pcie@20000000 { 866 compatible = "qcom,pcie-ipq6018"; 867 reg = <0x0 0x20000000 0x0 0xf1d>, 868 <0x0 0x20000f20 0x0 0xa8>, 869 <0x0 0x20001000 0x0 0x1000>, 870 <0x0 0x80000 0x0 0x4000>, 871 <0x0 0x20100000 0x0 0x1000>; 872 reg-names = "dbi", "elbi", "atu", "parf", "config"; 873 874 device_type = "pci"; 875 linux,pci-domain = <0>; 876 bus-range = <0x00 0xff>; 877 num-lanes = <1>; 878 max-link-speed = <3>; 879 #address-cells = <3>; 880 #size-cells = <2>; 881 882 phys = <&pcie_phy>; 883 phy-names = "pciephy"; 884 885 ranges = <0x81000000 0x0 0x00000000 0x0 0x20200000 0x0 0x10000>, 886 <0x82000000 0x0 0x20220000 0x0 0x20220000 0x0 0xfde0000>; 887 888 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 897 interrupt-names = "msi0", 898 "msi1", 899 "msi2", 900 "msi3", 901 "msi4", 902 "msi5", 903 "msi6", 904 "msi7", 905 "global"; 906 907 #interrupt-cells = <1>; 908 interrupt-map-mask = <0 0 0 0x7>; 909 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, /* int_a */ 910 <0 0 0 2 &intc 0 0 GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ 911 <0 0 0 3 &intc 0 0 GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ 912 <0 0 0 4 &intc 0 0 GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ 913 914 clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, 915 <&gcc GCC_PCIE0_AXI_M_CLK>, 916 <&gcc GCC_PCIE0_AXI_S_CLK>, 917 <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, 918 <&gcc PCIE0_RCHNG_CLK>; 919 clock-names = "iface", 920 "axi_m", 921 "axi_s", 922 "axi_bridge", 923 "rchng"; 924 925 resets = <&gcc GCC_PCIE0_PIPE_ARES>, 926 <&gcc GCC_PCIE0_SLEEP_ARES>, 927 <&gcc GCC_PCIE0_CORE_STICKY_ARES>, 928 <&gcc GCC_PCIE0_AXI_MASTER_ARES>, 929 <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, 930 <&gcc GCC_PCIE0_AHB_ARES>, 931 <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, 932 <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; 933 reset-names = "pipe", 934 "sleep", 935 "sticky", 936 "axi_m", 937 "axi_s", 938 "ahb", 939 "axi_m_sticky", 940 "axi_s_sticky"; 941 942 status = "disabled"; 943 944 pcie@0 { 945 device_type = "pci"; 946 reg = <0x0 0x0 0x0 0x0 0x0>; 947 bus-range = <0x01 0xff>; 948 949 #address-cells = <3>; 950 #size-cells = <2>; 951 ranges; 952 }; 953 }; 954 }; 955 956 thermal-zones { 957 nss-top-thermal { 958 polling-delay-passive = <250>; 959 thermal-sensors = <&tsens 4>; 960 961 trips { 962 nss-top-critical { 963 temperature = <125000>; 964 hysteresis = <1000>; 965 type = "critical"; 966 }; 967 }; 968 }; 969 970 nss-thermal { 971 polling-delay-passive = <250>; 972 thermal-sensors = <&tsens 5>; 973 974 trips { 975 nss-critical { 976 temperature = <125000>; 977 hysteresis = <1000>; 978 type = "critical"; 979 }; 980 }; 981 }; 982 983 wcss-phya0-thermal { 984 polling-delay-passive = <250>; 985 thermal-sensors = <&tsens 7>; 986 987 trips { 988 wcss-phya0-critical { 989 temperature = <125000>; 990 hysteresis = <1000>; 991 type = "critical"; 992 }; 993 }; 994 }; 995 996 wcss-phya1-thermal { 997 polling-delay-passive = <250>; 998 polling-delay = <1000>; 999 thermal-sensors = <&tsens 8>; 1000 1001 trips { 1002 wcss-phya1-critical { 1003 temperature = <125000>; 1004 hysteresis = <1000>; 1005 type = "critical"; 1006 }; 1007 }; 1008 }; 1009 1010 cpu-thermal { 1011 polling-delay-passive = <250>; 1012 thermal-sensors = <&tsens 13>; 1013 1014 trips { 1015 cpu-critical { 1016 temperature = <125000>; 1017 hysteresis = <1000>; 1018 type = "critical"; 1019 }; 1020 1021 cpu_alert: cpu-passive { 1022 temperature = <110000>; 1023 hysteresis = <1000>; 1024 type = "passive"; 1025 }; 1026 }; 1027 1028 cooling-maps { 1029 map0 { 1030 trip = <&cpu_alert>; 1031 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1032 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1033 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 1034 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 1035 }; 1036 }; 1037 }; 1038 1039 lpass-thermal { 1040 polling-delay-passive = <250>; 1041 thermal-sensors = <&tsens 14>; 1042 1043 trips { 1044 lpass-critical { 1045 temperature = <125000>; 1046 hysteresis = <1000>; 1047 type = "critical"; 1048 }; 1049 }; 1050 }; 1051 1052 ddrss-top-thermal { 1053 polling-delay-passive = <250>; 1054 thermal-sensors = <&tsens 15>; 1055 1056 trips { 1057 ddrss-top-critical { 1058 temperature = <125000>; 1059 hysteresis = <1000>; 1060 type = "critical"; 1061 }; 1062 }; 1063 }; 1064 }; 1065 1066 timer { 1067 compatible = "arm,armv8-timer"; 1068 interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1069 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1070 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1071 <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1072 }; 1073 1074 wcss: wcss-smp2p { 1075 compatible = "qcom,smp2p"; 1076 qcom,smem = <435>, <428>; 1077 1078 interrupt-parent = <&intc>; 1079 interrupts = <GIC_SPI 322 IRQ_TYPE_EDGE_RISING>; 1080 1081 mboxes = <&apcs_glb 9>; 1082 1083 qcom,local-pid = <0>; 1084 qcom,remote-pid = <1>; 1085 1086 wcss_smp2p_out: master-kernel { 1087 qcom,entry-name = "master-kernel"; 1088 #qcom,smem-state-cells = <1>; 1089 }; 1090 1091 wcss_smp2p_in: slave-kernel { 1092 qcom,entry-name = "slave-kernel"; 1093 interrupt-controller; 1094 #interrupt-cells = <2>; 1095 }; 1096 }; 1097};
~/
Read-only file preview.