hamoa.dtsi

   1// SPDX-License-Identifier: BSD-3-Clause
   2/*
   3 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved.
   4 */
   5
   6#include <dt-bindings/clock/qcom,rpmh.h>
   7#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
   8#include <dt-bindings/clock/qcom,sm8450-videocc.h>
   9#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
  10#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
  11#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
  12#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
  13#include <dt-bindings/dma/qcom-gpi.h>
  14#include <dt-bindings/interconnect/qcom,icc.h>
  15#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
  16#include <dt-bindings/interrupt-controller/arm-gic.h>
  17#include <dt-bindings/mailbox/qcom-ipcc.h>
  18#include <dt-bindings/phy/phy-qcom-qmp.h>
  19#include <dt-bindings/power/qcom,rpmhpd.h>
  20#include <dt-bindings/power/qcom-rpmpd.h>
  21#include <dt-bindings/soc/qcom,gpr.h>
  22#include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
  24#include <dt-bindings/thermal/thermal.h>
  25
  26/ {
  27	interrupt-parent = <&intc>;
  28
  29	#address-cells = <2>;
  30	#size-cells = <2>;
  31
  32	chosen { };
  33
  34	clocks {
  35		xo_board: xo-board {
  36			compatible = "fixed-clock";
  37			clock-frequency = <76800000>;
  38			#clock-cells = <0>;
  39		};
  40
  41		sleep_clk: sleep-clk {
  42			compatible = "fixed-clock";
  43			clock-frequency = <32764>;
  44			#clock-cells = <0>;
  45		};
  46
  47		bi_tcxo_div2: bi-tcxo-div2-clk {
  48			compatible = "fixed-factor-clock";
  49			#clock-cells = <0>;
  50
  51			clocks = <&rpmhcc RPMH_CXO_CLK>;
  52			clock-mult = <1>;
  53			clock-div = <2>;
  54		};
  55
  56		bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
  57			compatible = "fixed-factor-clock";
  58			#clock-cells = <0>;
  59
  60			clocks = <&rpmhcc RPMH_CXO_CLK_A>;
  61			clock-mult = <1>;
  62			clock-div = <2>;
  63		};
  64	};
  65
  66	cpus {
  67		#address-cells = <2>;
  68		#size-cells = <0>;
  69
  70		cpu0: cpu@0 {
  71			device_type = "cpu";
  72			compatible = "qcom,oryon";
  73			reg = <0x0 0x0>;
  74			enable-method = "psci";
  75			next-level-cache = <&l2_0>;
  76			power-domains = <&cpu_pd0>, <&scmi_dvfs 0>;
  77			power-domain-names = "psci", "perf";
  78
  79			l2_0: l2-cache {
  80				compatible = "cache";
  81				cache-level = <2>;
  82				cache-unified;
  83			};
  84		};
  85
  86		cpu1: cpu@100 {
  87			device_type = "cpu";
  88			compatible = "qcom,oryon";
  89			reg = <0x0 0x100>;
  90			enable-method = "psci";
  91			next-level-cache = <&l2_0>;
  92			power-domains = <&cpu_pd1>, <&scmi_dvfs 0>;
  93			power-domain-names = "psci", "perf";
  94		};
  95
  96		cpu2: cpu@200 {
  97			device_type = "cpu";
  98			compatible = "qcom,oryon";
  99			reg = <0x0 0x200>;
 100			enable-method = "psci";
 101			next-level-cache = <&l2_0>;
 102			power-domains = <&cpu_pd2>, <&scmi_dvfs 0>;
 103			power-domain-names = "psci", "perf";
 104		};
 105
 106		cpu3: cpu@300 {
 107			device_type = "cpu";
 108			compatible = "qcom,oryon";
 109			reg = <0x0 0x300>;
 110			enable-method = "psci";
 111			next-level-cache = <&l2_0>;
 112			power-domains = <&cpu_pd3>, <&scmi_dvfs 0>;
 113			power-domain-names = "psci", "perf";
 114		};
 115
 116		cpu4: cpu@10000 {
 117			device_type = "cpu";
 118			compatible = "qcom,oryon";
 119			reg = <0x0 0x10000>;
 120			enable-method = "psci";
 121			next-level-cache = <&l2_1>;
 122			power-domains = <&cpu_pd4>, <&scmi_dvfs 1>;
 123			power-domain-names = "psci", "perf";
 124
 125			l2_1: l2-cache {
 126				compatible = "cache";
 127				cache-level = <2>;
 128				cache-unified;
 129			};
 130		};
 131
 132		cpu5: cpu@10100 {
 133			device_type = "cpu";
 134			compatible = "qcom,oryon";
 135			reg = <0x0 0x10100>;
 136			enable-method = "psci";
 137			next-level-cache = <&l2_1>;
 138			power-domains = <&cpu_pd5>, <&scmi_dvfs 1>;
 139			power-domain-names = "psci", "perf";
 140		};
 141
 142		cpu6: cpu@10200 {
 143			device_type = "cpu";
 144			compatible = "qcom,oryon";
 145			reg = <0x0 0x10200>;
 146			enable-method = "psci";
 147			next-level-cache = <&l2_1>;
 148			power-domains = <&cpu_pd6>, <&scmi_dvfs 1>;
 149			power-domain-names = "psci", "perf";
 150		};
 151
 152		cpu7: cpu@10300 {
 153			device_type = "cpu";
 154			compatible = "qcom,oryon";
 155			reg = <0x0 0x10300>;
 156			enable-method = "psci";
 157			next-level-cache = <&l2_1>;
 158			power-domains = <&cpu_pd7>, <&scmi_dvfs 1>;
 159			power-domain-names = "psci", "perf";
 160		};
 161
 162		cpu8: cpu@20000 {
 163			device_type = "cpu";
 164			compatible = "qcom,oryon";
 165			reg = <0x0 0x20000>;
 166			enable-method = "psci";
 167			next-level-cache = <&l2_2>;
 168			power-domains = <&cpu_pd8>, <&scmi_dvfs 2>;
 169			power-domain-names = "psci", "perf";
 170
 171			l2_2: l2-cache {
 172				compatible = "cache";
 173				cache-level = <2>;
 174				cache-unified;
 175			};
 176		};
 177
 178		cpu9: cpu@20100 {
 179			device_type = "cpu";
 180			compatible = "qcom,oryon";
 181			reg = <0x0 0x20100>;
 182			enable-method = "psci";
 183			next-level-cache = <&l2_2>;
 184			power-domains = <&cpu_pd9>, <&scmi_dvfs 2>;
 185			power-domain-names = "psci", "perf";
 186		};
 187
 188		cpu10: cpu@20200 {
 189			device_type = "cpu";
 190			compatible = "qcom,oryon";
 191			reg = <0x0 0x20200>;
 192			enable-method = "psci";
 193			next-level-cache = <&l2_2>;
 194			power-domains = <&cpu_pd10>, <&scmi_dvfs 2>;
 195			power-domain-names = "psci", "perf";
 196		};
 197
 198		cpu11: cpu@20300 {
 199			device_type = "cpu";
 200			compatible = "qcom,oryon";
 201			reg = <0x0 0x20300>;
 202			enable-method = "psci";
 203			next-level-cache = <&l2_2>;
 204			power-domains = <&cpu_pd11>, <&scmi_dvfs 2>;
 205			power-domain-names = "psci", "perf";
 206		};
 207
 208		cpu-map {
 209			cluster0 {
 210				core0 {
 211					cpu = <&cpu0>;
 212				};
 213
 214				core1 {
 215					cpu = <&cpu1>;
 216				};
 217
 218				core2 {
 219					cpu = <&cpu2>;
 220				};
 221
 222				core3 {
 223					cpu = <&cpu3>;
 224				};
 225			};
 226
 227			cluster1 {
 228				core0 {
 229					cpu = <&cpu4>;
 230				};
 231
 232				core1 {
 233					cpu = <&cpu5>;
 234				};
 235
 236				core2 {
 237					cpu = <&cpu6>;
 238				};
 239
 240				core3 {
 241					cpu = <&cpu7>;
 242				};
 243			};
 244
 245			cpu_map_cluster2: cluster2 {
 246				core0 {
 247					cpu = <&cpu8>;
 248				};
 249
 250				core1 {
 251					cpu = <&cpu9>;
 252				};
 253
 254				core2 {
 255					cpu = <&cpu10>;
 256				};
 257
 258				core3 {
 259					cpu = <&cpu11>;
 260				};
 261			};
 262		};
 263
 264		idle-states {
 265			entry-method = "psci";
 266
 267			cluster_c4: cpu-sleep-0 {
 268				compatible = "arm,idle-state";
 269				idle-state-name = "ret";
 270				arm,psci-suspend-param = <0x00000004>;
 271				entry-latency-us = <180>;
 272				exit-latency-us = <320>;
 273				min-residency-us = <600>;
 274			};
 275		};
 276
 277		domain-idle-states {
 278			cluster_cl4: cluster-sleep-0 {
 279				compatible = "domain-idle-state";
 280				arm,psci-suspend-param = <0x01000044>;
 281				entry-latency-us = <350>;
 282				exit-latency-us = <500>;
 283				min-residency-us = <2500>;
 284			};
 285
 286			cluster_cl5: cluster-sleep-1 {
 287				compatible = "domain-idle-state";
 288				arm,psci-suspend-param = <0x01000054>;
 289				entry-latency-us = <2200>;
 290				exit-latency-us = <4000>;
 291				min-residency-us = <7000>;
 292			};
 293		};
 294	};
 295
 296	dummy-sink {
 297		compatible = "arm,coresight-dummy-sink";
 298
 299		in-ports {
 300			port {
 301				eud_in: endpoint {
 302					remote-endpoint = <&swao_rep_out1>;
 303				};
 304			};
 305		};
 306	};
 307
 308	firmware {
 309		scm: scm {
 310			compatible = "qcom,scm-x1e80100", "qcom,scm";
 311			interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
 312					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 313			qcom,dload-mode = <&tcsr 0x19000>;
 314		};
 315
 316		scmi {
 317			compatible = "arm,scmi";
 318			mboxes = <&cpucp_mbox 0>, <&cpucp_mbox 2>;
 319			mbox-names = "tx", "rx";
 320			shmem = <&cpu_scp_lpri0>, <&cpu_scp_lpri1>;
 321
 322			#address-cells = <1>;
 323			#size-cells = <0>;
 324
 325			scmi_dvfs: protocol@13 {
 326				reg = <0x13>;
 327				#power-domain-cells = <1>;
 328			};
 329		};
 330	};
 331
 332	clk_virt: interconnect-0 {
 333		compatible = "qcom,x1e80100-clk-virt";
 334		#interconnect-cells = <2>;
 335		qcom,bcm-voters = <&apps_bcm_voter>;
 336	};
 337
 338	mc_virt: interconnect-1 {
 339		compatible = "qcom,x1e80100-mc-virt";
 340		#interconnect-cells = <2>;
 341		qcom,bcm-voters = <&apps_bcm_voter>;
 342	};
 343
 344	memory@80000000 {
 345		device_type = "memory";
 346		/* We expect the bootloader to fill in the size */
 347		reg = <0 0x80000000 0 0>;
 348	};
 349
 350	pmu {
 351		compatible = "arm,armv8-pmuv3";
 352		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
 353	};
 354
 355	psci {
 356		compatible = "arm,psci-1.0";
 357		method = "smc";
 358
 359		cpu_pd0: power-domain-cpu0 {
 360			#power-domain-cells = <0>;
 361			power-domains = <&cluster_pd0>;
 362			domain-idle-states = <&cluster_c4>;
 363		};
 364
 365		cpu_pd1: power-domain-cpu1 {
 366			#power-domain-cells = <0>;
 367			power-domains = <&cluster_pd0>;
 368			domain-idle-states = <&cluster_c4>;
 369		};
 370
 371		cpu_pd2: power-domain-cpu2 {
 372			#power-domain-cells = <0>;
 373			power-domains = <&cluster_pd0>;
 374			domain-idle-states = <&cluster_c4>;
 375		};
 376
 377		cpu_pd3: power-domain-cpu3 {
 378			#power-domain-cells = <0>;
 379			power-domains = <&cluster_pd0>;
 380			domain-idle-states = <&cluster_c4>;
 381		};
 382
 383		cpu_pd4: power-domain-cpu4 {
 384			#power-domain-cells = <0>;
 385			power-domains = <&cluster_pd1>;
 386			domain-idle-states = <&cluster_c4>;
 387		};
 388
 389		cpu_pd5: power-domain-cpu5 {
 390			#power-domain-cells = <0>;
 391			power-domains = <&cluster_pd1>;
 392			domain-idle-states = <&cluster_c4>;
 393		};
 394
 395		cpu_pd6: power-domain-cpu6 {
 396			#power-domain-cells = <0>;
 397			power-domains = <&cluster_pd1>;
 398			domain-idle-states = <&cluster_c4>;
 399		};
 400
 401		cpu_pd7: power-domain-cpu7 {
 402			#power-domain-cells = <0>;
 403			power-domains = <&cluster_pd1>;
 404			domain-idle-states = <&cluster_c4>;
 405		};
 406
 407		cpu_pd8: power-domain-cpu8 {
 408			#power-domain-cells = <0>;
 409			power-domains = <&cluster_pd2>;
 410			domain-idle-states = <&cluster_c4>;
 411		};
 412
 413		cpu_pd9: power-domain-cpu9 {
 414			#power-domain-cells = <0>;
 415			power-domains = <&cluster_pd2>;
 416			domain-idle-states = <&cluster_c4>;
 417		};
 418
 419		cpu_pd10: power-domain-cpu10 {
 420			#power-domain-cells = <0>;
 421			power-domains = <&cluster_pd2>;
 422			domain-idle-states = <&cluster_c4>;
 423		};
 424
 425		cpu_pd11: power-domain-cpu11 {
 426			#power-domain-cells = <0>;
 427			power-domains = <&cluster_pd2>;
 428			domain-idle-states = <&cluster_c4>;
 429		};
 430
 431		cluster_pd0: power-domain-cpu-cluster0 {
 432			#power-domain-cells = <0>;
 433			domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
 434			power-domains = <&system_pd>;
 435		};
 436
 437		cluster_pd1: power-domain-cpu-cluster1 {
 438			#power-domain-cells = <0>;
 439			domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
 440			power-domains = <&system_pd>;
 441		};
 442
 443		cluster_pd2: power-domain-cpu-cluster2 {
 444			#power-domain-cells = <0>;
 445			domain-idle-states = <&cluster_cl4>, <&cluster_cl5>;
 446			power-domains = <&system_pd>;
 447		};
 448
 449		system_pd: power-domain-system {
 450			#power-domain-cells = <0>;
 451			/* TODO: system-wide idle states */
 452		};
 453	};
 454
 455	reserved-memory {
 456		#address-cells = <2>;
 457		#size-cells = <2>;
 458		ranges;
 459
 460		gunyah_hyp_mem: gunyah-hyp@80000000 {
 461			reg = <0x0 0x80000000 0x0 0x800000>;
 462			no-map;
 463		};
 464
 465		hyp_elf_package_mem: hyp-elf-package@80800000 {
 466			reg = <0x0 0x80800000 0x0 0x200000>;
 467			no-map;
 468		};
 469
 470		ncc_mem: ncc@80a00000 {
 471			reg = <0x0 0x80a00000 0x0 0x400000>;
 472			no-map;
 473		};
 474
 475		cpucp_log_mem: cpucp-log@80e00000 {
 476			reg = <0x0 0x80e00000 0x0 0x40000>;
 477			no-map;
 478		};
 479
 480		cpucp_mem: cpucp@80e40000 {
 481			reg = <0x0 0x80e40000 0x0 0x540000>;
 482			no-map;
 483		};
 484
 485		reserved-region@81380000 {
 486			reg = <0x0 0x81380000 0x0 0x80000>;
 487			no-map;
 488		};
 489
 490		tags_mem: tags-region@81400000 {
 491			reg = <0x0 0x81400000 0x0 0x1a0000>;
 492			no-map;
 493		};
 494
 495		xbl_dtlog_mem: xbl-dtlog@81a00000 {
 496			reg = <0x0 0x81a00000 0x0 0x40000>;
 497			no-map;
 498		};
 499
 500		xbl_ramdump_mem: xbl-ramdump@81a40000 {
 501			reg = <0x0 0x81a40000 0x0 0x1c0000>;
 502			no-map;
 503		};
 504
 505		aop_image_mem: aop-image@81c00000 {
 506			reg = <0x0 0x81c00000 0x0 0x60000>;
 507			no-map;
 508		};
 509
 510		aop_cmd_db_mem: aop-cmd-db@81c60000 {
 511			compatible = "qcom,cmd-db";
 512			reg = <0x0 0x81c60000 0x0 0x20000>;
 513			no-map;
 514		};
 515
 516		aop_config_mem: aop-config@81c80000 {
 517			reg = <0x0 0x81c80000 0x0 0x20000>;
 518			no-map;
 519		};
 520
 521		tme_crash_dump_mem: tme-crash-dump@81ca0000 {
 522			reg = <0x0 0x81ca0000 0x0 0x40000>;
 523			no-map;
 524		};
 525
 526		tme_log_mem: tme-log@81ce0000 {
 527			reg = <0x0 0x81ce0000 0x0 0x4000>;
 528			no-map;
 529		};
 530
 531		uefi_log_mem: uefi-log@81ce4000 {
 532			reg = <0x0 0x81ce4000 0x0 0x10000>;
 533			no-map;
 534		};
 535
 536		secdata_apss_mem: secdata-apss@81cff000 {
 537			reg = <0x0 0x81cff000 0x0 0x1000>;
 538			no-map;
 539		};
 540
 541		pdp_ns_shared_mem: pdp-ns-shared@81e00000 {
 542			reg = <0x0 0x81e00000 0x0 0x100000>;
 543			no-map;
 544		};
 545
 546		gpu_prr_mem: gpu-prr@81f00000 {
 547			reg = <0x0 0x81f00000 0x0 0x10000>;
 548			no-map;
 549		};
 550
 551		tpm_control_mem: tpm-control@81f10000 {
 552			reg = <0x0 0x81f10000 0x0 0x10000>;
 553			no-map;
 554		};
 555
 556		usb_ucsi_shared_mem: usb-ucsi-shared@81f20000 {
 557			reg = <0x0 0x81f20000 0x0 0x10000>;
 558			no-map;
 559		};
 560
 561		pld_pep_mem: pld-pep@81f30000 {
 562			reg = <0x0 0x81f30000 0x0 0x6000>;
 563			no-map;
 564		};
 565
 566		pld_gmu_mem: pld-gmu@81f36000 {
 567			reg = <0x0 0x81f36000 0x0 0x1000>;
 568			no-map;
 569		};
 570
 571		pld_pdp_mem: pld-pdp@81f37000 {
 572			reg = <0x0 0x81f37000 0x0 0x1000>;
 573			no-map;
 574		};
 575
 576		tz_stat_mem: tz-stat@82700000 {
 577			reg = <0x0 0x82700000 0x0 0x100000>;
 578			no-map;
 579		};
 580
 581		xbl_tmp_buffer_mem: xbl-tmp-buffer@82800000 {
 582			reg = <0x0 0x82800000 0x0 0xc00000>;
 583			no-map;
 584		};
 585
 586		adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@84b00000 {
 587			reg = <0x0 0x84b00000 0x0 0x800000>;
 588			no-map;
 589		};
 590
 591		spu_secure_shared_memory_mem: spu-secure-shared-memory@85300000 {
 592			reg = <0x0 0x85300000 0x0 0x80000>;
 593			no-map;
 594		};
 595
 596		adsp_boot_dtb_mem: adsp-boot-dtb@866c0000 {
 597			reg = <0x0 0x866c0000 0x0 0x40000>;
 598			no-map;
 599		};
 600
 601		spss_region_mem: spss-region@86700000 {
 602			reg = <0x0 0x86700000 0x0 0x400000>;
 603			no-map;
 604		};
 605
 606		adsp_boot_mem: adsp-boot@86b00000 {
 607			reg = <0x0 0x86b00000 0x0 0xc00000>;
 608			no-map;
 609		};
 610
 611		video_mem: video@87700000 {
 612			reg = <0x0 0x87700000 0x0 0x700000>;
 613			no-map;
 614		};
 615
 616		adspslpi_mem: adspslpi@87e00000 {
 617			reg = <0x0 0x87e00000 0x0 0x3a00000>;
 618			no-map;
 619		};
 620
 621		q6_adsp_dtb_mem: q6-adsp-dtb@8b800000 {
 622			reg = <0x0 0x8b800000 0x0 0x80000>;
 623			no-map;
 624		};
 625
 626		cdsp_mem: cdsp@8b900000 {
 627			reg = <0x0 0x8b900000 0x0 0x2000000>;
 628			no-map;
 629		};
 630
 631		q6_cdsp_dtb_mem: q6-cdsp-dtb@8d900000 {
 632			reg = <0x0 0x8d900000 0x0 0x80000>;
 633			no-map;
 634		};
 635
 636		gpu_microcode_mem: gpu-microcode@8d9fe000 {
 637			reg = <0x0 0x8d9fe000 0x0 0x2000>;
 638			no-map;
 639		};
 640
 641		cvp_mem: cvp@8da00000 {
 642			reg = <0x0 0x8da00000 0x0 0x700000>;
 643			no-map;
 644		};
 645
 646		camera_mem: camera@8e100000 {
 647			reg = <0x0 0x8e100000 0x0 0x800000>;
 648			no-map;
 649		};
 650
 651		av1_encoder_mem: av1-encoder@8e900000 {
 652			reg = <0x0 0x8e900000 0x0 0x700000>;
 653			no-map;
 654		};
 655
 656		reserved-region@8f000000 {
 657			reg = <0x0 0x8f000000 0x0 0xa00000>;
 658			no-map;
 659		};
 660
 661		wpss_mem: wpss@8fa00000 {
 662			reg = <0x0 0x8fa00000 0x0 0x1900000>;
 663			no-map;
 664		};
 665
 666		q6_wpss_dtb_mem: q6-wpss-dtb@91300000 {
 667			reg = <0x0 0x91300000 0x0 0x80000>;
 668			no-map;
 669		};
 670
 671		xbl_sc_mem: xbl-sc@d8000000 {
 672			reg = <0x0 0xd8000000 0x0 0x40000>;
 673			no-map;
 674		};
 675
 676		reserved-region@d8040000 {
 677			reg = <0x0 0xd8040000 0x0 0xa0000>;
 678			no-map;
 679		};
 680
 681		qtee_mem: qtee@d80e0000 {
 682			reg = <0x0 0xd80e0000 0x0 0x520000>;
 683			no-map;
 684		};
 685
 686		ta_mem: ta@d8600000 {
 687			reg = <0x0 0xd8600000 0x0 0x8a00000>;
 688			no-map;
 689		};
 690
 691		tags_mem1: tags@e1000000 {
 692			reg = <0x0 0xe1000000 0x0 0x26a0000>;
 693			no-map;
 694		};
 695
 696		llcc_lpi_mem: llcc-lpi@ff800000 {
 697			reg = <0x0 0xff800000 0x0 0x600000>;
 698			no-map;
 699		};
 700
 701		smem_mem: smem@ffe00000 {
 702			compatible = "qcom,smem";
 703			reg = <0x0 0xffe00000 0x0 0x200000>;
 704			hwlocks = <&tcsr_mutex 3>;
 705			no-map;
 706		};
 707	};
 708
 709	qup_opp_table_100mhz: opp-table-qup100mhz {
 710		compatible = "operating-points-v2";
 711
 712		opp-75000000 {
 713			opp-hz = /bits/ 64 <75000000>;
 714			required-opps = <&rpmhpd_opp_low_svs>;
 715		};
 716
 717		opp-100000000 {
 718			opp-hz = /bits/ 64 <100000000>;
 719			required-opps = <&rpmhpd_opp_svs>;
 720		};
 721	};
 722
 723	qup_opp_table_120mhz: opp-table-qup120mhz {
 724		compatible = "operating-points-v2";
 725
 726		opp-75000000 {
 727			opp-hz = /bits/ 64 <75000000>;
 728			required-opps = <&rpmhpd_opp_low_svs>;
 729		};
 730
 731		opp-120000000 {
 732			opp-hz = /bits/ 64 <120000000>;
 733			required-opps = <&rpmhpd_opp_svs>;
 734		};
 735	};
 736
 737	smp2p-adsp {
 738		compatible = "qcom,smp2p";
 739
 740		interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
 741					     IPCC_MPROC_SIGNAL_SMP2P
 742					     IRQ_TYPE_EDGE_RISING>;
 743
 744		mboxes = <&ipcc IPCC_CLIENT_LPASS
 745				IPCC_MPROC_SIGNAL_SMP2P>;
 746
 747		qcom,smem = <443>, <429>;
 748		qcom,local-pid = <0>;
 749		qcom,remote-pid = <2>;
 750
 751		smp2p_adsp_out: master-kernel {
 752			qcom,entry-name = "master-kernel";
 753			#qcom,smem-state-cells = <1>;
 754		};
 755
 756		smp2p_adsp_in: slave-kernel {
 757			qcom,entry-name = "slave-kernel";
 758			interrupt-controller;
 759			#interrupt-cells = <2>;
 760		};
 761	};
 762
 763	smp2p-cdsp {
 764		compatible = "qcom,smp2p";
 765
 766		interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
 767					     IPCC_MPROC_SIGNAL_SMP2P
 768					     IRQ_TYPE_EDGE_RISING>;
 769
 770		mboxes = <&ipcc IPCC_CLIENT_CDSP
 771				IPCC_MPROC_SIGNAL_SMP2P>;
 772
 773		qcom,smem = <94>, <432>;
 774		qcom,local-pid = <0>;
 775		qcom,remote-pid = <5>;
 776
 777		smp2p_cdsp_out: master-kernel {
 778			qcom,entry-name = "master-kernel";
 779			#qcom,smem-state-cells = <1>;
 780		};
 781
 782		smp2p_cdsp_in: slave-kernel {
 783			qcom,entry-name = "slave-kernel";
 784			interrupt-controller;
 785			#interrupt-cells = <2>;
 786		};
 787	};
 788
 789	soc: soc@0 {
 790		compatible = "simple-bus";
 791
 792		#address-cells = <2>;
 793		#size-cells = <2>;
 794		dma-ranges = <0 0 0 0 0x100 0>;
 795		ranges = <0 0 0 0 0x100 0>;
 796
 797		gcc: clock-controller@100000 {
 798			compatible = "qcom,x1e80100-gcc";
 799			reg = <0 0x00100000 0 0x200000>;
 800
 801			clocks = <&bi_tcxo_div2>,
 802				 <&sleep_clk>,
 803				 <&pcie3_phy>,
 804				 <&pcie4_phy>,
 805				 <&pcie5_phy>,
 806				 <&pcie6a_phy>,
 807				 <0>,
 808				 <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 809				 <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 810				 <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
 811				 <0>,
 812				 <0>,
 813				 <0>,
 814				 <0>,
 815				 <0>,
 816				 <0>,
 817				 <0>,
 818				 <0>,
 819				 <0>,
 820				 <0>,
 821				 <0>,
 822				 <0>,
 823				 <0>,
 824				 <0>,
 825				 <0>,
 826				 <0>,
 827				 <0>,
 828				 <0>,
 829				 <0>,
 830				 <0>,
 831				 <0>,
 832				 <0>,
 833				 <0>,
 834				 <0>,
 835				 <0>,
 836				 <0>,
 837				 <0>;
 838
 839			power-domains = <&rpmhpd RPMHPD_CX>;
 840			#clock-cells = <1>;
 841			#reset-cells = <1>;
 842			#power-domain-cells = <1>;
 843		};
 844
 845		ipcc: mailbox@408000 {
 846			compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
 847			reg = <0 0x00408000 0 0x1000>;
 848
 849			interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
 850			interrupt-controller;
 851			#interrupt-cells = <3>;
 852
 853			#mbox-cells = <2>;
 854		};
 855
 856		gpi_dma2: dma-controller@800000 {
 857			compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
 858			reg = <0 0x00800000 0 0x60000>;
 859
 860			interrupts = <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>,
 861				     <GIC_SPI 789 IRQ_TYPE_LEVEL_HIGH>,
 862				     <GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>,
 863				     <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH>,
 864				     <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH>,
 865				     <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH>,
 866				     <GIC_SPI 794 IRQ_TYPE_LEVEL_HIGH>,
 867				     <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH>,
 868				     <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH>,
 869				     <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH>,
 870				     <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH>,
 871				     <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH>;
 872
 873			dma-channels = <12>;
 874			dma-channel-mask = <0x3e>;
 875			#dma-cells = <3>;
 876
 877			iommus = <&apps_smmu 0x436 0x0>;
 878
 879			status = "disabled";
 880		};
 881
 882		qupv3_2: geniqup@8c0000 {
 883			compatible = "qcom,geni-se-qup";
 884			reg = <0 0x008c0000 0 0x2000>;
 885
 886			clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
 887				 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
 888			clock-names = "m-ahb",
 889				      "s-ahb";
 890
 891			iommus = <&apps_smmu 0x423 0x0>;
 892
 893			#address-cells = <2>;
 894			#size-cells = <2>;
 895			ranges;
 896
 897			status = "disabled";
 898
 899			i2c16: i2c@880000 {
 900				compatible = "qcom,geni-i2c";
 901				reg = <0 0x00880000 0 0x4000>;
 902
 903				interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
 904
 905				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 906				clock-names = "se";
 907
 908				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 909						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 910						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
 911						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
 912						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 913						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 914				interconnect-names = "qup-core",
 915						     "qup-config",
 916						     "qup-memory";
 917
 918				power-domains = <&rpmhpd RPMHPD_CX>;
 919				required-opps = <&rpmhpd_opp_low_svs>;
 920
 921				dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
 922				       <&gpi_dma2 1 0 QCOM_GPI_I2C>;
 923				dma-names = "tx",
 924					    "rx";
 925
 926				pinctrl-0 = <&qup_i2c16_data_clk>;
 927				pinctrl-names = "default";
 928
 929				#address-cells = <1>;
 930				#size-cells = <0>;
 931
 932				status = "disabled";
 933			};
 934
 935			spi16: spi@880000 {
 936				compatible = "qcom,geni-spi";
 937				reg = <0 0x00880000 0 0x4000>;
 938
 939				interrupts = <GIC_SPI 808 IRQ_TYPE_LEVEL_HIGH>;
 940
 941				clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
 942				clock-names = "se";
 943
 944				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 945						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 946						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
 947						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
 948						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 949						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 950				interconnect-names = "qup-core",
 951						     "qup-config",
 952						     "qup-memory";
 953
 954				power-domains = <&rpmhpd RPMHPD_CX>;
 955				operating-points-v2 = <&qup_opp_table_120mhz>;
 956
 957				dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>,
 958				       <&gpi_dma2 1 0 QCOM_GPI_SPI>;
 959				dma-names = "tx",
 960					    "rx";
 961
 962				pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>;
 963				pinctrl-names = "default";
 964
 965				#address-cells = <1>;
 966				#size-cells = <0>;
 967
 968				status = "disabled";
 969			};
 970
 971			i2c17: i2c@884000 {
 972				compatible = "qcom,geni-i2c";
 973				reg = <0 0x00884000 0 0x4000>;
 974
 975				interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
 976
 977				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
 978				clock-names = "se";
 979
 980				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
 981						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
 982						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
 983						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
 984						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
 985						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 986				interconnect-names = "qup-core",
 987						     "qup-config",
 988						     "qup-memory";
 989
 990				power-domains = <&rpmhpd RPMHPD_CX>;
 991				required-opps = <&rpmhpd_opp_low_svs>;
 992
 993				dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
 994				       <&gpi_dma2 1 1 QCOM_GPI_I2C>;
 995				dma-names = "tx",
 996					    "rx";
 997
 998				pinctrl-0 = <&qup_i2c17_data_clk>;
 999				pinctrl-names = "default";
1000
1001				#address-cells = <1>;
1002				#size-cells = <0>;
1003
1004				status = "disabled";
1005			};
1006
1007			spi17: spi@884000 {
1008				compatible = "qcom,geni-spi";
1009				reg = <0 0x00884000 0 0x4000>;
1010
1011				interrupts = <GIC_SPI 809 IRQ_TYPE_LEVEL_HIGH>;
1012
1013				clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
1014				clock-names = "se";
1015
1016				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1017						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1018						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1019						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1020						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1021						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1022				interconnect-names = "qup-core",
1023						     "qup-config",
1024						     "qup-memory";
1025
1026				power-domains = <&rpmhpd RPMHPD_CX>;
1027				operating-points-v2 = <&qup_opp_table_120mhz>;
1028
1029				dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>,
1030				       <&gpi_dma2 1 1 QCOM_GPI_SPI>;
1031				dma-names = "tx",
1032					    "rx";
1033
1034				pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>;
1035				pinctrl-names = "default";
1036
1037				#address-cells = <1>;
1038				#size-cells = <0>;
1039
1040				status = "disabled";
1041			};
1042
1043			i2c18: i2c@888000 {
1044				compatible = "qcom,geni-i2c";
1045				reg = <0 0x00888000 0 0x4000>;
1046
1047				interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
1048
1049				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1050				clock-names = "se";
1051
1052				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1053						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1054						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1055						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1056						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1057						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1058				interconnect-names = "qup-core",
1059						     "qup-config",
1060						     "qup-memory";
1061
1062				power-domains = <&rpmhpd RPMHPD_CX>;
1063				required-opps = <&rpmhpd_opp_low_svs>;
1064
1065				dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
1066				       <&gpi_dma2 1 2 QCOM_GPI_I2C>;
1067				dma-names = "tx",
1068					    "rx";
1069
1070				pinctrl-0 = <&qup_i2c18_data_clk>;
1071				pinctrl-names = "default";
1072
1073				#address-cells = <1>;
1074				#size-cells = <0>;
1075
1076				status = "disabled";
1077			};
1078
1079			spi18: spi@888000 {
1080				compatible = "qcom,geni-spi";
1081				reg = <0 0x00888000 0 0x4000>;
1082
1083				interrupts = <GIC_SPI 810 IRQ_TYPE_LEVEL_HIGH>;
1084
1085				clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
1086				clock-names = "se";
1087
1088				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1089						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1090						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1091						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1092						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1093						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1094				interconnect-names = "qup-core",
1095						     "qup-config",
1096						     "qup-memory";
1097
1098				power-domains = <&rpmhpd RPMHPD_CX>;
1099				operating-points-v2 = <&qup_opp_table_100mhz>;
1100
1101				dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>,
1102				       <&gpi_dma2 1 2 QCOM_GPI_SPI>;
1103				dma-names = "tx",
1104					    "rx";
1105
1106				pinctrl-0 = <&qup_spi18_data_clk>, <&qup_spi18_cs>;
1107				pinctrl-names = "default";
1108
1109				#address-cells = <1>;
1110				#size-cells = <0>;
1111
1112				status = "disabled";
1113			};
1114
1115			i2c19: i2c@88c000 {
1116				compatible = "qcom,geni-i2c";
1117				reg = <0 0x0088c000 0 0x4000>;
1118
1119				interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1120
1121				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1122				clock-names = "se";
1123
1124				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1125						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1126						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1127						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1128						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1129						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1130				interconnect-names = "qup-core",
1131						     "qup-config",
1132						     "qup-memory";
1133
1134				power-domains = <&rpmhpd RPMHPD_CX>;
1135				required-opps = <&rpmhpd_opp_low_svs>;
1136
1137				dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
1138				       <&gpi_dma2 1 3 QCOM_GPI_I2C>;
1139				dma-names = "tx",
1140					    "rx";
1141
1142				pinctrl-0 = <&qup_i2c19_data_clk>;
1143				pinctrl-names = "default";
1144
1145				#address-cells = <1>;
1146				#size-cells = <0>;
1147
1148				status = "disabled";
1149			};
1150
1151			spi19: spi@88c000 {
1152				compatible = "qcom,geni-spi";
1153				reg = <0 0x0088c000 0 0x4000>;
1154
1155				interrupts = <GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>;
1156
1157				clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
1158				clock-names = "se";
1159
1160				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1161						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1162						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1163						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1164						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1165						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1166				interconnect-names = "qup-core",
1167						     "qup-config",
1168						     "qup-memory";
1169
1170				power-domains = <&rpmhpd RPMHPD_CX>;
1171				operating-points-v2 = <&qup_opp_table_100mhz>;
1172
1173				dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>,
1174				       <&gpi_dma2 1 3 QCOM_GPI_SPI>;
1175				dma-names = "tx",
1176					    "rx";
1177
1178				pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>;
1179				pinctrl-names = "default";
1180
1181				#address-cells = <1>;
1182				#size-cells = <0>;
1183
1184				status = "disabled";
1185			};
1186
1187			i2c20: i2c@890000 {
1188				compatible = "qcom,geni-i2c";
1189				reg = <0 0x00890000 0 0x4000>;
1190
1191				interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1192
1193				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1194				clock-names = "se";
1195
1196				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1197						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1198						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1199						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1200						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1201						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1202				interconnect-names = "qup-core",
1203						     "qup-config",
1204						     "qup-memory";
1205
1206				power-domains = <&rpmhpd RPMHPD_CX>;
1207				required-opps = <&rpmhpd_opp_low_svs>;
1208
1209				dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
1210				       <&gpi_dma2 1 4 QCOM_GPI_I2C>;
1211				dma-names = "tx",
1212					    "rx";
1213
1214				pinctrl-0 = <&qup_i2c20_data_clk>;
1215				pinctrl-names = "default";
1216
1217				#address-cells = <1>;
1218				#size-cells = <0>;
1219
1220				status = "disabled";
1221			};
1222
1223			spi20: spi@890000 {
1224				compatible = "qcom,geni-spi";
1225				reg = <0 0x00890000 0 0x4000>;
1226
1227				interrupts = <GIC_SPI 812 IRQ_TYPE_LEVEL_HIGH>;
1228
1229				clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
1230				clock-names = "se";
1231
1232				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1233						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1234						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1235						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1236						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1237						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1238				interconnect-names = "qup-core",
1239						     "qup-config",
1240						     "qup-memory";
1241
1242				power-domains = <&rpmhpd RPMHPD_CX>;
1243				operating-points-v2 = <&qup_opp_table_100mhz>;
1244
1245				dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>,
1246				       <&gpi_dma2 1 4 QCOM_GPI_SPI>;
1247				dma-names = "tx",
1248					    "rx";
1249
1250				pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>;
1251				pinctrl-names = "default";
1252
1253				#address-cells = <1>;
1254				#size-cells = <0>;
1255
1256				status = "disabled";
1257			};
1258
1259			i2c21: i2c@894000 {
1260				compatible = "qcom,geni-i2c";
1261				reg = <0 0x00894000 0 0x4000>;
1262
1263				interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1264
1265				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1266				clock-names = "se";
1267
1268				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1269						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1270						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1271						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1272						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1273						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1274				interconnect-names = "qup-core",
1275						     "qup-config",
1276						     "qup-memory";
1277
1278				power-domains = <&rpmhpd RPMHPD_CX>;
1279				required-opps = <&rpmhpd_opp_low_svs>;
1280
1281				dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
1282				       <&gpi_dma2 1 5 QCOM_GPI_I2C>;
1283				dma-names = "tx",
1284					    "rx";
1285
1286				pinctrl-0 = <&qup_i2c21_data_clk>;
1287				pinctrl-names = "default";
1288
1289				#address-cells = <1>;
1290				#size-cells = <0>;
1291
1292				status = "disabled";
1293			};
1294
1295			spi21: spi@894000 {
1296				compatible = "qcom,geni-spi";
1297				reg = <0 0x00894000 0 0x4000>;
1298
1299				interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1300
1301				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1302				clock-names = "se";
1303
1304				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1305						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1306						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1307						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1308						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1309						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1310				interconnect-names = "qup-core",
1311						     "qup-config",
1312						     "qup-memory";
1313
1314				power-domains = <&rpmhpd RPMHPD_CX>;
1315				operating-points-v2 = <&qup_opp_table_100mhz>;
1316
1317				dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>,
1318				       <&gpi_dma2 1 5 QCOM_GPI_SPI>;
1319				dma-names = "tx",
1320					    "rx";
1321
1322				pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>;
1323				pinctrl-names = "default";
1324
1325				#address-cells = <1>;
1326				#size-cells = <0>;
1327
1328				status = "disabled";
1329			};
1330
1331			uart21: serial@894000 {
1332				compatible = "qcom,geni-uart";
1333				reg = <0 0x00894000 0 0x4000>;
1334
1335				interrupts = <GIC_SPI 813 IRQ_TYPE_LEVEL_HIGH>;
1336
1337				clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
1338				clock-names = "se";
1339
1340				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1341						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1342						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1343						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
1344				interconnect-names = "qup-core",
1345						     "qup-config";
1346
1347				power-domains = <&rpmhpd RPMHPD_CX>;
1348				operating-points-v2 = <&qup_opp_table_100mhz>;
1349
1350				pinctrl-0 = <&qup_uart21_default>;
1351				pinctrl-names = "default";
1352
1353				status = "disabled";
1354			};
1355
1356			i2c22: i2c@898000 {
1357				compatible = "qcom,geni-i2c";
1358				reg = <0 0x00898000 0 0x4000>;
1359
1360				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1361
1362				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1363				clock-names = "se";
1364
1365				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1366						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1367						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1368						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1369						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1370						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1371				interconnect-names = "qup-core",
1372						     "qup-config",
1373						     "qup-memory";
1374
1375				power-domains = <&rpmhpd RPMHPD_CX>;
1376				required-opps = <&rpmhpd_opp_low_svs>;
1377
1378				dmas = <&gpi_dma2 0 6 QCOM_GPI_I2C>,
1379				       <&gpi_dma2 1 6 QCOM_GPI_I2C>;
1380				dma-names = "tx",
1381					    "rx";
1382
1383				pinctrl-0 = <&qup_i2c22_data_clk>;
1384				pinctrl-names = "default";
1385
1386				#address-cells = <1>;
1387				#size-cells = <0>;
1388
1389				status = "disabled";
1390			};
1391
1392			spi22: spi@898000 {
1393				compatible = "qcom,geni-spi";
1394				reg = <0 0x00898000 0 0x4000>;
1395
1396				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
1397
1398				clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
1399				clock-names = "se";
1400
1401				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1402						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1403						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1404						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1405						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1406						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1407				interconnect-names = "qup-core",
1408						     "qup-config",
1409						     "qup-memory";
1410
1411				power-domains = <&rpmhpd RPMHPD_CX>;
1412				operating-points-v2 = <&qup_opp_table_100mhz>;
1413
1414				dmas = <&gpi_dma2 0 6 QCOM_GPI_SPI>,
1415				       <&gpi_dma2 1 6 QCOM_GPI_SPI>;
1416				dma-names = "tx",
1417					    "rx";
1418
1419				pinctrl-0 = <&qup_spi22_data_clk>, <&qup_spi22_cs>;
1420				pinctrl-names = "default";
1421
1422				#address-cells = <1>;
1423				#size-cells = <0>;
1424
1425				status = "disabled";
1426			};
1427
1428			i2c23: i2c@89c000 {
1429				compatible = "qcom,geni-i2c";
1430				reg = <0 0x0089c000 0 0x4000>;
1431
1432				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1433
1434				clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1435				clock-names = "se";
1436
1437				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1438						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1439						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1440						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1441						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1442						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1443				interconnect-names = "qup-core",
1444						     "qup-config",
1445						     "qup-memory";
1446
1447				power-domains = <&rpmhpd RPMHPD_CX>;
1448				required-opps = <&rpmhpd_opp_low_svs>;
1449
1450				dmas = <&gpi_dma2 0 7 QCOM_GPI_I2C>,
1451				       <&gpi_dma2 1 7 QCOM_GPI_I2C>;
1452				dma-names = "tx",
1453					    "rx";
1454
1455				pinctrl-0 = <&qup_i2c23_data_clk>;
1456				pinctrl-names = "default";
1457
1458				#address-cells = <1>;
1459				#size-cells = <0>;
1460
1461				status = "disabled";
1462			};
1463
1464			spi23: spi@89c000 {
1465				compatible = "qcom,geni-spi";
1466				reg = <0 0x0089c000 0 0x4000>;
1467
1468				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
1469
1470				clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>;
1471				clock-names = "se";
1472
1473				interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS
1474						 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>,
1475						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1476						 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>,
1477						<&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS
1478						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1479				interconnect-names = "qup-core",
1480						     "qup-config",
1481						     "qup-memory";
1482
1483				power-domains = <&rpmhpd RPMHPD_CX>;
1484				operating-points-v2 = <&qup_opp_table_100mhz>;
1485
1486				dmas = <&gpi_dma2 0 7 QCOM_GPI_SPI>,
1487				       <&gpi_dma2 1 7 QCOM_GPI_SPI>;
1488				dma-names = "tx",
1489					    "rx";
1490
1491				pinctrl-0 = <&qup_spi23_data_clk>, <&qup_spi23_cs>;
1492				pinctrl-names = "default";
1493
1494				#address-cells = <1>;
1495				#size-cells = <0>;
1496
1497				status = "disabled";
1498			};
1499		};
1500
1501		gpi_dma1: dma-controller@a00000 {
1502			compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
1503			reg = <0 0x00a00000 0 0x60000>;
1504
1505			interrupts = <GIC_SPI 776 IRQ_TYPE_LEVEL_HIGH>,
1506				     <GIC_SPI 777 IRQ_TYPE_LEVEL_HIGH>,
1507				     <GIC_SPI 778 IRQ_TYPE_LEVEL_HIGH>,
1508				     <GIC_SPI 779 IRQ_TYPE_LEVEL_HIGH>,
1509				     <GIC_SPI 780 IRQ_TYPE_LEVEL_HIGH>,
1510				     <GIC_SPI 781 IRQ_TYPE_LEVEL_HIGH>,
1511				     <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>,
1512				     <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>,
1513				     <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
1514				     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>,
1515				     <GIC_SPI 786 IRQ_TYPE_LEVEL_HIGH>,
1516				     <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>;
1517
1518			dma-channels = <12>;
1519			dma-channel-mask = <0x3e>;
1520			#dma-cells = <3>;
1521
1522			iommus = <&apps_smmu 0x136 0x0>;
1523
1524			status = "disabled";
1525		};
1526
1527		qupv3_1: geniqup@ac0000 {
1528			compatible = "qcom,geni-se-qup";
1529			reg = <0 0x00ac0000 0 0x2000>;
1530
1531			clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1532				 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1533			clock-names = "m-ahb",
1534				      "s-ahb";
1535
1536			iommus = <&apps_smmu 0x123 0x0>;
1537
1538			#address-cells = <2>;
1539			#size-cells = <2>;
1540			ranges;
1541
1542			status = "disabled";
1543
1544			i2c8: i2c@a80000 {
1545				compatible = "qcom,geni-i2c";
1546				reg = <0 0x00a80000 0 0x4000>;
1547
1548				interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1549
1550				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1551				clock-names = "se";
1552
1553				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1554						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1555						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1556						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1557						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1558						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1559				interconnect-names = "qup-core",
1560						     "qup-config",
1561						     "qup-memory";
1562
1563				power-domains = <&rpmhpd RPMHPD_CX>;
1564				required-opps = <&rpmhpd_opp_low_svs>;
1565
1566				dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
1567				       <&gpi_dma1 1 0 QCOM_GPI_I2C>;
1568				dma-names = "tx",
1569					    "rx";
1570
1571				pinctrl-0 = <&qup_i2c8_data_clk>;
1572				pinctrl-names = "default";
1573
1574				#address-cells = <1>;
1575				#size-cells = <0>;
1576
1577				status = "disabled";
1578			};
1579
1580			spi8: spi@a80000 {
1581				compatible = "qcom,geni-spi";
1582				reg = <0 0x00a80000 0 0x4000>;
1583
1584				interrupts = <GIC_SPI 800 IRQ_TYPE_LEVEL_HIGH>;
1585
1586				clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1587				clock-names = "se";
1588
1589				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1590						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1591						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1592						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1593						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1594						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1595				interconnect-names = "qup-core",
1596						     "qup-config",
1597						     "qup-memory";
1598
1599				power-domains = <&rpmhpd RPMHPD_CX>;
1600				operating-points-v2 = <&qup_opp_table_120mhz>;
1601
1602				dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>,
1603				       <&gpi_dma1 1 0 QCOM_GPI_SPI>;
1604				dma-names = "tx",
1605					    "rx";
1606
1607				pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
1608				pinctrl-names = "default";
1609
1610				#address-cells = <1>;
1611				#size-cells = <0>;
1612
1613				status = "disabled";
1614			};
1615
1616			i2c9: i2c@a84000 {
1617				compatible = "qcom,geni-i2c";
1618				reg = <0 0x00a84000 0 0x4000>;
1619
1620				interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1621
1622				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1623				clock-names = "se";
1624
1625				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1626						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1627						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1628						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1629						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1630						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1631				interconnect-names = "qup-core",
1632						     "qup-config",
1633						     "qup-memory";
1634
1635				power-domains = <&rpmhpd RPMHPD_CX>;
1636				required-opps = <&rpmhpd_opp_low_svs>;
1637
1638				dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
1639				       <&gpi_dma1 1 1 QCOM_GPI_I2C>;
1640				dma-names = "tx",
1641					    "rx";
1642
1643				pinctrl-0 = <&qup_i2c9_data_clk>;
1644				pinctrl-names = "default";
1645
1646				#address-cells = <1>;
1647				#size-cells = <0>;
1648
1649				status = "disabled";
1650			};
1651
1652			spi9: spi@a84000 {
1653				compatible = "qcom,geni-spi";
1654				reg = <0 0x00a84000 0 0x4000>;
1655
1656				interrupts = <GIC_SPI 801 IRQ_TYPE_LEVEL_HIGH>;
1657
1658				clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1659				clock-names = "se";
1660
1661				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1662						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1663						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1664						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1665						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1666						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1667				interconnect-names = "qup-core",
1668						     "qup-config",
1669						     "qup-memory";
1670
1671				power-domains = <&rpmhpd RPMHPD_CX>;
1672				operating-points-v2 = <&qup_opp_table_120mhz>;
1673
1674				dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>,
1675				       <&gpi_dma1 1 1 QCOM_GPI_SPI>;
1676				dma-names = "tx",
1677					    "rx";
1678
1679				pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
1680				pinctrl-names = "default";
1681
1682				#address-cells = <1>;
1683				#size-cells = <0>;
1684
1685				status = "disabled";
1686			};
1687
1688			i2c10: i2c@a88000 {
1689				compatible = "qcom,geni-i2c";
1690				reg = <0 0x00a88000 0 0x4000>;
1691
1692				interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1693
1694				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1695				clock-names = "se";
1696
1697				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1698						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1699						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1700						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1701						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1702						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1703				interconnect-names = "qup-core",
1704						     "qup-config",
1705						     "qup-memory";
1706
1707				power-domains = <&rpmhpd RPMHPD_CX>;
1708				required-opps = <&rpmhpd_opp_low_svs>;
1709
1710				dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
1711				       <&gpi_dma1 1 2 QCOM_GPI_I2C>;
1712				dma-names = "tx",
1713					    "rx";
1714
1715				pinctrl-0 = <&qup_i2c10_data_clk>;
1716				pinctrl-names = "default";
1717
1718				#address-cells = <1>;
1719				#size-cells = <0>;
1720
1721				status = "disabled";
1722			};
1723
1724			spi10: spi@a88000 {
1725				compatible = "qcom,geni-spi";
1726				reg = <0 0x00a88000 0 0x4000>;
1727
1728				interrupts = <GIC_SPI 802 IRQ_TYPE_LEVEL_HIGH>;
1729
1730				clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1731				clock-names = "se";
1732
1733				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1734						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1735						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1736						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1737						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1738						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1739				interconnect-names = "qup-core",
1740						     "qup-config",
1741						     "qup-memory";
1742
1743				power-domains = <&rpmhpd RPMHPD_CX>;
1744				operating-points-v2 = <&qup_opp_table_100mhz>;
1745
1746				dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>,
1747				       <&gpi_dma1 1 2 QCOM_GPI_SPI>;
1748				dma-names = "tx",
1749					    "rx";
1750
1751				pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
1752				pinctrl-names = "default";
1753
1754				#address-cells = <1>;
1755				#size-cells = <0>;
1756
1757				status = "disabled";
1758			};
1759
1760			i2c11: i2c@a8c000 {
1761				compatible = "qcom,geni-i2c";
1762				reg = <0 0x00a8c000 0 0x4000>;
1763
1764				interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1765
1766				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1767				clock-names = "se";
1768
1769				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1770						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1771						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1772						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1773						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1774						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1775				interconnect-names = "qup-core",
1776						     "qup-config",
1777						     "qup-memory";
1778
1779				power-domains = <&rpmhpd RPMHPD_CX>;
1780				required-opps = <&rpmhpd_opp_low_svs>;
1781
1782				dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
1783				       <&gpi_dma1 1 3 QCOM_GPI_I2C>;
1784				dma-names = "tx",
1785					    "rx";
1786
1787				pinctrl-0 = <&qup_i2c11_data_clk>;
1788				pinctrl-names = "default";
1789
1790				#address-cells = <1>;
1791				#size-cells = <0>;
1792
1793				status = "disabled";
1794			};
1795
1796			spi11: spi@a8c000 {
1797				compatible = "qcom,geni-spi";
1798				reg = <0 0x00a8c000 0 0x4000>;
1799
1800				interrupts = <GIC_SPI 803 IRQ_TYPE_LEVEL_HIGH>;
1801
1802				clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1803				clock-names = "se";
1804
1805				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1806						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1807						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1808						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1809						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1810						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1811				interconnect-names = "qup-core",
1812						     "qup-config",
1813						     "qup-memory";
1814
1815				power-domains = <&rpmhpd RPMHPD_CX>;
1816				operating-points-v2 = <&qup_opp_table_100mhz>;
1817
1818				dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>,
1819				       <&gpi_dma1 1 3 QCOM_GPI_SPI>;
1820				dma-names = "tx",
1821					    "rx";
1822
1823				pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
1824				pinctrl-names = "default";
1825
1826				#address-cells = <1>;
1827				#size-cells = <0>;
1828
1829				status = "disabled";
1830			};
1831
1832			i2c12: i2c@a90000 {
1833				compatible = "qcom,geni-i2c";
1834				reg = <0 0x00a90000 0 0x4000>;
1835
1836				interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1837
1838				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1839				clock-names = "se";
1840
1841				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1842						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1843						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1844						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1845						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1846						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1847				interconnect-names = "qup-core",
1848						     "qup-config",
1849						     "qup-memory";
1850
1851				power-domains = <&rpmhpd RPMHPD_CX>;
1852				required-opps = <&rpmhpd_opp_low_svs>;
1853
1854				dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
1855				       <&gpi_dma1 1 4 QCOM_GPI_I2C>;
1856				dma-names = "tx",
1857					    "rx";
1858
1859				pinctrl-0 = <&qup_i2c12_data_clk>;
1860				pinctrl-names = "default";
1861
1862				#address-cells = <1>;
1863				#size-cells = <0>;
1864
1865				status = "disabled";
1866			};
1867
1868			spi12: spi@a90000 {
1869				compatible = "qcom,geni-spi";
1870				reg = <0 0x00a90000 0 0x4000>;
1871
1872				interrupts = <GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>;
1873
1874				clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1875				clock-names = "se";
1876
1877				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1878						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1879						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1880						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1881						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1882						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1883				interconnect-names = "qup-core",
1884						     "qup-config",
1885						     "qup-memory";
1886
1887				power-domains = <&rpmhpd RPMHPD_CX>;
1888				operating-points-v2 = <&qup_opp_table_100mhz>;
1889
1890				dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>,
1891				       <&gpi_dma1 1 4 QCOM_GPI_SPI>;
1892				dma-names = "tx",
1893					    "rx";
1894
1895				pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
1896				pinctrl-names = "default";
1897
1898				#address-cells = <1>;
1899				#size-cells = <0>;
1900
1901				status = "disabled";
1902			};
1903
1904			i2c13: i2c@a94000 {
1905				compatible = "qcom,geni-i2c";
1906				reg = <0 0x00a94000 0 0x4000>;
1907
1908				interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1909
1910				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1911				clock-names = "se";
1912
1913				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1914						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1915						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1916						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1917						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1918						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1919				interconnect-names = "qup-core",
1920						     "qup-config",
1921						     "qup-memory";
1922
1923				power-domains = <&rpmhpd RPMHPD_CX>;
1924				required-opps = <&rpmhpd_opp_low_svs>;
1925
1926				dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
1927				       <&gpi_dma1 1 5 QCOM_GPI_I2C>;
1928				dma-names = "tx",
1929					    "rx";
1930
1931				pinctrl-0 = <&qup_i2c13_data_clk>;
1932				pinctrl-names = "default";
1933
1934				#address-cells = <1>;
1935				#size-cells = <0>;
1936
1937				status = "disabled";
1938			};
1939
1940			spi13: spi@a94000 {
1941				compatible = "qcom,geni-spi";
1942				reg = <0 0x00a94000 0 0x4000>;
1943
1944				interrupts = <GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>;
1945
1946				clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1947				clock-names = "se";
1948
1949				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1950						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1951						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1952						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1953						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1954						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1955				interconnect-names = "qup-core",
1956						     "qup-config",
1957						     "qup-memory";
1958
1959				power-domains = <&rpmhpd RPMHPD_CX>;
1960				operating-points-v2 = <&qup_opp_table_100mhz>;
1961
1962				dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>,
1963				       <&gpi_dma1 1 5 QCOM_GPI_SPI>;
1964				dma-names = "tx",
1965					    "rx";
1966
1967				pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
1968				pinctrl-names = "default";
1969
1970				#address-cells = <1>;
1971				#size-cells = <0>;
1972
1973				status = "disabled";
1974			};
1975
1976			i2c14: i2c@a98000 {
1977				compatible = "qcom,geni-i2c";
1978				reg = <0 0x00a98000 0 0x4000>;
1979
1980				interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
1981
1982				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1983				clock-names = "se";
1984
1985				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
1986						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
1987						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
1988						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
1989						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
1990						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
1991				interconnect-names = "qup-core",
1992						     "qup-config",
1993						     "qup-memory";
1994
1995				power-domains = <&rpmhpd RPMHPD_CX>;
1996				required-opps = <&rpmhpd_opp_low_svs>;
1997
1998				dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>,
1999				       <&gpi_dma1 1 6 QCOM_GPI_I2C>;
2000				dma-names = "tx",
2001					    "rx";
2002
2003				pinctrl-0 = <&qup_i2c14_data_clk>;
2004				pinctrl-names = "default";
2005
2006				#address-cells = <1>;
2007				#size-cells = <0>;
2008
2009				status = "disabled";
2010			};
2011
2012			spi14: spi@a98000 {
2013				compatible = "qcom,geni-spi";
2014				reg = <0 0x00a98000 0 0x4000>;
2015
2016				interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
2017
2018				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2019				clock-names = "se";
2020
2021				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
2022						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
2023						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2024						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
2025						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
2026						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2027				interconnect-names = "qup-core",
2028						     "qup-config",
2029						     "qup-memory";
2030
2031				power-domains = <&rpmhpd RPMHPD_CX>;
2032				operating-points-v2 = <&qup_opp_table_100mhz>;
2033
2034				dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>,
2035				       <&gpi_dma1 1 6 QCOM_GPI_SPI>;
2036				dma-names = "tx",
2037					    "rx";
2038
2039				pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
2040				pinctrl-names = "default";
2041
2042				#address-cells = <1>;
2043				#size-cells = <0>;
2044
2045				status = "disabled";
2046			};
2047
2048			uart14: serial@a98000 {
2049				compatible = "qcom,geni-uart";
2050				reg = <0 0x00a98000 0 0x4000>;
2051
2052				interrupts = <GIC_SPI 806 IRQ_TYPE_LEVEL_HIGH>;
2053
2054				clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
2055				clock-names = "se";
2056
2057				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
2058						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
2059						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2060						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
2061				interconnect-names = "qup-core",
2062						     "qup-config";
2063
2064				power-domains = <&rpmhpd RPMHPD_CX>;
2065				operating-points-v2 = <&qup_opp_table_100mhz>;
2066
2067				pinctrl-0 = <&qup_uart14_default>;
2068				pinctrl-names = "default";
2069
2070				status = "disabled";
2071			};
2072
2073			i2c15: i2c@a9c000 {
2074				compatible = "qcom,geni-i2c";
2075				reg = <0 0x00a9c000 0 0x4000>;
2076
2077				interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
2078
2079				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2080				clock-names = "se";
2081
2082				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
2083						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
2084						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2085						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
2086						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
2087						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2088				interconnect-names = "qup-core",
2089						     "qup-config",
2090						     "qup-memory";
2091
2092				power-domains = <&rpmhpd RPMHPD_CX>;
2093				required-opps = <&rpmhpd_opp_low_svs>;
2094
2095				dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>,
2096				       <&gpi_dma1 1 7 QCOM_GPI_I2C>;
2097				dma-names = "tx",
2098					    "rx";
2099
2100				pinctrl-0 = <&qup_i2c15_data_clk>;
2101				pinctrl-names = "default";
2102
2103				#address-cells = <1>;
2104				#size-cells = <0>;
2105
2106				status = "disabled";
2107			};
2108
2109			spi15: spi@a9c000 {
2110				compatible = "qcom,geni-spi";
2111				reg = <0 0x00a9c000 0 0x4000>;
2112
2113				interrupts = <GIC_SPI 807 IRQ_TYPE_LEVEL_HIGH>;
2114
2115				clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
2116				clock-names = "se";
2117
2118				interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS
2119						 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
2120						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2121						 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>,
2122						<&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS
2123						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2124				interconnect-names = "qup-core",
2125						     "qup-config",
2126						     "qup-memory";
2127
2128				power-domains = <&rpmhpd RPMHPD_CX>;
2129				operating-points-v2 = <&qup_opp_table_100mhz>;
2130
2131				dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>,
2132				       <&gpi_dma1 1 7 QCOM_GPI_SPI>;
2133				dma-names = "tx",
2134					    "rx";
2135
2136				pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
2137				pinctrl-names = "default";
2138
2139				#address-cells = <1>;
2140				#size-cells = <0>;
2141
2142				status = "disabled";
2143			};
2144		};
2145
2146		gpi_dma0: dma-controller@b00000  {
2147			compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
2148			reg = <0 0x00b00000 0 0x60000>;
2149
2150			interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
2151				     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>,
2152				     <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>,
2153				     <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
2154				     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>,
2155				     <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>,
2156				     <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
2157				     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>,
2158				     <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>,
2159				     <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
2160				     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>,
2161				     <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>;
2162
2163			dma-channels = <12>;
2164			dma-channel-mask = <0x3e>;
2165			#dma-cells = <3>;
2166
2167			iommus = <&apps_smmu 0x456 0x0>;
2168
2169			status = "disabled";
2170		};
2171
2172		qupv3_0: geniqup@bc0000 {
2173			compatible = "qcom,geni-se-qup";
2174			reg = <0 0x00bc0000 0 0x2000>;
2175
2176			clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
2177				 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
2178			clock-names = "m-ahb",
2179				      "s-ahb";
2180
2181			iommus = <&apps_smmu 0x443 0x0>;
2182			#address-cells = <2>;
2183			#size-cells = <2>;
2184			ranges;
2185
2186			status = "disabled";
2187
2188			i2c0: i2c@b80000 {
2189				compatible = "qcom,geni-i2c";
2190				reg = <0 0x00b80000 0 0x4000>;
2191
2192				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2193
2194				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
2195				clock-names = "se";
2196
2197				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2198						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2199						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2200						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2201						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2202						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2203				interconnect-names = "qup-core",
2204						     "qup-config",
2205						     "qup-memory";
2206
2207				power-domains = <&rpmhpd RPMHPD_CX>;
2208				required-opps = <&rpmhpd_opp_low_svs>;
2209
2210				dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
2211				       <&gpi_dma0 1 0 QCOM_GPI_I2C>;
2212				dma-names = "tx",
2213					    "rx";
2214
2215				pinctrl-0 = <&qup_i2c0_data_clk>;
2216				pinctrl-names = "default";
2217
2218				#address-cells = <1>;
2219				#size-cells = <0>;
2220
2221				status = "disabled";
2222			};
2223
2224			spi0: spi@b80000 {
2225				compatible = "qcom,geni-spi";
2226				reg = <0 0x00b80000 0 0x4000>;
2227
2228				interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
2229
2230				clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
2231				clock-names = "se";
2232
2233				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2234						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2235						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2236						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2237						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2238						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2239				interconnect-names = "qup-core",
2240						     "qup-config",
2241						     "qup-memory";
2242
2243				power-domains = <&rpmhpd RPMHPD_CX>;
2244				operating-points-v2 = <&qup_opp_table_120mhz>;
2245
2246				dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
2247				       <&gpi_dma0 1 0 QCOM_GPI_SPI>;
2248				dma-names = "tx",
2249					    "rx";
2250
2251				pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
2252				pinctrl-names = "default";
2253
2254				#address-cells = <1>;
2255				#size-cells = <0>;
2256
2257				status = "disabled";
2258			};
2259
2260			i2c1: i2c@b84000 {
2261				compatible = "qcom,geni-i2c";
2262				reg = <0 0x00b84000 0 0x4000>;
2263
2264				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2265
2266				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2267				clock-names = "se";
2268
2269				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2270						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2271						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2272						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2273						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2274						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2275				interconnect-names = "qup-core",
2276						     "qup-config",
2277						     "qup-memory";
2278
2279				power-domains = <&rpmhpd RPMHPD_CX>;
2280				required-opps = <&rpmhpd_opp_low_svs>;
2281
2282				dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
2283				       <&gpi_dma0 1 1 QCOM_GPI_I2C>;
2284				dma-names = "tx",
2285					    "rx";
2286
2287				pinctrl-0 = <&qup_i2c1_data_clk>;
2288				pinctrl-names = "default";
2289
2290				#address-cells = <1>;
2291				#size-cells = <0>;
2292
2293				status = "disabled";
2294			};
2295
2296			spi1: spi@b84000 {
2297				compatible = "qcom,geni-spi";
2298				reg = <0 0x00b84000 0 0x4000>;
2299
2300				interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
2301
2302				clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
2303				clock-names = "se";
2304
2305				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2306						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2307						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2308						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2309						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2310						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2311				interconnect-names = "qup-core",
2312						     "qup-config",
2313						     "qup-memory";
2314
2315				power-domains = <&rpmhpd RPMHPD_CX>;
2316				operating-points-v2 = <&qup_opp_table_120mhz>;
2317
2318				dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>,
2319				       <&gpi_dma0 1 1 QCOM_GPI_SPI>;
2320				dma-names = "tx",
2321					    "rx";
2322
2323				pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
2324				pinctrl-names = "default";
2325
2326				#address-cells = <1>;
2327				#size-cells = <0>;
2328
2329				status = "disabled";
2330			};
2331
2332			i2c2: i2c@b88000 {
2333				compatible = "qcom,geni-i2c";
2334				reg = <0 0x00b88000 0 0x4000>;
2335
2336				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2337
2338				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2339				clock-names = "se";
2340
2341				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2342						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2343						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2344						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2345						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2346						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2347				interconnect-names = "qup-core",
2348						     "qup-config",
2349						     "qup-memory";
2350
2351				power-domains = <&rpmhpd RPMHPD_CX>;
2352				required-opps = <&rpmhpd_opp_low_svs>;
2353
2354				dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
2355				       <&gpi_dma0 1 2 QCOM_GPI_I2C>;
2356				dma-names = "tx",
2357					    "rx";
2358
2359				pinctrl-0 = <&qup_i2c2_data_clk>;
2360				pinctrl-names = "default";
2361
2362				#address-cells = <1>;
2363				#size-cells = <0>;
2364
2365				status = "disabled";
2366			};
2367
2368			uart2: serial@b88000 {
2369				compatible = "qcom,geni-uart";
2370				reg = <0 0x00b88000 0 0x4000>;
2371
2372				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2373
2374				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2375				clock-names = "se";
2376
2377				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2378						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2379						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2380						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>;
2381				interconnect-names = "qup-core",
2382						     "qup-config";
2383
2384				power-domains = <&rpmhpd RPMHPD_CX>;
2385				operating-points-v2 = <&qup_opp_table_100mhz>;
2386
2387				pinctrl-0 = <&qup_uart2_default>;
2388				pinctrl-names = "default";
2389
2390				status = "disabled";
2391			};
2392
2393			spi2: spi@b88000 {
2394				compatible = "qcom,geni-spi";
2395				reg = <0 0x00b88000 0 0x4000>;
2396
2397				interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>;
2398
2399				clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
2400				clock-names = "se";
2401
2402				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2403						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2404						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2405						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2406						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2407						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2408				interconnect-names = "qup-core",
2409						     "qup-config",
2410						     "qup-memory";
2411
2412				power-domains = <&rpmhpd RPMHPD_CX>;
2413				operating-points-v2 = <&qup_opp_table_100mhz>;
2414
2415				dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
2416				       <&gpi_dma0 1 2 QCOM_GPI_SPI>;
2417				dma-names = "tx",
2418					    "rx";
2419
2420				pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
2421				pinctrl-names = "default";
2422
2423				#address-cells = <1>;
2424				#size-cells = <0>;
2425
2426				status = "disabled";
2427			};
2428
2429			i2c3: i2c@b8c000 {
2430				compatible = "qcom,geni-i2c";
2431				reg = <0 0x00b8c000 0 0x4000>;
2432
2433				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2434
2435				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2436				clock-names = "se";
2437
2438				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2439						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2440						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2441						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2442						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2443						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2444				interconnect-names = "qup-core",
2445						     "qup-config",
2446						     "qup-memory";
2447
2448				power-domains = <&rpmhpd RPMHPD_CX>;
2449				required-opps = <&rpmhpd_opp_low_svs>;
2450
2451				dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
2452				       <&gpi_dma0 1 3 QCOM_GPI_I2C>;
2453				dma-names = "tx",
2454					    "rx";
2455
2456				pinctrl-0 = <&qup_i2c3_data_clk>;
2457				pinctrl-names = "default";
2458
2459				#address-cells = <1>;
2460				#size-cells = <0>;
2461
2462				status = "disabled";
2463			};
2464
2465			spi3: spi@b8c000 {
2466				compatible = "qcom,geni-spi";
2467				reg = <0 0x00b8c000 0 0x4000>;
2468
2469				interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
2470
2471				clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
2472				clock-names = "se";
2473
2474				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2475						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2476						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2477						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2478						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2479						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2480				interconnect-names = "qup-core",
2481						     "qup-config",
2482						     "qup-memory";
2483
2484				power-domains = <&rpmhpd RPMHPD_CX>;
2485				operating-points-v2 = <&qup_opp_table_100mhz>;
2486
2487				dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>,
2488				       <&gpi_dma0 1 3 QCOM_GPI_SPI>;
2489				dma-names = "tx",
2490					    "rx";
2491
2492				pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
2493				pinctrl-names = "default";
2494
2495				#address-cells = <1>;
2496				#size-cells = <0>;
2497
2498				status = "disabled";
2499			};
2500
2501			i2c4: i2c@b90000 {
2502				compatible = "qcom,geni-i2c";
2503				reg = <0 0x00b90000 0 0x4000>;
2504
2505				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2506
2507				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2508				clock-names = "se";
2509
2510				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2511						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2512						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2513						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2514						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2515						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2516				interconnect-names = "qup-core",
2517						     "qup-config",
2518						     "qup-memory";
2519
2520				power-domains = <&rpmhpd RPMHPD_CX>;
2521				required-opps = <&rpmhpd_opp_low_svs>;
2522
2523				dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
2524				       <&gpi_dma0 1 4 QCOM_GPI_I2C>;
2525				dma-names = "tx",
2526					    "rx";
2527
2528				pinctrl-0 = <&qup_i2c4_data_clk>;
2529				pinctrl-names = "default";
2530
2531				#address-cells = <1>;
2532				#size-cells = <0>;
2533
2534				status = "disabled";
2535			};
2536
2537			spi4: spi@b90000 {
2538				compatible = "qcom,geni-spi";
2539				reg = <0 0x00b90000 0 0x4000>;
2540
2541				interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
2542
2543				clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
2544				clock-names = "se";
2545
2546				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2547						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2548						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2549						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2550						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2551						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2552				interconnect-names = "qup-core",
2553						     "qup-config",
2554						     "qup-memory";
2555
2556				power-domains = <&rpmhpd RPMHPD_CX>;
2557				operating-points-v2 = <&qup_opp_table_100mhz>;
2558
2559				dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>,
2560				       <&gpi_dma0 1 4 QCOM_GPI_SPI>;
2561				dma-names = "tx",
2562					    "rx";
2563
2564				pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
2565				pinctrl-names = "default";
2566
2567				#address-cells = <1>;
2568				#size-cells = <0>;
2569
2570				status = "disabled";
2571			};
2572
2573			i2c5: i2c@b94000 {
2574				compatible = "qcom,geni-i2c";
2575				reg = <0 0x00b94000 0 0x4000>;
2576
2577				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2578
2579				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2580				clock-names = "se";
2581
2582				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2583						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2584						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2585						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2586						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2587						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2588				interconnect-names = "qup-core",
2589						     "qup-config",
2590						     "qup-memory";
2591
2592				power-domains = <&rpmhpd RPMHPD_CX>;
2593				required-opps = <&rpmhpd_opp_low_svs>;
2594
2595				dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
2596				       <&gpi_dma0 1 5 QCOM_GPI_I2C>;
2597				dma-names = "tx",
2598					    "rx";
2599
2600				pinctrl-0 = <&qup_i2c5_data_clk>;
2601				pinctrl-names = "default";
2602
2603				#address-cells = <1>;
2604				#size-cells = <0>;
2605
2606				status = "disabled";
2607			};
2608
2609			spi5: spi@b94000 {
2610				compatible = "qcom,geni-spi";
2611				reg = <0 0x00b94000 0 0x4000>;
2612
2613				interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>;
2614
2615				clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
2616				clock-names = "se";
2617
2618				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2619						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2620						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2621						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2622						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2623						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2624				interconnect-names = "qup-core",
2625						     "qup-config",
2626						     "qup-memory";
2627
2628				power-domains = <&rpmhpd RPMHPD_CX>;
2629				operating-points-v2 = <&qup_opp_table_100mhz>;
2630
2631				dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
2632				       <&gpi_dma0 1 5 QCOM_GPI_SPI>;
2633				dma-names = "tx",
2634					    "rx";
2635
2636				pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
2637				pinctrl-names = "default";
2638
2639				#address-cells = <1>;
2640				#size-cells = <0>;
2641
2642				status = "disabled";
2643			};
2644
2645			i2c6: i2c@b98000 {
2646				compatible = "qcom,geni-i2c";
2647				reg = <0 0x00b98000 0 0x4000>;
2648
2649				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2650
2651				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2652				clock-names = "se";
2653
2654				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2655						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2656						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2657						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2658						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2659						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2660				interconnect-names = "qup-core",
2661						     "qup-config",
2662						     "qup-memory";
2663
2664				power-domains = <&rpmhpd RPMHPD_CX>;
2665				required-opps = <&rpmhpd_opp_low_svs>;
2666
2667				dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
2668				       <&gpi_dma0 1 6 QCOM_GPI_I2C>;
2669				dma-names = "tx",
2670					    "rx";
2671
2672				pinctrl-0 = <&qup_i2c6_data_clk>;
2673				pinctrl-names = "default";
2674
2675				#address-cells = <1>;
2676				#size-cells = <0>;
2677
2678				status = "disabled";
2679			};
2680
2681			spi6: spi@b98000 {
2682				compatible = "qcom,geni-spi";
2683				reg = <0 0x00b98000 0 0x4000>;
2684
2685				interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>;
2686
2687				clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
2688				clock-names = "se";
2689
2690				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2691						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2692						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2693						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2694						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2695						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2696				interconnect-names = "qup-core",
2697						     "qup-config",
2698						     "qup-memory";
2699
2700				power-domains = <&rpmhpd RPMHPD_CX>;
2701				operating-points-v2 = <&qup_opp_table_100mhz>;
2702
2703				dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
2704				       <&gpi_dma0 1 6 QCOM_GPI_SPI>;
2705				dma-names = "tx",
2706					    "rx";
2707
2708				pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
2709				pinctrl-names = "default";
2710
2711				#address-cells = <1>;
2712				#size-cells = <0>;
2713
2714				status = "disabled";
2715			};
2716
2717			i2c7: i2c@b9c000 {
2718				compatible = "qcom,geni-i2c";
2719				reg = <0 0x00b9c000 0 0x4000>;
2720
2721				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2722
2723				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2724				clock-names = "se";
2725
2726				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2727						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2728						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2729						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2730						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2731						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2732				interconnect-names = "qup-core",
2733						     "qup-config",
2734						     "qup-memory";
2735
2736				power-domains = <&rpmhpd RPMHPD_CX>;
2737				required-opps = <&rpmhpd_opp_low_svs>;
2738
2739				dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
2740				       <&gpi_dma0 1 7 QCOM_GPI_I2C>;
2741				dma-names = "tx",
2742					    "rx";
2743
2744				pinctrl-0 = <&qup_i2c7_data_clk>;
2745				pinctrl-names = "default";
2746
2747				#address-cells = <1>;
2748				#size-cells = <0>;
2749
2750				status = "disabled";
2751			};
2752
2753			spi7: spi@b9c000 {
2754				compatible = "qcom,geni-spi";
2755				reg = <0 0x00b9c000 0 0x4000>;
2756
2757				interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>;
2758
2759				clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
2760				clock-names = "se";
2761
2762				interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS
2763						 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>,
2764						<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
2765						 &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ACTIVE_ONLY>,
2766						<&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS
2767						 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
2768				interconnect-names = "qup-core",
2769						     "qup-config",
2770						     "qup-memory";
2771
2772				power-domains = <&rpmhpd RPMHPD_CX>;
2773				operating-points-v2 = <&qup_opp_table_100mhz>;
2774
2775				dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>,
2776				       <&gpi_dma0 1 7 QCOM_GPI_SPI>;
2777				dma-names = "tx",
2778					    "rx";
2779
2780				pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
2781				pinctrl-names = "default";
2782
2783				#address-cells = <1>;
2784				#size-cells = <0>;
2785
2786				status = "disabled";
2787			};
2788		};
2789
2790		tsens0: thermal-sensor@c271000 {
2791			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2792			reg = <0 0x0c271000 0 0x1000>,
2793			      <0 0x0c222000 0 0x1000>;
2794
2795			interrupts-extended = <&pdc 26 IRQ_TYPE_LEVEL_HIGH>,
2796					      <&intc GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>;
2797			interrupt-names = "uplow",
2798					  "critical";
2799
2800			#qcom,sensors = <16>;
2801
2802			#thermal-sensor-cells = <1>;
2803		};
2804
2805		tsens1: thermal-sensor@c272000 {
2806			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2807			reg = <0 0x0c272000 0 0x1000>,
2808			      <0 0x0c223000 0 0x1000>;
2809
2810			interrupts-extended = <&pdc 27 IRQ_TYPE_LEVEL_HIGH>,
2811					      <&intc GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>;
2812			interrupt-names = "uplow",
2813					  "critical";
2814
2815			#qcom,sensors = <16>;
2816
2817			#thermal-sensor-cells = <1>;
2818		};
2819
2820		tsens2: thermal-sensor@c273000 {
2821			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2822			reg = <0 0x0c273000 0 0x1000>,
2823			      <0 0x0c224000 0 0x1000>;
2824
2825			interrupts-extended = <&pdc 28 IRQ_TYPE_LEVEL_HIGH>,
2826					      <&intc GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
2827			interrupt-names = "uplow",
2828					  "critical";
2829
2830			#qcom,sensors = <16>;
2831
2832			#thermal-sensor-cells = <1>;
2833		};
2834
2835		tsens3: thermal-sensor@c274000 {
2836			compatible = "qcom,x1e80100-tsens", "qcom,tsens-v2";
2837			reg = <0 0x0c274000 0 0x1000>,
2838			      <0 0x0c225000 0 0x1000>;
2839
2840			interrupts-extended = <&pdc 29 IRQ_TYPE_LEVEL_HIGH>,
2841					      <&intc GIC_SPI 770 IRQ_TYPE_LEVEL_HIGH>;
2842			interrupt-names = "uplow",
2843					  "critical";
2844
2845			#qcom,sensors = <16>;
2846
2847			#thermal-sensor-cells = <1>;
2848		};
2849
2850		usb_1_ss0_hsphy: phy@fd3000 {
2851			compatible = "qcom,x1e80100-snps-eusb2-phy",
2852				     "qcom,sm8550-snps-eusb2-phy";
2853			reg = <0 0x00fd3000 0 0x154>;
2854			#phy-cells = <0>;
2855
2856			clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2857			clock-names = "ref";
2858
2859			resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2860
2861			status = "disabled";
2862		};
2863
2864		usb_1_ss0_qmpphy: phy@fd5000 {
2865			compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2866			reg = <0 0x00fd5000 0 0x4000>;
2867
2868			clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2869				 <&rpmhcc RPMH_CXO_CLK>,
2870				 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
2871				 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2872			clock-names = "aux",
2873				      "ref",
2874				      "com_aux",
2875				      "usb3_pipe";
2876
2877			power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
2878
2879			resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2880				 <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
2881			reset-names = "phy",
2882				      "common";
2883
2884			#clock-cells = <1>;
2885			#phy-cells = <1>;
2886
2887			mode-switch;
2888			orientation-switch;
2889
2890			status = "disabled";
2891
2892			ports {
2893				#address-cells = <1>;
2894				#size-cells = <0>;
2895
2896				port@0 {
2897					reg = <0>;
2898
2899					usb_1_ss0_qmpphy_out: endpoint {
2900					};
2901				};
2902
2903				port@1 {
2904					reg = <1>;
2905
2906					usb_1_ss0_qmpphy_usb_ss_in: endpoint {
2907						remote-endpoint = <&usb_1_ss0_dwc3_ss>;
2908					};
2909				};
2910
2911				port@2 {
2912					reg = <2>;
2913
2914					usb_1_ss0_qmpphy_dp_in: endpoint {
2915						remote-endpoint = <&mdss_dp0_out>;
2916					};
2917				};
2918			};
2919		};
2920
2921		usb_1_ss1_hsphy: phy@fd9000 {
2922			compatible = "qcom,x1e80100-snps-eusb2-phy",
2923				     "qcom,sm8550-snps-eusb2-phy";
2924			reg = <0 0x00fd9000 0 0x154>;
2925			#phy-cells = <0>;
2926
2927			clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2928			clock-names = "ref";
2929
2930			resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
2931
2932			status = "disabled";
2933		};
2934
2935		usb_1_ss1_qmpphy: phy@fda000 {
2936			compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
2937			reg = <0 0x00fda000 0 0x4000>;
2938
2939			clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
2940				 <&tcsr TCSR_USB4_1_CLKREF_EN>,
2941				 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
2942				 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
2943			clock-names = "aux",
2944				      "ref",
2945				      "com_aux",
2946				      "usb3_pipe";
2947
2948			power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
2949
2950			resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
2951				 <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
2952			reset-names = "phy",
2953				      "common";
2954
2955			#clock-cells = <1>;
2956			#phy-cells = <1>;
2957
2958			mode-switch;
2959			orientation-switch;
2960
2961			status = "disabled";
2962
2963			ports {
2964				#address-cells = <1>;
2965				#size-cells = <0>;
2966
2967				port@0 {
2968					reg = <0>;
2969
2970					usb_1_ss1_qmpphy_out: endpoint {
2971					};
2972				};
2973
2974				port@1 {
2975					reg = <1>;
2976
2977					usb_1_ss1_qmpphy_usb_ss_in: endpoint {
2978						remote-endpoint = <&usb_1_ss1_dwc3_ss>;
2979					};
2980				};
2981
2982				port@2 {
2983					reg = <2>;
2984
2985					usb_1_ss1_qmpphy_dp_in: endpoint {
2986						remote-endpoint = <&mdss_dp1_out>;
2987					};
2988				};
2989			};
2990		};
2991
2992		usb_1_ss2_hsphy: phy@fde000 {
2993			compatible = "qcom,x1e80100-snps-eusb2-phy",
2994				     "qcom,sm8550-snps-eusb2-phy";
2995			reg = <0 0x00fde000 0 0x154>;
2996			#phy-cells = <0>;
2997
2998			clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
2999			clock-names = "ref";
3000
3001			resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
3002
3003			status = "disabled";
3004		};
3005
3006		usb_1_ss2_qmpphy: phy@fdf000 {
3007			compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
3008			reg = <0 0x00fdf000 0 0x4000>;
3009
3010			clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
3011				 <&tcsr TCSR_USB4_2_CLKREF_EN>,
3012				 <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
3013				 <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
3014			clock-names = "aux",
3015				      "ref",
3016				      "com_aux",
3017				      "usb3_pipe";
3018
3019			power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
3020
3021			resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
3022				 <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
3023			reset-names = "phy",
3024				      "common";
3025
3026			#clock-cells = <1>;
3027			#phy-cells = <1>;
3028
3029			mode-switch;
3030			orientation-switch;
3031
3032			status = "disabled";
3033
3034			ports {
3035				#address-cells = <1>;
3036				#size-cells = <0>;
3037
3038				port@0 {
3039					reg = <0>;
3040
3041					usb_1_ss2_qmpphy_out: endpoint {
3042					};
3043				};
3044
3045				port@1 {
3046					reg = <1>;
3047
3048					usb_1_ss2_qmpphy_usb_ss_in: endpoint {
3049						remote-endpoint = <&usb_1_ss2_dwc3_ss>;
3050					};
3051				};
3052
3053				port@2 {
3054					reg = <2>;
3055
3056					usb_1_ss2_qmpphy_dp_in: endpoint {
3057						remote-endpoint = <&mdss_dp2_out>;
3058					};
3059				};
3060			};
3061		};
3062
3063		cnoc_main: interconnect@1500000 {
3064			compatible = "qcom,x1e80100-cnoc-main";
3065			reg = <0 0x01500000 0 0x14400>;
3066
3067			qcom,bcm-voters = <&apps_bcm_voter>;
3068
3069			#interconnect-cells = <2>;
3070		};
3071
3072		config_noc: interconnect@1600000 {
3073			compatible = "qcom,x1e80100-cnoc-cfg";
3074			reg = <0 0x01600000 0 0x6600>;
3075
3076			qcom,bcm-voters = <&apps_bcm_voter>;
3077
3078			#interconnect-cells = <2>;
3079		};
3080
3081		system_noc: interconnect@1680000 {
3082			compatible = "qcom,x1e80100-system-noc";
3083			reg = <0 0x01680000 0 0x1c080>;
3084
3085			qcom,bcm-voters = <&apps_bcm_voter>;
3086
3087			#interconnect-cells = <2>;
3088		};
3089
3090		pcie_south_anoc: interconnect@16c0000 {
3091			compatible = "qcom,x1e80100-pcie-south-anoc";
3092			reg = <0 0x016c0000 0 0xd080>;
3093
3094			qcom,bcm-voters = <&apps_bcm_voter>;
3095
3096			#interconnect-cells = <2>;
3097		};
3098
3099		pcie_center_anoc: interconnect@16d0000 {
3100			compatible = "qcom,x1e80100-pcie-center-anoc";
3101			reg = <0 0x016d0000 0 0x7000>;
3102
3103			qcom,bcm-voters = <&apps_bcm_voter>;
3104
3105			#interconnect-cells = <2>;
3106		};
3107
3108		aggre1_noc: interconnect@16e0000 {
3109			compatible = "qcom,x1e80100-aggre1-noc";
3110			reg = <0 0x016e0000 0 0x14400>;
3111
3112			qcom,bcm-voters = <&apps_bcm_voter>;
3113
3114			#interconnect-cells = <2>;
3115		};
3116
3117		aggre2_noc: interconnect@1700000 {
3118			compatible = "qcom,x1e80100-aggre2-noc";
3119			reg = <0 0x01700000 0 0x1c400>;
3120
3121			qcom,bcm-voters = <&apps_bcm_voter>;
3122
3123			#interconnect-cells = <2>;
3124		};
3125
3126		pcie_north_anoc: interconnect@1740000 {
3127			compatible = "qcom,x1e80100-pcie-north-anoc";
3128			reg = <0 0x01740000 0 0x9080>;
3129
3130			qcom,bcm-voters = <&apps_bcm_voter>;
3131
3132			#interconnect-cells = <2>;
3133		};
3134
3135		usb_center_anoc: interconnect@1750000 {
3136			compatible = "qcom,x1e80100-usb-center-anoc";
3137			reg = <0 0x01750000 0 0x8800>;
3138
3139			qcom,bcm-voters = <&apps_bcm_voter>;
3140
3141			#interconnect-cells = <2>;
3142		};
3143
3144		usb_north_anoc: interconnect@1760000 {
3145			compatible = "qcom,x1e80100-usb-north-anoc";
3146			reg = <0 0x01760000 0 0x7080>;
3147
3148			qcom,bcm-voters = <&apps_bcm_voter>;
3149
3150			#interconnect-cells = <2>;
3151		};
3152
3153		usb_south_anoc: interconnect@1770000 {
3154			compatible = "qcom,x1e80100-usb-south-anoc";
3155			reg = <0 0x01770000 0 0xf080>;
3156
3157			qcom,bcm-voters = <&apps_bcm_voter>;
3158
3159			#interconnect-cells = <2>;
3160		};
3161
3162		mmss_noc: interconnect@1780000 {
3163			compatible = "qcom,x1e80100-mmss-noc";
3164			reg = <0 0x01780000 0 0x5B800>;
3165
3166			qcom,bcm-voters = <&apps_bcm_voter>;
3167
3168			#interconnect-cells = <2>;
3169		};
3170
3171		pcie3: pcie@1bd0000 {
3172			device_type = "pci";
3173			compatible = "qcom,pcie-x1e80100";
3174			reg = <0x0 0x01bd0000 0x0 0x3000>,
3175			      <0x0 0x78000000 0x0 0xf20>,
3176			      <0x0 0x78000f40 0x0 0xa8>,
3177			      <0x0 0x78001000 0x0 0x1000>,
3178			      <0x0 0x78100000 0x0 0x100000>,
3179			      <0x0 0x01bd3000 0x0 0x1000>;
3180			reg-names = "parf",
3181				    "dbi",
3182				    "elbi",
3183				    "atu",
3184				    "config",
3185				    "mhi";
3186			#address-cells = <3>;
3187			#size-cells = <2>;
3188			ranges = <0x01000000 0x0 0x00000000 0x0 0x78200000 0x0 0x100000>,
3189				 <0x02000000 0x0 0x78300000 0x0 0x78300000 0x0 0x3d00000>,
3190				 <0x03000000 0x7 0x40000000 0x7 0x40000000 0x0 0x40000000>;
3191			bus-range = <0x00 0xff>;
3192
3193			dma-coherent;
3194
3195			linux,pci-domain = <3>;
3196			num-lanes = <8>;
3197
3198			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
3199				     <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
3200				     <GIC_SPI 769 IRQ_TYPE_LEVEL_HIGH>,
3201				     <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>,
3202				     <GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
3203				     <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
3204				     <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
3205				     <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
3206				     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
3207			interrupt-names = "msi0",
3208					  "msi1",
3209					  "msi2",
3210					  "msi3",
3211					  "msi4",
3212					  "msi5",
3213					  "msi6",
3214					  "msi7",
3215					  "global";
3216
3217			#interrupt-cells = <1>;
3218			interrupt-map-mask = <0 0 0 0x7>;
3219			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
3220					<0 0 0 2 &intc 0 0 GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>,
3221					<0 0 0 3 &intc 0 0 GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
3222					<0 0 0 4 &intc 0 0 GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
3223
3224			clocks = <&gcc GCC_PCIE_3_AUX_CLK>,
3225				 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
3226				 <&gcc GCC_PCIE_3_MSTR_AXI_CLK>,
3227				 <&gcc GCC_PCIE_3_SLV_AXI_CLK>,
3228				 <&gcc GCC_PCIE_3_SLV_Q2A_AXI_CLK>,
3229				 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3230				 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3231			clock-names = "aux",
3232				      "cfg",
3233				      "bus_master",
3234				      "bus_slave",
3235				      "slave_q2a",
3236				      "noc_aggr",
3237				      "cnoc_sf_axi";
3238
3239			assigned-clocks = <&gcc GCC_PCIE_3_AUX_CLK>;
3240			assigned-clock-rates = <19200000>;
3241
3242			interconnects = <&pcie_north_anoc MASTER_PCIE_3 QCOM_ICC_TAG_ALWAYS
3243					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3244					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3245					 &cnoc_main SLAVE_PCIE_3 QCOM_ICC_TAG_ACTIVE_ONLY>;
3246			interconnect-names = "pcie-mem",
3247					     "cpu-pcie";
3248
3249			resets = <&gcc GCC_PCIE_3_BCR>,
3250				 <&gcc GCC_PCIE_3_LINK_DOWN_BCR>;
3251			reset-names = "pci",
3252				      "link_down";
3253
3254			power-domains = <&gcc GCC_PCIE_3_GDSC>;
3255
3256			phys = <&pcie3_phy>;
3257			phy-names = "pciephy";
3258
3259			eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555
3260						     0x5555 0x5555 0x5555 0x5555>;
3261			eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55 0x55 0x55 0x55 0x55>;
3262
3263			operating-points-v2 = <&pcie3_opp_table>;
3264
3265			status = "disabled";
3266
3267			pcie3_opp_table: opp-table {
3268				compatible = "operating-points-v2";
3269
3270				/* 2.5GT/s x1 */
3271				opp-2500000-1 {
3272					opp-hz = /bits/ 64 <2500000>;
3273					required-opps = <&rpmhpd_opp_low_svs>;
3274					opp-peak-kBps = <250000 1>;
3275					opp-level = <1>;
3276				};
3277
3278				/* 2.5 GT/s x2 */
3279				opp-5000000-1 {
3280					opp-hz = /bits/ 64 <5000000>;
3281					required-opps = <&rpmhpd_opp_low_svs>;
3282					opp-peak-kBps = <500000 1>;
3283					opp-level = <1>;
3284				};
3285
3286				/* 2.5 GT/s x4 */
3287				opp-10000000-1 {
3288					opp-hz = /bits/ 64 <10000000>;
3289					required-opps = <&rpmhpd_opp_low_svs>;
3290					opp-peak-kBps = <1000000 1>;
3291					opp-level = <1>;
3292				};
3293
3294				/* 2.5 GT/s x8 */
3295				opp-20000000-1 {
3296					opp-hz = /bits/ 64 <20000000>;
3297					required-opps = <&rpmhpd_opp_low_svs>;
3298					opp-peak-kBps = <2000000 1>;
3299					opp-level = <1>;
3300				};
3301
3302				/* 5 GT/s x1 */
3303				opp-5000000-2 {
3304					opp-hz = /bits/ 64 <5000000>;
3305					required-opps = <&rpmhpd_opp_low_svs>;
3306					opp-peak-kBps = <500000 1>;
3307					opp-level = <2>;
3308				};
3309
3310				/* 5 GT/s x2 */
3311				opp-10000000-2 {
3312					opp-hz = /bits/ 64 <10000000>;
3313					required-opps = <&rpmhpd_opp_low_svs>;
3314					opp-peak-kBps = <1000000 1>;
3315					opp-level = <2>;
3316				};
3317
3318				/* 5 GT/s x4 */
3319				opp-20000000-2 {
3320					opp-hz = /bits/ 64 <20000000>;
3321					required-opps = <&rpmhpd_opp_low_svs>;
3322					opp-peak-kBps = <2000000 1>;
3323					opp-level = <2>;
3324				};
3325
3326				/* 5 GT/s x8 */
3327				opp-40000000-2 {
3328					opp-hz = /bits/ 64 <40000000>;
3329					required-opps = <&rpmhpd_opp_low_svs>;
3330					opp-peak-kBps = <4000000 1>;
3331					opp-level = <2>;
3332				};
3333
3334				/* 8 GT/s x1 */
3335				opp-8000000-3 {
3336					opp-hz = /bits/ 64 <8000000>;
3337					required-opps = <&rpmhpd_opp_svs>;
3338					opp-peak-kBps = <984500 1>;
3339					opp-level = <3>;
3340				};
3341
3342				/* 8 GT/s x2 */
3343				opp-16000000-3 {
3344					opp-hz = /bits/ 64 <16000000>;
3345					required-opps = <&rpmhpd_opp_svs>;
3346					opp-peak-kBps = <1969000 1>;
3347					opp-level = <3>;
3348				};
3349
3350				/* 8 GT/s x4 */
3351				opp-32000000-3 {
3352					opp-hz = /bits/ 64 <32000000>;
3353					required-opps = <&rpmhpd_opp_svs>;
3354					opp-peak-kBps = <3938000 1>;
3355					opp-level = <3>;
3356				};
3357
3358				/* 8 GT/s x8 */
3359				opp-64000000-3 {
3360					opp-hz = /bits/ 64 <64000000>;
3361					required-opps = <&rpmhpd_opp_svs>;
3362					opp-peak-kBps = <7876000 1>;
3363					opp-level = <3>;
3364				};
3365
3366				/* 16 GT/s x1 */
3367				opp-16000000-4 {
3368					opp-hz = /bits/ 64 <16000000>;
3369					required-opps = <&rpmhpd_opp_svs>;
3370					opp-peak-kBps = <1969000 1>;
3371					opp-level = <4>;
3372				};
3373
3374				/* 16 GT/s x2 */
3375				opp-32000000-4 {
3376					opp-hz = /bits/ 64 <32000000>;
3377					required-opps = <&rpmhpd_opp_svs>;
3378					opp-peak-kBps = <3938000 1>;
3379					opp-level = <4>;
3380				};
3381
3382				/* 16 GT/s x4 */
3383				opp-64000000-4 {
3384					opp-hz = /bits/ 64 <64000000>;
3385					required-opps = <&rpmhpd_opp_svs>;
3386					opp-peak-kBps = <7876000 1>;
3387					opp-level = <4>;
3388				};
3389
3390				/* 16 GT/s x8 */
3391				opp-128000000-4 {
3392					opp-hz = /bits/ 64 <128000000>;
3393					required-opps = <&rpmhpd_opp_svs>;
3394					opp-peak-kBps = <15753000 1>;
3395					opp-level = <4>;
3396				};
3397			};
3398
3399			pcie3_port: pcie@0 {
3400				device_type = "pci";
3401				compatible = "pciclass,0604";
3402				reg = <0x0 0x0 0x0 0x0 0x0>;
3403				bus-range = <0x01 0xff>;
3404
3405				#address-cells = <3>;
3406				#size-cells = <2>;
3407				ranges;
3408			};
3409		};
3410
3411		pcie3_phy: phy@1be0000 {
3412			compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy";
3413			reg = <0 0x01be0000 0 0x10000>;
3414
3415			clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>,
3416				 <&gcc GCC_PCIE_3_CFG_AHB_CLK>,
3417				 <&tcsr TCSR_PCIE_8L_CLKREF_EN>,
3418				 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>,
3419				 <&gcc GCC_PCIE_3_PIPE_CLK>,
3420				 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>;
3421			clock-names = "aux",
3422				      "cfg_ahb",
3423				      "ref",
3424				      "rchng",
3425				      "pipe",
3426				      "pipediv2";
3427
3428			resets = <&gcc GCC_PCIE_3_PHY_BCR>,
3429				 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>;
3430			reset-names = "phy",
3431				      "phy_nocsr";
3432
3433			assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>;
3434			assigned-clock-rates = <100000000>;
3435
3436			power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>;
3437
3438			#clock-cells = <0>;
3439			clock-output-names = "pcie3_pipe_clk";
3440
3441			#phy-cells = <0>;
3442
3443			status = "disabled";
3444		};
3445
3446		pcie6a: pci@1bf8000 {
3447			device_type = "pci";
3448			compatible = "qcom,pcie-x1e80100";
3449			reg = <0 0x01bf8000 0 0x3000>,
3450			      <0 0x70000000 0 0xf20>,
3451			      <0 0x70000f40 0 0xa8>,
3452			      <0 0x70001000 0 0x1000>,
3453			      <0 0x70100000 0 0x100000>,
3454			      <0 0x01bfb000 0 0x1000>;
3455			reg-names = "parf",
3456				    "dbi",
3457				    "elbi",
3458				    "atu",
3459				    "config",
3460				    "mhi";
3461			#address-cells = <3>;
3462			#size-cells = <2>;
3463			ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>,
3464				 <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x3d00000>;
3465			bus-range = <0x00 0xff>;
3466
3467			dma-coherent;
3468
3469			linux,pci-domain = <6>;
3470			num-lanes = <4>;
3471
3472			msi-map = <0x0 &gic_its 0xe0000 0x10000>;
3473
3474			interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
3475				     <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
3476				     <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
3477				     <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
3478				     <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
3479				     <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
3480				     <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
3481				     <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>,
3482				     <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>;
3483			interrupt-names = "msi0",
3484					  "msi1",
3485					  "msi2",
3486					  "msi3",
3487					  "msi4",
3488					  "msi5",
3489					  "msi6",
3490					  "msi7",
3491					  "global";
3492
3493			#interrupt-cells = <1>;
3494			interrupt-map-mask = <0 0 0 0x7>;
3495			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>,
3496					<0 0 0 2 &intc 0 0 GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>,
3497					<0 0 0 3 &intc 0 0 GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>,
3498					<0 0 0 4 &intc 0 0 GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>;
3499
3500			clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,
3501				 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
3502				 <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,
3503				 <&gcc GCC_PCIE_6A_SLV_AXI_CLK>,
3504				 <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,
3505				 <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
3506				 <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;
3507			clock-names = "aux",
3508				      "cfg",
3509				      "bus_master",
3510				      "bus_slave",
3511				      "slave_q2a",
3512				      "noc_aggr",
3513				      "cnoc_sf_axi";
3514
3515			assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
3516			assigned-clock-rates = <19200000>;
3517
3518			interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS
3519					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3520					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3521					 &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ACTIVE_ONLY>;
3522			interconnect-names = "pcie-mem",
3523					     "cpu-pcie";
3524
3525			resets = <&gcc GCC_PCIE_6A_BCR>,
3526				 <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;
3527			reset-names = "pci",
3528				      "link_down";
3529
3530			power-domains = <&gcc GCC_PCIE_6A_GDSC>;
3531			required-opps = <&rpmhpd_opp_nom>;
3532
3533			phys = <&pcie6a_phy>;
3534			phy-names = "pciephy";
3535
3536			eq-presets-8gts = /bits/ 16 <0x5555 0x5555 0x5555 0x5555>;
3537			eq-presets-16gts = /bits/ 8 <0x55 0x55 0x55 0x55>;
3538
3539			status = "disabled";
3540		};
3541
3542		pcie6a_phy: phy@1bfc000 {
3543			compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy";
3544			reg = <0 0x01bfc000 0 0x2000>,
3545			      <0 0x01bfe000 0 0x2000>;
3546
3547			clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
3548				 <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
3549				 <&tcsr TCSR_PCIE_4L_CLKREF_EN>,
3550				 <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
3551				 <&gcc GCC_PCIE_6A_PIPE_CLK>,
3552				 <&gcc GCC_PCIE_6A_PIPEDIV2_CLK>;
3553			clock-names = "aux",
3554				      "cfg_ahb",
3555				      "ref",
3556				      "rchng",
3557				      "pipe",
3558				      "pipediv2";
3559
3560			resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
3561				 <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
3562			reset-names = "phy",
3563				      "phy_nocsr";
3564
3565			assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
3566			assigned-clock-rates = <100000000>;
3567
3568			power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
3569
3570			qcom,4ln-config-sel = <&tcsr 0x1a000 0>;
3571
3572			#clock-cells = <0>;
3573			clock-output-names = "pcie6a_pipe_clk";
3574
3575			#phy-cells = <0>;
3576
3577			status = "disabled";
3578		};
3579
3580		pcie5: pci@1c00000 {
3581			device_type = "pci";
3582			compatible = "qcom,pcie-x1e80100";
3583			reg = <0 0x01c00000 0 0x3000>,
3584			      <0 0x7e000000 0 0xf1d>,
3585			      <0 0x7e000f40 0 0xa8>,
3586			      <0 0x7e001000 0 0x1000>,
3587			      <0 0x7e100000 0 0x100000>,
3588			      <0 0x01c03000 0 0x1000>;
3589			reg-names = "parf",
3590				    "dbi",
3591				    "elbi",
3592				    "atu",
3593				    "config",
3594				    "mhi";
3595			#address-cells = <3>;
3596			#size-cells = <2>;
3597			ranges = <0x01000000 0x0 0x00000000 0x0 0x7e200000 0x0 0x100000>,
3598				 <0x02000000 0x0 0x7e300000 0x0 0x7e300000 0x0 0x1d00000>;
3599			bus-range = <0x00 0xff>;
3600
3601			dma-coherent;
3602
3603			linux,pci-domain = <5>;
3604			num-lanes = <2>;
3605
3606			interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3607				     <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3608				     <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3609				     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
3610				     <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
3611				     <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
3612				     <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>,
3613				     <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>,
3614				     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
3615			interrupt-names = "msi0",
3616					  "msi1",
3617					  "msi2",
3618					  "msi3",
3619					  "msi4",
3620					  "msi5",
3621					  "msi6",
3622					  "msi7",
3623					  "global";
3624
3625			#interrupt-cells = <1>;
3626			interrupt-map-mask = <0 0 0 0x7>;
3627			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
3628					<0 0 0 2 &intc 0 0 GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
3629					<0 0 0 3 &intc 0 0 GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
3630					<0 0 0 4 &intc 0 0 GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
3631
3632			clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
3633				 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
3634				 <&gcc GCC_PCIE_5_MSTR_AXI_CLK>,
3635				 <&gcc GCC_PCIE_5_SLV_AXI_CLK>,
3636				 <&gcc GCC_PCIE_5_SLV_Q2A_AXI_CLK>,
3637				 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3638				 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3639			clock-names = "aux",
3640				      "cfg",
3641				      "bus_master",
3642				      "bus_slave",
3643				      "slave_q2a",
3644				      "noc_aggr",
3645				      "cnoc_sf_axi";
3646
3647			assigned-clocks = <&gcc GCC_PCIE_5_AUX_CLK>;
3648			assigned-clock-rates = <19200000>;
3649
3650			interconnects = <&pcie_north_anoc MASTER_PCIE_5 QCOM_ICC_TAG_ALWAYS
3651					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3652					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3653					 &cnoc_main SLAVE_PCIE_5 QCOM_ICC_TAG_ACTIVE_ONLY>;
3654			interconnect-names = "pcie-mem",
3655					     "cpu-pcie";
3656
3657			resets = <&gcc GCC_PCIE_5_BCR>,
3658				 <&gcc GCC_PCIE_5_LINK_DOWN_BCR>;
3659			reset-names = "pci",
3660				      "link_down";
3661
3662			power-domains = <&gcc GCC_PCIE_5_GDSC>;
3663			required-opps = <&rpmhpd_opp_nom>;
3664
3665			phys = <&pcie5_phy>;
3666			phy-names = "pciephy";
3667
3668			eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
3669
3670			status = "disabled";
3671		};
3672
3673		pcie5_phy: phy@1c06000 {
3674			compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3675			reg = <0 0x01c06000 0 0x2000>;
3676
3677			clocks = <&gcc GCC_PCIE_5_AUX_CLK>,
3678				 <&gcc GCC_PCIE_5_CFG_AHB_CLK>,
3679				 <&tcsr TCSR_PCIE_2L_5_CLKREF_EN>,
3680				 <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>,
3681				 <&gcc GCC_PCIE_5_PIPE_CLK>,
3682				 <&gcc GCC_PCIE_5_PIPEDIV2_CLK>;
3683			clock-names = "aux",
3684				      "cfg_ahb",
3685				      "ref",
3686				      "rchng",
3687				      "pipe",
3688				      "pipediv2";
3689
3690			resets = <&gcc GCC_PCIE_5_PHY_BCR>,
3691				 <&gcc GCC_PCIE_5_NOCSR_COM_PHY_BCR>;
3692			reset-names = "phy",
3693				      "phy_nocsr";
3694
3695			assigned-clocks = <&gcc GCC_PCIE_5_PHY_RCHNG_CLK>;
3696			assigned-clock-rates = <100000000>;
3697
3698			power-domains = <&gcc GCC_PCIE_5_PHY_GDSC>;
3699
3700			#clock-cells = <0>;
3701			clock-output-names = "pcie5_pipe_clk";
3702
3703			#phy-cells = <0>;
3704
3705			status = "disabled";
3706		};
3707
3708		pcie4: pci@1c08000 {
3709			device_type = "pci";
3710			compatible = "qcom,pcie-x1e80100";
3711			reg = <0 0x01c08000 0 0x3000>,
3712			      <0 0x7c000000 0 0xf1d>,
3713			      <0 0x7c000f40 0 0xa8>,
3714			      <0 0x7c001000 0 0x1000>,
3715			      <0 0x7c100000 0 0x100000>,
3716			      <0 0x01c0b000 0 0x1000>;
3717			reg-names = "parf",
3718			            "dbi",
3719				    "elbi",
3720				    "atu",
3721				    "config",
3722				    "mhi";
3723			#address-cells = <3>;
3724			#size-cells = <2>;
3725			ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>,
3726				 <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>;
3727			bus-range = <0x00 0xff>;
3728
3729			dma-coherent;
3730
3731			linux,pci-domain = <4>;
3732			num-lanes = <2>;
3733
3734			msi-map = <0x0 &gic_its 0xc0000 0x10000>;
3735
3736			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
3737				     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
3738				     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
3739				     <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
3740				     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
3741				     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
3742				     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
3743				     <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
3744				     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
3745			interrupt-names = "msi0",
3746					  "msi1",
3747					  "msi2",
3748					  "msi3",
3749					  "msi4",
3750					  "msi5",
3751					  "msi6",
3752					  "msi7",
3753					  "global";
3754
3755			#interrupt-cells = <1>;
3756			interrupt-map-mask = <0 0 0 0x7>;
3757			interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
3758					<0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
3759					<0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
3760					<0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
3761
3762			clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3763				 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3764				 <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
3765				 <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
3766				 <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
3767				 <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
3768				 <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
3769			clock-names = "aux",
3770				      "cfg",
3771				      "bus_master",
3772				      "bus_slave",
3773				      "slave_q2a",
3774				      "noc_aggr",
3775				      "cnoc_sf_axi";
3776
3777			assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
3778			assigned-clock-rates = <19200000>;
3779
3780			interconnects = <&pcie_north_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
3781					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
3782					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
3783					 &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
3784			interconnect-names = "pcie-mem",
3785					     "cpu-pcie";
3786
3787			resets = <&gcc GCC_PCIE_4_BCR>,
3788				 <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
3789			reset-names = "pci",
3790				      "link_down";
3791
3792			power-domains = <&gcc GCC_PCIE_4_GDSC>;
3793			required-opps = <&rpmhpd_opp_nom>;
3794
3795			phys = <&pcie4_phy>;
3796			phy-names = "pciephy";
3797
3798			eq-presets-8gts = /bits/ 16 <0x5555 0x5555>;
3799
3800			status = "disabled";
3801
3802			pcie4_port0: pcie@0 {
3803				device_type = "pci";
3804				reg = <0x0 0x0 0x0 0x0 0x0>;
3805				bus-range = <0x01 0xff>;
3806
3807				#address-cells = <3>;
3808				#size-cells = <2>;
3809				ranges;
3810			};
3811		};
3812
3813		pcie4_phy: phy@1c0e000 {
3814			compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
3815			reg = <0 0x01c0e000 0 0x2000>;
3816
3817			clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
3818				 <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
3819				 <&tcsr TCSR_PCIE_2L_4_CLKREF_EN>,
3820				 <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
3821				 <&gcc GCC_PCIE_4_PIPE_CLK>,
3822				 <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
3823			clock-names = "aux",
3824				      "cfg_ahb",
3825				      "ref",
3826				      "rchng",
3827				      "pipe",
3828				      "pipediv2";
3829
3830			resets = <&gcc GCC_PCIE_4_PHY_BCR>,
3831				 <&gcc GCC_PCIE_4_NOCSR_COM_PHY_BCR>;
3832			reset-names = "phy",
3833				      "phy_nocsr";
3834
3835			assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
3836			assigned-clock-rates = <100000000>;
3837
3838			power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
3839
3840			#clock-cells = <0>;
3841			clock-output-names = "pcie4_pipe_clk";
3842
3843			#phy-cells = <0>;
3844
3845			status = "disabled";
3846		};
3847
3848		tcsr_mutex: hwlock@1f40000 {
3849			compatible = "qcom,tcsr-mutex";
3850			reg = <0 0x01f40000 0 0x20000>;
3851			#hwlock-cells = <1>;
3852		};
3853
3854		tcsr: clock-controller@1fc0000 {
3855			compatible = "qcom,x1e80100-tcsr", "syscon";
3856			reg = <0 0x01fc0000 0 0x30000>;
3857			clocks = <&rpmhcc RPMH_CXO_CLK>;
3858			#clock-cells = <1>;
3859			#reset-cells = <1>;
3860		};
3861
3862		gpu: gpu@3d00000 {
3863			compatible = "qcom,adreno-43050c01", "qcom,adreno";
3864			reg = <0x0 0x03d00000 0x0 0x40000>,
3865			      <0x0 0x03d9e000 0x0 0x1000>,
3866			      <0x0 0x03d61000 0x0 0x800>;
3867
3868			reg-names = "kgsl_3d0_reg_memory",
3869				    "cx_mem",
3870				    "cx_dbgc";
3871
3872			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
3873
3874			iommus = <&adreno_smmu 0 0x0>,
3875				 <&adreno_smmu 1 0x0>;
3876
3877			operating-points-v2 = <&gpu_opp_table>;
3878
3879			qcom,gmu = <&gmu>;
3880			#cooling-cells = <2>;
3881
3882			nvmem-cells = <&gpu_speed_bin>;
3883			nvmem-cell-names = "speed_bin";
3884
3885			interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
3886			interconnect-names = "gfx-mem";
3887
3888			status = "disabled";
3889
3890			gpu_zap_shader: zap-shader {
3891				memory-region = <&gpu_microcode_mem>;
3892			};
3893
3894			gpu_opp_table: opp-table {
3895				compatible = "operating-points-v2-adreno", "operating-points-v2";
3896
3897				opp-1500000000 {
3898					opp-hz = /bits/ 64 <1500000000>;
3899					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
3900					opp-peak-kBps = <16500000>;
3901					qcom,opp-acd-level = <0xa82a5ffd>;
3902					opp-supported-hw = <0x03>;
3903				};
3904
3905				opp-1375000000 {
3906					opp-hz = /bits/ 64 <1375000000>;
3907					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
3908					opp-peak-kBps = <16500000>;
3909					qcom,opp-acd-level = <0xa82a5ffd>;
3910					opp-supported-hw = <0x03>;
3911				};
3912
3913				opp-1250000000 {
3914					opp-hz = /bits/ 64 <1250000000>;
3915					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
3916					opp-peak-kBps = <16500000>;
3917					qcom,opp-acd-level = <0xa82a5ffd>;
3918					opp-supported-hw = <0x07>;
3919				};
3920
3921				opp-1175000000 {
3922					opp-hz = /bits/ 64 <1175000000>;
3923					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
3924					opp-peak-kBps = <14398438>;
3925					qcom,opp-acd-level = <0xa82a5ffd>;
3926					opp-supported-hw = <0x07>;
3927				};
3928
3929				opp-1100000000-0 {
3930					opp-hz = /bits/ 64 <1100000000>;
3931					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3932					opp-peak-kBps = <14398438>;
3933					qcom,opp-acd-level = <0xa82a5ffd>;
3934					opp-supported-hw = <0x07>;
3935				};
3936
3937				/* Only applicable for SKUs which has 1100Mhz as Fmax */
3938				opp-1100000000-1 {
3939					opp-hz = /bits/ 64 <1100000000>;
3940					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3941					opp-peak-kBps = <16500000>;
3942					qcom,opp-acd-level = <0xa82a5ffd>;
3943					opp-supported-hw = <0x08>;
3944				};
3945
3946				opp-1000000000 {
3947					opp-hz = /bits/ 64 <1000000000>;
3948					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3949					opp-peak-kBps = <14398438>;
3950					qcom,opp-acd-level = <0xa82b5ffd>;
3951					opp-supported-hw = <0x0f>;
3952				};
3953
3954				opp-925000000 {
3955					opp-hz = /bits/ 64 <925000000>;
3956					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3957					opp-peak-kBps = <14398438>;
3958					qcom,opp-acd-level = <0xa82b5ffd>;
3959					opp-supported-hw = <0x0f>;
3960				};
3961
3962				opp-800000000 {
3963					opp-hz = /bits/ 64 <800000000>;
3964					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3965					opp-peak-kBps = <12449219>;
3966					qcom,opp-acd-level = <0xa82c5ffd>;
3967					opp-supported-hw = <0x0f>;
3968				};
3969
3970				opp-744000000 {
3971					opp-hz = /bits/ 64 <744000000>;
3972					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
3973					opp-peak-kBps = <10687500>;
3974					qcom,opp-acd-level = <0x882e5ffd>;
3975					opp-supported-hw = <0x0f>;
3976				};
3977
3978				opp-687000000-0 {
3979					opp-hz = /bits/ 64 <687000000>;
3980					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3981					opp-peak-kBps = <8171875>;
3982					qcom,opp-acd-level = <0x882e5ffd>;
3983					opp-supported-hw = <0x0f>;
3984				};
3985
3986				/* Only applicable for SKUs which has 687Mhz as Fmax */
3987				opp-687000000-1 {
3988					opp-hz = /bits/ 64 <687000000>;
3989					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3990					opp-peak-kBps = <16500000>;
3991					qcom,opp-acd-level = <0x882e5ffd>;
3992					opp-supported-hw = <0x10>;
3993				};
3994
3995				opp-550000000 {
3996					opp-hz = /bits/ 64 <550000000>;
3997					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3998					opp-peak-kBps = <6074219>;
3999					qcom,opp-acd-level = <0xc0285ffd>;
4000					opp-supported-hw = <0x1f>;
4001				};
4002
4003				opp-390000000 {
4004					opp-hz = /bits/ 64 <390000000>;
4005					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4006					opp-peak-kBps = <3000000>;
4007					qcom,opp-acd-level = <0xc0285ffd>;
4008					opp-supported-hw = <0x1f>;
4009				};
4010
4011				opp-300000000 {
4012					opp-hz = /bits/ 64 <300000000>;
4013					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
4014					opp-peak-kBps = <2136719>;
4015					qcom,opp-acd-level = <0xc02b5ffd>;
4016					opp-supported-hw = <0x1f>;
4017				};
4018			};
4019		};
4020
4021		gmu: gmu@3d6a000 {
4022			compatible = "qcom,adreno-gmu-x185.1", "qcom,adreno-gmu";
4023			reg = <0x0 0x03d6a000 0x0 0x35000>,
4024			      <0x0 0x03d50000 0x0 0x10000>,
4025			      <0x0 0x0b280000 0x0 0x10000>;
4026			reg-names = "gmu", "rscc", "gmu_pdc";
4027
4028			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
4029				     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
4030			interrupt-names = "hfi", "gmu";
4031
4032			clocks = <&gpucc GPU_CC_AHB_CLK>,
4033				 <&gpucc GPU_CC_CX_GMU_CLK>,
4034				 <&gpucc GPU_CC_CXO_CLK>,
4035				 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
4036				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4037				 <&gpucc GPU_CC_HUB_CX_INT_CLK>,
4038				 <&gpucc GPU_CC_DEMET_CLK>;
4039			clock-names = "ahb",
4040				      "gmu",
4041				      "cxo",
4042				      "axi",
4043				      "memnoc",
4044				      "hub",
4045				      "demet";
4046
4047			power-domains = <&gpucc GPU_CX_GDSC>,
4048					<&gpucc GPU_GX_GDSC>;
4049			power-domain-names = "cx",
4050					     "gx";
4051
4052			iommus = <&adreno_smmu 5 0x0>;
4053
4054			qcom,qmp = <&aoss_qmp>;
4055
4056			operating-points-v2 = <&gmu_opp_table>;
4057
4058			gmu_opp_table: opp-table {
4059				compatible = "operating-points-v2";
4060
4061				opp-550000000 {
4062					opp-hz = /bits/ 64 <550000000>;
4063					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
4064				};
4065
4066				opp-220000000 {
4067					opp-hz = /bits/ 64 <220000000>;
4068					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
4069				};
4070			};
4071		};
4072
4073		gpucc: clock-controller@3d90000 {
4074			compatible = "qcom,x1e80100-gpucc";
4075			reg = <0 0x03d90000 0 0xa000>;
4076			clocks = <&bi_tcxo_div2>,
4077				 <&gcc GCC_GPU_GPLL0_CPH_CLK_SRC>,
4078				 <&gcc GCC_GPU_GPLL0_DIV_CPH_CLK_SRC>;
4079			#clock-cells = <1>;
4080			#reset-cells = <1>;
4081			#power-domain-cells = <1>;
4082		};
4083
4084		adreno_smmu: iommu@3da0000 {
4085			compatible = "qcom,x1e80100-smmu-500", "qcom,adreno-smmu",
4086				     "qcom,smmu-500", "arm,mmu-500";
4087			reg = <0x0 0x03da0000 0x0 0x40000>;
4088			#iommu-cells = <2>;
4089			#global-interrupts = <1>;
4090			interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
4091				     <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
4092				     <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
4093				     <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
4094				     <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
4095				     <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
4096				     <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
4097				     <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
4098				     <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
4099				     <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
4100				     <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
4101				     <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
4102				     <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
4103				     <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
4104				     <GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
4105				     <GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
4106				     <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
4107				     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
4108				     <GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
4109				     <GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
4110				     <GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
4111				     <GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
4112				     <GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
4113				     <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
4114				     <GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
4115				     <GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
4116			clocks = <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
4117				 <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
4118				 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
4119				 <&gpucc GPU_CC_AHB_CLK>;
4120			clock-names = "hlos",
4121				      "bus",
4122				      "iface",
4123				      "ahb";
4124			power-domains = <&gpucc GPU_CX_GDSC>;
4125			dma-coherent;
4126		};
4127
4128		gem_noc: interconnect@26400000 {
4129			compatible = "qcom,x1e80100-gem-noc";
4130			reg = <0 0x26400000 0 0x311200>;
4131
4132			qcom,bcm-voters = <&apps_bcm_voter>;
4133
4134			#interconnect-cells = <2>;
4135		};
4136
4137		nsp_noc: interconnect@320c0000 {
4138			compatible = "qcom,x1e80100-nsp-noc";
4139			reg = <0 0x320C0000 0 0xe080>;
4140
4141			qcom,bcm-voters = <&apps_bcm_voter>;
4142
4143			#interconnect-cells = <2>;
4144		};
4145
4146		remoteproc_adsp: remoteproc@6800000 {
4147			compatible = "qcom,x1e80100-adsp-pas";
4148			reg = <0x0 0x06800000 0x0 0x10000>;
4149
4150			interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
4151					      <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
4152					      <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
4153					      <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
4154					      <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
4155			interrupt-names = "wdog",
4156					  "fatal",
4157					  "ready",
4158					  "handover",
4159					  "stop-ack";
4160
4161			clocks = <&rpmhcc RPMH_CXO_CLK>;
4162			clock-names = "xo";
4163
4164			power-domains = <&rpmhpd RPMHPD_LCX>,
4165					<&rpmhpd RPMHPD_LMX>;
4166			power-domain-names = "lcx",
4167					     "lmx";
4168
4169			interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
4170					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
4171
4172			memory-region = <&adspslpi_mem>,
4173					<&q6_adsp_dtb_mem>;
4174
4175			qcom,qmp = <&aoss_qmp>;
4176
4177			qcom,smem-states = <&smp2p_adsp_out 0>;
4178			qcom,smem-state-names = "stop";
4179
4180			status = "disabled";
4181
4182			glink-edge {
4183				interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
4184							     IPCC_MPROC_SIGNAL_GLINK_QMP
4185							     IRQ_TYPE_EDGE_RISING>;
4186				mboxes = <&ipcc IPCC_CLIENT_LPASS
4187						IPCC_MPROC_SIGNAL_GLINK_QMP>;
4188
4189				label = "lpass";
4190				qcom,remote-pid = <2>;
4191
4192				fastrpc {
4193					compatible = "qcom,fastrpc";
4194					qcom,glink-channels = "fastrpcglink-apps-dsp";
4195					label = "adsp";
4196					qcom,non-secure-domain;
4197					#address-cells = <1>;
4198					#size-cells = <0>;
4199
4200					compute-cb@3 {
4201						compatible = "qcom,fastrpc-compute-cb";
4202						reg = <3>;
4203						iommus = <&apps_smmu 0x1003 0x80>,
4204							 <&apps_smmu 0x1063 0x0>;
4205						dma-coherent;
4206					};
4207
4208					compute-cb@4 {
4209						compatible = "qcom,fastrpc-compute-cb";
4210						reg = <4>;
4211						iommus = <&apps_smmu 0x1004 0x80>,
4212							 <&apps_smmu 0x1064 0x0>;
4213						dma-coherent;
4214					};
4215
4216					compute-cb@5 {
4217						compatible = "qcom,fastrpc-compute-cb";
4218						reg = <5>;
4219						iommus = <&apps_smmu 0x1005 0x80>,
4220							 <&apps_smmu 0x1065 0x0>;
4221						dma-coherent;
4222					};
4223
4224					compute-cb@6 {
4225						compatible = "qcom,fastrpc-compute-cb";
4226						reg = <6>;
4227						iommus = <&apps_smmu 0x1006 0x80>,
4228							 <&apps_smmu 0x1066 0x0>;
4229						dma-coherent;
4230					};
4231
4232					compute-cb@7 {
4233						compatible = "qcom,fastrpc-compute-cb";
4234						reg = <7>;
4235						iommus = <&apps_smmu 0x1007 0x80>,
4236							 <&apps_smmu 0x1067 0x0>;
4237						dma-coherent;
4238					};
4239				};
4240
4241				gpr {
4242					compatible = "qcom,gpr";
4243					qcom,glink-channels = "adsp_apps";
4244					qcom,domain = <GPR_DOMAIN_ID_ADSP>;
4245					qcom,intents = <512 20>;
4246					#address-cells = <1>;
4247					#size-cells = <0>;
4248
4249					q6apm: service@1 {
4250						compatible = "qcom,q6apm";
4251						reg = <GPR_APM_MODULE_IID>;
4252						#sound-dai-cells = <0>;
4253						qcom,protection-domain = "avs/audio",
4254									 "msm/adsp/audio_pd";
4255
4256						q6apmbedai: bedais {
4257							compatible = "qcom,q6apm-lpass-dais";
4258							#sound-dai-cells = <1>;
4259						};
4260
4261						q6apmdai: dais {
4262							compatible = "qcom,q6apm-dais";
4263							iommus = <&apps_smmu 0x1001 0x80>,
4264								 <&apps_smmu 0x1061 0x0>;
4265						};
4266					};
4267
4268					q6prm: service@2 {
4269						compatible = "qcom,q6prm";
4270						reg = <GPR_PRM_MODULE_IID>;
4271						qcom,protection-domain = "avs/audio",
4272									 "msm/adsp/audio_pd";
4273
4274						q6prmcc: clock-controller {
4275							compatible = "qcom,q6prm-lpass-clocks";
4276							#clock-cells = <2>;
4277						};
4278					};
4279				};
4280			};
4281		};
4282
4283		lpass_wsa2macro: codec@6aa0000 {
4284			compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4285			reg = <0 0x06aa0000 0 0x1000>;
4286			clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4287				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4288				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4289				 <&lpass_vamacro>;
4290			clock-names = "mclk",
4291				      "macro",
4292				      "dcodec",
4293				      "fsgen";
4294
4295			#clock-cells = <0>;
4296			clock-output-names = "wsa2-mclk";
4297			#sound-dai-cells = <1>;
4298			sound-name-prefix = "WSA2";
4299		};
4300
4301		swr3: soundwire@6ab0000 {
4302			compatible = "qcom,soundwire-v2.0.0";
4303			reg = <0 0x06ab0000 0 0x10000>;
4304			clocks = <&lpass_wsa2macro>;
4305			clock-names = "iface";
4306			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
4307			label = "WSA2";
4308
4309			pinctrl-0 = <&wsa2_swr_active>;
4310			pinctrl-names = "default";
4311			resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA2_CGCR>;
4312			reset-names = "swr_audio_cgcr";
4313
4314			qcom,din-ports = <4>;
4315			qcom,dout-ports = <9>;
4316
4317			qcom,ports-sinterval =		/bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
4318			qcom,ports-offset1 =		/bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4319			qcom,ports-offset2 =		/bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4320			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4321			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4322			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
4323			qcom,ports-block-pack-mode =	/bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
4324			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4325			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4326
4327			#address-cells = <2>;
4328			#size-cells = <0>;
4329			#sound-dai-cells = <1>;
4330			status = "disabled";
4331		};
4332
4333		lpass_rxmacro: codec@6ac0000 {
4334			compatible = "qcom,x1e80100-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro";
4335			reg = <0 0x06ac0000 0 0x1000>;
4336			clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4337				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4338				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4339				 <&lpass_vamacro>;
4340			clock-names = "mclk",
4341				      "macro",
4342				      "dcodec",
4343				      "fsgen";
4344
4345			#clock-cells = <0>;
4346			clock-output-names = "mclk";
4347			#sound-dai-cells = <1>;
4348		};
4349
4350		swr1: soundwire@6ad0000 {
4351			compatible = "qcom,soundwire-v2.0.0";
4352			reg = <0 0x06ad0000 0 0x10000>;
4353			clocks = <&lpass_rxmacro>;
4354			clock-names = "iface";
4355			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
4356			label = "RX";
4357
4358			pinctrl-0 = <&rx_swr_active>;
4359			pinctrl-names = "default";
4360
4361			resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>;
4362			reset-names = "swr_audio_cgcr";
4363			qcom,din-ports = <1>;
4364			qcom,dout-ports = <11>;
4365
4366			qcom,ports-sinterval =		/bits/ 16 <0x03 0x1f 0x1f 0x07 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4367			qcom,ports-offset1 =		/bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4368			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4369			qcom,ports-hstart =		/bits/ 8 <0xff 0x03 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4370			qcom,ports-hstop =		/bits/ 8 <0xff 0x06 0x0f 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4371			qcom,ports-word-length =	/bits/ 8 <0x01 0x07 0x04 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4372			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0x01 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4373			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4374			qcom,ports-lane-control =	/bits/ 8 <0x01 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4375
4376			#address-cells = <2>;
4377			#size-cells = <0>;
4378			#sound-dai-cells = <1>;
4379			status = "disabled";
4380		};
4381
4382		lpass_txmacro: codec@6ae0000 {
4383			compatible = "qcom,x1e80100-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro";
4384			reg = <0 0x06ae0000 0 0x1000>;
4385			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4386				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4387				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4388				 <&lpass_vamacro>;
4389			clock-names = "mclk",
4390				      "macro",
4391				      "dcodec",
4392				      "fsgen";
4393
4394			#clock-cells = <0>;
4395			clock-output-names = "mclk";
4396			#sound-dai-cells = <1>;
4397		};
4398
4399		lpass_wsamacro: codec@6b00000 {
4400			compatible = "qcom,x1e80100-lpass-wsa-macro", "qcom,sm8550-lpass-wsa-macro";
4401			reg = <0 0x06b00000 0 0x1000>;
4402			clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4403				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4404				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4405				 <&lpass_vamacro>;
4406			clock-names = "mclk",
4407				      "macro",
4408				      "dcodec",
4409				      "fsgen";
4410
4411			#clock-cells = <0>;
4412			clock-output-names = "mclk";
4413			#sound-dai-cells = <1>;
4414			sound-name-prefix = "WSA";
4415		};
4416
4417		swr0: soundwire@6b10000 {
4418			compatible = "qcom,soundwire-v2.0.0";
4419			reg = <0 0x06b10000 0 0x10000>;
4420			clocks = <&lpass_wsamacro>;
4421			clock-names = "iface";
4422			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
4423			label = "WSA";
4424
4425			pinctrl-0 = <&wsa_swr_active>;
4426			pinctrl-names = "default";
4427			resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>;
4428			reset-names = "swr_audio_cgcr";
4429
4430			qcom,din-ports = <4>;
4431			qcom,dout-ports = <9>;
4432
4433			qcom,ports-sinterval =		/bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0xc8 0xff 0xff 0x0f 0x0f 0xff 0x31f>;
4434			qcom,ports-offset1 =		/bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>;
4435			qcom,ports-offset2 =		/bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4436			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4437			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>;
4438			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>;
4439			qcom,ports-block-pack-mode =	/bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>;
4440			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4441			qcom,ports-lane-control =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>;
4442
4443			#address-cells = <2>;
4444			#size-cells = <0>;
4445			#sound-dai-cells = <1>;
4446			status = "disabled";
4447		};
4448
4449		lpass_audiocc: clock-controller@6b6c000 {
4450			compatible = "qcom,x1e80100-lpassaudiocc", "qcom,sc8280xp-lpassaudiocc";
4451			reg = <0 0x06b6c000 0 0x1000>;
4452			#clock-cells = <1>;
4453			#reset-cells = <1>;
4454		};
4455
4456		swr2: soundwire@6d30000 {
4457			compatible = "qcom,soundwire-v2.0.0";
4458			reg = <0 0x06d30000 0 0x10000>;
4459			clocks = <&lpass_txmacro>;
4460			clock-names = "iface";
4461			interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
4462				     <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
4463			interrupt-names = "core", "wakeup";
4464			label = "TX";
4465			resets = <&lpasscc LPASS_AUDIO_SWR_TX_CGCR>;
4466			reset-names = "swr_audio_cgcr";
4467
4468			pinctrl-0 = <&tx_swr_active>;
4469			pinctrl-names = "default";
4470
4471			qcom,din-ports = <4>;
4472			qcom,dout-ports = <1>;
4473
4474			qcom,ports-sinterval-low =	/bits/ 8 <0x00 0x01 0x03 0x03 0x00>;
4475			qcom,ports-offset1 =		/bits/ 8 <0x00 0x01 0x02 0x00 0x00>;
4476			qcom,ports-offset2 =		/bits/ 8 <0x00 0x00 0x00 0x00 0xff>;
4477			qcom,ports-hstart =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4478			qcom,ports-hstop =		/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4479			qcom,ports-word-length =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4480			qcom,ports-block-pack-mode =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4481			qcom,ports-block-group-count =	/bits/ 8 <0xff 0xff 0xff 0xff 0xff>;
4482			qcom,ports-lane-control =	/bits/ 8 <0xff 0x00 0x00 0x01 0xff>;
4483
4484			#address-cells = <2>;
4485			#size-cells = <0>;
4486			#sound-dai-cells = <1>;
4487			status = "disabled";
4488		};
4489
4490		lpass_vamacro: codec@6d44000 {
4491			compatible = "qcom,x1e80100-lpass-va-macro", "qcom,sm8550-lpass-va-macro";
4492			reg = <0 0x06d44000 0 0x1000>;
4493			clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4494				 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4495				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
4496			clock-names = "mclk",
4497				      "macro",
4498				      "dcodec";
4499
4500			#clock-cells = <0>;
4501			clock-output-names = "fsgen";
4502			#sound-dai-cells = <1>;
4503		};
4504
4505		lpass_tlmm: pinctrl@6e80000 {
4506			compatible = "qcom,x1e80100-lpass-lpi-pinctrl", "qcom,sm8550-lpass-lpi-pinctrl";
4507			reg = <0 0x06e80000 0 0x20000>,
4508			      <0 0x07250000 0 0x10000>;
4509
4510			clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
4511				 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
4512			clock-names = "core", "audio";
4513
4514			gpio-controller;
4515			#gpio-cells = <2>;
4516			gpio-ranges = <&lpass_tlmm 0 0 23>;
4517
4518			tx_swr_active: tx-swr-active-state {
4519				clk-pins {
4520					pins = "gpio0";
4521					function = "swr_tx_clk";
4522					drive-strength = <2>;
4523					slew-rate = <1>;
4524					bias-disable;
4525				};
4526
4527				data-pins {
4528					pins = "gpio1", "gpio2";
4529					function = "swr_tx_data";
4530					drive-strength = <2>;
4531					slew-rate = <1>;
4532					bias-bus-hold;
4533				};
4534			};
4535
4536			rx_swr_active: rx-swr-active-state {
4537				clk-pins {
4538					pins = "gpio3";
4539					function = "swr_rx_clk";
4540					drive-strength = <2>;
4541					slew-rate = <1>;
4542					bias-disable;
4543				};
4544
4545				data-pins {
4546					pins = "gpio4", "gpio5";
4547					function = "swr_rx_data";
4548					drive-strength = <2>;
4549					slew-rate = <1>;
4550					bias-bus-hold;
4551				};
4552			};
4553
4554			dmic01_default: dmic01-default-state {
4555				clk-pins {
4556					pins = "gpio6";
4557					function = "dmic1_clk";
4558					drive-strength = <8>;
4559					output-high;
4560				};
4561
4562				data-pins {
4563					pins = "gpio7";
4564					function = "dmic1_data";
4565					drive-strength = <8>;
4566					input-enable;
4567				};
4568			};
4569
4570			dmic23_default: dmic23-default-state {
4571				clk-pins {
4572					pins = "gpio8";
4573					function = "dmic2_clk";
4574					drive-strength = <8>;
4575					output-high;
4576				};
4577
4578				data-pins {
4579					pins = "gpio9";
4580					function = "dmic2_data";
4581					drive-strength = <8>;
4582					input-enable;
4583				};
4584			};
4585
4586			wsa_swr_active: wsa-swr-active-state {
4587				clk-pins {
4588					pins = "gpio10";
4589					function = "wsa_swr_clk";
4590					drive-strength = <2>;
4591					slew-rate = <1>;
4592					bias-disable;
4593				};
4594
4595				data-pins {
4596					pins = "gpio11";
4597					function = "wsa_swr_data";
4598					drive-strength = <2>;
4599					slew-rate = <1>;
4600					bias-bus-hold;
4601				};
4602			};
4603
4604			wsa2_swr_active: wsa2-swr-active-state {
4605				clk-pins {
4606					pins = "gpio15";
4607					function = "wsa2_swr_clk";
4608					drive-strength = <2>;
4609					slew-rate = <1>;
4610					bias-disable;
4611				};
4612
4613				data-pins {
4614					pins = "gpio16";
4615					function = "wsa2_swr_data";
4616					drive-strength = <2>;
4617					slew-rate = <1>;
4618					bias-bus-hold;
4619				};
4620			};
4621		};
4622
4623		lpasscc: clock-controller@6ea0000 {
4624			compatible = "qcom,x1e80100-lpasscc", "qcom,sc8280xp-lpasscc";
4625			reg = <0 0x06ea0000 0 0x12000>;
4626			#clock-cells = <1>;
4627			#reset-cells = <1>;
4628		};
4629
4630		lpass_ag_noc: interconnect@7e40000 {
4631			compatible = "qcom,x1e80100-lpass-ag-noc";
4632			reg = <0 0x07e40000 0 0xe080>;
4633
4634			qcom,bcm-voters = <&apps_bcm_voter>;
4635
4636			#interconnect-cells = <2>;
4637		};
4638
4639		lpass_lpiaon_noc: interconnect@7400000 {
4640			compatible = "qcom,x1e80100-lpass-lpiaon-noc";
4641			reg = <0 0x07400000 0 0x19080>;
4642
4643			qcom,bcm-voters = <&apps_bcm_voter>;
4644
4645			#interconnect-cells = <2>;
4646		};
4647
4648		lpass_lpicx_noc: interconnect@7430000 {
4649			compatible = "qcom,x1e80100-lpass-lpicx-noc";
4650			reg = <0 0x07430000 0 0x3A200>;
4651
4652			qcom,bcm-voters = <&apps_bcm_voter>;
4653
4654			#interconnect-cells = <2>;
4655		};
4656
4657		sdhc_2: mmc@8804000 {
4658			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
4659			reg = <0 0x08804000 0 0x1000>;
4660
4661			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
4662				     <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
4663			interrupt-names = "hc_irq", "pwr_irq";
4664
4665			clocks = <&gcc GCC_SDCC2_AHB_CLK>,
4666				 <&gcc GCC_SDCC2_APPS_CLK>,
4667				 <&rpmhcc RPMH_CXO_CLK>;
4668			clock-names = "iface", "core", "xo";
4669			iommus = <&apps_smmu 0x520 0>;
4670			qcom,dll-config = <0x0007642c>;
4671			qcom,ddr-config = <0x80040868>;
4672			power-domains = <&rpmhpd RPMHPD_CX>;
4673			operating-points-v2 = <&sdhc2_opp_table>;
4674
4675			interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS
4676					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4677					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
4678					 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
4679			interconnect-names = "sdhc-ddr", "cpu-sdhc";
4680			bus-width = <4>;
4681			dma-coherent;
4682
4683			status = "disabled";
4684
4685			sdhc2_opp_table: opp-table {
4686				compatible = "operating-points-v2";
4687
4688				opp-19200000 {
4689					opp-hz = /bits/ 64 <19200000>;
4690					required-opps = <&rpmhpd_opp_min_svs>;
4691				};
4692
4693				opp-50000000 {
4694					opp-hz = /bits/ 64 <50000000>;
4695					required-opps = <&rpmhpd_opp_low_svs>;
4696				};
4697
4698				opp-100000000 {
4699					opp-hz = /bits/ 64 <100000000>;
4700					required-opps = <&rpmhpd_opp_svs>;
4701				};
4702
4703				opp-202000000 {
4704					opp-hz = /bits/ 64 <202000000>;
4705					required-opps = <&rpmhpd_opp_svs_l1>;
4706				};
4707			};
4708		};
4709
4710		sdhc_4: mmc@8844000 {
4711			compatible = "qcom,x1e80100-sdhci", "qcom,sdhci-msm-v5";
4712			reg = <0 0x08844000 0 0x1000>;
4713
4714			interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
4715				     <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
4716			interrupt-names = "hc_irq", "pwr_irq";
4717
4718			clocks = <&gcc GCC_SDCC4_AHB_CLK>,
4719				 <&gcc GCC_SDCC4_APPS_CLK>,
4720				 <&rpmhcc RPMH_CXO_CLK>;
4721			clock-names = "iface", "core", "xo";
4722			iommus = <&apps_smmu 0x160 0>;
4723			qcom,dll-config = <0x0007642c>;
4724			qcom,ddr-config = <0x80040868>;
4725			power-domains = <&rpmhpd RPMHPD_CX>;
4726			operating-points-v2 = <&sdhc4_opp_table>;
4727
4728			interconnects = <&aggre2_noc MASTER_SDCC_4 QCOM_ICC_TAG_ALWAYS
4729					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4730					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
4731					 &config_noc SLAVE_SDCC_4 QCOM_ICC_TAG_ACTIVE_ONLY>;
4732			interconnect-names = "sdhc-ddr", "cpu-sdhc";
4733			bus-width = <4>;
4734			dma-coherent;
4735
4736			status = "disabled";
4737
4738			sdhc4_opp_table: opp-table {
4739				compatible = "operating-points-v2";
4740
4741				opp-19200000 {
4742					opp-hz = /bits/ 64 <19200000>;
4743					required-opps = <&rpmhpd_opp_min_svs>;
4744				};
4745
4746				opp-50000000 {
4747					opp-hz = /bits/ 64 <50000000>;
4748					required-opps = <&rpmhpd_opp_low_svs>;
4749				};
4750
4751				opp-100000000 {
4752					opp-hz = /bits/ 64 <100000000>;
4753					required-opps = <&rpmhpd_opp_svs>;
4754				};
4755
4756				opp-202000000 {
4757					opp-hz = /bits/ 64 <202000000>;
4758					required-opps = <&rpmhpd_opp_svs_l1>;
4759				};
4760			};
4761		};
4762
4763		usb_2_hsphy: phy@88e0000 {
4764			compatible = "qcom,x1e80100-snps-eusb2-phy",
4765				     "qcom,sm8550-snps-eusb2-phy";
4766			reg = <0 0x088e0000 0 0x154>;
4767			#phy-cells = <0>;
4768
4769			clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
4770			clock-names = "ref";
4771
4772			resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
4773
4774			status = "disabled";
4775		};
4776
4777		usb_mp_hsphy0: phy@88e1000 {
4778			compatible = "qcom,x1e80100-snps-eusb2-phy",
4779				     "qcom,sm8550-snps-eusb2-phy";
4780			reg = <0 0x088e1000 0 0x154>;
4781			#phy-cells = <0>;
4782
4783			clocks = <&tcsr TCSR_USB3_MP0_CLKREF_EN>;
4784			clock-names = "ref";
4785
4786			resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>;
4787
4788			status = "disabled";
4789		};
4790
4791		usb_mp_hsphy1: phy@88e2000 {
4792			compatible = "qcom,x1e80100-snps-eusb2-phy",
4793				     "qcom,sm8550-snps-eusb2-phy";
4794			reg = <0 0x088e2000 0 0x154>;
4795			#phy-cells = <0>;
4796
4797			clocks = <&tcsr TCSR_USB3_MP1_CLKREF_EN>;
4798			clock-names = "ref";
4799
4800			resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>;
4801
4802			status = "disabled";
4803		};
4804
4805		usb_mp_qmpphy0: phy@88e3000 {
4806			compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
4807			reg = <0 0x088e3000 0 0x2000>;
4808
4809			clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
4810				 <&rpmhcc RPMH_CXO_CLK>,
4811				 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
4812				 <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>;
4813			clock-names = "aux",
4814				      "ref",
4815				      "com_aux",
4816				      "pipe";
4817
4818			resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>,
4819				 <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>;
4820			reset-names = "phy",
4821				      "phy_phy";
4822
4823			power-domains = <&gcc GCC_USB3_MP_SS0_PHY_GDSC>;
4824
4825			#clock-cells = <0>;
4826			clock-output-names = "usb_mp_phy0_pipe_clk";
4827
4828			#phy-cells = <0>;
4829
4830			status = "disabled";
4831		};
4832
4833		usb_mp_qmpphy1: phy@88e5000 {
4834			compatible = "qcom,x1e80100-qmp-usb3-uni-phy";
4835			reg = <0 0x088e5000 0 0x2000>;
4836
4837			clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>,
4838				 <&rpmhcc RPMH_CXO_CLK>,
4839				 <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>,
4840				 <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>;
4841			clock-names = "aux",
4842				      "ref",
4843				      "com_aux",
4844				      "pipe";
4845
4846			resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>,
4847				 <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>;
4848			reset-names = "phy",
4849				      "phy_phy";
4850
4851			power-domains = <&gcc GCC_USB3_MP_SS1_PHY_GDSC>;
4852
4853			#clock-cells = <0>;
4854			clock-output-names = "usb_mp_phy1_pipe_clk";
4855
4856			#phy-cells = <0>;
4857
4858			status = "disabled";
4859		};
4860
4861		usb_1_ss2: usb@a0f8800 {
4862			compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4863			reg = <0 0x0a0f8800 0 0x400>;
4864
4865			clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
4866				 <&gcc GCC_USB30_TERT_MASTER_CLK>,
4867				 <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
4868				 <&gcc GCC_USB30_TERT_SLEEP_CLK>,
4869				 <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4870				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4871				 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4872				 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4873				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4874			clock-names = "cfg_noc",
4875				      "core",
4876				      "iface",
4877				      "sleep",
4878				      "mock_utmi",
4879				      "noc_aggr",
4880				      "noc_aggr_north",
4881				      "noc_aggr_south",
4882				      "noc_sys";
4883
4884			assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
4885					  <&gcc GCC_USB30_TERT_MASTER_CLK>;
4886			assigned-clock-rates = <19200000>,
4887					       <200000000>;
4888
4889			interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
4890					      <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
4891					      <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
4892					      <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
4893			interrupt-names = "pwr_event",
4894					  "dp_hs_phy_irq",
4895					  "dm_hs_phy_irq",
4896					  "ss_phy_irq";
4897
4898			power-domains = <&gcc GCC_USB30_TERT_GDSC>;
4899			required-opps = <&rpmhpd_opp_nom>;
4900
4901			resets = <&gcc GCC_USB30_TERT_BCR>;
4902
4903			interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
4904					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
4905					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
4906					 &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ACTIVE_ONLY>;
4907			interconnect-names = "usb-ddr",
4908					     "apps-usb";
4909
4910			wakeup-source;
4911
4912			#address-cells = <2>;
4913			#size-cells = <2>;
4914			ranges;
4915
4916			status = "disabled";
4917
4918			usb_1_ss2_dwc3: usb@a000000 {
4919				compatible = "snps,dwc3";
4920				reg = <0 0x0a000000 0 0xcd00>;
4921
4922				interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
4923
4924				iommus = <&apps_smmu 0x14a0 0x0>;
4925
4926				phys = <&usb_1_ss2_hsphy>,
4927				       <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
4928				phy-names = "usb2-phy",
4929				            "usb3-phy";
4930
4931				snps,dis_u2_susphy_quirk;
4932				snps,dis_enblslpm_quirk;
4933				snps,usb3_lpm_capable;
4934				snps,dis-u1-entry-quirk;
4935				snps,dis-u2-entry-quirk;
4936
4937				dma-coherent;
4938
4939				ports {
4940					#address-cells = <1>;
4941					#size-cells = <0>;
4942
4943					port@0 {
4944						reg = <0>;
4945
4946						usb_1_ss2_dwc3_hs: endpoint {
4947						};
4948					};
4949
4950					port@1 {
4951						reg = <1>;
4952
4953						usb_1_ss2_dwc3_ss: endpoint {
4954							remote-endpoint = <&usb_1_ss2_qmpphy_usb_ss_in>;
4955						};
4956					};
4957				};
4958			};
4959		};
4960
4961		usb_2: usb@a2f8800 {
4962			compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
4963			reg = <0 0x0a2f8800 0 0x400>;
4964			#address-cells = <2>;
4965			#size-cells = <2>;
4966			ranges;
4967
4968			clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
4969				 <&gcc GCC_USB20_MASTER_CLK>,
4970				 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
4971				 <&gcc GCC_USB20_SLEEP_CLK>,
4972				 <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4973				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
4974				 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
4975				 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
4976				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
4977			clock-names = "cfg_noc",
4978				      "core",
4979				      "iface",
4980				      "sleep",
4981				      "mock_utmi",
4982				      "noc_aggr",
4983				      "noc_aggr_north",
4984				      "noc_aggr_south",
4985				      "noc_sys";
4986
4987			assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
4988					  <&gcc GCC_USB20_MASTER_CLK>;
4989			assigned-clock-rates = <19200000>, <200000000>;
4990
4991			interrupts-extended = <&intc GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
4992					      <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
4993					      <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
4994			interrupt-names = "pwr_event",
4995					  "dp_hs_phy_irq",
4996					  "dm_hs_phy_irq";
4997
4998			power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
4999			required-opps = <&rpmhpd_opp_nom>;
5000
5001			resets = <&gcc GCC_USB20_PRIM_BCR>;
5002
5003			interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
5004					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
5005					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
5006					 &config_noc SLAVE_USB2 QCOM_ICC_TAG_ACTIVE_ONLY>;
5007			interconnect-names = "usb-ddr",
5008					     "apps-usb";
5009
5010			qcom,select-utmi-as-pipe-clk;
5011			wakeup-source;
5012
5013			status = "disabled";
5014
5015			usb_2_dwc3: usb@a200000 {
5016				compatible = "snps,dwc3";
5017				reg = <0 0x0a200000 0 0xcd00>;
5018				interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
5019				iommus = <&apps_smmu 0x14e0 0x0>;
5020				phys = <&usb_2_hsphy>;
5021				phy-names = "usb2-phy";
5022				maximum-speed = "high-speed";
5023				snps,dis-u1-entry-quirk;
5024				snps,dis-u2-entry-quirk;
5025
5026				dma-coherent;
5027
5028				port {
5029					usb_2_dwc3_hs: endpoint {
5030					};
5031				};
5032			};
5033		};
5034
5035		usb_mp: usb@a4f8800 {
5036			compatible = "qcom,x1e80100-dwc3-mp", "qcom,dwc3";
5037			reg = <0 0x0a4f8800 0 0x400>;
5038
5039			clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>,
5040				 <&gcc GCC_USB30_MP_MASTER_CLK>,
5041				 <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>,
5042				 <&gcc GCC_USB30_MP_SLEEP_CLK>,
5043				 <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
5044				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
5045				 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
5046				 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
5047				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
5048			clock-names = "cfg_noc",
5049				      "core",
5050				      "iface",
5051				      "sleep",
5052				      "mock_utmi",
5053				      "noc_aggr",
5054				      "noc_aggr_north",
5055				      "noc_aggr_south",
5056				      "noc_sys";
5057
5058			assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>,
5059					  <&gcc GCC_USB30_MP_MASTER_CLK>;
5060			assigned-clock-rates = <19200000>,
5061					       <200000000>;
5062
5063			interrupts-extended = <&intc GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
5064					      <&intc GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
5065					      <&intc GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
5066					      <&intc GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
5067					      <&pdc 52 IRQ_TYPE_EDGE_BOTH>,
5068					      <&pdc 51 IRQ_TYPE_EDGE_BOTH>,
5069					      <&pdc 54 IRQ_TYPE_EDGE_BOTH>,
5070					      <&pdc 53 IRQ_TYPE_EDGE_BOTH>,
5071					      <&pdc 55 IRQ_TYPE_LEVEL_HIGH>,
5072					      <&pdc 56 IRQ_TYPE_LEVEL_HIGH>;
5073			interrupt-names = "pwr_event_1", "pwr_event_2",
5074					  "hs_phy_1",	 "hs_phy_2",
5075					  "dp_hs_phy_1", "dm_hs_phy_1",
5076					  "dp_hs_phy_2", "dm_hs_phy_2",
5077					  "ss_phy_1",	 "ss_phy_2";
5078
5079			power-domains = <&gcc GCC_USB30_MP_GDSC>;
5080			required-opps = <&rpmhpd_opp_nom>;
5081
5082			resets = <&gcc GCC_USB30_MP_BCR>;
5083
5084			interconnects = <&usb_north_anoc MASTER_USB3_MP QCOM_ICC_TAG_ALWAYS
5085					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
5086					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
5087					 &config_noc SLAVE_USB3_MP QCOM_ICC_TAG_ACTIVE_ONLY>;
5088			interconnect-names = "usb-ddr",
5089					     "apps-usb";
5090
5091			wakeup-source;
5092
5093			#address-cells = <2>;
5094			#size-cells = <2>;
5095			ranges;
5096
5097			status = "disabled";
5098
5099			usb_mp_dwc3: usb@a400000 {
5100				compatible = "snps,dwc3";
5101				reg = <0 0x0a400000 0 0xcd00>;
5102
5103				interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
5104
5105				iommus = <&apps_smmu 0x1400 0x0>;
5106
5107				phys = <&usb_mp_hsphy0>, <&usb_mp_qmpphy0>,
5108				       <&usb_mp_hsphy1>, <&usb_mp_qmpphy1>;
5109				phy-names = "usb2-0", "usb3-0",
5110					    "usb2-1", "usb3-1";
5111				dr_mode = "host";
5112
5113				snps,dis_u2_susphy_quirk;
5114				snps,dis_enblslpm_quirk;
5115				snps,usb3_lpm_capable;
5116				snps,dis-u1-entry-quirk;
5117				snps,dis-u2-entry-quirk;
5118
5119				dma-coherent;
5120			};
5121		};
5122
5123		usb_1_ss0: usb@a6f8800 {
5124			compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
5125			reg = <0 0x0a6f8800 0 0x400>;
5126
5127			clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
5128				 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
5129				 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
5130				 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
5131				 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5132				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
5133				 <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
5134				 <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
5135				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
5136			clock-names = "cfg_noc",
5137				      "core",
5138				      "iface",
5139				      "sleep",
5140				      "mock_utmi",
5141				      "noc_aggr",
5142				      "noc_aggr_north",
5143				      "noc_aggr_south",
5144				      "noc_sys";
5145
5146			assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
5147					  <&gcc GCC_USB30_PRIM_MASTER_CLK>;
5148			assigned-clock-rates = <19200000>,
5149					       <200000000>;
5150
5151			interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
5152					      <&pdc 61 IRQ_TYPE_EDGE_BOTH>,
5153					      <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
5154					      <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
5155			interrupt-names = "pwr_event",
5156					  "dp_hs_phy_irq",
5157					  "dm_hs_phy_irq",
5158					  "ss_phy_irq";
5159
5160			power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
5161			required-opps = <&rpmhpd_opp_nom>;
5162
5163			resets = <&gcc GCC_USB30_PRIM_BCR>;
5164
5165			wakeup-source;
5166
5167			#address-cells = <2>;
5168			#size-cells = <2>;
5169			ranges;
5170
5171			status = "disabled";
5172
5173			usb_1_ss0_dwc3: usb@a600000 {
5174				compatible = "snps,dwc3";
5175				reg = <0 0x0a600000 0 0xcd00>;
5176
5177				interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
5178
5179				iommus = <&apps_smmu 0x1420 0x0>;
5180
5181				phys = <&usb_1_ss0_hsphy>,
5182				       <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
5183				phy-names = "usb2-phy",
5184					    "usb3-phy";
5185
5186				snps,dis_u2_susphy_quirk;
5187				snps,dis_enblslpm_quirk;
5188				snps,usb3_lpm_capable;
5189				snps,dis-u1-entry-quirk;
5190				snps,dis-u2-entry-quirk;
5191
5192				dma-coherent;
5193
5194				ports {
5195					#address-cells = <1>;
5196					#size-cells = <0>;
5197
5198					port@0 {
5199						reg = <0>;
5200
5201						usb_1_ss0_dwc3_hs: endpoint {
5202						};
5203					};
5204
5205					port@1 {
5206						reg = <1>;
5207
5208						usb_1_ss0_dwc3_ss: endpoint {
5209							remote-endpoint = <&usb_1_ss0_qmpphy_usb_ss_in>;
5210						};
5211					};
5212				};
5213			};
5214		};
5215
5216		usb_1_ss1: usb@a8f8800 {
5217			compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
5218			reg = <0 0x0a8f8800 0 0x400>;
5219
5220			clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
5221				 <&gcc GCC_USB30_SEC_MASTER_CLK>,
5222				 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
5223				 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
5224				 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
5225				 <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
5226				 <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
5227				 <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
5228				 <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
5229			clock-names = "cfg_noc",
5230				      "core",
5231				      "iface",
5232				      "sleep",
5233				      "mock_utmi",
5234				      "noc_aggr",
5235				      "noc_aggr_north",
5236				      "noc_aggr_south",
5237				      "noc_sys";
5238
5239			assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
5240					  <&gcc GCC_USB30_SEC_MASTER_CLK>;
5241			assigned-clock-rates = <19200000>,
5242					       <200000000>;
5243
5244			interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
5245					      <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
5246					      <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
5247					      <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
5248			interrupt-names = "pwr_event",
5249					  "dp_hs_phy_irq",
5250					  "dm_hs_phy_irq",
5251					  "ss_phy_irq";
5252
5253			power-domains = <&gcc GCC_USB30_SEC_GDSC>;
5254			required-opps = <&rpmhpd_opp_nom>;
5255
5256			resets = <&gcc GCC_USB30_SEC_BCR>;
5257
5258			interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
5259					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
5260					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
5261					 &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
5262			interconnect-names = "usb-ddr",
5263					     "apps-usb";
5264
5265			wakeup-source;
5266
5267			#address-cells = <2>;
5268			#size-cells = <2>;
5269			ranges;
5270
5271			status = "disabled";
5272
5273			usb_1_ss1_dwc3: usb@a800000 {
5274				compatible = "snps,dwc3";
5275				reg = <0 0x0a800000 0 0xcd00>;
5276
5277				interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
5278
5279				iommus = <&apps_smmu 0x1460 0x0>;
5280
5281				phys = <&usb_1_ss1_hsphy>,
5282				       <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
5283				phy-names = "usb2-phy",
5284					    "usb3-phy";
5285
5286				snps,dis_u2_susphy_quirk;
5287				snps,dis_enblslpm_quirk;
5288				snps,usb3_lpm_capable;
5289				snps,dis-u1-entry-quirk;
5290				snps,dis-u2-entry-quirk;
5291
5292				dma-coherent;
5293
5294				ports {
5295					#address-cells = <1>;
5296					#size-cells = <0>;
5297
5298					port@0 {
5299						reg = <0>;
5300
5301						usb_1_ss1_dwc3_hs: endpoint {
5302						};
5303					};
5304
5305					port@1 {
5306						reg = <1>;
5307
5308						usb_1_ss1_dwc3_ss: endpoint {
5309							remote-endpoint = <&usb_1_ss1_qmpphy_usb_ss_in>;
5310						};
5311					};
5312				};
5313			};
5314		};
5315
5316		iris: video-codec@aa00000 {
5317			compatible = "qcom,x1e80100-iris", "qcom,sm8550-iris";
5318
5319			reg = <0 0x0aa00000 0 0xf0000>;
5320			interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
5321
5322			power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
5323					<&videocc VIDEO_CC_MVS0_GDSC>,
5324					<&rpmhpd RPMHPD_MXC>,
5325					<&rpmhpd RPMHPD_MMCX>;
5326			power-domain-names = "venus",
5327					     "vcodec0",
5328					     "mxc",
5329					     "mmcx";
5330			operating-points-v2 = <&iris_opp_table>;
5331
5332			clocks = <&gcc GCC_VIDEO_AXI0_CLK>,
5333				 <&videocc VIDEO_CC_MVS0C_CLK>,
5334				 <&videocc VIDEO_CC_MVS0_CLK>;
5335			clock-names = "iface",
5336				      "core",
5337				      "vcodec0_core";
5338
5339			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
5340					 &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
5341					<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
5342					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
5343			interconnect-names = "cpu-cfg",
5344					     "video-mem";
5345
5346			memory-region = <&video_mem>;
5347
5348			resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>;
5349			reset-names = "bus";
5350
5351			iommus = <&apps_smmu 0x1940 0>,
5352				 <&apps_smmu 0x1947 0>;
5353			dma-coherent;
5354
5355			/*
5356			 * IRIS firmware is signed by vendors, only
5357			 * enable on boards where the proper signed firmware
5358			 * is available.
5359			 */
5360			status = "disabled";
5361
5362			iris_opp_table: opp-table {
5363				compatible = "operating-points-v2";
5364
5365				opp-192000000 {
5366					opp-hz = /bits/ 64 <192000000>;
5367					required-opps = <&rpmhpd_opp_low_svs_d1>,
5368							<&rpmhpd_opp_low_svs_d1>;
5369				};
5370
5371				opp-240000000 {
5372					opp-hz = /bits/ 64 <240000000>;
5373					required-opps = <&rpmhpd_opp_svs>,
5374							<&rpmhpd_opp_low_svs>;
5375				};
5376
5377				opp-338000000 {
5378					opp-hz = /bits/ 64 <338000000>;
5379					required-opps = <&rpmhpd_opp_svs>,
5380							<&rpmhpd_opp_svs>;
5381				};
5382
5383				opp-366000000 {
5384					opp-hz = /bits/ 64 <366000000>;
5385					required-opps = <&rpmhpd_opp_svs_l1>,
5386							<&rpmhpd_opp_svs_l1>;
5387				};
5388
5389				opp-444000000 {
5390					opp-hz = /bits/ 64 <444000000>;
5391					required-opps = <&rpmhpd_opp_nom>,
5392							<&rpmhpd_opp_nom>;
5393				};
5394
5395				opp-481000000 {
5396					opp-hz = /bits/ 64 <481000000>;
5397					required-opps = <&rpmhpd_opp_turbo>,
5398							<&rpmhpd_opp_turbo>;
5399				};
5400			};
5401		};
5402
5403		videocc: clock-controller@aaf0000 {
5404			compatible = "qcom,x1e80100-videocc";
5405			reg = <0 0x0aaf0000 0 0x10000>;
5406			clocks = <&bi_tcxo_div2>,
5407				 <&gcc GCC_VIDEO_AHB_CLK>;
5408			power-domains = <&rpmhpd RPMHPD_MMCX>,
5409					<&rpmhpd RPMHPD_MXC>;
5410			required-opps = <&rpmhpd_opp_low_svs>,
5411					<&rpmhpd_opp_low_svs>;
5412			#clock-cells = <1>;
5413			#reset-cells = <1>;
5414			#power-domain-cells = <1>;
5415		};
5416
5417		mdss: display-subsystem@ae00000 {
5418			compatible = "qcom,x1e80100-mdss";
5419			reg = <0 0x0ae00000 0 0x1000>;
5420			reg-names = "mdss";
5421
5422			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5423
5424			clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
5425				 <&gcc GCC_DISP_HF_AXI_CLK>,
5426				 <&dispcc DISP_CC_MDSS_MDP_CLK>;
5427
5428			resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
5429
5430			interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
5431					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
5432					<&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
5433					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
5434					<&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
5435					 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
5436			interconnect-names = "mdp0-mem",
5437					     "mdp1-mem",
5438					     "cpu-cfg";
5439
5440			power-domains = <&dispcc MDSS_GDSC>;
5441
5442			iommus = <&apps_smmu 0x1c00 0x2>;
5443
5444			interrupt-controller;
5445			#interrupt-cells = <1>;
5446
5447			#address-cells = <2>;
5448			#size-cells = <2>;
5449			ranges;
5450
5451			status = "disabled";
5452
5453			mdss_mdp: display-controller@ae01000 {
5454				compatible = "qcom,x1e80100-dpu";
5455				reg = <0 0x0ae01000 0 0x8f000>,
5456				      <0 0x0aeb0000 0 0x2008>;
5457				reg-names = "mdp",
5458					    "vbif";
5459
5460				interrupts-extended = <&mdss 0>;
5461
5462				clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
5463					 <&dispcc DISP_CC_MDSS_AHB_CLK>,
5464					 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
5465					 <&dispcc DISP_CC_MDSS_MDP_CLK>,
5466					 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
5467				clock-names = "nrt_bus",
5468					      "iface",
5469					      "lut",
5470					      "core",
5471					      "vsync";
5472
5473				operating-points-v2 = <&mdp_opp_table>;
5474
5475				power-domains = <&rpmhpd RPMHPD_MMCX>;
5476
5477				ports {
5478					#address-cells = <1>;
5479					#size-cells = <0>;
5480
5481					port@0 {
5482						reg = <0>;
5483
5484						mdss_intf0_out: endpoint {
5485							remote-endpoint = <&mdss_dp0_in>;
5486						};
5487					};
5488
5489					port@4 {
5490						reg = <4>;
5491
5492						mdss_intf4_out: endpoint {
5493							remote-endpoint = <&mdss_dp1_in>;
5494						};
5495					};
5496
5497					port@5 {
5498						reg = <5>;
5499
5500						mdss_intf5_out: endpoint {
5501							remote-endpoint = <&mdss_dp3_in>;
5502						};
5503					};
5504
5505					port@6 {
5506						reg = <6>;
5507
5508						mdss_intf6_out: endpoint {
5509							remote-endpoint = <&mdss_dp2_in>;
5510						};
5511					};
5512				};
5513
5514				mdp_opp_table: opp-table {
5515					compatible = "operating-points-v2";
5516
5517					opp-200000000 {
5518						opp-hz = /bits/ 64 <200000000>;
5519						required-opps = <&rpmhpd_opp_low_svs>;
5520					};
5521
5522					opp-325000000 {
5523						opp-hz = /bits/ 64 <325000000>;
5524						required-opps = <&rpmhpd_opp_svs>;
5525					};
5526
5527					opp-375000000 {
5528						opp-hz = /bits/ 64 <375000000>;
5529						required-opps = <&rpmhpd_opp_svs_l1>;
5530					};
5531
5532					opp-514000000 {
5533						opp-hz = /bits/ 64 <514000000>;
5534						required-opps = <&rpmhpd_opp_nom>;
5535					};
5536
5537					opp-575000000 {
5538						opp-hz = /bits/ 64 <575000000>;
5539						required-opps = <&rpmhpd_opp_nom_l1>;
5540					};
5541				};
5542			};
5543
5544			mdss_dp0: displayport-controller@ae90000 {
5545				compatible = "qcom,x1e80100-dp";
5546				reg = <0 0x0ae90000 0 0x200>,
5547				      <0 0x0ae90200 0 0x200>,
5548				      <0 0x0ae90400 0 0xc00>,
5549				      <0 0x0ae91000 0 0x400>,
5550				      <0 0x0ae91400 0 0x400>;
5551
5552				interrupts-extended = <&mdss 12>;
5553
5554				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
5555					 <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
5556					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
5557					 <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
5558					 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
5559					 <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
5560				clock-names = "core_iface",
5561					      "core_aux",
5562					      "ctrl_link",
5563					      "ctrl_link_iface",
5564					      "stream_pixel",
5565					      "stream_1_pixel";
5566
5567				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
5568						  <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
5569						  <&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>;
5570				assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5571							 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
5572							 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
5573
5574				operating-points-v2 = <&mdss_dp0_opp_table>;
5575
5576				power-domains = <&rpmhpd RPMHPD_MMCX>;
5577
5578				phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
5579				phy-names = "dp";
5580
5581				#sound-dai-cells = <0>;
5582
5583				status = "disabled";
5584
5585				ports {
5586					#address-cells = <1>;
5587					#size-cells = <0>;
5588
5589					port@0 {
5590						reg = <0>;
5591
5592						mdss_dp0_in: endpoint {
5593							remote-endpoint = <&mdss_intf0_out>;
5594						};
5595					};
5596
5597					port@1 {
5598						reg = <1>;
5599
5600						mdss_dp0_out: endpoint {
5601							data-lanes = <0 1 2 3>;
5602							remote-endpoint = <&usb_1_ss0_qmpphy_dp_in>;
5603						};
5604					};
5605				};
5606
5607				mdss_dp0_opp_table: opp-table {
5608					compatible = "operating-points-v2";
5609
5610					opp-160000000 {
5611						opp-hz = /bits/ 64 <160000000>;
5612						required-opps = <&rpmhpd_opp_low_svs>;
5613					};
5614
5615					opp-270000000 {
5616						opp-hz = /bits/ 64 <270000000>;
5617						required-opps = <&rpmhpd_opp_svs>;
5618					};
5619
5620					opp-540000000 {
5621						opp-hz = /bits/ 64 <540000000>;
5622						required-opps = <&rpmhpd_opp_svs_l1>;
5623					};
5624
5625					opp-810000000 {
5626						opp-hz = /bits/ 64 <810000000>;
5627						required-opps = <&rpmhpd_opp_nom>;
5628					};
5629				};
5630			};
5631
5632			mdss_dp1: displayport-controller@ae98000 {
5633				compatible = "qcom,x1e80100-dp";
5634				reg = <0 0x0ae98000 0 0x200>,
5635				      <0 0x0ae98200 0 0x200>,
5636				      <0 0x0ae98400 0 0xc00>,
5637				      <0 0x0ae99000 0 0x400>,
5638				      <0 0x0ae99400 0 0x400>;
5639
5640				interrupts-extended = <&mdss 13>;
5641
5642				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
5643					 <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
5644					 <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
5645					 <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
5646					 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>,
5647					 <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK>;
5648				clock-names = "core_iface",
5649					      "core_aux",
5650					      "ctrl_link",
5651					      "ctrl_link_iface",
5652					      "stream_pixel",
5653					      "stream_1_pixel";
5654
5655				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
5656						  <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>,
5657						  <&dispcc DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC>;
5658				assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5659							 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
5660							 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
5661
5662				operating-points-v2 = <&mdss_dp1_opp_table>;
5663
5664				power-domains = <&rpmhpd RPMHPD_MMCX>;
5665
5666				phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
5667				phy-names = "dp";
5668
5669				#sound-dai-cells = <0>;
5670
5671				status = "disabled";
5672
5673				ports {
5674					#address-cells = <1>;
5675					#size-cells = <0>;
5676
5677					port@0 {
5678						reg = <0>;
5679
5680						mdss_dp1_in: endpoint {
5681							remote-endpoint = <&mdss_intf4_out>;
5682						};
5683					};
5684
5685					port@1 {
5686						reg = <1>;
5687
5688						mdss_dp1_out: endpoint {
5689							data-lanes = <0 1 2 3>;
5690							remote-endpoint = <&usb_1_ss1_qmpphy_dp_in>;
5691						};
5692					};
5693				};
5694
5695				mdss_dp1_opp_table: opp-table {
5696					compatible = "operating-points-v2";
5697
5698					opp-160000000 {
5699						opp-hz = /bits/ 64 <160000000>;
5700						required-opps = <&rpmhpd_opp_low_svs>;
5701					};
5702
5703					opp-270000000 {
5704						opp-hz = /bits/ 64 <270000000>;
5705						required-opps = <&rpmhpd_opp_svs>;
5706					};
5707
5708					opp-540000000 {
5709						opp-hz = /bits/ 64 <540000000>;
5710						required-opps = <&rpmhpd_opp_svs_l1>;
5711					};
5712
5713					opp-810000000 {
5714						opp-hz = /bits/ 64 <810000000>;
5715						required-opps = <&rpmhpd_opp_nom>;
5716					};
5717				};
5718			};
5719
5720			mdss_dp2: displayport-controller@ae9a000 {
5721				compatible = "qcom,x1e80100-dp";
5722				reg = <0 0x0ae9a000 0 0x200>,
5723				      <0 0x0ae9a200 0 0x200>,
5724				      <0 0x0ae9a400 0 0xc00>,
5725				      <0 0x0ae9b000 0 0x400>,
5726				      <0 0x0ae9b400 0 0x400>;
5727
5728				interrupts-extended = <&mdss 14>;
5729
5730				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
5731					 <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
5732					 <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
5733					 <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
5734					 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>,
5735					 <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK>;
5736				clock-names = "core_iface",
5737					      "core_aux",
5738					      "ctrl_link",
5739					      "ctrl_link_iface",
5740					      "stream_pixel",
5741					      "stream_1_pixel";
5742
5743				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
5744						  <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>,
5745						  <&dispcc DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC>;
5746				assigned-clock-parents = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>,
5747							 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
5748							 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
5749
5750				operating-points-v2 = <&mdss_dp2_opp_table>;
5751
5752				power-domains = <&rpmhpd RPMHPD_MMCX>;
5753
5754				phys = <&usb_1_ss2_qmpphy QMP_USB43DP_DP_PHY>;
5755				phy-names = "dp";
5756
5757				#sound-dai-cells = <0>;
5758
5759				status = "disabled";
5760
5761				ports {
5762					#address-cells = <1>;
5763					#size-cells = <0>;
5764
5765					port@0 {
5766						reg = <0>;
5767						mdss_dp2_in: endpoint {
5768							remote-endpoint = <&mdss_intf6_out>;
5769						};
5770					};
5771
5772					port@1 {
5773						reg = <1>;
5774
5775						mdss_dp2_out: endpoint {
5776							data-lanes = <0 1 2 3>;
5777							remote-endpoint = <&usb_1_ss2_qmpphy_dp_in>;
5778						};
5779					};
5780				};
5781
5782				mdss_dp2_opp_table: opp-table {
5783					compatible = "operating-points-v2";
5784
5785					opp-160000000 {
5786						opp-hz = /bits/ 64 <160000000>;
5787						required-opps = <&rpmhpd_opp_low_svs>;
5788					};
5789
5790					opp-270000000 {
5791						opp-hz = /bits/ 64 <270000000>;
5792						required-opps = <&rpmhpd_opp_svs>;
5793					};
5794
5795					opp-540000000 {
5796						opp-hz = /bits/ 64 <540000000>;
5797						required-opps = <&rpmhpd_opp_svs_l1>;
5798					};
5799
5800					opp-810000000 {
5801						opp-hz = /bits/ 64 <810000000>;
5802						required-opps = <&rpmhpd_opp_nom>;
5803					};
5804				};
5805			};
5806
5807			mdss_dp3: displayport-controller@aea0000 {
5808				compatible = "qcom,x1e80100-dp";
5809				reg = <0 0x0aea0000 0 0x200>,
5810				      <0 0x0aea0200 0 0x200>,
5811				      <0 0x0aea0400 0 0xc00>,
5812				      <0 0x0aea1000 0 0x400>,
5813				      <0 0x0aea1400 0 0x400>;
5814
5815				interrupts-extended = <&mdss 15>;
5816
5817				clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
5818					 <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
5819					 <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
5820					 <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
5821					 <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
5822				clock-names = "core_iface",
5823					      "core_aux",
5824					      "ctrl_link",
5825					      "ctrl_link_iface",
5826					      "stream_pixel";
5827
5828				assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
5829						  <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
5830				assigned-clock-parents = <&mdss_dp3_phy 0>,
5831							 <&mdss_dp3_phy 1>;
5832
5833				operating-points-v2 = <&mdss_dp3_opp_table>;
5834
5835				power-domains = <&rpmhpd RPMHPD_MMCX>;
5836
5837				phys = <&mdss_dp3_phy>;
5838				phy-names = "dp";
5839
5840				#sound-dai-cells = <0>;
5841
5842				status = "disabled";
5843
5844				ports {
5845					#address-cells = <1>;
5846					#size-cells = <0>;
5847
5848					port@0 {
5849						reg = <0>;
5850
5851						mdss_dp3_in: endpoint {
5852							remote-endpoint = <&mdss_intf5_out>;
5853						};
5854					};
5855
5856					port@1 {
5857						reg = <1>;
5858
5859						mdss_dp3_out: endpoint {
5860						};
5861					};
5862				};
5863
5864				mdss_dp3_opp_table: opp-table {
5865					compatible = "operating-points-v2";
5866
5867					opp-160000000 {
5868						opp-hz = /bits/ 64 <160000000>;
5869						required-opps = <&rpmhpd_opp_low_svs>;
5870					};
5871
5872					opp-270000000 {
5873						opp-hz = /bits/ 64 <270000000>;
5874						required-opps = <&rpmhpd_opp_svs>;
5875					};
5876
5877					opp-540000000 {
5878						opp-hz = /bits/ 64 <540000000>;
5879						required-opps = <&rpmhpd_opp_svs_l1>;
5880					};
5881
5882					opp-810000000 {
5883						opp-hz = /bits/ 64 <810000000>;
5884						required-opps = <&rpmhpd_opp_nom>;
5885					};
5886				};
5887			};
5888
5889		};
5890
5891		mdss_dp2_phy: phy@aec2a00 {
5892			compatible = "qcom,x1e80100-dp-phy";
5893			reg = <0 0x0aec2a00 0 0x19c>,
5894			      <0 0x0aec2200 0 0xec>,
5895			      <0 0x0aec2600 0 0xec>,
5896			      <0 0x0aec2000 0 0x1c8>;
5897
5898			clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
5899				 <&dispcc DISP_CC_MDSS_AHB_CLK>,
5900				 <&tcsr TCSR_EDP_CLKREF_EN>;
5901			clock-names = "aux",
5902				      "cfg_ahb",
5903				      "ref";
5904
5905			power-domains = <&rpmhpd RPMHPD_MX>;
5906
5907			#clock-cells = <1>;
5908			#phy-cells = <0>;
5909
5910			status = "disabled";
5911		};
5912
5913		mdss_dp3_phy: phy@aec5a00 {
5914			compatible = "qcom,x1e80100-dp-phy";
5915			reg = <0 0x0aec5a00 0 0x19c>,
5916			      <0 0x0aec5200 0 0xec>,
5917			      <0 0x0aec5600 0 0xec>,
5918			      <0 0x0aec5000 0 0x1c8>;
5919
5920			clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
5921				 <&dispcc DISP_CC_MDSS_AHB_CLK>,
5922				 <&tcsr TCSR_EDP_CLKREF_EN>;
5923			clock-names = "aux",
5924				      "cfg_ahb",
5925				      "ref";
5926
5927			power-domains = <&rpmhpd RPMHPD_MX>;
5928
5929			#clock-cells = <1>;
5930			#phy-cells = <0>;
5931
5932			status = "disabled";
5933		};
5934
5935		dispcc: clock-controller@af00000 {
5936			compatible = "qcom,x1e80100-dispcc";
5937			reg = <0 0x0af00000 0 0x20000>;
5938			clocks = <&bi_tcxo_div2>,
5939				 <&bi_tcxo_ao_div2>,
5940				 <&gcc GCC_DISP_AHB_CLK>,
5941				 <&sleep_clk>,
5942				 <0>, /* dsi0 */
5943				 <0>,
5944				 <0>, /* dsi1 */
5945				 <0>,
5946				 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
5947				 <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
5948				 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
5949				 <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
5950				 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp2 */
5951				 <&usb_1_ss2_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
5952				 <&mdss_dp3_phy 0>, /* dp3 */
5953				 <&mdss_dp3_phy 1>;
5954			power-domains = <&rpmhpd RPMHPD_MMCX>;
5955			required-opps = <&rpmhpd_opp_low_svs>;
5956			#clock-cells = <1>;
5957			#reset-cells = <1>;
5958			#power-domain-cells = <1>;
5959		};
5960
5961		pdc: interrupt-controller@b220000 {
5962			compatible = "qcom,x1e80100-pdc", "qcom,pdc";
5963			reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
5964
5965			qcom,pdc-ranges = <0 480 42>, <42 251 5>,
5966					  <47 522 52>, <99 609 32>,
5967					  <131 717 12>, <143 816 19>;
5968			#interrupt-cells = <2>;
5969			interrupt-parent = <&intc>;
5970			interrupt-controller;
5971		};
5972
5973		aoss_qmp: power-management@c300000 {
5974			compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
5975			reg = <0 0x0c300000 0 0x400>;
5976			interrupt-parent = <&ipcc>;
5977			interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
5978						     IRQ_TYPE_EDGE_RISING>;
5979			mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
5980
5981			#clock-cells = <0>;
5982		};
5983
5984		sram@c3f0000 {
5985			compatible = "qcom,rpmh-stats";
5986			reg = <0 0x0c3f0000 0 0x400>;
5987		};
5988
5989		spmi: arbiter@c400000 {
5990			compatible = "qcom,x1e80100-spmi-pmic-arb";
5991			reg = <0 0x0c400000 0 0x3000>,
5992			      <0 0x0c500000 0 0x400000>,
5993			      <0 0x0c440000 0 0x80000>;
5994			reg-names = "core", "chnls", "obsrvr";
5995
5996			qcom,ee = <0>;
5997			qcom,channel = <0>;
5998
5999			#address-cells = <2>;
6000			#size-cells = <2>;
6001			ranges;
6002
6003			spmi_bus0: spmi@c42d000 {
6004				reg = <0 0x0c42d000 0 0x4000>,
6005				      <0 0x0c4c0000 0 0x10000>;
6006				reg-names = "cnfg", "intr";
6007
6008				interrupt-names = "periph_irq";
6009				interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
6010				interrupt-controller;
6011				#interrupt-cells = <4>;
6012
6013				#address-cells = <2>;
6014				#size-cells = <0>;
6015			};
6016
6017			spmi_bus1: spmi@c432000 {
6018				reg = <0 0x0c432000 0 0x4000>,
6019				      <0 0x0c4d0000 0 0x10000>;
6020				reg-names = "cnfg", "intr";
6021
6022				interrupt-names = "periph_irq";
6023				interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
6024				interrupt-controller;
6025				#interrupt-cells = <4>;
6026
6027				#address-cells = <2>;
6028				#size-cells = <0>;
6029			};
6030		};
6031
6032		tlmm: pinctrl@f100000 {
6033			compatible = "qcom,x1e80100-tlmm";
6034			reg = <0 0x0f100000 0 0xf00000>;
6035
6036			interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
6037
6038			gpio-controller;
6039			#gpio-cells = <2>;
6040
6041			interrupt-controller;
6042			#interrupt-cells = <2>;
6043
6044			gpio-ranges = <&tlmm 0 0 239>;
6045			wakeup-parent = <&pdc>;
6046
6047			edp0_hpd_default: edp0-hpd-default-state {
6048				pins = "gpio119";
6049				function = "edp0_hot";
6050				bias-disable;
6051			};
6052
6053			qup_i2c0_data_clk: qup-i2c0-data-clk-state {
6054				/* SDA, SCL */
6055				pins = "gpio0", "gpio1";
6056				function = "qup0_se0";
6057				drive-strength = <2>;
6058				bias-pull-up = <2200>;
6059			};
6060
6061			qup_i2c1_data_clk: qup-i2c1-data-clk-state {
6062				/* SDA, SCL */
6063				pins = "gpio4", "gpio5";
6064				function = "qup0_se1";
6065				drive-strength = <2>;
6066				bias-pull-up = <2200>;
6067			};
6068
6069			qup_i2c2_data_clk: qup-i2c2-data-clk-state {
6070				/* SDA, SCL */
6071				pins = "gpio8", "gpio9";
6072				function = "qup0_se2";
6073				drive-strength = <2>;
6074				bias-pull-up = <2200>;
6075			};
6076
6077			qup_i2c3_data_clk: qup-i2c3-data-clk-state {
6078				/* SDA, SCL */
6079				pins = "gpio12", "gpio13";
6080				function = "qup0_se3";
6081				drive-strength = <2>;
6082				bias-pull-up = <2200>;
6083			};
6084
6085			qup_i2c4_data_clk: qup-i2c4-data-clk-state {
6086				/* SDA, SCL */
6087				pins = "gpio16", "gpio17";
6088				function = "qup0_se4";
6089				drive-strength = <2>;
6090				bias-pull-up = <2200>;
6091			};
6092
6093			qup_i2c5_data_clk: qup-i2c5-data-clk-state {
6094				/* SDA, SCL */
6095				pins = "gpio20", "gpio21";
6096				function = "qup0_se5";
6097				drive-strength = <2>;
6098				bias-pull-up = <2200>;
6099			};
6100
6101			qup_i2c6_data_clk: qup-i2c6-data-clk-state {
6102				/* SDA, SCL */
6103				pins = "gpio24", "gpio25";
6104				function = "qup0_se6";
6105				drive-strength = <2>;
6106				bias-pull-up = <2200>;
6107			};
6108
6109			qup_i2c7_data_clk: qup-i2c7-data-clk-state {
6110				/* SDA, SCL */
6111				pins = "gpio14", "gpio15";
6112				function = "qup0_se7";
6113				drive-strength = <2>;
6114				bias-pull-up = <2200>;
6115			};
6116
6117			qup_i2c8_data_clk: qup-i2c8-data-clk-state {
6118				/* SDA, SCL */
6119				pins = "gpio32", "gpio33";
6120				function = "qup1_se0";
6121				drive-strength = <2>;
6122				bias-pull-up = <2200>;
6123			};
6124
6125			qup_i2c9_data_clk: qup-i2c9-data-clk-state {
6126				/* SDA, SCL */
6127				pins = "gpio36", "gpio37";
6128				function = "qup1_se1";
6129				drive-strength = <2>;
6130				bias-pull-up = <2200>;
6131			};
6132
6133			qup_i2c10_data_clk: qup-i2c10-data-clk-state {
6134				/* SDA, SCL */
6135				pins = "gpio40", "gpio41";
6136				function = "qup1_se2";
6137				drive-strength = <2>;
6138				bias-pull-up = <2200>;
6139			};
6140
6141			qup_i2c11_data_clk: qup-i2c11-data-clk-state {
6142				/* SDA, SCL */
6143				pins = "gpio44", "gpio45";
6144				function = "qup1_se3";
6145				drive-strength = <2>;
6146				bias-pull-up = <2200>;
6147			};
6148
6149			qup_i2c12_data_clk: qup-i2c12-data-clk-state {
6150				/* SDA, SCL */
6151				pins = "gpio48", "gpio49";
6152				function = "qup1_se4";
6153				drive-strength = <2>;
6154				bias-pull-up = <2200>;
6155			};
6156
6157			qup_i2c13_data_clk: qup-i2c13-data-clk-state {
6158				/* SDA, SCL */
6159				pins = "gpio52", "gpio53";
6160				function = "qup1_se5";
6161				drive-strength = <2>;
6162				bias-pull-up = <2200>;
6163			};
6164
6165			qup_i2c14_data_clk: qup-i2c14-data-clk-state {
6166				/* SDA, SCL */
6167				pins = "gpio56", "gpio57";
6168				function = "qup1_se6";
6169				drive-strength = <2>;
6170				bias-pull-up = <2200>;
6171			};
6172
6173			qup_i2c15_data_clk: qup-i2c15-data-clk-state {
6174				/* SDA, SCL */
6175				pins = "gpio54", "gpio55";
6176				function = "qup1_se7";
6177				drive-strength = <2>;
6178				bias-pull-up = <2200>;
6179			};
6180
6181			qup_i2c16_data_clk: qup-i2c16-data-clk-state {
6182				/* SDA, SCL */
6183				pins = "gpio64", "gpio65";
6184				function = "qup2_se0";
6185				drive-strength = <2>;
6186				bias-pull-up = <2200>;
6187			};
6188
6189			qup_i2c17_data_clk: qup-i2c17-data-clk-state {
6190				/* SDA, SCL */
6191				pins = "gpio68", "gpio69";
6192				function = "qup2_se1";
6193				drive-strength = <2>;
6194				bias-pull-up = <2200>;
6195			};
6196
6197			qup_i2c18_data_clk: qup-i2c18-data-clk-state {
6198				/* SDA, SCL */
6199				pins = "gpio72", "gpio73";
6200				function = "qup2_se2";
6201				drive-strength = <2>;
6202				bias-pull-up = <2200>;
6203			};
6204
6205			qup_i2c19_data_clk: qup-i2c19-data-clk-state {
6206				/* SDA, SCL */
6207				pins = "gpio76", "gpio77";
6208				function = "qup2_se3";
6209				drive-strength = <2>;
6210				bias-pull-up = <2200>;
6211			};
6212
6213			qup_i2c20_data_clk: qup-i2c20-data-clk-state {
6214				/* SDA, SCL */
6215				pins = "gpio80", "gpio81";
6216				function = "qup2_se4";
6217				drive-strength = <2>;
6218				bias-pull-up = <2200>;
6219			};
6220
6221			qup_i2c21_data_clk: qup-i2c21-data-clk-state {
6222				/* SDA, SCL */
6223				pins = "gpio84", "gpio85";
6224				function = "qup2_se5";
6225				drive-strength = <2>;
6226				bias-pull-up = <2200>;
6227			};
6228
6229			qup_i2c22_data_clk: qup-i2c22-data-clk-state {
6230				/* SDA, SCL */
6231				pins = "gpio88", "gpio89";
6232				function = "qup2_se6";
6233				drive-strength = <2>;
6234				bias-pull-up = <2200>;
6235			};
6236
6237			qup_i2c23_data_clk: qup-i2c23-data-clk-state {
6238				/* SDA, SCL */
6239				pins = "gpio86", "gpio87";
6240				function = "qup2_se7";
6241				drive-strength = <2>;
6242				bias-pull-up = <2200>;
6243			};
6244
6245			qup_spi0_cs: qup-spi0-cs-state {
6246				pins = "gpio3";
6247				function = "qup0_se0";
6248				drive-strength = <6>;
6249				bias-disable;
6250			};
6251
6252			qup_spi0_data_clk: qup-spi0-data-clk-state {
6253				/* MISO, MOSI, CLK */
6254				pins = "gpio0", "gpio1", "gpio2";
6255				function = "qup0_se0";
6256				drive-strength = <6>;
6257				bias-disable;
6258			};
6259
6260			qup_spi1_cs: qup-spi1-cs-state {
6261				pins = "gpio7";
6262				function = "qup0_se1";
6263				drive-strength = <6>;
6264				bias-disable;
6265			};
6266
6267			qup_spi1_data_clk: qup-spi1-data-clk-state {
6268				/* MISO, MOSI, CLK */
6269				pins = "gpio4", "gpio5", "gpio6";
6270				function = "qup0_se1";
6271				drive-strength = <6>;
6272				bias-disable;
6273			};
6274
6275			qup_spi2_cs: qup-spi2-cs-state {
6276				pins = "gpio11";
6277				function = "qup0_se2";
6278				drive-strength = <6>;
6279				bias-disable;
6280			};
6281
6282			qup_spi2_data_clk: qup-spi2-data-clk-state {
6283				/* MISO, MOSI, CLK */
6284				pins = "gpio8", "gpio9", "gpio10";
6285				function = "qup0_se2";
6286				drive-strength = <6>;
6287				bias-disable;
6288			};
6289
6290			qup_spi3_cs: qup-spi3-cs-state {
6291				pins = "gpio15";
6292				function = "qup0_se3";
6293				drive-strength = <6>;
6294				bias-disable;
6295			};
6296
6297			qup_spi3_data_clk: qup-spi3-data-clk-state {
6298				/* MISO, MOSI, CLK */
6299				pins = "gpio12", "gpio13", "gpio14";
6300				function = "qup0_se3";
6301				drive-strength = <6>;
6302				bias-disable;
6303			};
6304
6305			qup_spi4_cs: qup-spi4-cs-state {
6306				pins = "gpio19";
6307				function = "qup0_se4";
6308				drive-strength = <6>;
6309				bias-disable;
6310			};
6311
6312			qup_spi4_data_clk: qup-spi4-data-clk-state {
6313				/* MISO, MOSI, CLK */
6314				pins = "gpio16", "gpio17", "gpio18";
6315				function = "qup0_se4";
6316				drive-strength = <6>;
6317				bias-disable;
6318			};
6319
6320			qup_spi5_cs: qup-spi5-cs-state {
6321				pins = "gpio23";
6322				function = "qup0_se5";
6323				drive-strength = <6>;
6324				bias-disable;
6325			};
6326
6327			qup_spi5_data_clk: qup-spi5-data-clk-state {
6328				/* MISO, MOSI, CLK */
6329				pins = "gpio20", "gpio21", "gpio22";
6330				function = "qup0_se5";
6331				drive-strength = <6>;
6332				bias-disable;
6333			};
6334
6335			qup_spi6_cs: qup-spi6-cs-state {
6336				pins = "gpio27";
6337				function = "qup0_se6";
6338				drive-strength = <6>;
6339				bias-disable;
6340			};
6341
6342			qup_spi6_data_clk: qup-spi6-data-clk-state {
6343				/* MISO, MOSI, CLK */
6344				pins = "gpio24", "gpio25", "gpio26";
6345				function = "qup0_se6";
6346				drive-strength = <6>;
6347				bias-disable;
6348			};
6349
6350			qup_spi7_cs: qup-spi7-cs-state {
6351				pins = "gpio13";
6352				function = "qup0_se7";
6353				drive-strength = <6>;
6354				bias-disable;
6355			};
6356
6357			qup_spi7_data_clk: qup-spi7-data-clk-state {
6358				/* MISO, MOSI, CLK */
6359				pins = "gpio14", "gpio15", "gpio12";
6360				function = "qup0_se7";
6361				drive-strength = <6>;
6362				bias-disable;
6363			};
6364
6365			qup_spi8_cs: qup-spi8-cs-state {
6366				pins = "gpio35";
6367				function = "qup1_se0";
6368				drive-strength = <6>;
6369				bias-disable;
6370			};
6371
6372			qup_spi8_data_clk: qup-spi8-data-clk-state {
6373				/* MISO, MOSI, CLK */
6374				pins = "gpio32", "gpio33", "gpio34";
6375				function = "qup1_se0";
6376				drive-strength = <6>;
6377				bias-disable;
6378			};
6379
6380			qup_spi9_cs: qup-spi9-cs-state {
6381				pins = "gpio39";
6382				function = "qup1_se1";
6383				drive-strength = <6>;
6384				bias-disable;
6385			};
6386
6387			qup_spi9_data_clk: qup-spi9-data-clk-state {
6388				/* MISO, MOSI, CLK */
6389				pins = "gpio36", "gpio37", "gpio38";
6390				function = "qup1_se1";
6391				drive-strength = <6>;
6392				bias-disable;
6393			};
6394
6395			qup_spi10_cs: qup-spi10-cs-state {
6396				pins = "gpio43";
6397				function = "qup1_se2";
6398				drive-strength = <6>;
6399				bias-disable;
6400			};
6401
6402			qup_spi10_data_clk: qup-spi10-data-clk-state {
6403				/* MISO, MOSI, CLK */
6404				pins = "gpio40", "gpio41", "gpio42";
6405				function = "qup1_se2";
6406				drive-strength = <6>;
6407				bias-disable;
6408			};
6409
6410			qup_spi11_cs: qup-spi11-cs-state {
6411				pins = "gpio47";
6412				function = "qup1_se3";
6413				drive-strength = <6>;
6414				bias-disable;
6415			};
6416
6417			qup_spi11_data_clk: qup-spi11-data-clk-state {
6418				/* MISO, MOSI, CLK */
6419				pins = "gpio44", "gpio45", "gpio46";
6420				function = "qup1_se3";
6421				drive-strength = <6>;
6422				bias-disable;
6423			};
6424
6425			qup_spi12_cs: qup-spi12-cs-state {
6426				pins = "gpio51";
6427				function = "qup1_se4";
6428				drive-strength = <6>;
6429				bias-disable;
6430			};
6431
6432			qup_spi12_data_clk: qup-spi12-data-clk-state {
6433				/* MISO, MOSI, CLK */
6434				pins = "gpio48", "gpio49", "gpio50";
6435				function = "qup1_se4";
6436				drive-strength = <6>;
6437				bias-disable;
6438			};
6439
6440			qup_spi13_cs: qup-spi13-cs-state {
6441				pins = "gpio55";
6442				function = "qup1_se5";
6443				drive-strength = <6>;
6444				bias-disable;
6445			};
6446
6447			qup_spi13_data_clk: qup-spi13-data-clk-state {
6448				/* MISO, MOSI, CLK */
6449				pins = "gpio52", "gpio53", "gpio54";
6450				function = "qup1_se5";
6451				drive-strength = <6>;
6452				bias-disable;
6453			};
6454
6455			qup_spi14_cs: qup-spi14-cs-state {
6456				pins = "gpio59";
6457				function = "qup1_se6";
6458				drive-strength = <6>;
6459				bias-disable;
6460			};
6461
6462			qup_spi14_data_clk: qup-spi14-data-clk-state {
6463				/* MISO, MOSI, CLK */
6464				pins = "gpio56", "gpio57", "gpio58";
6465				function = "qup1_se6";
6466				drive-strength = <6>;
6467				bias-disable;
6468			};
6469
6470			qup_spi15_cs: qup-spi15-cs-state {
6471				pins = "gpio53";
6472				function = "qup1_se7";
6473				drive-strength = <6>;
6474				bias-disable;
6475			};
6476
6477			qup_spi15_data_clk: qup-spi15-data-clk-state {
6478				/* MISO, MOSI, CLK */
6479				pins = "gpio54", "gpio55", "gpio52";
6480				function = "qup1_se7";
6481				drive-strength = <6>;
6482				bias-disable;
6483			};
6484
6485			qup_spi16_cs: qup-spi16-cs-state {
6486				pins = "gpio67";
6487				function = "qup2_se0";
6488				drive-strength = <6>;
6489				bias-disable;
6490			};
6491
6492			qup_spi16_data_clk: qup-spi16-data-clk-state {
6493				/* MISO, MOSI, CLK */
6494				pins = "gpio64", "gpio65", "gpio66";
6495				function = "qup2_se0";
6496				drive-strength = <6>;
6497				bias-disable;
6498			};
6499
6500			qup_spi17_cs: qup-spi17-cs-state {
6501				pins = "gpio71";
6502				function = "qup2_se1";
6503				drive-strength = <6>;
6504				bias-disable;
6505			};
6506
6507			qup_spi17_data_clk: qup-spi17-data-clk-state {
6508				/* MISO, MOSI, CLK */
6509				pins = "gpio68", "gpio69", "gpio70";
6510				function = "qup2_se1";
6511				drive-strength = <6>;
6512				bias-disable;
6513			};
6514
6515			qup_spi18_cs: qup-spi18-cs-state {
6516				pins = "gpio75";
6517				function = "qup2_se2";
6518				drive-strength = <6>;
6519				bias-disable;
6520			};
6521
6522			qup_spi18_data_clk: qup-spi18-data-clk-state {
6523				/* MISO, MOSI, CLK */
6524				pins = "gpio72", "gpio73", "gpio74";
6525				function = "qup2_se2";
6526				drive-strength = <6>;
6527				bias-disable;
6528			};
6529
6530			qup_spi19_cs: qup-spi19-cs-state {
6531				pins = "gpio79";
6532				function = "qup2_se3";
6533				drive-strength = <6>;
6534				bias-disable;
6535			};
6536
6537			qup_spi19_data_clk: qup-spi19-data-clk-state {
6538				/* MISO, MOSI, CLK */
6539				pins = "gpio76", "gpio77", "gpio78";
6540				function = "qup2_se3";
6541				drive-strength = <6>;
6542				bias-disable;
6543			};
6544
6545			qup_spi20_cs: qup-spi20-cs-state {
6546				pins = "gpio83";
6547				function = "qup2_se4";
6548				drive-strength = <6>;
6549				bias-disable;
6550			};
6551
6552			qup_spi20_data_clk: qup-spi20-data-clk-state {
6553				/* MISO, MOSI, CLK */
6554				pins = "gpio80", "gpio81", "gpio82";
6555				function = "qup2_se4";
6556				drive-strength = <6>;
6557				bias-disable;
6558			};
6559
6560			qup_spi21_cs: qup-spi21-cs-state {
6561				pins = "gpio87";
6562				function = "qup2_se5";
6563				drive-strength = <6>;
6564				bias-disable;
6565			};
6566
6567			qup_spi21_data_clk: qup-spi21-data-clk-state {
6568				/* MISO, MOSI, CLK */
6569				pins = "gpio84", "gpio85", "gpio86";
6570				function = "qup2_se5";
6571				drive-strength = <6>;
6572				bias-disable;
6573			};
6574
6575			qup_spi22_cs: qup-spi22-cs-state {
6576				pins = "gpio91";
6577				function = "qup2_se6";
6578				drive-strength = <6>;
6579				bias-disable;
6580			};
6581
6582			qup_spi22_data_clk: qup-spi22-data-clk-state {
6583				/* MISO, MOSI, CLK */
6584				pins = "gpio88", "gpio89", "gpio90";
6585				function = "qup2_se6";
6586				drive-strength = <6>;
6587				bias-disable;
6588			};
6589
6590			qup_spi23_cs: qup-spi23-cs-state {
6591				pins = "gpio85";
6592				function = "qup2_se7";
6593				drive-strength = <6>;
6594				bias-disable;
6595			};
6596
6597			qup_spi23_data_clk: qup-spi23-data-clk-state {
6598				/* MISO, MOSI, CLK */
6599				pins = "gpio86", "gpio87", "gpio84";
6600				function = "qup2_se7";
6601				drive-strength = <6>;
6602				bias-disable;
6603			};
6604
6605			qup_uart2_default: qup-uart2-default-state {
6606				cts-pins {
6607					pins = "gpio8";
6608					function = "qup0_se2";
6609					drive-strength = <2>;
6610					bias-disable;
6611				};
6612
6613				rts-pins {
6614					pins = "gpio9";
6615					function = "qup0_se2";
6616					drive-strength = <2>;
6617					bias-disable;
6618				};
6619
6620				tx-pins {
6621					pins = "gpio10";
6622					function = "qup0_se2";
6623					drive-strength = <2>;
6624					bias-disable;
6625				};
6626
6627				rx-pins {
6628					pins = "gpio11";
6629					function = "qup0_se2";
6630					drive-strength = <2>;
6631					bias-disable;
6632				};
6633			};
6634
6635			qup_uart14_default: qup-uart14-default-state {
6636				cts-pins {
6637					pins = "gpio56";
6638					function = "qup1_se6";
6639					bias-bus-hold;
6640				};
6641
6642				rts-pins {
6643					pins = "gpio57";
6644					function = "qup1_se6";
6645					drive-strength = <2>;
6646					bias-disable;
6647				};
6648
6649				tx-pins {
6650					pins = "gpio58";
6651					function = "qup1_se6";
6652					drive-strength = <2>;
6653					bias-disable;
6654				};
6655
6656				rx-pins {
6657					pins = "gpio59";
6658					function = "qup1_se6";
6659					bias-pull-up;
6660				};
6661			};
6662
6663			qup_uart21_default: qup-uart21-default-state {
6664				tx-pins {
6665					pins = "gpio86";
6666					function = "qup2_se5";
6667					drive-strength = <2>;
6668					bias-disable;
6669				};
6670
6671				rx-pins {
6672					pins = "gpio87";
6673					function = "qup2_se5";
6674					drive-strength = <2>;
6675					bias-disable;
6676				};
6677			};
6678
6679			sdc2_default: sdc2-default-state {
6680				clk-pins {
6681					pins = "sdc2_clk";
6682					drive-strength = <16>;
6683					bias-disable;
6684				};
6685
6686				cmd-pins {
6687					pins = "sdc2_cmd";
6688					drive-strength = <10>;
6689					bias-pull-up;
6690				};
6691
6692				data-pins {
6693					pins = "sdc2_data";
6694					drive-strength = <10>;
6695					bias-pull-up;
6696				};
6697			};
6698
6699			sdc2_sleep: sdc2-sleep-state {
6700				clk-pins {
6701					pins = "sdc2_clk";
6702					drive-strength = <2>;
6703					bias-disable;
6704				};
6705
6706				cmd-pins {
6707					pins = "sdc2_cmd";
6708					drive-strength = <2>;
6709					bias-pull-up;
6710				};
6711
6712				data-pins {
6713					pins = "sdc2_data";
6714					drive-strength = <2>;
6715					bias-pull-up;
6716				};
6717			};
6718		};
6719
6720		stm@10002000 {
6721			compatible = "arm,coresight-stm", "arm,primecell";
6722			reg = <0x0 0x10002000 0x0 0x1000>,
6723			      <0x0 0x16280000 0x0 0x180000>;
6724			reg-names = "stm-base",
6725				    "stm-stimulus-base";
6726
6727			clocks = <&aoss_qmp>;
6728			clock-names = "apb_pclk";
6729
6730			out-ports {
6731				port {
6732					stm_out: endpoint {
6733						remote-endpoint = <&funnel0_in7>;
6734					};
6735				};
6736			};
6737		};
6738
6739		tpdm@10003000 {
6740			compatible = "qcom,coresight-tpdm", "arm,primecell";
6741			reg = <0x0 0x10003000 0x0 0x1000>;
6742
6743			clocks = <&aoss_qmp>;
6744			clock-names = "apb_pclk";
6745
6746			qcom,cmb-element-bits = <32>;
6747			qcom,cmb-msrs-num = <32>;
6748			status = "disabled";
6749
6750			out-ports {
6751				port {
6752					dcc_tpdm_out: endpoint {
6753						remote-endpoint = <&qdss_tpda_in0>;
6754					};
6755				};
6756			};
6757		};
6758
6759		tpda@10004000 {
6760			compatible = "qcom,coresight-tpda", "arm,primecell";
6761			reg = <0x0 0x10004000 0x0 0x1000>;
6762
6763			clocks = <&aoss_qmp>;
6764			clock-names = "apb_pclk";
6765
6766			in-ports {
6767				#address-cells = <1>;
6768				#size-cells = <0>;
6769
6770				port@0 {
6771					reg = <0>;
6772
6773					qdss_tpda_in0: endpoint {
6774						remote-endpoint = <&dcc_tpdm_out>;
6775					};
6776				};
6777
6778				port@1 {
6779					reg = <1>;
6780
6781					qdss_tpda_in1: endpoint {
6782						remote-endpoint = <&qdss_tpdm_out>;
6783					};
6784				};
6785			};
6786
6787			out-ports {
6788				port {
6789					qdss_tpda_out: endpoint {
6790						remote-endpoint = <&funnel0_in6>;
6791					};
6792				};
6793			};
6794		};
6795
6796		tpdm@1000f000 {
6797			compatible = "qcom,coresight-tpdm", "arm,primecell";
6798			reg = <0x0 0x1000f000 0x0 0x1000>;
6799
6800			clocks = <&aoss_qmp>;
6801			clock-names = "apb_pclk";
6802
6803			qcom,cmb-element-bits = <32>;
6804			qcom,cmb-msrs-num = <32>;
6805
6806			out-ports {
6807				port {
6808					qdss_tpdm_out: endpoint {
6809						remote-endpoint = <&qdss_tpda_in1>;
6810					};
6811				};
6812			};
6813		};
6814
6815		funnel@10041000 {
6816			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6817			reg = <0x0 0x10041000 0x0 0x1000>;
6818
6819			clocks = <&aoss_qmp>;
6820			clock-names = "apb_pclk";
6821
6822			in-ports {
6823				#address-cells = <1>;
6824				#size-cells = <0>;
6825
6826				port@6 {
6827					reg = <6>;
6828
6829					funnel0_in6: endpoint {
6830						remote-endpoint = <&qdss_tpda_out>;
6831					};
6832				};
6833
6834				port@7 {
6835					reg = <7>;
6836
6837					funnel0_in7: endpoint {
6838						remote-endpoint = <&stm_out>;
6839					};
6840				};
6841			};
6842
6843			out-ports {
6844				port {
6845					funnel0_out: endpoint {
6846						remote-endpoint = <&qdss_funnel_in0>;
6847					};
6848				};
6849			};
6850		};
6851
6852		funnel@10042000 {
6853			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6854			reg = <0x0 0x10042000 0x0 0x1000>;
6855
6856			clocks = <&aoss_qmp>;
6857			clock-names = "apb_pclk";
6858
6859			in-ports {
6860				#address-cells = <1>;
6861				#size-cells = <0>;
6862
6863				port@2 {
6864					reg = <2>;
6865
6866					funnel1_in2: endpoint {
6867						remote-endpoint = <&tmess_funnel_out>;
6868					};
6869				};
6870
6871				port@5 {
6872					reg = <5>;
6873
6874					funnel1_in5: endpoint {
6875						remote-endpoint = <&dlst_funnel_out>;
6876					};
6877				};
6878
6879				port@6 {
6880					reg = <6>;
6881
6882					funnel1_in6: endpoint {
6883						remote-endpoint = <&dlct1_funnel_out>;
6884					};
6885				};
6886			};
6887
6888			out-ports {
6889				port {
6890					funnel1_out: endpoint {
6891						remote-endpoint = <&qdss_funnel_in1>;
6892					};
6893				};
6894			};
6895		};
6896
6897		funnel@10045000 {
6898			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
6899			reg = <0x0 0x10045000 0x0 0x1000>;
6900
6901			clocks = <&aoss_qmp>;
6902			clock-names = "apb_pclk";
6903
6904			in-ports {
6905				#address-cells = <1>;
6906				#size-cells = <0>;
6907
6908				port@0 {
6909					reg = <0>;
6910
6911					qdss_funnel_in0: endpoint {
6912						remote-endpoint = <&funnel0_out>;
6913					};
6914				};
6915
6916				port@1 {
6917					reg = <1>;
6918
6919					qdss_funnel_in1: endpoint {
6920						remote-endpoint = <&funnel1_out>;
6921					};
6922				};
6923			};
6924
6925			out-ports {
6926				port {
6927					qdss_funnel_out: endpoint {
6928						remote-endpoint = <&aoss_funnel_in7>;
6929					};
6930				};
6931			};
6932		};
6933
6934		tpdm@10800000 {
6935			compatible = "qcom,coresight-tpdm", "arm,primecell";
6936			reg = <0x0 0x10800000 0x0 0x1000>;
6937
6938			clocks = <&aoss_qmp>;
6939			clock-names = "apb_pclk";
6940
6941			qcom,cmb-element-bits = <64>;
6942			qcom,cmb-msrs-num = <32>;
6943
6944			out-ports {
6945				port {
6946					mxa_tpdm_out: endpoint {
6947						remote-endpoint = <&dlct2_tpda_in15>;
6948					};
6949				};
6950			};
6951		};
6952
6953		tpdm@1082c000 {
6954			compatible = "qcom,coresight-tpdm", "arm,primecell";
6955			reg = <0x0 0x1082c000 0x0 0x1000>;
6956
6957			clocks = <&aoss_qmp>;
6958			clock-names = "apb_pclk";
6959
6960			qcom,dsb-element-bits = <32>;
6961			qcom,dsb-msrs-num = <32>;
6962
6963			out-ports {
6964				port {
6965					gcc_tpdm_out: endpoint {
6966						remote-endpoint = <&dlct1_tpda_in21>;
6967					};
6968				};
6969			};
6970		};
6971
6972		tpdm@10841000 {
6973			compatible = "qcom,coresight-tpdm", "arm,primecell";
6974			reg = <0x0 0x10841000 0x0 0x1000>;
6975
6976			clocks = <&aoss_qmp>;
6977			clock-names = "apb_pclk";
6978
6979			qcom,cmb-element-bits = <32>;
6980			qcom,cmb-msrs-num = <32>;
6981
6982			out-ports {
6983				port {
6984					prng_tpdm_out: endpoint {
6985						remote-endpoint = <&dlct1_tpda_in19>;
6986					};
6987				};
6988			};
6989		};
6990
6991		tpdm@10844000 {
6992			compatible = "qcom,coresight-tpdm", "arm,primecell";
6993			reg = <0x0 0x10844000 0x0 0x1000>;
6994
6995			clocks = <&aoss_qmp>;
6996			clock-names = "apb_pclk";
6997
6998			qcom,dsb-element-bits = <32>;
6999			qcom,dsb-msrs-num = <32>;
7000
7001			out-ports {
7002				port {
7003					lpass_cx_tpdm_out: endpoint {
7004						remote-endpoint = <&lpass_cx_funnel_in0>;
7005					};
7006				};
7007			};
7008		};
7009
7010		funnel@10846000 {
7011			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7012			reg = <0x0 0x10846000 0x0 0x1000>;
7013
7014			clocks = <&aoss_qmp>;
7015			clock-names = "apb_pclk";
7016
7017			in-ports {
7018				port {
7019					lpass_cx_funnel_in0: endpoint {
7020						remote-endpoint = <&lpass_cx_tpdm_out>;
7021					};
7022				};
7023			};
7024
7025			out-ports {
7026				port {
7027					lpass_cx_funnel_out: endpoint {
7028						remote-endpoint = <&dlct1_tpda_in4>;
7029					};
7030				};
7031			};
7032		};
7033
7034		cti@1098b000 {
7035			compatible = "arm,coresight-cti", "arm,primecell";
7036			reg = <0x0 0x1098b000 0x0 0x1000>;
7037
7038			clocks = <&aoss_qmp>;
7039			clock-names = "apb_pclk";
7040		};
7041
7042		tpdm@109d0000 {
7043			compatible = "qcom,coresight-tpdm", "arm,primecell";
7044			reg = <0x0 0x109d0000 0x0 0x1000>;
7045
7046			clocks = <&aoss_qmp>;
7047			clock-names = "apb_pclk";
7048
7049			qcom,dsb-element-bits = <32>;
7050			qcom,dsb-msrs-num = <32>;
7051			status = "disabled";
7052
7053			out-ports {
7054				port {
7055					qm_tpdm_out: endpoint {
7056						remote-endpoint = <&dlct1_tpda_in20>;
7057					};
7058				};
7059			};
7060		};
7061
7062		tpdm@10ac0000 {
7063			compatible = "qcom,coresight-tpdm", "arm,primecell";
7064			reg = <0x0 0x10ac0000 0x0 0x1000>;
7065
7066			clocks = <&aoss_qmp>;
7067			clock-names = "apb_pclk";
7068
7069			qcom,dsb-element-bits = <32>;
7070			qcom,dsb-msrs-num = <32>;
7071			status = "disabled";
7072
7073			out-ports {
7074				port {
7075					dlst_tpdm0_out: endpoint {
7076						remote-endpoint = <&dlst_tpda_in8>;
7077					};
7078				};
7079			};
7080		};
7081
7082		tpdm@10ac1000 {
7083			compatible = "qcom,coresight-tpdm", "arm,primecell";
7084			reg = <0x0 0x10ac1000 0x0 0x1000>;
7085
7086			clocks = <&aoss_qmp>;
7087			clock-names = "apb_pclk";
7088
7089			qcom,cmb-element-bits = <64>;
7090			qcom,cmb-msrs-num = <32>;
7091
7092			out-ports {
7093				port {
7094					dlst_tpdm1_out: endpoint {
7095						remote-endpoint = <&dlst_tpda_in9>;
7096					};
7097				};
7098			};
7099		};
7100
7101		tpda@10ac4000 {
7102			compatible = "qcom,coresight-tpda", "arm,primecell";
7103			reg = <0x0 0x10ac4000 0x0 0x1000>;
7104
7105			clocks = <&aoss_qmp>;
7106			clock-names = "apb_pclk";
7107
7108			in-ports {
7109				#address-cells = <1>;
7110				#size-cells = <0>;
7111
7112				port@8 {
7113					reg = <8>;
7114
7115					dlst_tpda_in8: endpoint {
7116						remote-endpoint = <&dlst_tpdm0_out>;
7117					};
7118				};
7119
7120				port@9 {
7121					reg = <9>;
7122
7123					dlst_tpda_in9: endpoint {
7124						remote-endpoint = <&dlst_tpdm1_out>;
7125					};
7126				};
7127			};
7128
7129			out-ports {
7130				port {
7131					dlst_tpda_out: endpoint {
7132						remote-endpoint = <&dlst_funnel_in0>;
7133					};
7134				};
7135			};
7136		};
7137
7138		funnel@10ac5000 {
7139			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7140			reg = <0x0 0x10ac5000 0x0 0x1000>;
7141
7142			clocks = <&aoss_qmp>;
7143			clock-names = "apb_pclk";
7144
7145			in-ports {
7146				port {
7147					dlst_funnel_in0: endpoint {
7148						remote-endpoint = <&dlst_tpda_out>;
7149					};
7150				};
7151			};
7152
7153			out-ports {
7154				port {
7155					dlst_funnel_out: endpoint {
7156						remote-endpoint = <&funnel1_in5>;
7157					};
7158				};
7159			};
7160		};
7161
7162		funnel@10b04000 {
7163			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7164			reg = <0x0 0x10b04000 0x0 0x1000>;
7165
7166			clocks = <&aoss_qmp>;
7167			clock-names = "apb_pclk";
7168
7169			in-ports {
7170				#address-cells = <1>;
7171				#size-cells = <0>;
7172
7173				port@3 {
7174					reg = <3>;
7175
7176					aoss_funnel_in3: endpoint {
7177						remote-endpoint = <&ddr_lpi_funnel_out>;
7178					};
7179				};
7180
7181				port@6 {
7182					reg = <6>;
7183
7184					aoss_funnel_in6: endpoint {
7185						remote-endpoint = <&aoss_tpda_out>;
7186					};
7187				};
7188
7189				port@7 {
7190					reg = <7>;
7191
7192					aoss_funnel_in7: endpoint {
7193						remote-endpoint = <&qdss_funnel_out>;
7194					};
7195				};
7196			};
7197
7198			out-ports {
7199				port {
7200					aoss_funnel_out: endpoint {
7201						remote-endpoint = <&etf0_in>;
7202					};
7203				};
7204			};
7205		};
7206
7207		etf0: tmc@10b05000 {
7208			compatible = "arm,coresight-tmc", "arm,primecell";
7209			reg = <0x0 0x10b05000 0x0 0x1000>;
7210
7211			clocks = <&aoss_qmp>;
7212			clock-names = "apb_pclk";
7213
7214			in-ports {
7215				port {
7216					etf0_in: endpoint {
7217						remote-endpoint = <&aoss_funnel_out>;
7218					};
7219				};
7220			};
7221
7222			out-ports {
7223				port {
7224					etf0_out: endpoint {
7225						remote-endpoint = <&swao_rep_in>;
7226					};
7227				};
7228			};
7229		};
7230
7231		replicator@10b06000 {
7232			compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
7233			reg = <0x0 0x10b06000 0x0 0x1000>;
7234
7235			clocks = <&aoss_qmp>;
7236			clock-names = "apb_pclk";
7237
7238			in-ports {
7239				port {
7240					swao_rep_in: endpoint {
7241						remote-endpoint = <&etf0_out>;
7242					};
7243				};
7244			};
7245
7246			out-ports {
7247				port {
7248					swao_rep_out1: endpoint {
7249						remote-endpoint = <&eud_in>;
7250					};
7251				};
7252			};
7253		};
7254
7255		tpda@10b08000 {
7256			compatible = "qcom,coresight-tpda", "arm,primecell";
7257			reg = <0x0 0x10b08000 0x0 0x1000>;
7258
7259			clocks = <&aoss_qmp>;
7260			clock-names = "apb_pclk";
7261
7262			in-ports {
7263				#address-cells = <1>;
7264				#size-cells = <0>;
7265
7266				port@0 {
7267					reg = <0>;
7268
7269					aoss_tpda_in0: endpoint {
7270						remote-endpoint = <&aoss_tpdm0_out>;
7271					};
7272				};
7273
7274				port@1 {
7275					reg = <1>;
7276
7277					aoss_tpda_in1: endpoint {
7278						remote-endpoint = <&aoss_tpdm1_out>;
7279					};
7280				};
7281
7282				port@2 {
7283					reg = <2>;
7284
7285					aoss_tpda_in2: endpoint {
7286						remote-endpoint = <&aoss_tpdm2_out>;
7287					};
7288				};
7289
7290				port@3 {
7291					reg = <3>;
7292
7293					aoss_tpda_in3: endpoint {
7294						remote-endpoint = <&aoss_tpdm3_out>;
7295					};
7296				};
7297
7298				port@4 {
7299					reg = <4>;
7300
7301					aoss_tpda_in4: endpoint {
7302						remote-endpoint = <&aoss_tpdm4_out>;
7303					};
7304				};
7305			};
7306
7307			out-ports {
7308				port {
7309					aoss_tpda_out: endpoint {
7310						remote-endpoint = <&aoss_funnel_in6>;
7311					};
7312				};
7313			};
7314		};
7315
7316		tpdm@10b09000 {
7317			compatible = "qcom,coresight-tpdm", "arm,primecell";
7318			reg = <0x0 0x10b09000 0x0 0x1000>;
7319
7320			clocks = <&aoss_qmp>;
7321			clock-names = "apb_pclk";
7322
7323			qcom,cmb-element-bits = <64>;
7324			qcom,cmb-msrs-num = <32>;
7325
7326			out-ports {
7327				port {
7328					aoss_tpdm0_out: endpoint {
7329						remote-endpoint = <&aoss_tpda_in0>;
7330					};
7331				};
7332			};
7333		};
7334
7335		tpdm@10b0a000 {
7336			compatible = "qcom,coresight-tpdm", "arm,primecell";
7337			reg = <0x0 0x10b0a000 0x0 0x1000>;
7338
7339			clocks = <&aoss_qmp>;
7340			clock-names = "apb_pclk";
7341
7342			qcom,cmb-element-bits = <64>;
7343			qcom,cmb-msrs-num = <32>;
7344
7345			out-ports {
7346				port {
7347					aoss_tpdm1_out: endpoint {
7348						remote-endpoint = <&aoss_tpda_in1>;
7349					};
7350				};
7351			};
7352		};
7353
7354		tpdm@10b0b000 {
7355			compatible = "qcom,coresight-tpdm", "arm,primecell";
7356			reg = <0x0 0x10b0b000 0x0 0x1000>;
7357
7358			clocks = <&aoss_qmp>;
7359			clock-names = "apb_pclk";
7360
7361			qcom,cmb-element-bits = <64>;
7362			qcom,cmb-msrs-num = <32>;
7363
7364			out-ports {
7365				port {
7366					aoss_tpdm2_out: endpoint {
7367						remote-endpoint = <&aoss_tpda_in2>;
7368					};
7369				};
7370			};
7371		};
7372
7373		tpdm@10b0c000 {
7374			compatible = "qcom,coresight-tpdm", "arm,primecell";
7375			reg = <0x0 0x10b0c000 0x0 0x1000>;
7376
7377			clocks = <&aoss_qmp>;
7378			clock-names = "apb_pclk";
7379
7380			qcom,cmb-element-bits = <64>;
7381			qcom,cmb-msrs-num = <32>;
7382
7383			out-ports {
7384				port {
7385					aoss_tpdm3_out: endpoint {
7386						remote-endpoint = <&aoss_tpda_in3>;
7387					};
7388				};
7389			};
7390		};
7391
7392		tpdm@10b0d000 {
7393			compatible = "qcom,coresight-tpdm", "arm,primecell";
7394			reg = <0x0 0x10b0d000 0x0 0x1000>;
7395
7396			clocks = <&aoss_qmp>;
7397			clock-names = "apb_pclk";
7398
7399			qcom,dsb-element-bits = <32>;
7400			qcom,dsb-msrs-num = <32>;
7401
7402			out-ports {
7403				port {
7404					aoss_tpdm4_out: endpoint {
7405						remote-endpoint = <&aoss_tpda_in4>;
7406					};
7407				};
7408			};
7409		};
7410
7411		tpdm@10b20000 {
7412			compatible = "qcom,coresight-tpdm", "arm,primecell";
7413			reg = <0x0 0x10b20000 0x0 0x1000>;
7414
7415			clocks = <&aoss_qmp>;
7416			clock-names = "apb_pclk";
7417
7418			qcom,dsb-element-bits = <32>;
7419			qcom,dsb-msrs-num = <32>;
7420			status = "disabled";
7421
7422			out-ports {
7423				port {
7424					lpicc_tpdm_out: endpoint {
7425						remote-endpoint = <&ddr_lpi_tpda_in>;
7426					};
7427				};
7428			};
7429		};
7430
7431		tpda@10b23000 {
7432			compatible = "qcom,coresight-tpda", "arm,primecell";
7433			reg = <0x0 0x10b23000 0x0 0x1000>;
7434
7435			clocks = <&aoss_qmp>;
7436			clock-names = "apb_pclk";
7437			status = "disabled";
7438
7439			in-ports {
7440				port {
7441					ddr_lpi_tpda_in: endpoint {
7442						remote-endpoint = <&lpicc_tpdm_out>;
7443					};
7444				};
7445			};
7446
7447			out-ports {
7448				port {
7449					ddr_lpi_tpda_out: endpoint {
7450						remote-endpoint = <&ddr_lpi_funnel_in0>;
7451					};
7452				};
7453			};
7454		};
7455
7456		funnel@10b24000 {
7457			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7458			reg = <0x0 0x10b24000 0x0 0x1000>;
7459
7460			clocks = <&aoss_qmp>;
7461			clock-names = "apb_pclk";
7462			status = "disabled";
7463
7464			in-ports {
7465				port {
7466					ddr_lpi_funnel_in0: endpoint {
7467						remote-endpoint = <&ddr_lpi_tpda_out>;
7468					};
7469				};
7470			};
7471
7472			out-ports {
7473				port {
7474					ddr_lpi_funnel_out: endpoint {
7475						remote-endpoint = <&aoss_funnel_in3>;
7476					};
7477				};
7478			};
7479		};
7480
7481		tpdm@10c08000 {
7482			compatible = "qcom,coresight-tpdm", "arm,primecell";
7483			reg = <0x0 0x10c08000 0x0 0x1000>;
7484
7485			clocks = <&aoss_qmp>;
7486			clock-names = "apb_pclk";
7487
7488			qcom,dsb-element-bits = <32>;
7489			qcom,dsb-msrs-num = <32>;
7490
7491			out-ports {
7492				port {
7493					mm_tpdm_out: endpoint {
7494						remote-endpoint = <&mm_funnel_in4>;
7495					};
7496				};
7497			};
7498		};
7499
7500		funnel@10c0b000 {
7501			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7502			reg = <0x0 0x10c0b000 0x0 0x1000>;
7503
7504			clocks = <&aoss_qmp>;
7505			clock-names = "apb_pclk";
7506
7507			in-ports {
7508				#address-cells = <1>;
7509				#size-cells = <0>;
7510
7511				port@4 {
7512					reg = <4>;
7513
7514					mm_funnel_in4: endpoint {
7515						remote-endpoint = <&mm_tpdm_out>;
7516					};
7517				};
7518			};
7519
7520			out-ports {
7521				port {
7522					mm_funnel_out: endpoint {
7523						remote-endpoint = <&dlct2_tpda_in4>;
7524					};
7525				};
7526			};
7527		};
7528
7529		tpdm@10c28000 {
7530			compatible = "qcom,coresight-tpdm", "arm,primecell";
7531			reg = <0x0 0x10c28000 0x0 0x1000>;
7532
7533			clocks = <&aoss_qmp>;
7534			clock-names = "apb_pclk";
7535
7536			qcom,dsb-element-bits = <32>;
7537			qcom,dsb-msrs-num = <32>;
7538
7539			out-ports {
7540				port {
7541					dlct1_tpdm_out: endpoint {
7542						remote-endpoint = <&dlct1_tpda_in26>;
7543					};
7544				};
7545			};
7546		};
7547
7548		tpdm@10c29000 {
7549			compatible = "qcom,coresight-tpdm", "arm,primecell";
7550			reg = <0x0 0x10c29000 0x0 0x1000>;
7551
7552			clocks = <&aoss_qmp>;
7553			clock-names = "apb_pclk";
7554
7555			qcom,cmb-element-bits = <64>;
7556			qcom,cmb-msrs-num = <32>;
7557
7558			out-ports {
7559				port {
7560					ipcc_tpdm_out: endpoint {
7561						remote-endpoint = <&dlct1_tpda_in27>;
7562					};
7563				};
7564			};
7565		};
7566
7567		tpda@10c2b000 {
7568			compatible = "qcom,coresight-tpda", "arm,primecell";
7569			reg = <0x0 0x10c2b000 0x0 0x1000>;
7570
7571			clocks = <&aoss_qmp>;
7572			clock-names = "apb_pclk";
7573
7574			in-ports {
7575				#address-cells = <1>;
7576				#size-cells = <0>;
7577
7578				port@4 {
7579					reg = <4>;
7580
7581					dlct1_tpda_in4: endpoint {
7582						remote-endpoint = <&lpass_cx_funnel_out>;
7583					};
7584				};
7585
7586				port@13 {
7587					reg = <19>;
7588
7589					dlct1_tpda_in19: endpoint {
7590						remote-endpoint = <&prng_tpdm_out>;
7591					};
7592				};
7593
7594				port@14 {
7595					reg = <20>;
7596
7597					dlct1_tpda_in20: endpoint {
7598						remote-endpoint = <&qm_tpdm_out>;
7599					};
7600				};
7601
7602				port@15 {
7603					reg = <21>;
7604
7605					dlct1_tpda_in21: endpoint {
7606						remote-endpoint = <&gcc_tpdm_out>;
7607					};
7608				};
7609
7610				port@1a {
7611					reg = <26>;
7612
7613					dlct1_tpda_in26: endpoint {
7614						remote-endpoint = <&dlct1_tpdm_out>;
7615					};
7616				};
7617
7618				port@1b {
7619					reg = <27>;
7620
7621					dlct1_tpda_in27: endpoint {
7622						remote-endpoint = <&ipcc_tpdm_out>;
7623					};
7624				};
7625			};
7626
7627			out-ports {
7628				port {
7629					dlct1_tpda_out: endpoint {
7630						remote-endpoint = <&dlct1_funnel_in0>;
7631					};
7632				};
7633			};
7634		};
7635
7636		funnel@10c2c000 {
7637			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7638			reg = <0x0 0x10c2c000 0x0 0x1000>;
7639
7640			clocks = <&aoss_qmp>;
7641			clock-names = "apb_pclk";
7642
7643			in-ports {
7644				#address-cells = <1>;
7645				#size-cells = <0>;
7646
7647				port@0 {
7648					reg = <0>;
7649
7650					dlct1_funnel_in0: endpoint {
7651						remote-endpoint = <&dlct1_tpda_out>;
7652					};
7653				};
7654
7655				port@4 {
7656					reg = <4>;
7657
7658					dlct1_funnel_in4: endpoint {
7659						remote-endpoint = <&dlct2_funnel_out>;
7660					};
7661				};
7662
7663				port@5 {
7664					reg = <5>;
7665
7666					dlct1_funnel_in5: endpoint {
7667						remote-endpoint = <&ddr_funnel0_out>;
7668					};
7669				};
7670			};
7671
7672			out-ports {
7673				port {
7674					dlct1_funnel_out: endpoint {
7675						remote-endpoint = <&funnel1_in6>;
7676					};
7677				};
7678			};
7679		};
7680
7681		tpdm@10c38000 {
7682			compatible = "qcom,coresight-tpdm", "arm,primecell";
7683			reg = <0x0 0x10c38000 0x0 0x1000>;
7684
7685			clocks = <&aoss_qmp>;
7686			clock-names = "apb_pclk";
7687
7688			qcom,cmb-element-bits = <64>;
7689			qcom,cmb-msrs-num = <32>;
7690
7691			out-ports {
7692				port {
7693					dlct2_tpdm0_out: endpoint {
7694						remote-endpoint = <&dlct2_tpda_in16>;
7695					};
7696				};
7697			};
7698		};
7699
7700		tpdm@10c39000 {
7701			compatible = "qcom,coresight-tpdm", "arm,primecell";
7702			reg = <0x0 0x10c39000 0x0 0x1000>;
7703
7704			clocks = <&aoss_qmp>;
7705			clock-names = "apb_pclk";
7706
7707			qcom,cmb-element-bits = <64>;
7708			qcom,cmb-msrs-num = <32>;
7709
7710			out-ports {
7711				port {
7712					dlct2_tpdm1_out: endpoint {
7713						remote-endpoint = <&dlct2_tpda_in17>;
7714					};
7715				};
7716			};
7717		};
7718
7719		tpda@10c3c000 {
7720			compatible = "qcom,coresight-tpda", "arm,primecell";
7721			reg = <0x0 0x10c3c000 0x0 0x1000>;
7722
7723			clocks = <&aoss_qmp>;
7724			clock-names = "apb_pclk";
7725
7726			in-ports {
7727				#address-cells = <1>;
7728				#size-cells = <0>;
7729
7730				port@4 {
7731					reg = <4>;
7732
7733					dlct2_tpda_in4: endpoint {
7734						remote-endpoint = <&mm_funnel_out>;
7735					};
7736				};
7737
7738				port@f {
7739					reg = <15>;
7740
7741					dlct2_tpda_in15: endpoint {
7742						remote-endpoint = <&mxa_tpdm_out>;
7743					};
7744				};
7745
7746				port@10 {
7747					reg = <16>;
7748
7749					dlct2_tpda_in16: endpoint {
7750						remote-endpoint = <&dlct2_tpdm0_out>;
7751					};
7752				};
7753
7754				port@11 {
7755					reg = <17>;
7756
7757					dlct2_tpda_in17: endpoint {
7758						remote-endpoint = <&dlct2_tpdm1_out>;
7759					};
7760				};
7761			};
7762
7763			out-ports {
7764				port {
7765					dlct2_tpda_out: endpoint {
7766						remote-endpoint = <&dlct2_funnel_in0>;
7767					};
7768				};
7769			};
7770		};
7771
7772		funnel@10c3d000 {
7773			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7774			reg = <0x0 0x10c3d000 0x0 0x1000>;
7775
7776			clocks = <&aoss_qmp>;
7777			clock-names = "apb_pclk";
7778
7779			in-ports {
7780				port {
7781					dlct2_funnel_in0: endpoint {
7782						remote-endpoint = <&dlct2_tpda_out>;
7783					};
7784				};
7785			};
7786
7787			out-ports {
7788				port {
7789					dlct2_funnel_out: endpoint {
7790						remote-endpoint = <&dlct1_funnel_in4>;
7791					};
7792				};
7793			};
7794		};
7795
7796		tpdm@10cc1000 {
7797			compatible = "qcom,coresight-tpdm", "arm,primecell";
7798			reg = <0x0 0x10cc1000 0x0 0x1000>;
7799
7800			clocks = <&aoss_qmp>;
7801			clock-names = "apb_pclk";
7802
7803			qcom,cmb-element-bits = <64>;
7804			qcom,cmb-msrs-num = <32>;
7805			qcom,dsb-element-bits = <32>;
7806			qcom,dsb-msrs-num = <32>;
7807			status = "disabled";
7808
7809			out-ports {
7810				port {
7811					tmess_tpdm1_out: endpoint {
7812						remote-endpoint = <&tmess_tpda_in2>;
7813					};
7814				};
7815			};
7816		};
7817
7818		tpda@10cc4000 {
7819			compatible = "qcom,coresight-tpda", "arm,primecell";
7820			reg = <0x0 0x10cc4000 0x0 0x1000>;
7821
7822			clocks = <&aoss_qmp>;
7823			clock-names = "apb_pclk";
7824
7825			in-ports {
7826				#address-cells = <1>;
7827				#size-cells = <0>;
7828
7829				port@2 {
7830					reg = <2>;
7831
7832					tmess_tpda_in2: endpoint {
7833						remote-endpoint = <&tmess_tpdm1_out>;
7834					};
7835				};
7836			};
7837
7838			out-ports {
7839				port {
7840					tmess_tpda_out: endpoint {
7841						remote-endpoint = <&tmess_funnel_in0>;
7842					};
7843				};
7844			};
7845		};
7846
7847		funnel@10cc5000 {
7848			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7849			reg = <0x0 0x10cc5000 0x0 0x1000>;
7850
7851			clocks = <&aoss_qmp>;
7852			clock-names = "apb_pclk";
7853
7854			in-ports {
7855				port {
7856					tmess_funnel_in0: endpoint {
7857						remote-endpoint = <&tmess_tpda_out>;
7858					};
7859				};
7860			};
7861
7862			out-ports {
7863				port {
7864					tmess_funnel_out: endpoint {
7865						remote-endpoint = <&funnel1_in2>;
7866					};
7867				};
7868			};
7869		};
7870
7871		funnel@10d04000 {
7872			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
7873			reg = <0x0 0x10d04000 0x0 0x1000>;
7874
7875			clocks = <&aoss_qmp>;
7876			clock-names = "apb_pclk";
7877
7878			in-ports {
7879				#address-cells = <1>;
7880				#size-cells = <0>;
7881
7882				port@6 {
7883					reg = <6>;
7884
7885					ddr_funnel0_in6: endpoint {
7886						remote-endpoint = <&ddr_funnel1_out>;
7887					};
7888				};
7889			};
7890
7891			out-ports {
7892				port {
7893					ddr_funnel0_out: endpoint {
7894						remote-endpoint = <&dlct1_funnel_in5>;
7895					};
7896				};
7897			};
7898		};
7899
7900		tpdm@10d08000 {
7901			compatible = "qcom,coresight-tpdm", "arm,primecell";
7902			reg = <0x0 0x10d08000 0x0 0x1000>;
7903
7904			clocks = <&aoss_qmp>;
7905			clock-names = "apb_pclk";
7906
7907			qcom,cmb-element-bits = <32>;
7908			qcom,cmb-msrs-num = <32>;
7909
7910			out-ports {
7911				port {
7912					llcc0_tpdm_out: endpoint {
7913						remote-endpoint = <&llcc_tpda_in0>;
7914					};
7915				};
7916			};
7917		};
7918
7919		tpdm@10d09000 {
7920			compatible = "qcom,coresight-tpdm", "arm,primecell";
7921			reg = <0x0 0x10d09000 0x0 0x1000>;
7922
7923			clocks = <&aoss_qmp>;
7924			clock-names = "apb_pclk";
7925
7926			qcom,cmb-element-bits = <32>;
7927			qcom,cmb-msrs-num = <32>;
7928
7929			out-ports {
7930				port {
7931					llcc1_tpdm_out: endpoint {
7932						remote-endpoint = <&llcc_tpda_in1>;
7933					};
7934				};
7935			};
7936		};
7937
7938		tpdm@10d0a000 {
7939			compatible = "qcom,coresight-tpdm", "arm,primecell";
7940			reg = <0x0 0x10d0a000 0x0 0x1000>;
7941
7942			clocks = <&aoss_qmp>;
7943			clock-names = "apb_pclk";
7944
7945			qcom,cmb-element-bits = <32>;
7946			qcom,cmb-msrs-num = <32>;
7947
7948			out-ports {
7949				port {
7950					llcc2_tpdm_out: endpoint {
7951						remote-endpoint = <&llcc_tpda_in2>;
7952					};
7953				};
7954			};
7955		};
7956
7957		tpdm@10d0b000 {
7958			compatible = "qcom,coresight-tpdm", "arm,primecell";
7959			reg = <0x0 0x10d0b000 0x0 0x1000>;
7960
7961			clocks = <&aoss_qmp>;
7962			clock-names = "apb_pclk";
7963
7964			qcom,cmb-element-bits = <32>;
7965			qcom,cmb-msrs-num = <32>;
7966
7967			out-ports {
7968				port {
7969					llcc3_tpdm_out: endpoint {
7970						remote-endpoint = <&llcc_tpda_in3>;
7971					};
7972				};
7973			};
7974		};
7975
7976		tpdm@10d0c000 {
7977			compatible = "qcom,coresight-tpdm", "arm,primecell";
7978			reg = <0x0 0x10d0c000 0x0 0x1000>;
7979
7980			clocks = <&aoss_qmp>;
7981			clock-names = "apb_pclk";
7982
7983			qcom,cmb-element-bits = <32>;
7984			qcom,cmb-msrs-num = <32>;
7985
7986			out-ports {
7987				port {
7988					llcc4_tpdm_out: endpoint {
7989						remote-endpoint = <&llcc_tpda_in4>;
7990					};
7991				};
7992			};
7993		};
7994
7995		tpdm@10d0d000 {
7996			compatible = "qcom,coresight-tpdm", "arm,primecell";
7997			reg = <0x0 0x10d0d000 0x0 0x1000>;
7998
7999			clocks = <&aoss_qmp>;
8000			clock-names = "apb_pclk";
8001
8002			qcom,cmb-element-bits = <32>;
8003			qcom,cmb-msrs-num = <32>;
8004
8005			out-ports {
8006				port {
8007					llcc5_tpdm_out: endpoint {
8008						remote-endpoint = <&llcc_tpda_in5>;
8009					};
8010				};
8011			};
8012		};
8013
8014		tpdm@10d0e000 {
8015			compatible = "qcom,coresight-tpdm", "arm,primecell";
8016			reg = <0x0 0x10d0e000 0x0 0x1000>;
8017
8018			clocks = <&aoss_qmp>;
8019			clock-names = "apb_pclk";
8020
8021			qcom,cmb-element-bits = <32>;
8022			qcom,cmb-msrs-num = <32>;
8023
8024			out-ports {
8025				port {
8026					llcc6_tpdm_out: endpoint {
8027						remote-endpoint = <&llcc_tpda_in6>;
8028					};
8029				};
8030			};
8031		};
8032
8033		tpdm@10d0f000 {
8034			compatible = "qcom,coresight-tpdm", "arm,primecell";
8035			reg = <0x0 0x10d0f000 0x0 0x1000>;
8036
8037			clocks = <&aoss_qmp>;
8038			clock-names = "apb_pclk";
8039
8040			qcom,cmb-element-bits = <32>;
8041			qcom,cmb-msrs-num = <32>;
8042
8043			out-ports {
8044				port {
8045					llcc7_tpdm_out: endpoint {
8046						remote-endpoint = <&llcc_tpda_in7>;
8047					};
8048				};
8049			};
8050		};
8051
8052		tpda@10d12000 {
8053			compatible = "qcom,coresight-tpda", "arm,primecell";
8054			reg = <0x0 0x10d12000 0x0 0x1000>;
8055
8056			clocks = <&aoss_qmp>;
8057			clock-names = "apb_pclk";
8058
8059			in-ports {
8060				#address-cells = <1>;
8061				#size-cells = <0>;
8062
8063				port@0 {
8064					reg = <0>;
8065
8066					llcc_tpda_in0: endpoint {
8067						remote-endpoint = <&llcc0_tpdm_out>;
8068					};
8069				};
8070
8071				port@1 {
8072					reg = <1>;
8073
8074					llcc_tpda_in1: endpoint {
8075						remote-endpoint = <&llcc1_tpdm_out>;
8076					};
8077				};
8078
8079				port@2 {
8080					reg = <2>;
8081
8082					llcc_tpda_in2: endpoint {
8083						remote-endpoint = <&llcc2_tpdm_out>;
8084					};
8085				};
8086
8087				port@3 {
8088					reg = <3>;
8089
8090					llcc_tpda_in3: endpoint {
8091						remote-endpoint = <&llcc3_tpdm_out>;
8092					};
8093				};
8094
8095				port@4 {
8096					reg = <4>;
8097
8098					llcc_tpda_in4: endpoint {
8099						remote-endpoint = <&llcc4_tpdm_out>;
8100					};
8101				};
8102
8103				port@5 {
8104					reg = <5>;
8105
8106					llcc_tpda_in5: endpoint {
8107						remote-endpoint = <&llcc5_tpdm_out>;
8108					};
8109				};
8110
8111				port@6 {
8112					reg = <6>;
8113
8114					llcc_tpda_in6: endpoint {
8115						remote-endpoint = <&llcc6_tpdm_out>;
8116					};
8117				};
8118
8119				port@7 {
8120					reg = <7>;
8121
8122					llcc_tpda_in7: endpoint {
8123						remote-endpoint = <&llcc7_tpdm_out>;
8124					};
8125				};
8126			};
8127
8128			out-ports {
8129				port {
8130					llcc_tpda_out: endpoint {
8131						remote-endpoint = <&ddr_funnel1_in0>;
8132					};
8133				};
8134			};
8135		};
8136
8137		funnel@10d13000 {
8138			compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
8139			reg = <0x0 0x10d13000 0x0 0x1000>;
8140
8141			clocks = <&aoss_qmp>;
8142			clock-names = "apb_pclk";
8143
8144			in-ports {
8145				port {
8146					ddr_funnel1_in0: endpoint {
8147						remote-endpoint = <&llcc_tpda_out>;
8148					};
8149				};
8150			};
8151
8152			out-ports {
8153				port {
8154					ddr_funnel1_out: endpoint {
8155						remote-endpoint = <&ddr_funnel0_in6>;
8156					};
8157				};
8158			};
8159		};
8160
8161		apps_smmu: iommu@15000000 {
8162			compatible = "qcom,x1e80100-smmu-500", "qcom,smmu-500", "arm,mmu-500";
8163			reg = <0 0x15000000 0 0x100000>;
8164
8165			interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
8166				     <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
8167				     <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
8168				     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
8169				     <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
8170				     <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
8171				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
8172				     <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
8173				     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
8174				     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
8175				     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
8176				     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
8177				     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
8178				     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
8179				     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
8180				     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
8181				     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
8182				     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
8183				     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
8184				     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
8185				     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
8186				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
8187				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
8188				     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
8189				     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
8190				     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
8191				     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
8192				     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
8193				     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
8194				     <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
8195				     <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
8196				     <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
8197				     <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
8198				     <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
8199				     <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
8200				     <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
8201				     <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
8202				     <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
8203				     <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
8204				     <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
8205				     <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
8206				     <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
8207				     <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
8208				     <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
8209				     <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
8210				     <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
8211				     <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
8212				     <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
8213				     <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
8214				     <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
8215				     <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
8216				     <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
8217				     <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
8218				     <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
8219				     <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
8220				     <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
8221				     <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
8222				     <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
8223				     <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
8224				     <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
8225				     <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
8226				     <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
8227				     <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
8228				     <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
8229				     <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
8230				     <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
8231				     <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
8232				     <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
8233				     <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
8234				     <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
8235				     <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
8236				     <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
8237				     <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
8238				     <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
8239				     <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
8240				     <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
8241				     <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
8242				     <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
8243				     <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
8244				     <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
8245				     <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
8246				     <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
8247				     <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
8248				     <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
8249				     <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
8250				     <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
8251				     <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
8252				     <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
8253				     <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
8254				     <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
8255				     <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
8256				     <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
8257				     <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
8258				     <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
8259				     <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
8260				     <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
8261				     <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>;
8262
8263			#iommu-cells = <2>;
8264			#global-interrupts = <1>;
8265
8266			dma-coherent;
8267		};
8268
8269		pcie_smmu: iommu@15400000 {
8270			compatible = "arm,smmu-v3";
8271			reg = <0 0x15400000 0 0x80000>;
8272			#iommu-cells = <1>;
8273			interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
8274				     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
8275				     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>;
8276			interrupt-names = "eventq",
8277					  "gerror",
8278					  "cmdq-sync";
8279			dma-coherent;
8280			status = "reserved"; /* Controlled by Gunyah. */
8281		};
8282
8283		intc: interrupt-controller@17000000 {
8284			compatible = "arm,gic-v3";
8285			reg = <0 0x17000000 0 0x10000>,     /* GICD */
8286			      <0 0x17080000 0 0x300000>;    /* GICR * 12 */
8287
8288			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
8289
8290			#interrupt-cells = <3>;
8291			interrupt-controller;
8292
8293			#redistributor-regions = <1>;
8294			redistributor-stride = <0x0 0x40000>;
8295
8296			#address-cells = <2>;
8297			#size-cells = <2>;
8298			ranges;
8299
8300			gic_its: msi-controller@17040000 {
8301				compatible = "arm,gic-v3-its";
8302				reg = <0 0x17040000 0 0x40000>;
8303
8304				msi-controller;
8305				#msi-cells = <1>;
8306			};
8307		};
8308
8309		cpucp_mbox: mailbox@17430000 {
8310			compatible = "qcom,x1e80100-cpucp-mbox";
8311			reg = <0 0x17430000 0 0x10000>, <0 0x18830000 0 0x10000>;
8312			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
8313			#mbox-cells = <1>;
8314		};
8315
8316		apps_rsc: rsc@17500000 {
8317			compatible = "qcom,rpmh-rsc";
8318			reg = <0 0x17500000 0 0x10000>,
8319			      <0 0x17510000 0 0x10000>,
8320			      <0 0x17520000 0 0x10000>;
8321			reg-names = "drv-0", "drv-1", "drv-2";
8322
8323			interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
8324				     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
8325				     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
8326			qcom,tcs-offset = <0xd00>;
8327			qcom,drv-id = <2>;
8328			qcom,tcs-config = <ACTIVE_TCS    3>, <SLEEP_TCS     2>,
8329					  <WAKE_TCS      2>, <CONTROL_TCS   0>;
8330
8331			label = "apps_rsc";
8332			power-domains = <&system_pd>;
8333
8334			apps_bcm_voter: bcm-voter {
8335				compatible = "qcom,bcm-voter";
8336			};
8337
8338			rpmhcc: clock-controller {
8339				compatible = "qcom,x1e80100-rpmh-clk";
8340
8341				clocks = <&xo_board>;
8342				clock-names = "xo";
8343
8344				#clock-cells = <1>;
8345			};
8346
8347			rpmhpd: power-controller {
8348				compatible = "qcom,x1e80100-rpmhpd";
8349
8350				operating-points-v2 = <&rpmhpd_opp_table>;
8351
8352				#power-domain-cells = <1>;
8353
8354				rpmhpd_opp_table: opp-table {
8355					compatible = "operating-points-v2";
8356
8357					rpmhpd_opp_ret: opp-16 {
8358						opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
8359					};
8360
8361					rpmhpd_opp_min_svs: opp-48 {
8362						opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
8363					};
8364
8365					rpmhpd_opp_low_svs_d2: opp-52 {
8366						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>;
8367					};
8368
8369					rpmhpd_opp_low_svs_d1: opp-56 {
8370						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
8371					};
8372
8373					rpmhpd_opp_low_svs_d0: opp-60 {
8374						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>;
8375					};
8376
8377					rpmhpd_opp_low_svs: opp-64 {
8378						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
8379					};
8380
8381					rpmhpd_opp_low_svs_l1: opp-80 {
8382						opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
8383					};
8384
8385					rpmhpd_opp_svs: opp-128 {
8386						opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
8387					};
8388
8389					rpmhpd_opp_svs_l0: opp-144 {
8390						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
8391					};
8392
8393					rpmhpd_opp_svs_l1: opp-192 {
8394						opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
8395					};
8396
8397					rpmhpd_opp_nom: opp-256 {
8398						opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
8399					};
8400
8401					rpmhpd_opp_nom_l1: opp-320 {
8402						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
8403					};
8404
8405					rpmhpd_opp_nom_l2: opp-336 {
8406						opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
8407					};
8408
8409					rpmhpd_opp_turbo: opp-384 {
8410						opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
8411					};
8412
8413					rpmhpd_opp_turbo_l1: opp-416 {
8414						opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
8415					};
8416				};
8417			};
8418		};
8419
8420		timer@17800000 {
8421			compatible = "arm,armv7-timer-mem";
8422			reg = <0 0x17800000 0 0x1000>;
8423
8424			#address-cells = <2>;
8425			#size-cells = <1>;
8426			ranges = <0 0 0 0 0x20000000>;
8427
8428			frame@17801000 {
8429				reg = <0 0x17801000 0x1000>,
8430				      <0 0x17802000 0x1000>;
8431
8432				interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
8433					     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
8434
8435				frame-number = <0>;
8436			};
8437
8438			frame@17803000 {
8439				reg = <0 0x17803000 0x1000>;
8440
8441				interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
8442
8443				frame-number = <1>;
8444
8445				status = "disabled";
8446			};
8447
8448			frame@17805000 {
8449				reg = <0 0x17805000 0x1000>;
8450
8451				interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
8452
8453				frame-number = <2>;
8454
8455				status = "disabled";
8456			};
8457
8458			frame@17807000 {
8459				reg = <0 0x17807000 0x1000>;
8460
8461				interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
8462
8463				frame-number = <3>;
8464
8465				status = "disabled";
8466			};
8467
8468			frame@17809000 {
8469				reg = <0 0x17809000 0x1000>;
8470
8471				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
8472
8473				frame-number = <4>;
8474
8475				status = "disabled";
8476			};
8477
8478			frame@1780b000 {
8479				reg = <0 0x1780b000 0x1000>;
8480
8481				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
8482
8483				frame-number = <5>;
8484
8485				status = "disabled";
8486			};
8487
8488			frame@1780d000 {
8489				reg = <0 0x1780d000 0x1000>;
8490
8491				interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
8492
8493				frame-number = <6>;
8494
8495				status = "disabled";
8496			};
8497		};
8498
8499		sram: sram@18b4e000 {
8500			compatible = "mmio-sram";
8501			reg = <0x0 0x18b4e000 0x0 0x400>;
8502
8503			#address-cells = <1>;
8504			#size-cells = <1>;
8505			ranges = <0x0 0x0 0x18b4e000 0x400>;
8506
8507			cpu_scp_lpri0: scp-sram-section@0 {
8508				compatible = "arm,scmi-shmem";
8509				reg = <0x0 0x200>;
8510			};
8511
8512			cpu_scp_lpri1: scp-sram-section@200 {
8513				compatible = "arm,scmi-shmem";
8514				reg = <0x200 0x200>;
8515			};
8516		};
8517
8518		sbsa_watchdog: watchdog@1c840000 {
8519			compatible = "arm,sbsa-gwdt";
8520			reg = <0 0x1c840000 0 0x1000>,
8521			      <0 0x1c850000 0 0x1000>;
8522			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
8523		};
8524
8525		qfprom: efuse@221c8000 {
8526			compatible = "qcom,x1e80100-qfprom", "qcom,qfprom";
8527			reg = <0 0x221c8000 0 0x1000>;
8528			#address-cells = <1>;
8529			#size-cells = <1>;
8530
8531			gpu_speed_bin: gpu-speed-bin@119 {
8532				reg = <0x119 0x2>;
8533				bits = <7 8>;
8534			};
8535		};
8536
8537		pmu@24091000 {
8538			compatible = "qcom,x1e80100-llcc-bwmon", "qcom,sc7280-llcc-bwmon";
8539			reg = <0 0x24091000 0 0x1000>;
8540
8541			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
8542
8543			interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
8544					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>;
8545
8546			operating-points-v2 = <&llcc_bwmon_opp_table>;
8547
8548			llcc_bwmon_opp_table: opp-table {
8549				compatible = "operating-points-v2";
8550
8551				opp-0 {
8552					opp-peak-kBps = <800000>;
8553				};
8554
8555				opp-1 {
8556					opp-peak-kBps = <2188000>;
8557				};
8558
8559				opp-2 {
8560					opp-peak-kBps = <3072000>;
8561				};
8562
8563				opp-3 {
8564					opp-peak-kBps = <6220800>;
8565				};
8566
8567				opp-4 {
8568					opp-peak-kBps = <6835200>;
8569				};
8570
8571				opp-5 {
8572					opp-peak-kBps = <8371200>;
8573				};
8574
8575				opp-6 {
8576					opp-peak-kBps = <10944000>;
8577				};
8578
8579				opp-7 {
8580					opp-peak-kBps = <12748800>;
8581				};
8582
8583				opp-8 {
8584					opp-peak-kBps = <14745600>;
8585				};
8586
8587				opp-9 {
8588					opp-peak-kBps = <16896000>;
8589				};
8590			};
8591		};
8592
8593		/* cluster0 */
8594		bwmon_cluster0: pmu@240b3400 {
8595			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8596			reg = <0 0x240b3400 0 0x600>;
8597
8598			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
8599
8600			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
8601					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
8602
8603			operating-points-v2 = <&cpu_bwmon_opp_table>;
8604		};
8605
8606		/* cluster2 */
8607		bwmon_cluster2: pmu@240b5400 {
8608			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8609			reg = <0 0x240b5400 0 0x600>;
8610
8611			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
8612
8613			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
8614					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
8615
8616			operating-points-v2 = <&cpu_bwmon_opp_table>;
8617
8618			cpu_bwmon_opp_table: opp-table {
8619				compatible = "operating-points-v2";
8620
8621				opp-0 {
8622					opp-peak-kBps = <4800000>;
8623				};
8624
8625				opp-1 {
8626					opp-peak-kBps = <7464000>;
8627				};
8628
8629				opp-2 {
8630					opp-peak-kBps = <9600000>;
8631				};
8632
8633				opp-3 {
8634					opp-peak-kBps = <12896000>;
8635				};
8636
8637				opp-4 {
8638					opp-peak-kBps = <14928000>;
8639				};
8640
8641				opp-5 {
8642					opp-peak-kBps = <17064000>;
8643				};
8644			};
8645		};
8646
8647		/* cluster1 */
8648		pmu@240b6400 {
8649			compatible = "qcom,x1e80100-cpu-bwmon", "qcom,sdm845-bwmon";
8650			reg = <0 0x240b6400 0 0x600>;
8651
8652			interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
8653
8654			interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
8655					 &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>;
8656
8657			operating-points-v2 = <&cpu_bwmon_opp_table>;
8658		};
8659
8660		system-cache-controller@25000000 {
8661			compatible = "qcom,x1e80100-llcc";
8662			reg = <0 0x25000000 0 0x200000>,
8663			      <0 0x25200000 0 0x200000>,
8664			      <0 0x25400000 0 0x200000>,
8665			      <0 0x25600000 0 0x200000>,
8666			      <0 0x25800000 0 0x200000>,
8667			      <0 0x25a00000 0 0x200000>,
8668			      <0 0x25c00000 0 0x200000>,
8669			      <0 0x25e00000 0 0x200000>,
8670			      <0 0x26000000 0 0x200000>,
8671			      <0 0x26200000 0 0x200000>;
8672			reg-names = "llcc0_base",
8673				    "llcc1_base",
8674				    "llcc2_base",
8675				    "llcc3_base",
8676				    "llcc4_base",
8677				    "llcc5_base",
8678				    "llcc6_base",
8679				    "llcc7_base",
8680				    "llcc_broadcast_base",
8681				    "llcc_broadcast_and_base";
8682			interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
8683		};
8684
8685		remoteproc_cdsp: remoteproc@32300000 {
8686			compatible = "qcom,x1e80100-cdsp-pas";
8687			reg = <0x0 0x32300000 0x0 0x10000>;
8688
8689			interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
8690					      <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
8691					      <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
8692					      <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
8693					      <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
8694			interrupt-names = "wdog",
8695					  "fatal",
8696					  "ready",
8697					  "handover",
8698					  "stop-ack";
8699
8700			clocks = <&rpmhcc RPMH_CXO_CLK>;
8701			clock-names = "xo";
8702
8703			power-domains = <&rpmhpd RPMHPD_CX>,
8704					<&rpmhpd RPMHPD_MXC>,
8705					<&rpmhpd RPMHPD_NSP>;
8706			power-domain-names = "cx",
8707					     "mxc",
8708					     "nsp";
8709
8710			interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
8711					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
8712
8713			memory-region = <&cdsp_mem>,
8714					<&q6_cdsp_dtb_mem>;
8715
8716			qcom,qmp = <&aoss_qmp>;
8717
8718			qcom,smem-states = <&smp2p_cdsp_out 0>;
8719			qcom,smem-state-names = "stop";
8720
8721			status = "disabled";
8722
8723			glink-edge {
8724				interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
8725							     IPCC_MPROC_SIGNAL_GLINK_QMP
8726							     IRQ_TYPE_EDGE_RISING>;
8727				mboxes = <&ipcc IPCC_CLIENT_CDSP
8728						IPCC_MPROC_SIGNAL_GLINK_QMP>;
8729
8730				label = "cdsp";
8731				qcom,remote-pid = <5>;
8732
8733				fastrpc {
8734					compatible = "qcom,fastrpc";
8735					qcom,glink-channels = "fastrpcglink-apps-dsp";
8736					label = "cdsp";
8737					qcom,non-secure-domain;
8738					#address-cells = <1>;
8739					#size-cells = <0>;
8740
8741					compute-cb@1 {
8742						compatible = "qcom,fastrpc-compute-cb";
8743						reg = <1>;
8744						iommus = <&apps_smmu 0x0c01 0x20>;
8745						dma-coherent;
8746					};
8747
8748					compute-cb@2 {
8749						compatible = "qcom,fastrpc-compute-cb";
8750						reg = <2>;
8751						iommus = <&apps_smmu 0x0c02 0x20>;
8752						dma-coherent;
8753					};
8754
8755					compute-cb@3 {
8756						compatible = "qcom,fastrpc-compute-cb";
8757						reg = <3>;
8758						iommus = <&apps_smmu 0x0c03 0x20>;
8759						dma-coherent;
8760					};
8761
8762					compute-cb@4 {
8763						compatible = "qcom,fastrpc-compute-cb";
8764						reg = <4>;
8765						iommus = <&apps_smmu 0x0c04 0x20>;
8766						dma-coherent;
8767					};
8768
8769					compute-cb@5 {
8770						compatible = "qcom,fastrpc-compute-cb";
8771						reg = <5>;
8772						iommus = <&apps_smmu 0x0c05 0x20>;
8773						dma-coherent;
8774					};
8775
8776					compute-cb@6 {
8777						compatible = "qcom,fastrpc-compute-cb";
8778						reg = <6>;
8779						iommus = <&apps_smmu 0x0c06 0x20>;
8780						dma-coherent;
8781					};
8782
8783					compute-cb@7 {
8784						compatible = "qcom,fastrpc-compute-cb";
8785						reg = <7>;
8786						iommus = <&apps_smmu 0x0c07 0x20>;
8787						dma-coherent;
8788					};
8789
8790					compute-cb@8 {
8791						compatible = "qcom,fastrpc-compute-cb";
8792						reg = <8>;
8793						iommus = <&apps_smmu 0x0c08 0x20>;
8794						dma-coherent;
8795					};
8796
8797					/* note: compute-cb@9 is secure */
8798
8799					compute-cb@10 {
8800						compatible = "qcom,fastrpc-compute-cb";
8801						reg = <10>;
8802						iommus = <&apps_smmu 0x0c0c 0x20>;
8803						dma-coherent;
8804					};
8805
8806					compute-cb@11 {
8807						compatible = "qcom,fastrpc-compute-cb";
8808						reg = <11>;
8809						iommus = <&apps_smmu 0x0c0d 0x20>;
8810						dma-coherent;
8811					};
8812
8813					compute-cb@12 {
8814						compatible = "qcom,fastrpc-compute-cb";
8815						reg = <12>;
8816						iommus = <&apps_smmu 0x0c0e 0x20>;
8817						dma-coherent;
8818					};
8819
8820					compute-cb@13 {
8821						compatible = "qcom,fastrpc-compute-cb";
8822						reg = <13>;
8823						iommus = <&apps_smmu 0x0c0f 0x20>;
8824						dma-coherent;
8825					};
8826				};
8827			};
8828		};
8829	};
8830
8831	timer {
8832		compatible = "arm,armv8-timer";
8833
8834		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
8835			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
8836			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
8837			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
8838	};
8839
8840	thermal_zones: thermal-zones {
8841		aoss0-thermal {
8842			thermal-sensors = <&tsens0 0>;
8843
8844			trips {
8845				trip-point0 {
8846					temperature = <90000>;
8847					hysteresis = <2000>;
8848					type = "hot";
8849				};
8850
8851				aoss0-critical {
8852					temperature = <115000>;
8853					hysteresis = <1000>;
8854					type = "critical";
8855				};
8856			};
8857		};
8858
8859		cpu0-0-top-thermal {
8860			thermal-sensors = <&tsens0 1>;
8861
8862			trips {
8863				cpu-critical {
8864					temperature = <115000>;
8865					hysteresis = <1000>;
8866					type = "critical";
8867				};
8868			};
8869		};
8870
8871		cpu0-0-btm-thermal {
8872			thermal-sensors = <&tsens0 2>;
8873
8874			trips {
8875				cpu-critical {
8876					temperature = <115000>;
8877					hysteresis = <1000>;
8878					type = "critical";
8879				};
8880			};
8881		};
8882
8883		cpu0-1-top-thermal {
8884			thermal-sensors = <&tsens0 3>;
8885
8886			trips {
8887				cpu-critical {
8888					temperature = <115000>;
8889					hysteresis = <1000>;
8890					type = "critical";
8891				};
8892			};
8893		};
8894
8895		cpu0-1-btm-thermal {
8896			thermal-sensors = <&tsens0 4>;
8897
8898			trips {
8899				cpu-critical {
8900					temperature = <115000>;
8901					hysteresis = <1000>;
8902					type = "critical";
8903				};
8904			};
8905		};
8906
8907		cpu0-2-top-thermal {
8908			thermal-sensors = <&tsens0 5>;
8909
8910			trips {
8911				cpu-critical {
8912					temperature = <115000>;
8913					hysteresis = <1000>;
8914					type = "critical";
8915				};
8916			};
8917		};
8918
8919		cpu0-2-btm-thermal {
8920			thermal-sensors = <&tsens0 6>;
8921
8922			trips {
8923				cpu-critical {
8924					temperature = <115000>;
8925					hysteresis = <1000>;
8926					type = "critical";
8927				};
8928			};
8929		};
8930
8931		cpu0-3-top-thermal {
8932			thermal-sensors = <&tsens0 7>;
8933
8934			trips {
8935				cpu-critical {
8936					temperature = <115000>;
8937					hysteresis = <1000>;
8938					type = "critical";
8939				};
8940			};
8941		};
8942
8943		cpu0-3-btm-thermal {
8944			thermal-sensors = <&tsens0 8>;
8945
8946			trips {
8947				cpu-critical {
8948					temperature = <115000>;
8949					hysteresis = <1000>;
8950					type = "critical";
8951				};
8952			};
8953		};
8954
8955		cpuss0-top-thermal {
8956			thermal-sensors = <&tsens0 9>;
8957
8958			trips {
8959				cpuss2-critical {
8960					temperature = <115000>;
8961					hysteresis = <1000>;
8962					type = "critical";
8963				};
8964			};
8965		};
8966
8967		cpuss0-btm-thermal {
8968			thermal-sensors = <&tsens0 10>;
8969
8970			trips {
8971				cpuss2-critical {
8972					temperature = <115000>;
8973					hysteresis = <1000>;
8974					type = "critical";
8975				};
8976			};
8977		};
8978
8979		mem-thermal {
8980			thermal-sensors = <&tsens0 11>;
8981
8982			trips {
8983				trip-point0 {
8984					temperature = <90000>;
8985					hysteresis = <2000>;
8986					type = "hot";
8987				};
8988
8989				mem-critical {
8990					temperature = <115000>;
8991					hysteresis = <0>;
8992					type = "critical";
8993				};
8994			};
8995		};
8996
8997		video-thermal {
8998			thermal-sensors = <&tsens0 12>;
8999
9000			trips {
9001				trip-point0 {
9002					temperature = <90000>;
9003					hysteresis = <2000>;
9004					type = "hot";
9005				};
9006
9007				video-critical {
9008					temperature = <115000>;
9009					hysteresis = <1000>;
9010					type = "critical";
9011				};
9012			};
9013		};
9014
9015		aoss1-thermal {
9016			thermal-sensors = <&tsens1 0>;
9017
9018			trips {
9019				trip-point0 {
9020					temperature = <90000>;
9021					hysteresis = <2000>;
9022					type = "hot";
9023				};
9024
9025				aoss0-critical {
9026					temperature = <115000>;
9027					hysteresis = <1000>;
9028					type = "critical";
9029				};
9030			};
9031		};
9032
9033		cpu1-0-top-thermal {
9034			thermal-sensors = <&tsens1 1>;
9035
9036			trips {
9037				cpu-critical {
9038					temperature = <115000>;
9039					hysteresis = <1000>;
9040					type = "critical";
9041				};
9042			};
9043		};
9044
9045		cpu1-0-btm-thermal {
9046			thermal-sensors = <&tsens1 2>;
9047
9048			trips {
9049				cpu-critical {
9050					temperature = <115000>;
9051					hysteresis = <1000>;
9052					type = "critical";
9053				};
9054			};
9055		};
9056
9057		cpu1-1-top-thermal {
9058			thermal-sensors = <&tsens1 3>;
9059
9060			trips {
9061				cpu-critical {
9062					temperature = <115000>;
9063					hysteresis = <1000>;
9064					type = "critical";
9065				};
9066			};
9067		};
9068
9069		cpu1-1-btm-thermal {
9070			thermal-sensors = <&tsens1 4>;
9071
9072			trips {
9073				cpu-critical {
9074					temperature = <115000>;
9075					hysteresis = <1000>;
9076					type = "critical";
9077				};
9078			};
9079		};
9080
9081		cpu1-2-top-thermal {
9082			thermal-sensors = <&tsens1 5>;
9083
9084			trips {
9085				cpu-critical {
9086					temperature = <115000>;
9087					hysteresis = <1000>;
9088					type = "critical";
9089				};
9090			};
9091		};
9092
9093		cpu1-2-btm-thermal {
9094			thermal-sensors = <&tsens1 6>;
9095
9096			trips {
9097				cpu-critical {
9098					temperature = <115000>;
9099					hysteresis = <1000>;
9100					type = "critical";
9101				};
9102			};
9103		};
9104
9105		cpu1-3-top-thermal {
9106			thermal-sensors = <&tsens1 7>;
9107
9108			trips {
9109				cpu-critical {
9110					temperature = <115000>;
9111					hysteresis = <1000>;
9112					type = "critical";
9113				};
9114			};
9115		};
9116
9117		cpu1-3-btm-thermal {
9118			thermal-sensors = <&tsens1 8>;
9119
9120			trips {
9121				cpu-critical {
9122					temperature = <115000>;
9123					hysteresis = <1000>;
9124					type = "critical";
9125				};
9126			};
9127		};
9128
9129		cpuss1-top-thermal {
9130			thermal-sensors = <&tsens1 9>;
9131
9132			trips {
9133				cpuss2-critical {
9134					temperature = <115000>;
9135					hysteresis = <1000>;
9136					type = "critical";
9137				};
9138			};
9139		};
9140
9141		cpuss1-btm-thermal {
9142			thermal-sensors = <&tsens1 10>;
9143
9144			trips {
9145				cpuss2-critical {
9146					temperature = <115000>;
9147					hysteresis = <1000>;
9148					type = "critical";
9149				};
9150			};
9151		};
9152
9153		aoss2-thermal {
9154			thermal-sensors = <&tsens2 0>;
9155
9156			trips {
9157				trip-point0 {
9158					temperature = <90000>;
9159					hysteresis = <2000>;
9160					type = "hot";
9161				};
9162
9163				aoss0-critical {
9164					temperature = <115000>;
9165					hysteresis = <1000>;
9166					type = "critical";
9167				};
9168			};
9169		};
9170
9171		cpu2-0-top-thermal {
9172			thermal-sensors = <&tsens2 1>;
9173
9174			trips {
9175				cpu-critical {
9176					temperature = <115000>;
9177					hysteresis = <1000>;
9178					type = "critical";
9179				};
9180			};
9181		};
9182
9183		cpu2-0-btm-thermal {
9184			thermal-sensors = <&tsens2 2>;
9185
9186			trips {
9187				cpu-critical {
9188					temperature = <115000>;
9189					hysteresis = <1000>;
9190					type = "critical";
9191				};
9192			};
9193		};
9194
9195		cpu2-1-top-thermal {
9196			thermal-sensors = <&tsens2 3>;
9197
9198			trips {
9199				cpu-critical {
9200					temperature = <115000>;
9201					hysteresis = <1000>;
9202					type = "critical";
9203				};
9204			};
9205		};
9206
9207		cpu2-1-btm-thermal {
9208			thermal-sensors = <&tsens2 4>;
9209
9210			trips {
9211				cpu-critical {
9212					temperature = <115000>;
9213					hysteresis = <1000>;
9214					type = "critical";
9215				};
9216			};
9217		};
9218
9219		cpu2-2-top-thermal {
9220			thermal-sensors = <&tsens2 5>;
9221
9222			trips {
9223				cpu-critical {
9224					temperature = <115000>;
9225					hysteresis = <1000>;
9226					type = "critical";
9227				};
9228			};
9229		};
9230
9231		cpu2-2-btm-thermal {
9232			thermal-sensors = <&tsens2 6>;
9233
9234			trips {
9235				cpu-critical {
9236					temperature = <115000>;
9237					hysteresis = <1000>;
9238					type = "critical";
9239				};
9240			};
9241		};
9242
9243		cpu2-3-top-thermal {
9244			thermal-sensors = <&tsens2 7>;
9245
9246			trips {
9247				cpu-critical {
9248					temperature = <115000>;
9249					hysteresis = <1000>;
9250					type = "critical";
9251				};
9252			};
9253		};
9254
9255		cpu2-3-btm-thermal {
9256			thermal-sensors = <&tsens2 8>;
9257
9258			trips {
9259				cpu-critical {
9260					temperature = <115000>;
9261					hysteresis = <1000>;
9262					type = "critical";
9263				};
9264			};
9265		};
9266
9267		cpuss2-top-thermal {
9268			thermal-sensors = <&tsens2 9>;
9269
9270			trips {
9271				cpuss2-critical {
9272					temperature = <115000>;
9273					hysteresis = <1000>;
9274					type = "critical";
9275				};
9276			};
9277		};
9278
9279		cpuss2-btm-thermal {
9280			thermal-sensors = <&tsens2 10>;
9281
9282			trips {
9283				cpuss2-critical {
9284					temperature = <115000>;
9285					hysteresis = <1000>;
9286					type = "critical";
9287				};
9288			};
9289		};
9290
9291		aoss3-thermal {
9292			thermal-sensors = <&tsens3 0>;
9293
9294			trips {
9295				trip-point0 {
9296					temperature = <90000>;
9297					hysteresis = <2000>;
9298					type = "hot";
9299				};
9300
9301				aoss0-critical {
9302					temperature = <115000>;
9303					hysteresis = <1000>;
9304					type = "critical";
9305				};
9306			};
9307		};
9308
9309		nsp0-thermal {
9310			thermal-sensors = <&tsens3 1>;
9311
9312			trips {
9313				trip-point0 {
9314					temperature = <90000>;
9315					hysteresis = <2000>;
9316					type = "hot";
9317				};
9318
9319				nsp0-critical {
9320					temperature = <115000>;
9321					hysteresis = <1000>;
9322					type = "critical";
9323				};
9324			};
9325		};
9326
9327		nsp1-thermal {
9328			thermal-sensors = <&tsens3 2>;
9329
9330			trips {
9331				trip-point0 {
9332					temperature = <90000>;
9333					hysteresis = <2000>;
9334					type = "hot";
9335				};
9336
9337				nsp1-critical {
9338					temperature = <115000>;
9339					hysteresis = <1000>;
9340					type = "critical";
9341				};
9342			};
9343		};
9344
9345		nsp2-thermal {
9346			thermal-sensors = <&tsens3 3>;
9347
9348			trips {
9349				trip-point0 {
9350					temperature = <90000>;
9351					hysteresis = <2000>;
9352					type = "hot";
9353				};
9354
9355				nsp2-critical {
9356					temperature = <115000>;
9357					hysteresis = <1000>;
9358					type = "critical";
9359				};
9360			};
9361		};
9362
9363		nsp3-thermal {
9364			thermal-sensors = <&tsens3 4>;
9365
9366			trips {
9367				trip-point0 {
9368					temperature = <90000>;
9369					hysteresis = <2000>;
9370					type = "hot";
9371				};
9372
9373				nsp3-critical {
9374					temperature = <115000>;
9375					hysteresis = <1000>;
9376					type = "critical";
9377				};
9378			};
9379		};
9380
9381		gpuss-0-thermal {
9382			polling-delay-passive = <200>;
9383
9384			thermal-sensors = <&tsens3 5>;
9385
9386			cooling-maps {
9387				map0 {
9388					trip = <&gpuss0_alert0>;
9389					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9390				};
9391			};
9392
9393			trips {
9394				gpuss0_alert0: trip-point0 {
9395					temperature = <95000>;
9396					hysteresis = <1000>;
9397					type = "passive";
9398				};
9399
9400				gpu-critical {
9401					temperature = <115000>;
9402					hysteresis = <1000>;
9403					type = "critical";
9404				};
9405			};
9406		};
9407
9408		gpuss-1-thermal {
9409			polling-delay-passive = <200>;
9410
9411			thermal-sensors = <&tsens3 6>;
9412
9413			cooling-maps {
9414				map0 {
9415					trip = <&gpuss1_alert0>;
9416					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9417				};
9418			};
9419
9420			trips {
9421				gpuss1_alert0: trip-point0 {
9422					temperature = <95000>;
9423					hysteresis = <1000>;
9424					type = "passive";
9425				};
9426
9427				gpu-critical {
9428					temperature = <115000>;
9429					hysteresis = <1000>;
9430					type = "critical";
9431				};
9432			};
9433		};
9434
9435		gpuss-2-thermal {
9436			polling-delay-passive = <200>;
9437
9438			thermal-sensors = <&tsens3 7>;
9439
9440			cooling-maps {
9441				map0 {
9442					trip = <&gpuss2_alert0>;
9443					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9444				};
9445			};
9446
9447			trips {
9448				gpuss2_alert0: trip-point0 {
9449					temperature = <95000>;
9450					hysteresis = <1000>;
9451					type = "passive";
9452				};
9453
9454				gpu-critical {
9455					temperature = <115000>;
9456					hysteresis = <1000>;
9457					type = "critical";
9458				};
9459			};
9460		};
9461
9462		gpuss-3-thermal {
9463			polling-delay-passive = <200>;
9464
9465			thermal-sensors = <&tsens3 8>;
9466
9467			cooling-maps {
9468				map0 {
9469					trip = <&gpuss3_alert0>;
9470					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9471				};
9472			};
9473
9474			trips {
9475				gpuss3_alert0: trip-point0 {
9476					temperature = <95000>;
9477					hysteresis = <1000>;
9478					type = "passive";
9479				};
9480
9481				gpu-critical {
9482					temperature = <115000>;
9483					hysteresis = <1000>;
9484					type = "critical";
9485				};
9486			};
9487		};
9488
9489		gpuss-4-thermal {
9490			polling-delay-passive = <200>;
9491
9492			thermal-sensors = <&tsens3 9>;
9493
9494			cooling-maps {
9495				map0 {
9496					trip = <&gpuss4_alert0>;
9497					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9498				};
9499			};
9500
9501			trips {
9502				gpuss4_alert0: trip-point0 {
9503					temperature = <95000>;
9504					hysteresis = <1000>;
9505					type = "passive";
9506				};
9507
9508				gpu-critical {
9509					temperature = <115000>;
9510					hysteresis = <1000>;
9511					type = "critical";
9512				};
9513			};
9514		};
9515
9516		gpuss-5-thermal {
9517			polling-delay-passive = <200>;
9518
9519			thermal-sensors = <&tsens3 10>;
9520
9521			cooling-maps {
9522				map0 {
9523					trip = <&gpuss5_alert0>;
9524					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9525				};
9526			};
9527
9528			trips {
9529				gpuss5_alert0: trip-point0 {
9530					temperature = <95000>;
9531					hysteresis = <1000>;
9532					type = "passive";
9533				};
9534
9535				gpu-critical {
9536					temperature = <115000>;
9537					hysteresis = <1000>;
9538					type = "critical";
9539				};
9540			};
9541		};
9542
9543		gpuss-6-thermal {
9544			polling-delay-passive = <200>;
9545
9546			thermal-sensors = <&tsens3 11>;
9547
9548			cooling-maps {
9549				map0 {
9550					trip = <&gpuss6_alert0>;
9551					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9552				};
9553			};
9554
9555			trips {
9556				gpuss6_alert0: trip-point0 {
9557					temperature = <95000>;
9558					hysteresis = <1000>;
9559					type = "passive";
9560				};
9561
9562				gpu-critical {
9563					temperature = <115000>;
9564					hysteresis = <1000>;
9565					type = "critical";
9566				};
9567			};
9568		};
9569
9570		gpuss-7-thermal {
9571			polling-delay-passive = <200>;
9572
9573			thermal-sensors = <&tsens3 12>;
9574
9575			cooling-maps {
9576				map0 {
9577					trip = <&gpuss7_alert0>;
9578					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
9579				};
9580			};
9581
9582			trips {
9583				gpuss7_alert0: trip-point0 {
9584					temperature = <95000>;
9585					hysteresis = <1000>;
9586					type = "passive";
9587				};
9588
9589				gpu-critical {
9590					temperature = <115000>;
9591					hysteresis = <1000>;
9592					type = "critical";
9593				};
9594			};
9595		};
9596
9597		camera0-thermal {
9598			thermal-sensors = <&tsens3 13>;
9599
9600			trips {
9601				trip-point0 {
9602					temperature = <90000>;
9603					hysteresis = <2000>;
9604					type = "hot";
9605				};
9606
9607				camera0-critical {
9608					temperature = <115000>;
9609					hysteresis = <1000>;
9610					type = "critical";
9611				};
9612			};
9613		};
9614
9615		camera1-thermal {
9616			thermal-sensors = <&tsens3 14>;
9617
9618			trips {
9619				trip-point0 {
9620					temperature = <90000>;
9621					hysteresis = <2000>;
9622					type = "hot";
9623				};
9624
9625				camera0-critical {
9626					temperature = <115000>;
9627					hysteresis = <1000>;
9628					type = "critical";
9629				};
9630			};
9631		};
9632	};
9633};