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agatti.dtsi
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linux-6.19.14/arch/arm64/boot/dts/qcom/agatti.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) 2/* 3 * Copyright (c) 2023, Linaro Ltd 4 * 5 * Based on sm6115.dtsi and previous efforts by Shawn Guo & Loic Poulain. 6 */ 7 8#include <dt-bindings/clock/qcom,dispcc-qcm2290.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-qcm2290.h> 11#include <dt-bindings/clock/qcom,qcm2290-gpucc.h> 12#include <dt-bindings/clock/qcom,rpmcc.h> 13#include <dt-bindings/dma/qcom-gpi.h> 14#include <dt-bindings/firmware/qcom,scm.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/interrupt-controller/arm-gic.h> 17#include <dt-bindings/interconnect/qcom,qcm2290.h> 18#include <dt-bindings/interconnect/qcom,rpm-icc.h> 19#include <dt-bindings/power/qcom-rpmpd.h> 20#include <dt-bindings/soc/qcom,apr.h> 21#include <dt-bindings/sound/qcom,q6asm.h> 22#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 23 24/ { 25 interrupt-parent = <&intc>; 26 27 #address-cells = <2>; 28 #size-cells = <2>; 29 30 chosen { }; 31 32 clocks { 33 xo_board: xo-board { 34 compatible = "fixed-clock"; 35 #clock-cells = <0>; 36 }; 37 38 sleep_clk: sleep-clk { 39 compatible = "fixed-clock"; 40 clock-frequency = <32764>; 41 #clock-cells = <0>; 42 }; 43 }; 44 45 cpus { 46 #address-cells = <2>; 47 #size-cells = <0>; 48 49 cpu0: cpu@0 { 50 device_type = "cpu"; 51 compatible = "arm,cortex-a53"; 52 reg = <0x0 0x0>; 53 clocks = <&cpufreq_hw 0>; 54 capacity-dmips-mhz = <1024>; 55 dynamic-power-coefficient = <100>; 56 enable-method = "psci"; 57 next-level-cache = <&l2_0>; 58 qcom,freq-domain = <&cpufreq_hw 0>; 59 power-domains = <&cpu_pd0>; 60 power-domain-names = "psci"; 61 l2_0: l2-cache { 62 compatible = "cache"; 63 cache-level = <2>; 64 cache-unified; 65 }; 66 }; 67 68 cpu1: cpu@1 { 69 device_type = "cpu"; 70 compatible = "arm,cortex-a53"; 71 reg = <0x0 0x1>; 72 clocks = <&cpufreq_hw 0>; 73 capacity-dmips-mhz = <1024>; 74 dynamic-power-coefficient = <100>; 75 enable-method = "psci"; 76 next-level-cache = <&l2_0>; 77 qcom,freq-domain = <&cpufreq_hw 0>; 78 power-domains = <&cpu_pd1>; 79 power-domain-names = "psci"; 80 }; 81 82 cpu2: cpu@2 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a53"; 85 reg = <0x0 0x2>; 86 clocks = <&cpufreq_hw 0>; 87 capacity-dmips-mhz = <1024>; 88 dynamic-power-coefficient = <100>; 89 enable-method = "psci"; 90 next-level-cache = <&l2_0>; 91 qcom,freq-domain = <&cpufreq_hw 0>; 92 power-domains = <&cpu_pd2>; 93 power-domain-names = "psci"; 94 }; 95 96 cpu3: cpu@3 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a53"; 99 reg = <0x0 0x3>; 100 clocks = <&cpufreq_hw 0>; 101 capacity-dmips-mhz = <1024>; 102 dynamic-power-coefficient = <100>; 103 enable-method = "psci"; 104 next-level-cache = <&l2_0>; 105 qcom,freq-domain = <&cpufreq_hw 0>; 106 power-domains = <&cpu_pd3>; 107 power-domain-names = "psci"; 108 }; 109 110 cpu-map { 111 cluster0 { 112 core0 { 113 cpu = <&cpu0>; 114 }; 115 116 core1 { 117 cpu = <&cpu1>; 118 }; 119 120 core2 { 121 cpu = <&cpu2>; 122 }; 123 124 core3 { 125 cpu = <&cpu3>; 126 }; 127 }; 128 }; 129 130 domain-idle-states { 131 cluster_sleep: cluster-sleep-0 { 132 compatible = "domain-idle-state"; 133 arm,psci-suspend-param = <0x41000043>; 134 entry-latency-us = <800>; 135 exit-latency-us = <2118>; 136 min-residency-us = <7376>; 137 }; 138 }; 139 140 idle-states { 141 entry-method = "psci"; 142 143 cpu_sleep: cpu-sleep-0 { 144 compatible = "arm,idle-state"; 145 idle-state-name = "power-collapse"; 146 arm,psci-suspend-param = <0x40000003>; 147 entry-latency-us = <290>; 148 exit-latency-us = <376>; 149 min-residency-us = <1182>; 150 local-timer-stop; 151 }; 152 }; 153 }; 154 155 firmware { 156 scm: scm { 157 compatible = "qcom,scm-qcm2290", "qcom,scm"; 158 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 159 clock-names = "core"; 160 qcom,dload-mode = <&tcsr_regs 0x13000>; 161 #reset-cells = <1>; 162 interconnects = <&system_noc MASTER_CRYPTO_CORE0 RPM_ALWAYS_TAG 163 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 164 }; 165 }; 166 167 memory@40000000 { 168 device_type = "memory"; 169 /* We expect the bootloader to fill in the size */ 170 reg = <0 0x40000000 0 0>; 171 }; 172 173 pmu { 174 compatible = "arm,cortex-a53-pmu"; 175 interrupts = <GIC_PPI 6 IRQ_TYPE_LEVEL_HIGH>; 176 }; 177 178 psci { 179 compatible = "arm,psci-1.0"; 180 method = "smc"; 181 182 cpu_pd0: power-domain-cpu0 { 183 #power-domain-cells = <0>; 184 power-domains = <&cluster_pd>; 185 domain-idle-states = <&cpu_sleep>; 186 }; 187 188 cpu_pd1: power-domain-cpu1 { 189 #power-domain-cells = <0>; 190 power-domains = <&cluster_pd>; 191 domain-idle-states = <&cpu_sleep>; 192 }; 193 194 cpu_pd2: power-domain-cpu2 { 195 #power-domain-cells = <0>; 196 power-domains = <&cluster_pd>; 197 domain-idle-states = <&cpu_sleep>; 198 }; 199 200 cpu_pd3: power-domain-cpu3 { 201 #power-domain-cells = <0>; 202 power-domains = <&cluster_pd>; 203 domain-idle-states = <&cpu_sleep>; 204 }; 205 206 cluster_pd: power-domain-cpu-cluster { 207 #power-domain-cells = <0>; 208 power-domains = <&mpm>; 209 domain-idle-states = <&cluster_sleep>; 210 }; 211 }; 212 213 rpm: remoteproc { 214 compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; 215 216 glink-edge { 217 compatible = "qcom,glink-rpm"; 218 interrupts = <GIC_SPI 194 IRQ_TYPE_EDGE_RISING>; 219 qcom,rpm-msg-ram = <&rpm_msg_ram>; 220 mboxes = <&apcs_glb 0>; 221 222 rpm_requests: rpm-requests { 223 compatible = "qcom,rpm-qcm2290", "qcom,glink-smd-rpm"; 224 qcom,glink-channels = "rpm_requests"; 225 226 rpmcc: clock-controller { 227 compatible = "qcom,rpmcc-qcm2290", "qcom,rpmcc"; 228 clocks = <&xo_board>; 229 clock-names = "xo"; 230 #clock-cells = <1>; 231 }; 232 233 rpmpd: power-controller { 234 compatible = "qcom,qcm2290-rpmpd"; 235 #power-domain-cells = <1>; 236 operating-points-v2 = <&rpmpd_opp_table>; 237 238 rpmpd_opp_table: opp-table { 239 compatible = "operating-points-v2"; 240 241 rpmpd_opp_min_svs: opp1 { 242 opp-level = <RPM_SMD_LEVEL_MIN_SVS>; 243 }; 244 245 rpmpd_opp_low_svs: opp2 { 246 opp-level = <RPM_SMD_LEVEL_LOW_SVS>; 247 }; 248 249 rpmpd_opp_svs: opp3 { 250 opp-level = <RPM_SMD_LEVEL_SVS>; 251 }; 252 253 rpmpd_opp_svs_plus: opp4 { 254 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>; 255 }; 256 257 rpmpd_opp_nom: opp5 { 258 opp-level = <RPM_SMD_LEVEL_NOM>; 259 }; 260 261 rpmpd_opp_nom_plus: opp6 { 262 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>; 263 }; 264 265 rpmpd_opp_turbo: opp7 { 266 opp-level = <RPM_SMD_LEVEL_TURBO>; 267 }; 268 269 rpmpd_opp_turbo_plus: opp8 { 270 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>; 271 }; 272 }; 273 }; 274 }; 275 }; 276 277 mpm: interrupt-controller { 278 compatible = "qcom,mpm"; 279 qcom,rpm-msg-ram = <&apss_mpm>; 280 interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>; 281 mboxes = <&apcs_glb 1>; 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 #power-domain-cells = <0>; 285 interrupt-parent = <&intc>; 286 qcom,mpm-pin-count = <96>; 287 qcom,mpm-pin-map = <2 275>, /* TSENS0 uplow */ 288 <5 296>, /* Soundwire master_irq */ 289 <12 422>, /* DWC3 ss_phy_irq */ 290 <24 79>, /* Soundwire wake_irq */ 291 <86 183>, /* MPM wake, SPMI */ 292 <90 260>; /* QUSB2_PHY DP+DM */ 293 }; 294 }; 295 296 reserved_memory: reserved-memory { 297 #address-cells = <2>; 298 #size-cells = <2>; 299 ranges; 300 301 hyp_mem: hyp@45700000 { 302 reg = <0x0 0x45700000 0x0 0x600000>; 303 no-map; 304 }; 305 306 xbl_aop_mem: xbl-aop@45e00000 { 307 reg = <0x0 0x45e00000 0x0 0x140000>; 308 no-map; 309 }; 310 311 sec_apps_mem: sec-apps@45fff000 { 312 reg = <0x0 0x45fff000 0x0 0x1000>; 313 no-map; 314 }; 315 316 smem_mem: smem@46000000 { 317 compatible = "qcom,smem"; 318 reg = <0x0 0x46000000 0x0 0x200000>; 319 no-map; 320 321 hwlocks = <&tcsr_mutex 3>; 322 qcom,rpm-msg-ram = <&rpm_msg_ram>; 323 }; 324 325 pil_modem_mem: modem@4ab00000 { 326 reg = <0x0 0x4ab00000 0x0 0x6900000>; 327 no-map; 328 }; 329 330 pil_video_mem: video@51400000 { 331 reg = <0x0 0x51400000 0x0 0x500000>; 332 no-map; 333 }; 334 335 wlan_msa_mem: wlan-msa@51900000 { 336 reg = <0x0 0x51900000 0x0 0x100000>; 337 no-map; 338 }; 339 340 pil_adsp_mem: adsp@51a00000 { 341 reg = <0x0 0x51a00000 0x0 0x1c00000>; 342 no-map; 343 }; 344 345 pil_ipa_fw_mem: ipa-fw@53600000 { 346 reg = <0x0 0x53600000 0x0 0x10000>; 347 no-map; 348 }; 349 350 pil_ipa_gsi_mem: ipa-gsi@53610000 { 351 reg = <0x0 0x53610000 0x0 0x5000>; 352 no-map; 353 }; 354 355 pil_gpu_mem: zap@53615000 { 356 compatible = "shared-dma-pool"; 357 reg = <0x0 0x53615000 0x0 0x2000>; 358 no-map; 359 }; 360 361 cont_splash_memory: framebuffer@5c000000 { 362 reg = <0x0 0x5c000000 0x0 0x00f00000>; 363 no-map; 364 }; 365 366 dfps_data_memory: dpfs-data@5cf00000 { 367 reg = <0x0 0x5cf00000 0x0 0x0100000>; 368 no-map; 369 }; 370 371 removed_mem: reserved@60000000 { 372 reg = <0x0 0x60000000 0x0 0x3900000>; 373 no-map; 374 }; 375 376 rmtfs_mem: memory@89b01000 { 377 compatible = "qcom,rmtfs-mem"; 378 reg = <0x0 0x89b01000 0x0 0x200000>; 379 no-map; 380 381 qcom,client-id = <1>; 382 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA QCOM_SCM_VMID_NAV>; 383 }; 384 }; 385 386 smp2p-adsp { 387 compatible = "qcom,smp2p"; 388 qcom,smem = <443>, <429>; 389 390 interrupts = <GIC_SPI 279 IRQ_TYPE_EDGE_RISING>; 391 392 mboxes = <&apcs_glb 10>; 393 394 qcom,local-pid = <0>; 395 qcom,remote-pid = <2>; 396 397 adsp_smp2p_out: master-kernel { 398 qcom,entry-name = "master-kernel"; 399 #qcom,smem-state-cells = <1>; 400 }; 401 402 adsp_smp2p_in: slave-kernel { 403 qcom,entry-name = "slave-kernel"; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 }; 407 }; 408 409 smp2p-mpss { 410 compatible = "qcom,smp2p"; 411 qcom,smem = <435>, <428>; 412 413 interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>; 414 415 mboxes = <&apcs_glb 14>; 416 417 qcom,local-pid = <0>; 418 qcom,remote-pid = <1>; 419 420 modem_smp2p_out: master-kernel { 421 qcom,entry-name = "master-kernel"; 422 #qcom,smem-state-cells = <1>; 423 }; 424 425 modem_smp2p_in: slave-kernel { 426 qcom,entry-name = "slave-kernel"; 427 interrupt-controller; 428 #interrupt-cells = <2>; 429 }; 430 431 wlan_smp2p_in: wlan-wpss-to-ap { 432 qcom,entry-name = "wlan"; 433 interrupt-controller; 434 #interrupt-cells = <2>; 435 }; 436 }; 437 438 soc: soc@0 { 439 compatible = "simple-bus"; 440 #address-cells = <2>; 441 #size-cells = <2>; 442 ranges = <0 0 0 0 0x10 0>; 443 dma-ranges = <0 0 0 0 0x10 0>; 444 445 tcsr_mutex: hwlock@340000 { 446 compatible = "qcom,tcsr-mutex"; 447 reg = <0x0 0x00340000 0x0 0x20000>; 448 #hwlock-cells = <1>; 449 }; 450 451 tcsr_regs: syscon@3c0000 { 452 compatible = "qcom,qcm2290-tcsr", "syscon"; 453 reg = <0x0 0x003c0000 0x0 0x40000>; 454 }; 455 456 tlmm: pinctrl@500000 { 457 compatible = "qcom,qcm2290-tlmm"; 458 reg = <0x0 0x00500000 0x0 0x300000>; 459 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; 460 gpio-controller; 461 gpio-ranges = <&tlmm 0 0 127>; 462 wakeup-parent = <&mpm>; 463 #gpio-cells = <2>; 464 interrupt-controller; 465 #interrupt-cells = <2>; 466 467 qup_i2c0_default: qup-i2c0-default-state { 468 pins = "gpio0", "gpio1"; 469 function = "qup0"; 470 drive-strength = <2>; 471 bias-pull-up; 472 }; 473 474 qup_i2c1_default: qup-i2c1-default-state { 475 pins = "gpio4", "gpio5"; 476 function = "qup1"; 477 drive-strength = <2>; 478 bias-pull-up; 479 }; 480 481 qup_i2c2_default: qup-i2c2-default-state { 482 pins = "gpio6", "gpio7"; 483 function = "qup2"; 484 drive-strength = <2>; 485 bias-pull-up; 486 }; 487 488 qup_i2c3_default: qup-i2c3-default-state { 489 pins = "gpio8", "gpio9"; 490 function = "qup3"; 491 drive-strength = <2>; 492 bias-pull-up; 493 }; 494 495 qup_i2c4_default: qup-i2c4-default-state { 496 pins = "gpio12", "gpio13"; 497 function = "qup4"; 498 drive-strength = <2>; 499 bias-pull-up; 500 }; 501 502 qup_i2c5_default: qup-i2c5-default-state { 503 pins = "gpio14", "gpio15"; 504 function = "qup5"; 505 drive-strength = <2>; 506 bias-pull-up; 507 }; 508 509 qup_spi0_default: qup-spi0-default-state { 510 pins = "gpio0", "gpio1","gpio2", "gpio3"; 511 function = "qup0"; 512 drive-strength = <2>; 513 bias-pull-up; 514 }; 515 516 qup_spi1_default: qup-spi1-default-state { 517 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 518 function = "qup1"; 519 drive-strength = <2>; 520 bias-pull-up; 521 }; 522 523 qup_spi2_default: qup-spi2-default-state { 524 pins = "gpio6", "gpio7", "gpio71", "gpio80"; 525 function = "qup2"; 526 drive-strength = <2>; 527 bias-pull-up; 528 }; 529 530 qup_spi3_default: qup-spi3-default-state { 531 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 532 function = "qup3"; 533 drive-strength = <2>; 534 bias-pull-up; 535 }; 536 537 qup_spi4_default: qup-spi4-default-state { 538 pins = "gpio12", "gpio13", "gpio96", "gpio97"; 539 function = "qup4"; 540 drive-strength = <2>; 541 bias-pull-up; 542 }; 543 544 qup_spi5_default: qup-spi5-default-state { 545 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 546 function = "qup5"; 547 drive-strength = <2>; 548 bias-pull-up; 549 }; 550 551 qup_uart0_default: qup-uart0-default-state { 552 pins = "gpio0", "gpio1", "gpio2", "gpio3"; 553 function = "qup0"; 554 drive-strength = <2>; 555 bias-disable; 556 }; 557 558 qup_uart1_default: qup-uart1-default-state { 559 pins = "gpio4", "gpio5", "gpio69", "gpio70"; 560 function = "qup1"; 561 drive-strength = <2>; 562 bias-disable; 563 }; 564 565 qup_uart3_default: qup-uart3-default-state { 566 pins = "gpio8", "gpio9", "gpio10", "gpio11"; 567 function = "qup3"; 568 drive-strength = <2>; 569 bias-disable; 570 }; 571 572 qup_uart4_default: qup-uart4-default-state { 573 pins = "gpio12", "gpio13"; 574 function = "qup4"; 575 drive-strength = <2>; 576 bias-disable; 577 }; 578 579 qup_uart5_default: qup-uart5-default-state { 580 pins = "gpio14", "gpio15", "gpio16", "gpio17"; 581 function = "qup5"; 582 drive-strength = <2>; 583 bias-disable; 584 }; 585 586 cci0_default: cci0-default-state { 587 pins = "gpio22", "gpio23"; 588 function = "cci_i2c"; 589 drive-strength = <2>; 590 bias-disable; 591 }; 592 593 cci1_default: cci1-default-state { 594 pins = "gpio29", "gpio30"; 595 function = "cci_i2c"; 596 drive-strength = <2>; 597 bias-disable; 598 }; 599 600 sdc1_state_on: sdc1-on-state { 601 clk-pins { 602 pins = "sdc1_clk"; 603 drive-strength = <16>; 604 bias-disable; 605 }; 606 607 cmd-pins { 608 pins = "sdc1_cmd"; 609 drive-strength = <10>; 610 bias-pull-up; 611 }; 612 613 data-pins { 614 pins = "sdc1_data"; 615 drive-strength = <10>; 616 bias-pull-up; 617 }; 618 619 rclk-pins { 620 pins = "sdc1_rclk"; 621 bias-pull-down; 622 }; 623 }; 624 625 sdc1_state_off: sdc1-off-state { 626 clk-pins { 627 pins = "sdc1_clk"; 628 drive-strength = <2>; 629 bias-disable; 630 }; 631 632 cmd-pins { 633 pins = "sdc1_cmd"; 634 drive-strength = <2>; 635 bias-pull-up; 636 }; 637 638 data-pins { 639 pins = "sdc1_data"; 640 drive-strength = <2>; 641 bias-pull-up; 642 }; 643 644 rclk-pins { 645 pins = "sdc1_rclk"; 646 bias-pull-down; 647 }; 648 }; 649 650 sdc2_state_on: sdc2-on-state { 651 clk-pins { 652 pins = "sdc2_clk"; 653 drive-strength = <16>; 654 bias-disable; 655 }; 656 657 cmd-pins { 658 pins = "sdc2_cmd"; 659 drive-strength = <10>; 660 bias-pull-up; 661 }; 662 663 data-pins { 664 pins = "sdc2_data"; 665 drive-strength = <10>; 666 bias-pull-up; 667 }; 668 }; 669 670 sdc2_state_off: sdc2-off-state { 671 clk-pins { 672 pins = "sdc2_clk"; 673 drive-strength = <2>; 674 bias-disable; 675 }; 676 677 cmd-pins { 678 pins = "sdc2_cmd"; 679 drive-strength = <2>; 680 bias-pull-up; 681 }; 682 683 data-pins { 684 pins = "sdc2_data"; 685 drive-strength = <2>; 686 bias-pull-up; 687 }; 688 }; 689 }; 690 691 lpass_tlmm: pinctrl@a7c0000 { 692 compatible = "qcom,qcm2290-lpass-lpi-pinctrl", 693 "qcom,sm6115-lpass-lpi-pinctrl"; 694 reg = <0x0 0x0a7c0000 0x0 0x20000>, 695 <0x0 0x0a950000 0x0 0x10000>; 696 697 clocks = <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 698 clock-names = "audio"; 699 700 gpio-controller; 701 #gpio-cells = <2>; 702 gpio-ranges = <&lpass_tlmm 0 0 19>; 703 704 lpi_i2s2_active: lpi-i2s2-active-state { 705 sck-pins { 706 pins = "gpio10"; 707 function = "i2s2_clk"; 708 bias-disable; 709 drive-strength = <8>; 710 }; 711 712 ws-pins { 713 pins = "gpio11"; 714 function = "i2s2_ws"; 715 bias-disable; 716 drive-strength = <8>; 717 }; 718 719 data-pins { 720 pins = "gpio12"; 721 function = "i2s2_data"; 722 bias-disable; 723 drive-strength = <8>; 724 }; 725 }; 726 }; 727 728 gcc: clock-controller@1400000 { 729 compatible = "qcom,gcc-qcm2290"; 730 reg = <0x0 0x01400000 0x0 0x1f0000>; 731 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>; 732 clock-names = "bi_tcxo", "sleep_clk"; 733 #clock-cells = <1>; 734 #reset-cells = <1>; 735 #power-domain-cells = <1>; 736 }; 737 738 usb_hsphy: phy@1613000 { 739 compatible = "qcom,qcm2290-qusb2-phy"; 740 reg = <0x0 0x01613000 0x0 0x180>; 741 742 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 743 <&rpmcc RPM_SMD_XO_CLK_SRC>; 744 clock-names = "cfg_ahb", "ref"; 745 746 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 747 nvmem-cells = <&qusb2_hstx_trim>; 748 #phy-cells = <0>; 749 750 status = "disabled"; 751 }; 752 753 usb_qmpphy: phy@1615000 { 754 compatible = "qcom,qcm2290-qmp-usb3-phy"; 755 reg = <0x0 0x01615000 0x0 0x1000>; 756 757 clocks = <&gcc GCC_AHB2PHY_USB_CLK>, 758 <&gcc GCC_USB3_PRIM_CLKREF_CLK>, 759 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 760 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 761 clock-names = "cfg_ahb", 762 "ref", 763 "com_aux", 764 "pipe"; 765 766 resets = <&gcc GCC_USB3_PHY_PRIM_SP0_BCR>, 767 <&gcc GCC_USB3PHY_PHY_PRIM_SP0_BCR>; 768 reset-names = "phy", 769 "phy_phy"; 770 771 #clock-cells = <0>; 772 clock-output-names = "usb3_phy_pipe_clk_src"; 773 774 #phy-cells = <0>; 775 orientation-switch; 776 777 qcom,tcsr-reg = <&tcsr_regs 0xb244>; 778 779 status = "disabled"; 780 781 ports { 782 #address-cells = <1>; 783 #size-cells = <0>; 784 785 port@0 { 786 reg = <0>; 787 788 usb_qmpphy_out: endpoint { 789 }; 790 }; 791 792 port@1 { 793 reg = <1>; 794 795 usb_qmpphy_usb_ss_in: endpoint { 796 remote-endpoint = <&usb_dwc3_ss>; 797 }; 798 }; 799 }; 800 }; 801 802 system_noc: interconnect@1880000 { 803 compatible = "qcom,qcm2290-snoc"; 804 reg = <0x0 0x01880000 0x0 0x60200>; 805 #interconnect-cells = <2>; 806 807 qup_virt: interconnect-qup { 808 compatible = "qcom,qcm2290-qup-virt"; 809 #interconnect-cells = <2>; 810 }; 811 812 mmnrt_virt: interconnect-mmnrt { 813 compatible = "qcom,qcm2290-mmnrt-virt"; 814 #interconnect-cells = <2>; 815 }; 816 817 mmrt_virt: interconnect-mmrt { 818 compatible = "qcom,qcm2290-mmrt-virt"; 819 #interconnect-cells = <2>; 820 }; 821 }; 822 823 config_noc: interconnect@1900000 { 824 compatible = "qcom,qcm2290-cnoc"; 825 reg = <0x0 0x01900000 0x0 0x8200>; 826 #interconnect-cells = <2>; 827 }; 828 829 cryptobam: dma-controller@1b04000 { 830 compatible = "qcom,bam-v1.7.0"; 831 reg = <0x0 0x01b04000 0x0 0x24000>; 832 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 833 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 834 clock-names = "bam_clk"; 835 #dma-cells = <1>; 836 qcom,ee = <0>; 837 qcom,controlled-remotely; 838 iommus = <&apps_smmu 0x0084 0x11>, 839 <&apps_smmu 0x0086 0x11>; 840 }; 841 842 crypto: crypto@1b3a000 { 843 compatible = "qcom,qcm2290-qce", "qcom,ipq4019-qce", "qcom,qce"; 844 reg = <0x0 0x01b3a000 0x0 0x6000>; 845 clocks = <&rpmcc RPM_SMD_CE1_CLK>; 846 clock-names = "core"; 847 dmas = <&cryptobam 6>, <&cryptobam 7>; 848 dma-names = "rx", "tx"; 849 iommus = <&apps_smmu 0x0084 0x11>, 850 <&apps_smmu 0x0086 0x11>; 851 }; 852 853 qfprom@1b44000 { 854 compatible = "qcom,qcm2290-qfprom", "qcom,qfprom"; 855 reg = <0x0 0x01b44000 0x0 0x3000>; 856 #address-cells = <1>; 857 #size-cells = <1>; 858 859 qusb2_hstx_trim: hstx-trim@25b { 860 reg = <0x25b 0x1>; 861 bits = <1 4>; 862 }; 863 864 gpu_speed_bin: gpu-speed-bin@2006 { 865 reg = <0x2006 0x2>; 866 bits = <5 8>; 867 }; 868 }; 869 870 pmu@1b8e300 { 871 compatible = "qcom,qcm2290-cpu-bwmon", "qcom,sdm845-bwmon"; 872 reg = <0x0 0x01b8e300 0x0 0x600>; 873 interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>; 874 875 operating-points-v2 = <&cpu_bwmon_opp_table>; 876 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 877 &bimc SLAVE_EBI1 RPM_ACTIVE_TAG>; 878 879 cpu_bwmon_opp_table: opp-table { 880 compatible = "operating-points-v2"; 881 882 opp-0 { 883 opp-peak-kBps = <(200 * 4 * 1000)>; 884 }; 885 886 opp-1 { 887 opp-peak-kBps = <(300 * 4 * 1000)>; 888 }; 889 890 opp-2 { 891 opp-peak-kBps = <(451 * 4 * 1000)>; 892 }; 893 894 opp-3 { 895 opp-peak-kBps = <(547 * 4 * 1000)>; 896 }; 897 898 opp-4 { 899 opp-peak-kBps = <(681 * 4 * 1000)>; 900 }; 901 902 opp-5 { 903 opp-peak-kBps = <(768 * 4 * 1000)>; 904 }; 905 906 opp-6 { 907 opp-peak-kBps = <(1017 * 4 * 1000)>; 908 }; 909 910 opp-7 { 911 opp-peak-kBps = <(1353 * 4 * 1000)>; 912 }; 913 914 opp-8 { 915 opp-peak-kBps = <(1555 * 4 * 1000)>; 916 }; 917 918 opp-9 { 919 opp-peak-kBps = <(1804 * 4 * 1000)>; 920 }; 921 }; 922 }; 923 924 spmi_bus: spmi@1c40000 { 925 compatible = "qcom,spmi-pmic-arb"; 926 reg = <0x0 0x01c40000 0x0 0x1100>, 927 <0x0 0x01e00000 0x0 0x2000000>, 928 <0x0 0x03e00000 0x0 0x100000>, 929 <0x0 0x03f00000 0x0 0xa0000>, 930 <0x0 0x01c0a000 0x0 0x26000>; 931 reg-names = "core", 932 "chnls", 933 "obsrvr", 934 "intr", 935 "cnfg"; 936 interrupts-extended = <&mpm 86 IRQ_TYPE_LEVEL_HIGH>; 937 interrupt-names = "periph_irq"; 938 qcom,ee = <0>; 939 qcom,channel = <0>; 940 #address-cells = <2>; 941 #size-cells = <0>; 942 interrupt-controller; 943 #interrupt-cells = <4>; 944 }; 945 946 tsens0: thermal-sensor@4411000 { 947 compatible = "qcom,qcm2290-tsens", "qcom,tsens-v2"; 948 reg = <0x0 0x04411000 0x0 0x1ff>, 949 <0x0 0x04410000 0x0 0x8>; 950 #qcom,sensors = <10>; 951 interrupts-extended = <&mpm 2 IRQ_TYPE_LEVEL_HIGH>, 952 <&intc GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 953 interrupt-names = "uplow", "critical"; 954 #thermal-sensor-cells = <1>; 955 }; 956 957 rng: rng@4453000 { 958 compatible = "qcom,prng-ee"; 959 reg = <0x0 0x04453000 0x0 0x1000>; 960 clocks = <&rpmcc RPM_SMD_HWKM_CLK>; 961 clock-names = "core"; 962 }; 963 964 bimc: interconnect@4480000 { 965 compatible = "qcom,qcm2290-bimc"; 966 reg = <0x0 0x04480000 0x0 0x80000>; 967 #interconnect-cells = <2>; 968 }; 969 970 rpm_msg_ram: sram@45f0000 { 971 compatible = "qcom,rpm-msg-ram", "mmio-sram"; 972 reg = <0x0 0x045f0000 0x0 0x7000>; 973 #address-cells = <1>; 974 #size-cells = <1>; 975 ranges = <0 0x0 0x045f0000 0x7000>; 976 977 apss_mpm: sram@1b8 { 978 reg = <0x1b8 0x48>; 979 }; 980 }; 981 982 sram@4690000 { 983 compatible = "qcom,rpm-stats"; 984 reg = <0x0 0x04690000 0x0 0x10000>; 985 }; 986 987 sdhc_1: mmc@4744000 { 988 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 989 reg = <0x0 0x04744000 0x0 0x1000>, 990 <0x0 0x04745000 0x0 0x1000>, 991 <0x0 0x04748000 0x0 0x8000>; 992 reg-names = "hc", 993 "cqhci", 994 "ice"; 995 996 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 997 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; 998 interrupt-names = "hc_irq", "pwr_irq"; 999 1000 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1001 <&gcc GCC_SDCC1_APPS_CLK>, 1002 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1003 <&gcc GCC_SDCC1_ICE_CORE_CLK>; 1004 clock-names = "iface", 1005 "core", 1006 "xo", 1007 "ice"; 1008 1009 resets = <&gcc GCC_SDCC1_BCR>; 1010 1011 power-domains = <&rpmpd QCM2290_VDDCX>; 1012 operating-points-v2 = <&sdhc1_opp_table>; 1013 iommus = <&apps_smmu 0xc0 0x0>; 1014 interconnects = <&system_noc MASTER_SDCC_1 RPM_ALWAYS_TAG 1015 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1016 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1017 &config_noc SLAVE_SDCC_1 RPM_ALWAYS_TAG>; 1018 interconnect-names = "sdhc-ddr", 1019 "cpu-sdhc"; 1020 1021 qcom,dll-config = <0x000f642c>; 1022 qcom,ddr-config = <0x80040868>; 1023 bus-width = <8>; 1024 1025 mmc-ddr-1_8v; 1026 mmc-hs200-1_8v; 1027 mmc-hs400-1_8v; 1028 mmc-hs400-enhanced-strobe; 1029 1030 status = "disabled"; 1031 1032 sdhc1_opp_table: opp-table { 1033 compatible = "operating-points-v2"; 1034 1035 opp-100000000 { 1036 opp-hz = /bits/ 64 <100000000>; 1037 required-opps = <&rpmpd_opp_low_svs>; 1038 opp-peak-kBps = <250000 133320>; 1039 opp-avg-kBps = <102400 65000>; 1040 }; 1041 1042 opp-192000000 { 1043 opp-hz = /bits/ 64 <192000000>; 1044 required-opps = <&rpmpd_opp_low_svs>; 1045 opp-peak-kBps = <800000 300000>; 1046 opp-avg-kBps = <204800 200000>; 1047 }; 1048 1049 opp-384000000 { 1050 opp-hz = /bits/ 64 <384000000>; 1051 required-opps = <&rpmpd_opp_svs_plus>; 1052 opp-peak-kBps = <800000 300000>; 1053 opp-avg-kBps = <204800 200000>; 1054 }; 1055 }; 1056 }; 1057 1058 sdhc_2: mmc@4784000 { 1059 compatible = "qcom,qcm2290-sdhci", "qcom,sdhci-msm-v5"; 1060 reg = <0x0 0x04784000 0x0 0x1000>; 1061 reg-names = "hc"; 1062 1063 interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1065 interrupt-names = "hc_irq", "pwr_irq"; 1066 1067 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 1068 <&gcc GCC_SDCC2_APPS_CLK>, 1069 <&rpmcc RPM_SMD_XO_CLK_SRC>; 1070 clock-names = "iface", 1071 "core", 1072 "xo"; 1073 1074 resets = <&gcc GCC_SDCC2_BCR>; 1075 1076 power-domains = <&rpmpd QCM2290_VDDCX>; 1077 operating-points-v2 = <&sdhc2_opp_table>; 1078 iommus = <&apps_smmu 0xa0 0x0>; 1079 interconnects = <&system_noc MASTER_SDCC_2 RPM_ALWAYS_TAG 1080 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1081 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1082 &config_noc SLAVE_SDCC_2 RPM_ALWAYS_TAG>; 1083 interconnect-names = "sdhc-ddr", 1084 "cpu-sdhc"; 1085 1086 qcom,dll-config = <0x0007642c>; 1087 qcom,ddr-config = <0x80040868>; 1088 bus-width = <4>; 1089 1090 status = "disabled"; 1091 1092 sdhc2_opp_table: opp-table { 1093 compatible = "operating-points-v2"; 1094 1095 opp-100000000 { 1096 opp-hz = /bits/ 64 <100000000>; 1097 required-opps = <&rpmpd_opp_low_svs>; 1098 opp-peak-kBps = <250000 133320>; 1099 opp-avg-kBps = <261438 150000>; 1100 }; 1101 1102 opp-202000000 { 1103 opp-hz = /bits/ 64 <202000000>; 1104 required-opps = <&rpmpd_opp_svs_plus>; 1105 opp-peak-kBps = <800000 300000>; 1106 opp-avg-kBps = <261438 300000>; 1107 }; 1108 }; 1109 }; 1110 1111 gpi_dma0: dma-controller@4a00000 { 1112 compatible = "qcom,qcm2290-gpi-dma", "qcom,sm6350-gpi-dma"; 1113 reg = <0x0 0x04a00000 0x0 0x60000>; 1114 interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1124 dma-channels = <10>; 1125 dma-channel-mask = <0x1f>; 1126 iommus = <&apps_smmu 0xf6 0x0>; 1127 #dma-cells = <3>; 1128 status = "disabled"; 1129 }; 1130 1131 qupv3_id_0: geniqup@4ac0000 { 1132 compatible = "qcom,geni-se-qup"; 1133 reg = <0x0 0x04ac0000 0x0 0x2000>; 1134 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1135 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1136 clock-names = "m-ahb", "s-ahb"; 1137 iommus = <&apps_smmu 0xe3 0x0>; 1138 #address-cells = <2>; 1139 #size-cells = <2>; 1140 ranges; 1141 status = "disabled"; 1142 1143 i2c0: i2c@4a80000 { 1144 compatible = "qcom,geni-i2c"; 1145 reg = <0x0 0x04a80000 0x0 0x4000>; 1146 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1147 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1148 clock-names = "se"; 1149 pinctrl-0 = <&qup_i2c0_default>; 1150 pinctrl-names = "default"; 1151 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1152 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1153 dma-names = "tx", "rx"; 1154 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1155 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1156 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1157 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1158 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1159 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1160 interconnect-names = "qup-core", 1161 "qup-config", 1162 "qup-memory"; 1163 #address-cells = <1>; 1164 #size-cells = <0>; 1165 status = "disabled"; 1166 }; 1167 1168 spi0: spi@4a80000 { 1169 compatible = "qcom,geni-spi"; 1170 reg = <0x0 0x04a80000 0x0 0x4000>; 1171 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1172 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1173 clock-names = "se"; 1174 pinctrl-0 = <&qup_spi0_default>; 1175 pinctrl-names = "default"; 1176 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1177 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1178 dma-names = "tx", "rx"; 1179 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1180 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1181 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1182 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1183 interconnect-names = "qup-core", 1184 "qup-config"; 1185 #address-cells = <1>; 1186 #size-cells = <0>; 1187 status = "disabled"; 1188 }; 1189 1190 uart0: serial@4a80000 { 1191 compatible = "qcom,geni-uart"; 1192 reg = <0x0 0x04a80000 0x0 0x4000>; 1193 interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>; 1194 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1195 clock-names = "se"; 1196 pinctrl-0 = <&qup_uart0_default>; 1197 pinctrl-names = "default"; 1198 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1199 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1200 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1201 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1202 interconnect-names = "qup-core", 1203 "qup-config"; 1204 status = "disabled"; 1205 }; 1206 1207 i2c1: i2c@4a84000 { 1208 compatible = "qcom,geni-i2c"; 1209 reg = <0x0 0x04a84000 0x0 0x4000>; 1210 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1211 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1212 clock-names = "se"; 1213 pinctrl-0 = <&qup_i2c1_default>; 1214 pinctrl-names = "default"; 1215 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1216 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1217 dma-names = "tx", "rx"; 1218 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1219 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1220 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1221 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1222 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1223 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1224 interconnect-names = "qup-core", 1225 "qup-config", 1226 "qup-memory"; 1227 #address-cells = <1>; 1228 #size-cells = <0>; 1229 status = "disabled"; 1230 }; 1231 1232 spi1: spi@4a84000 { 1233 compatible = "qcom,geni-spi"; 1234 reg = <0x0 0x04a84000 0x0 0x4000>; 1235 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1237 clock-names = "se"; 1238 pinctrl-0 = <&qup_spi1_default>; 1239 pinctrl-names = "default"; 1240 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1241 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1242 dma-names = "tx", "rx"; 1243 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1244 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1245 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1246 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1247 interconnect-names = "qup-core", 1248 "qup-config"; 1249 #address-cells = <1>; 1250 #size-cells = <0>; 1251 status = "disabled"; 1252 }; 1253 1254 uart1: serial@4a84000 { 1255 compatible = "qcom,geni-uart"; 1256 reg = <0x0 0x04a84000 0x0 0x4000>; 1257 interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1259 clock-names = "se"; 1260 pinctrl-0 = <&qup_uart1_default>; 1261 pinctrl-names = "default"; 1262 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1263 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1264 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1265 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1266 interconnect-names = "qup-core", 1267 "qup-config"; 1268 status = "disabled"; 1269 }; 1270 1271 i2c2: i2c@4a88000 { 1272 compatible = "qcom,geni-i2c"; 1273 reg = <0x0 0x04a88000 0x0 0x4000>; 1274 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1276 clock-names = "se"; 1277 pinctrl-0 = <&qup_i2c2_default>; 1278 pinctrl-names = "default"; 1279 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1280 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1281 dma-names = "tx", "rx"; 1282 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1283 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1284 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1285 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1286 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1287 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1288 interconnect-names = "qup-core", 1289 "qup-config", 1290 "qup-memory"; 1291 #address-cells = <1>; 1292 #size-cells = <0>; 1293 status = "disabled"; 1294 }; 1295 1296 spi2: spi@4a88000 { 1297 compatible = "qcom,geni-spi"; 1298 reg = <0x0 0x04a88000 0x0 0x4000>; 1299 interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>; 1300 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1301 clock-names = "se"; 1302 pinctrl-0 = <&qup_spi2_default>; 1303 pinctrl-names = "default"; 1304 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1305 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1306 dma-names = "tx", "rx"; 1307 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1308 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1309 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1310 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1311 interconnect-names = "qup-core", 1312 "qup-config"; 1313 #address-cells = <1>; 1314 #size-cells = <0>; 1315 status = "disabled"; 1316 }; 1317 1318 i2c3: i2c@4a8c000 { 1319 compatible = "qcom,geni-i2c"; 1320 reg = <0x0 0x04a8c000 0x0 0x4000>; 1321 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1322 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1323 clock-names = "se"; 1324 pinctrl-0 = <&qup_i2c3_default>; 1325 pinctrl-names = "default"; 1326 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1327 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1328 dma-names = "tx", "rx"; 1329 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1330 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1331 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1332 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1333 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1334 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1335 interconnect-names = "qup-core", 1336 "qup-config", 1337 "qup-memory"; 1338 #address-cells = <1>; 1339 #size-cells = <0>; 1340 status = "disabled"; 1341 }; 1342 1343 spi3: spi@4a8c000 { 1344 compatible = "qcom,geni-spi"; 1345 reg = <0x0 0x04a8c000 0x0 0x4000>; 1346 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1347 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1348 clock-names = "se"; 1349 pinctrl-0 = <&qup_spi3_default>; 1350 pinctrl-names = "default"; 1351 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1352 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1353 dma-names = "tx", "rx"; 1354 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1355 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1356 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1357 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1358 interconnect-names = "qup-core", 1359 "qup-config"; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 uart3: serial@4a8c000 { 1366 compatible = "qcom,geni-uart"; 1367 reg = <0x0 0x04a8c000 0x0 0x4000>; 1368 interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 1369 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1370 clock-names = "se"; 1371 pinctrl-0 = <&qup_uart3_default>; 1372 pinctrl-names = "default"; 1373 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1374 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1375 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1376 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1377 interconnect-names = "qup-core", 1378 "qup-config"; 1379 status = "disabled"; 1380 }; 1381 1382 i2c4: i2c@4a90000 { 1383 compatible = "qcom,geni-i2c"; 1384 reg = <0x0 0x04a90000 0x0 0x4000>; 1385 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1386 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1387 clock-names = "se"; 1388 pinctrl-0 = <&qup_i2c4_default>; 1389 pinctrl-names = "default"; 1390 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1391 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1392 dma-names = "tx", "rx"; 1393 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1394 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1395 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1396 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1397 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1398 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1399 interconnect-names = "qup-core", 1400 "qup-config", 1401 "qup-memory"; 1402 #address-cells = <1>; 1403 #size-cells = <0>; 1404 status = "disabled"; 1405 }; 1406 1407 spi4: spi@4a90000 { 1408 compatible = "qcom,geni-spi"; 1409 reg = <0x0 0x04a90000 0x0 0x4000>; 1410 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1411 clock-names = "se"; 1412 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1413 pinctrl-names = "default"; 1414 pinctrl-0 = <&qup_spi4_default>; 1415 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1416 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1417 dma-names = "tx", "rx"; 1418 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1419 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1420 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1421 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1422 interconnect-names = "qup-core", 1423 "qup-config"; 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 status = "disabled"; 1427 }; 1428 1429 uart4: serial@4a90000 { 1430 compatible = "qcom,geni-uart"; 1431 reg = <0x0 0x04a90000 0x0 0x4000>; 1432 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>; 1433 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1434 clock-names = "se"; 1435 pinctrl-0 = <&qup_uart4_default>; 1436 pinctrl-names = "default"; 1437 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1438 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1439 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1440 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1441 interconnect-names = "qup-core", 1442 "qup-config"; 1443 status = "disabled"; 1444 }; 1445 1446 i2c5: i2c@4a94000 { 1447 compatible = "qcom,geni-i2c"; 1448 reg = <0x0 0x04a94000 0x0 0x4000>; 1449 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1450 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1451 clock-names = "se"; 1452 pinctrl-0 = <&qup_i2c5_default>; 1453 pinctrl-names = "default"; 1454 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1455 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1456 dma-names = "tx", "rx"; 1457 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1458 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1459 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1460 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>, 1461 <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG 1462 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1463 interconnect-names = "qup-core", 1464 "qup-config", 1465 "qup-memory"; 1466 #address-cells = <1>; 1467 #size-cells = <0>; 1468 status = "disabled"; 1469 }; 1470 1471 spi5: spi@4a94000 { 1472 compatible = "qcom,geni-spi"; 1473 reg = <0x0 0x04a94000 0x0 0x4000>; 1474 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1475 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1476 clock-names = "se"; 1477 pinctrl-0 = <&qup_spi5_default>; 1478 pinctrl-names = "default"; 1479 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1480 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1481 dma-names = "tx", "rx"; 1482 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1483 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1484 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1485 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1486 interconnect-names = "qup-core", 1487 "qup-config"; 1488 #address-cells = <1>; 1489 #size-cells = <0>; 1490 status = "disabled"; 1491 }; 1492 1493 uart5: serial@4a94000 { 1494 compatible = "qcom,geni-uart"; 1495 reg = <0x0 0x04a94000 0x0 0x4000>; 1496 interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; 1497 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1498 clock-names = "se"; 1499 pinctrl-0 = <&qup_uart5_default>; 1500 pinctrl-names = "default"; 1501 interconnects = <&qup_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG 1502 &qup_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>, 1503 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1504 &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>; 1505 interconnect-names = "qup-core", 1506 "qup-config"; 1507 status = "disabled"; 1508 }; 1509 }; 1510 1511 usb: usb@4ef8800 { 1512 compatible = "qcom,qcm2290-dwc3", "qcom,dwc3"; 1513 reg = <0x0 0x04ef8800 0x0 0x400>; 1514 interrupts-extended = <&intc GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 1515 <&mpm 12 IRQ_TYPE_LEVEL_HIGH>; 1516 interrupt-names = "hs_phy_irq", 1517 "ss_phy_irq"; 1518 1519 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 1520 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 1521 <&gcc GCC_SYS_NOC_USB3_PRIM_AXI_CLK>, 1522 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 1523 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1524 <&gcc GCC_USB3_PRIM_CLKREF_CLK>; 1525 clock-names = "cfg_noc", 1526 "core", 1527 "iface", 1528 "sleep", 1529 "mock_utmi", 1530 "xo"; 1531 1532 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 1533 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 1534 assigned-clock-rates = <19200000>, <133333333>; 1535 1536 resets = <&gcc GCC_USB30_PRIM_BCR>; 1537 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 1538 /* TODO: USB<->IPA path */ 1539 interconnects = <&system_noc MASTER_USB3_0 RPM_ALWAYS_TAG 1540 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1541 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1542 &config_noc SLAVE_USB3 RPM_ALWAYS_TAG>; 1543 interconnect-names = "usb-ddr", 1544 "apps-usb"; 1545 wakeup-source; 1546 1547 #address-cells = <2>; 1548 #size-cells = <2>; 1549 ranges; 1550 1551 status = "disabled"; 1552 1553 usb_dwc3: usb@4e00000 { 1554 compatible = "snps,dwc3"; 1555 reg = <0x0 0x04e00000 0x0 0xcd00>; 1556 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1557 phys = <&usb_hsphy>, <&usb_qmpphy>; 1558 phy-names = "usb2-phy", "usb3-phy"; 1559 iommus = <&apps_smmu 0x120 0x0>; 1560 snps,dis_u2_susphy_quirk; 1561 snps,dis_enblslpm_quirk; 1562 snps,has-lpm-erratum; 1563 snps,hird-threshold = /bits/ 8 <0x10>; 1564 snps,usb3_lpm_capable; 1565 snps,parkmode-disable-ss-quirk; 1566 maximum-speed = "super-speed"; 1567 dr_mode = "otg"; 1568 usb-role-switch; 1569 1570 ports { 1571 #address-cells = <1>; 1572 #size-cells = <0>; 1573 1574 port@0 { 1575 reg = <0>; 1576 1577 usb_dwc3_hs: endpoint { 1578 }; 1579 }; 1580 1581 port@1 { 1582 reg = <1>; 1583 1584 usb_dwc3_ss: endpoint { 1585 remote-endpoint = <&usb_qmpphy_usb_ss_in>; 1586 }; 1587 }; 1588 }; 1589 }; 1590 }; 1591 1592 gpu: gpu@5900000 { 1593 compatible = "qcom,adreno-07000200", "qcom,adreno"; 1594 reg = <0x0 0x05900000 0x0 0x40000>, 1595 <0x0 0x0599e000 0x0 0x1000>, 1596 <0x0 0x05961000 0x0 0x800>; 1597 reg-names = "kgsl_3d0_reg_memory", 1598 "cx_mem", 1599 "cx_dbgc"; 1600 1601 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1602 1603 clocks = <&gpucc GPU_CC_GX_GFX3D_CLK>, 1604 <&gpucc GPU_CC_AHB_CLK>, 1605 <&gcc GCC_BIMC_GPU_AXI_CLK>, 1606 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1607 <&gpucc GPU_CC_CX_GMU_CLK>, 1608 <&gpucc GPU_CC_CXO_CLK>; 1609 clock-names = "core", 1610 "iface", 1611 "mem_iface", 1612 "alt_mem_iface", 1613 "gmu", 1614 "xo"; 1615 1616 interconnects = <&bimc MASTER_GFX3D RPM_ALWAYS_TAG 1617 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1618 interconnect-names = "gfx-mem"; 1619 1620 iommus = <&adreno_smmu 0 1>, 1621 <&adreno_smmu 2 0>; 1622 operating-points-v2 = <&gpu_opp_table>; 1623 power-domains = <&rpmpd QCM2290_VDDCX>; 1624 qcom,gmu = <&gmu_wrapper>; 1625 1626 nvmem-cells = <&gpu_speed_bin>; 1627 nvmem-cell-names = "speed_bin"; 1628 #cooling-cells = <2>; 1629 1630 status = "disabled"; 1631 1632 gpu_zap_shader: zap-shader { 1633 memory-region = <&pil_gpu_mem>; 1634 }; 1635 1636 gpu_opp_table: opp-table { 1637 compatible = "operating-points-v2"; 1638 1639 /* TODO: Scale RPM_SMD_BIMC_GPU_CLK w/ turbo freqs */ 1640 opp-1123200000 { 1641 opp-hz = /bits/ 64 <1123200000>; 1642 required-opps = <&rpmpd_opp_turbo_plus>; 1643 opp-peak-kBps = <6881000>; 1644 opp-supported-hw = <0x3>; 1645 turbo-mode; 1646 }; 1647 1648 opp-1017600000 { 1649 opp-hz = /bits/ 64 <1017600000>; 1650 required-opps = <&rpmpd_opp_turbo>; 1651 opp-peak-kBps = <6881000>; 1652 opp-supported-hw = <0x3>; 1653 turbo-mode; 1654 }; 1655 1656 opp-921600000 { 1657 opp-hz = /bits/ 64 <921600000>; 1658 required-opps = <&rpmpd_opp_nom_plus>; 1659 opp-peak-kBps = <6881000>; 1660 opp-supported-hw = <0x3>; 1661 }; 1662 1663 opp-844800000 { 1664 opp-hz = /bits/ 64 <844800000>; 1665 required-opps = <&rpmpd_opp_nom>; 1666 opp-peak-kBps = <6881000>; 1667 opp-supported-hw = <0x7>; 1668 }; 1669 1670 opp-672000000 { 1671 opp-hz = /bits/ 64 <672000000>; 1672 required-opps = <&rpmpd_opp_svs_plus>; 1673 opp-peak-kBps = <3879000>; 1674 opp-supported-hw = <0xf>; 1675 }; 1676 1677 opp-537600000 { 1678 opp-hz = /bits/ 64 <537600000>; 1679 required-opps = <&rpmpd_opp_svs>; 1680 opp-peak-kBps = <2929000>; 1681 opp-supported-hw = <0xf>; 1682 }; 1683 1684 opp-355200000 { 1685 opp-hz = /bits/ 64 <355200000>; 1686 required-opps = <&rpmpd_opp_low_svs>; 1687 opp-peak-kBps = <1720000>; 1688 opp-supported-hw = <0xf>; 1689 }; 1690 }; 1691 }; 1692 1693 gmu_wrapper: gmu@596a000 { 1694 compatible = "qcom,adreno-gmu-wrapper"; 1695 reg = <0x0 0x0596a000 0x0 0x30000>; 1696 reg-names = "gmu"; 1697 power-domains = <&gpucc GPU_CX_GDSC>, 1698 <&gpucc GPU_GX_GDSC>; 1699 power-domain-names = "cx", 1700 "gx"; 1701 }; 1702 1703 gpucc: clock-controller@5990000 { 1704 compatible = "qcom,qcm2290-gpucc"; 1705 reg = <0x0 0x05990000 0x0 0x9000>; 1706 clocks = <&gcc GCC_GPU_CFG_AHB_CLK>, 1707 <&rpmcc RPM_SMD_XO_CLK_SRC>, 1708 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 1709 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 1710 power-domains = <&rpmpd QCM2290_VDDCX>; 1711 required-opps = <&rpmpd_opp_low_svs>; 1712 #clock-cells = <1>; 1713 #reset-cells = <1>; 1714 #power-domain-cells = <1>; 1715 }; 1716 1717 adreno_smmu: iommu@59a0000 { 1718 compatible = "qcom,qcm2290-smmu-500", "qcom,adreno-smmu", 1719 "qcom,smmu-500", "arm,mmu-500"; 1720 reg = <0x0 0x059a0000 0x0 0x10000>; 1721 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 1722 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, 1723 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1724 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, 1726 <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, 1727 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, 1728 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, 1729 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1730 1731 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 1732 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 1733 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>; 1734 clock-names = "mem", 1735 "hlos", 1736 "iface"; 1737 1738 power-domains = <&gpucc GPU_CX_GDSC>; 1739 1740 #global-interrupts = <1>; 1741 #iommu-cells = <2>; 1742 }; 1743 1744 cci: cci@5c1b000 { 1745 compatible = "qcom,qcm2290-cci", "qcom,msm8996-cci"; 1746 reg = <0x0 0x5c1b000 0x0 0x1000>; 1747 1748 interrupts = <GIC_SPI 206 IRQ_TYPE_EDGE_RISING>; 1749 1750 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_CCI_0_CLK>; 1751 clock-names = "ahb", "cci"; 1752 assigned-clocks = <&gcc GCC_CAMSS_CCI_0_CLK>; 1753 assigned-clock-rates = <37500000>; 1754 1755 power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; 1756 1757 pinctrl-0 = <&cci0_default &cci1_default>; 1758 pinctrl-names = "default"; 1759 1760 #address-cells = <1>; 1761 #size-cells = <0>; 1762 1763 status = "disabled"; 1764 1765 cci_i2c0: i2c-bus@0 { 1766 reg = <0>; 1767 clock-frequency = <400000>; 1768 #address-cells = <1>; 1769 #size-cells = <0>; 1770 }; 1771 1772 cci_i2c1: i2c-bus@1 { 1773 reg = <1>; 1774 clock-frequency = <400000>; 1775 #address-cells = <1>; 1776 #size-cells = <0>; 1777 }; 1778 }; 1779 1780 camss: camss@5c11000 { 1781 compatible = "qcom,qcm2290-camss"; 1782 1783 reg = <0x0 0x5c11000 0x0 0x1000>, 1784 <0x0 0x5c6e000 0x0 0x1000>, 1785 <0x0 0x5c75000 0x0 0x1000>, 1786 <0x0 0x5c52000 0x0 0x1000>, 1787 <0x0 0x5c53000 0x0 0x1000>, 1788 <0x0 0x5c66000 0x0 0x400>, 1789 <0x0 0x5c68000 0x0 0x400>, 1790 <0x0 0x5c6f000 0x0 0x4000>, 1791 <0x0 0x5c76000 0x0 0x4000>; 1792 reg-names = "top", 1793 "csid0", 1794 "csid1", 1795 "csiphy0", 1796 "csiphy1", 1797 "csitpg0", 1798 "csitpg1", 1799 "vfe0", 1800 "vfe1"; 1801 1802 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 1803 <&gcc GCC_CAMSS_AXI_CLK>, 1804 <&gcc GCC_CAMSS_NRT_AXI_CLK>, 1805 <&gcc GCC_CAMSS_RT_AXI_CLK>, 1806 <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, 1807 <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, 1808 <&gcc GCC_CAMSS_CPHY_0_CLK>, 1809 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, 1810 <&gcc GCC_CAMSS_CPHY_1_CLK>, 1811 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, 1812 <&gcc GCC_CAMSS_TOP_AHB_CLK>, 1813 <&gcc GCC_CAMSS_TFE_0_CLK>, 1814 <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, 1815 <&gcc GCC_CAMSS_TFE_1_CLK>, 1816 <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK> ; 1817 clock-names = "ahb", 1818 "axi", 1819 "camnoc_nrt_axi", 1820 "camnoc_rt_axi", 1821 "csi0", 1822 "csi1", 1823 "csiphy0", 1824 "csiphy0_timer", 1825 "csiphy1", 1826 "csiphy1_timer", 1827 "top_ahb", 1828 "vfe0", 1829 "vfe0_cphy_rx", 1830 "vfe1", 1831 "vfe1_cphy_rx"; 1832 1833 interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, 1834 <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, 1835 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, 1836 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 1837 <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, 1838 <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, 1839 <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, 1840 <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; 1841 interrupt-names = "csid0", 1842 "csid1", 1843 "csiphy0", 1844 "csiphy1", 1845 "csitpg0", 1846 "csitpg1", 1847 "vfe0", 1848 "vfe1"; 1849 1850 interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 1851 &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, 1852 <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG 1853 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1854 <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG 1855 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; 1856 interconnect-names = "ahb", 1857 "hf_mnoc", 1858 "sf_mnoc"; 1859 1860 iommus = <&apps_smmu 0x400 0x0>, 1861 <&apps_smmu 0x800 0x0>, 1862 <&apps_smmu 0x820 0x0>, 1863 <&apps_smmu 0x840 0x0>; 1864 1865 power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; 1866 1867 status = "disabled"; 1868 1869 ports { 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 1873 port@0 { 1874 reg = <0>; 1875 }; 1876 1877 port@1 { 1878 reg = <1>; 1879 }; 1880 }; 1881 }; 1882 1883 mdss: display-subsystem@5e00000 { 1884 compatible = "qcom,qcm2290-mdss"; 1885 reg = <0x0 0x05e00000 0x0 0x1000>; 1886 reg-names = "mdss"; 1887 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; 1888 interrupt-controller; 1889 #interrupt-cells = <1>; 1890 1891 clocks = <&gcc GCC_DISP_AHB_CLK>, 1892 <&gcc GCC_DISP_HF_AXI_CLK>, 1893 <&dispcc DISP_CC_MDSS_MDP_CLK>; 1894 clock-names = "iface", 1895 "bus", 1896 "core"; 1897 1898 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 1899 1900 power-domains = <&dispcc MDSS_GDSC>; 1901 1902 iommus = <&apps_smmu 0x420 0x2>, 1903 <&apps_smmu 0x421 0x0>; 1904 interconnects = <&mmrt_virt MASTER_MDP0 RPM_ALWAYS_TAG 1905 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 1906 <&bimc MASTER_APPSS_PROC RPM_ALWAYS_TAG 1907 &config_noc SLAVE_DISPLAY_CFG RPM_ALWAYS_TAG>; 1908 interconnect-names = "mdp0-mem", 1909 "cpu-cfg"; 1910 1911 #address-cells = <2>; 1912 #size-cells = <2>; 1913 ranges; 1914 1915 status = "disabled"; 1916 1917 mdp: display-controller@5e01000 { 1918 compatible = "qcom,qcm2290-dpu"; 1919 reg = <0x0 0x05e01000 0x0 0x8f000>, 1920 <0x0 0x05eb0000 0x0 0x3000>; 1921 reg-names = "mdp", 1922 "vbif"; 1923 1924 interrupt-parent = <&mdss>; 1925 interrupts = <0>; 1926 1927 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 1928 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1929 <&dispcc DISP_CC_MDSS_MDP_CLK>, 1930 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 1931 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 1932 clock-names = "bus", 1933 "iface", 1934 "core", 1935 "lut", 1936 "vsync"; 1937 1938 operating-points-v2 = <&mdp_opp_table>; 1939 power-domains = <&rpmpd QCM2290_VDDCX>; 1940 1941 ports { 1942 #address-cells = <1>; 1943 #size-cells = <0>; 1944 1945 port@0 { 1946 reg = <0>; 1947 dpu_intf1_out: endpoint { 1948 remote-endpoint = <&mdss_dsi0_in>; 1949 }; 1950 }; 1951 }; 1952 1953 mdp_opp_table: opp-table { 1954 compatible = "operating-points-v2"; 1955 1956 opp-19200000 { 1957 opp-hz = /bits/ 64 <19200000>; 1958 required-opps = <&rpmpd_opp_min_svs>; 1959 }; 1960 1961 opp-192000000 { 1962 opp-hz = /bits/ 64 <192000000>; 1963 required-opps = <&rpmpd_opp_low_svs>; 1964 }; 1965 1966 opp-256000000 { 1967 opp-hz = /bits/ 64 <256000000>; 1968 required-opps = <&rpmpd_opp_svs>; 1969 }; 1970 1971 opp-307200000 { 1972 opp-hz = /bits/ 64 <307200000>; 1973 required-opps = <&rpmpd_opp_svs_plus>; 1974 }; 1975 1976 opp-384000000 { 1977 opp-hz = /bits/ 64 <384000000>; 1978 required-opps = <&rpmpd_opp_nom>; 1979 }; 1980 }; 1981 }; 1982 1983 mdss_dsi0: dsi@5e94000 { 1984 compatible = "qcom,qcm2290-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 1985 reg = <0x0 0x05e94000 0x0 0x400>; 1986 reg-names = "dsi_ctrl"; 1987 1988 interrupt-parent = <&mdss>; 1989 interrupts = <4>; 1990 1991 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 1992 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 1993 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 1994 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 1995 <&dispcc DISP_CC_MDSS_AHB_CLK>, 1996 <&gcc GCC_DISP_HF_AXI_CLK>; 1997 clock-names = "byte", 1998 "byte_intf", 1999 "pixel", 2000 "core", 2001 "iface", 2002 "bus"; 2003 2004 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 2005 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 2006 assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2007 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2008 2009 operating-points-v2 = <&dsi_opp_table>; 2010 power-domains = <&rpmpd QCM2290_VDDCX>; 2011 phys = <&mdss_dsi0_phy>; 2012 2013 #address-cells = <1>; 2014 #size-cells = <0>; 2015 2016 status = "disabled"; 2017 2018 dsi_opp_table: opp-table { 2019 compatible = "operating-points-v2"; 2020 2021 opp-19200000 { 2022 opp-hz = /bits/ 64 <19200000>; 2023 required-opps = <&rpmpd_opp_min_svs>; 2024 }; 2025 2026 opp-164000000 { 2027 opp-hz = /bits/ 64 <164000000>; 2028 required-opps = <&rpmpd_opp_low_svs>; 2029 }; 2030 2031 opp-187500000 { 2032 opp-hz = /bits/ 64 <187500000>; 2033 required-opps = <&rpmpd_opp_svs>; 2034 }; 2035 }; 2036 2037 ports { 2038 #address-cells = <1>; 2039 #size-cells = <0>; 2040 2041 port@0 { 2042 reg = <0>; 2043 2044 mdss_dsi0_in: endpoint { 2045 remote-endpoint = <&dpu_intf1_out>; 2046 }; 2047 }; 2048 2049 port@1 { 2050 reg = <1>; 2051 2052 mdss_dsi0_out: endpoint { 2053 }; 2054 }; 2055 }; 2056 }; 2057 2058 mdss_dsi0_phy: phy@5e94400 { 2059 compatible = "qcom,dsi-phy-14nm-2290"; 2060 reg = <0x0 0x05e94400 0x0 0x100>, 2061 <0x0 0x05e94500 0x0 0x300>, 2062 <0x0 0x05e94800 0x0 0x188>; 2063 reg-names = "dsi_phy", 2064 "dsi_phy_lane", 2065 "dsi_pll"; 2066 2067 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 2068 <&rpmcc RPM_SMD_XO_CLK_SRC>; 2069 clock-names = "iface", 2070 "ref"; 2071 2072 power-domains = <&rpmpd QCM2290_VDDMX>; 2073 required-opps = <&rpmpd_opp_nom>; 2074 2075 #clock-cells = <1>; 2076 #phy-cells = <0>; 2077 2078 status = "disabled"; 2079 }; 2080 }; 2081 2082 dispcc: clock-controller@5f00000 { 2083 compatible = "qcom,qcm2290-dispcc"; 2084 reg = <0x0 0x05f00000 0x0 0x20000>; 2085 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, 2086 <&rpmcc RPM_SMD_XO_A_CLK_SRC>, 2087 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 2088 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, 2089 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 2090 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; 2091 clock-names = "bi_tcxo", 2092 "bi_tcxo_ao", 2093 "gcc_disp_gpll0_clk_src", 2094 "gcc_disp_gpll0_div_clk_src", 2095 "dsi0_phy_pll_out_byteclk", 2096 "dsi0_phy_pll_out_dsiclk"; 2097 #power-domain-cells = <1>; 2098 #clock-cells = <1>; 2099 #reset-cells = <1>; 2100 }; 2101 2102 remoteproc_mpss: remoteproc@6080000 { 2103 compatible = "qcom,qcm2290-mpss-pas", "qcom,sm6115-mpss-pas"; 2104 reg = <0x0 0x06080000 0x0 0x100>; 2105 2106 interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING>, 2107 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2108 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2109 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2110 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 2111 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 2112 interrupt-names = "wdog", 2113 "fatal", 2114 "ready", 2115 "handover", 2116 "stop-ack", 2117 "shutdown-ack"; 2118 2119 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2120 clock-names = "xo"; 2121 2122 power-domains = <&rpmpd QCM2290_VDDCX>; 2123 2124 memory-region = <&pil_modem_mem>; 2125 2126 qcom,smem-states = <&modem_smp2p_out 0>; 2127 qcom,smem-state-names = "stop"; 2128 2129 status = "disabled"; 2130 2131 glink-edge { 2132 interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>; 2133 label = "mpss"; 2134 qcom,remote-pid = <1>; 2135 mboxes = <&apcs_glb 12>; 2136 }; 2137 }; 2138 2139 remoteproc_adsp: remoteproc@ab00000 { 2140 compatible = "qcom,qcm2290-adsp-pas", "qcom,sm6115-adsp-pas"; 2141 reg = <0x0 0x0ab00000 0x0 0x100>; 2142 2143 interrupts-extended = <&intc GIC_SPI 282 IRQ_TYPE_EDGE_RISING>, 2144 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2145 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 2146 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 2147 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>; 2148 interrupt-names = "wdog", 2149 "fatal", 2150 "ready", 2151 "handover", 2152 "stop-ack"; 2153 2154 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; 2155 clock-names = "xo"; 2156 2157 power-domains = <&rpmpd QCM2290_VDD_LPI_CX>, 2158 <&rpmpd QCM2290_VDD_LPI_MX>; 2159 2160 memory-region = <&pil_adsp_mem>; 2161 2162 qcom,smem-states = <&adsp_smp2p_out 0>; 2163 qcom,smem-state-names = "stop"; 2164 2165 status = "disabled"; 2166 2167 glink-edge { 2168 interrupts = <GIC_SPI 277 IRQ_TYPE_EDGE_RISING>; 2169 label = "lpass"; 2170 qcom,remote-pid = <2>; 2171 mboxes = <&apcs_glb 8>; 2172 2173 apr { 2174 compatible = "qcom,apr-v2"; 2175 qcom,glink-channels = "apr_audio_svc"; 2176 qcom,domain = <APR_DOMAIN_ADSP>; 2177 #address-cells = <1>; 2178 #size-cells = <0>; 2179 2180 service@3 { 2181 reg = <APR_SVC_ADSP_CORE>; 2182 compatible = "qcom,q6core"; 2183 qcom,protection-domain = "avs/audio", 2184 "msm/adsp/audio_pd"; 2185 }; 2186 2187 q6afe: service@4 { 2188 compatible = "qcom,q6afe"; 2189 reg = <APR_SVC_AFE>; 2190 qcom,protection-domain = "avs/audio", 2191 "msm/adsp/audio_pd"; 2192 q6afedai: dais { 2193 compatible = "qcom,q6afe-dais"; 2194 #address-cells = <1>; 2195 #size-cells = <0>; 2196 #sound-dai-cells = <1>; 2197 }; 2198 2199 q6afecc: clock-controller { 2200 compatible = "qcom,q6afe-clocks"; 2201 #clock-cells = <2>; 2202 }; 2203 }; 2204 2205 q6asm: service@7 { 2206 compatible = "qcom,q6asm"; 2207 reg = <APR_SVC_ASM>; 2208 qcom,protection-domain = "avs/audio", 2209 "msm/adsp/audio_pd"; 2210 q6asmdai: dais { 2211 compatible = "qcom,q6asm-dais"; 2212 #address-cells = <1>; 2213 #size-cells = <0>; 2214 #sound-dai-cells = <1>; 2215 iommus = <&apps_smmu 0x1c1 0x0>; 2216 2217 dai@0 { 2218 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 2219 }; 2220 2221 dai@1 { 2222 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 2223 }; 2224 2225 dai@2 { 2226 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 2227 }; 2228 }; 2229 }; 2230 2231 q6adm: service@8 { 2232 compatible = "qcom,q6adm"; 2233 reg = <APR_SVC_ADM>; 2234 qcom,protection-domain = "avs/audio", 2235 "msm/adsp/audio_pd"; 2236 q6routing: routing { 2237 compatible = "qcom,q6adm-routing"; 2238 #sound-dai-cells = <0>; 2239 }; 2240 }; 2241 }; 2242 }; 2243 }; 2244 2245 apps_smmu: iommu@c600000 { 2246 compatible = "qcom,qcm2290-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 2247 reg = <0x0 0x0c600000 0x0 0x80000>; 2248 #iommu-cells = <2>; 2249 #global-interrupts = <1>; 2250 2251 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>, 2252 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 2253 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 2254 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 2255 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>, 2256 <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, 2257 <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, 2258 <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>, 2259 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>, 2260 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, 2261 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 2262 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 2263 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 2264 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 2265 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 2266 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 2267 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 2268 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 2269 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 2270 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 2271 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 2272 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 2273 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 2274 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 2275 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 2276 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 2277 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 2278 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 2279 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 2280 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 2281 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 2282 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 2283 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 2284 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 2285 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 2286 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 2287 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 2288 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 2289 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2290 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2291 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2292 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, 2293 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 2294 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 2295 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 2296 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 2297 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 2298 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 2299 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 2300 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 2301 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 2302 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 2303 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 2304 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 2305 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 2306 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2307 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2308 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2309 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2310 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2311 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2312 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2313 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2314 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2315 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 2316 }; 2317 2318 venus: video-codec@5a00000 { 2319 compatible = "qcom,qcm2290-venus"; 2320 reg = <0 0x5a00000 0 0xf0000>; 2321 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 2322 2323 power-domains = <&gcc GCC_VENUS_GDSC>, 2324 <&gcc GCC_VCODEC0_GDSC>, 2325 <&rpmpd QCM2290_VDDCX>; 2326 power-domain-names = "venus", 2327 "vcodec0", 2328 "cx"; 2329 operating-points-v2 = <&venus_opp_table>; 2330 2331 clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, 2332 <&gcc GCC_VIDEO_AHB_CLK>, 2333 <&gcc GCC_VENUS_CTL_AXI_CLK>, 2334 <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, 2335 <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, 2336 <&gcc GCC_VCODEC0_AXI_CLK>; 2337 clock-names = "core", 2338 "iface", 2339 "bus", 2340 "throttle", 2341 "vcodec0_core", 2342 "vcodec0_bus"; 2343 2344 memory-region = <&pil_video_mem>; 2345 iommus = <&apps_smmu 0x860 0x0>, 2346 <&apps_smmu 0x880 0x0>, 2347 <&apps_smmu 0x861 0x04>, 2348 <&apps_smmu 0x863 0x0>, 2349 <&apps_smmu 0x804 0xe0>; 2350 2351 interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG 2352 &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, 2353 <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG 2354 &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; 2355 interconnect-names = "video-mem", 2356 "cpu-cfg"; 2357 2358 venus_opp_table: opp-table { 2359 compatible = "operating-points-v2"; 2360 2361 opp-133333333 { 2362 opp-hz = /bits/ 64 <133333333>; 2363 required-opps = <&rpmpd_opp_low_svs>; 2364 }; 2365 2366 opp-240000000 { 2367 opp-hz = /bits/ 64 <240000000>; 2368 required-opps = <&rpmpd_opp_svs>; 2369 }; 2370 }; 2371 }; 2372 2373 wifi: wifi@c800000 { 2374 compatible = "qcom,wcn3990-wifi"; 2375 reg = <0x0 0x0c800000 0x0 0x800000>; 2376 reg-names = "membase"; 2377 memory-region = <&wlan_msa_mem>; 2378 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 2379 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 2380 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 2381 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 2382 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 2383 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 2384 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 2385 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 2386 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 2387 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 2388 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 2389 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2390 iommus = <&apps_smmu 0x1a0 0x1>; 2391 qcom,msa-fixed-perm; 2392 status = "disabled"; 2393 }; 2394 2395 watchdog@f017000 { 2396 compatible = "qcom,apss-wdt-qcm2290", "qcom,kpss-wdt"; 2397 reg = <0x0 0x0f017000 0x0 0x1000>; 2398 interrupts = <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 2399 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 2400 clocks = <&sleep_clk>; 2401 }; 2402 2403 apcs_glb: mailbox@f111000 { 2404 compatible = "qcom,qcm2290-apcs-hmss-global"; 2405 reg = <0x0 0x0f111000 0x0 0x1000>; 2406 #mbox-cells = <1>; 2407 }; 2408 2409 timer@f120000 { 2410 compatible = "arm,armv7-timer-mem"; 2411 reg = <0x0 0x0f120000 0x0 0x1000>; 2412 #address-cells = <1>; 2413 #size-cells = <1>; 2414 ranges = <0 0x0 0x0f121000 0x8000>; 2415 2416 frame@0 { 2417 reg = <0x0 0x1000>, 2418 <0x1000 0x1000>; 2419 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 2420 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2421 frame-number = <0>; 2422 }; 2423 2424 frame@2000 { 2425 reg = <0x2000 0x1000>; 2426 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 2427 frame-number = <1>; 2428 status = "disabled"; 2429 }; 2430 2431 frame@3000 { 2432 reg = <0x3000 0x1000>; 2433 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 2434 frame-number = <2>; 2435 status = "disabled"; 2436 }; 2437 2438 frame@4000 { 2439 reg = <0x4000 0x1000>; 2440 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 2441 frame-number = <3>; 2442 status = "disabled"; 2443 }; 2444 2445 frame@5000 { 2446 reg = <0x5000 0x1000>; 2447 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 2448 frame-number = <4>; 2449 status = "disabled"; 2450 }; 2451 2452 frame@6000 { 2453 reg = <0x6000 0x1000>; 2454 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2455 frame-number = <5>; 2456 status = "disabled"; 2457 }; 2458 2459 frame@7000 { 2460 reg = <0x7000 0x1000>; 2461 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 2462 frame-number = <6>; 2463 status = "disabled"; 2464 }; 2465 }; 2466 2467 intc: interrupt-controller@f200000 { 2468 compatible = "arm,gic-v3"; 2469 reg = <0x0 0x0f200000 0x0 0x10000>, 2470 <0x0 0x0f300000 0x0 0x100000>; 2471 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2472 #interrupt-cells = <3>; 2473 interrupt-controller; 2474 interrupt-parent = <&intc>; 2475 #redistributor-regions = <1>; 2476 redistributor-stride = <0x0 0x20000>; 2477 }; 2478 2479 cpufreq_hw: cpufreq@f521000 { 2480 compatible = "qcom,qcm2290-cpufreq-hw", "qcom,cpufreq-hw"; 2481 reg = <0x0 0x0f521000 0x0 0x1000>; 2482 reg-names = "freq-domain0"; 2483 interrupts-extended = <&lmh_cluster 0>; 2484 interrupt-names = "dcvsh-irq-0"; 2485 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>; 2486 clock-names = "xo", "alternate"; 2487 2488 #freq-domain-cells = <1>; 2489 #clock-cells = <1>; 2490 }; 2491 2492 lmh_cluster: lmh@f550800 { 2493 compatible = "qcom,qcm2290-lmh", "qcom,sm8150-lmh"; 2494 reg = <0x0 0x0f550800 0x0 0x400>; 2495 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 2496 cpus = <&cpu0>; 2497 qcom,lmh-temp-arm-millicelsius = <65000>; 2498 qcom,lmh-temp-low-millicelsius = <94500>; 2499 qcom,lmh-temp-high-millicelsius = <95000>; 2500 interrupt-controller; 2501 #interrupt-cells = <1>; 2502 }; 2503 }; 2504 2505 thermal-zones { 2506 mapss-thermal { 2507 thermal-sensors = <&tsens0 0>; 2508 2509 trips { 2510 mapss_alert0: trip-point0 { 2511 temperature = <90000>; 2512 hysteresis = <2000>; 2513 type = "passive"; 2514 }; 2515 2516 mapss_alert1: trip-point1 { 2517 temperature = <95000>; 2518 hysteresis = <2000>; 2519 type = "passive"; 2520 }; 2521 2522 mapss_crit: mapss-crit { 2523 temperature = <110000>; 2524 hysteresis = <1000>; 2525 type = "critical"; 2526 }; 2527 }; 2528 }; 2529 2530 video-thermal { 2531 thermal-sensors = <&tsens0 1>; 2532 2533 trips { 2534 video_alert0: trip-point0 { 2535 temperature = <90000>; 2536 hysteresis = <2000>; 2537 type = "passive"; 2538 }; 2539 2540 video_alert1: trip-point1 { 2541 temperature = <95000>; 2542 hysteresis = <2000>; 2543 type = "passive"; 2544 }; 2545 2546 video_crit: video-crit { 2547 temperature = <110000>; 2548 hysteresis = <1000>; 2549 type = "critical"; 2550 }; 2551 }; 2552 }; 2553 2554 wlan-thermal { 2555 thermal-sensors = <&tsens0 2>; 2556 2557 trips { 2558 wlan_alert0: trip-point0 { 2559 temperature = <90000>; 2560 hysteresis = <2000>; 2561 type = "passive"; 2562 }; 2563 2564 wlan_alert1: trip-point1 { 2565 temperature = <95000>; 2566 hysteresis = <2000>; 2567 type = "passive"; 2568 }; 2569 2570 wlan_crit: wlan-crit { 2571 temperature = <110000>; 2572 hysteresis = <1000>; 2573 type = "critical"; 2574 }; 2575 }; 2576 }; 2577 2578 cpuss0-thermal { 2579 thermal-sensors = <&tsens0 3>; 2580 2581 trips { 2582 cpuss0_alert0: trip-point0 { 2583 temperature = <90000>; 2584 hysteresis = <2000>; 2585 type = "passive"; 2586 }; 2587 2588 cpuss0_alert1: trip-point1 { 2589 temperature = <95000>; 2590 hysteresis = <2000>; 2591 type = "passive"; 2592 }; 2593 2594 cpuss0_crit: cpuss0-crit { 2595 temperature = <110000>; 2596 hysteresis = <1000>; 2597 type = "critical"; 2598 }; 2599 }; 2600 }; 2601 2602 cpuss1-thermal { 2603 thermal-sensors = <&tsens0 4>; 2604 2605 trips { 2606 cpuss1_alert0: trip-point0 { 2607 temperature = <90000>; 2608 hysteresis = <2000>; 2609 type = "passive"; 2610 }; 2611 2612 cpuss1_alert1: trip-point1 { 2613 temperature = <95000>; 2614 hysteresis = <2000>; 2615 type = "passive"; 2616 }; 2617 2618 cpuss1_crit: cpuss1-crit { 2619 temperature = <110000>; 2620 hysteresis = <1000>; 2621 type = "critical"; 2622 }; 2623 }; 2624 }; 2625 2626 mdm0-thermal { 2627 thermal-sensors = <&tsens0 5>; 2628 2629 trips { 2630 mdm0_alert0: trip-point0 { 2631 temperature = <90000>; 2632 hysteresis = <2000>; 2633 type = "passive"; 2634 }; 2635 2636 mdm0_alert1: trip-point1 { 2637 temperature = <95000>; 2638 hysteresis = <2000>; 2639 type = "passive"; 2640 }; 2641 2642 mdm0_crit: mdm0-crit { 2643 temperature = <110000>; 2644 hysteresis = <1000>; 2645 type = "critical"; 2646 }; 2647 }; 2648 }; 2649 2650 mdm1-thermal { 2651 thermal-sensors = <&tsens0 6>; 2652 2653 trips { 2654 mdm1_alert0: trip-point0 { 2655 temperature = <90000>; 2656 hysteresis = <2000>; 2657 type = "passive"; 2658 }; 2659 2660 mdm1_alert1: trip-point1 { 2661 temperature = <95000>; 2662 hysteresis = <2000>; 2663 type = "passive"; 2664 }; 2665 2666 mdm1_crit: mdm1-crit { 2667 temperature = <110000>; 2668 hysteresis = <1000>; 2669 type = "critical"; 2670 }; 2671 }; 2672 }; 2673 2674 gpu-thermal { 2675 thermal-sensors = <&tsens0 7>; 2676 2677 trips { 2678 gpu_alert0: trip-point0 { 2679 temperature = <90000>; 2680 hysteresis = <2000>; 2681 type = "passive"; 2682 }; 2683 2684 gpu_alert1: trip-point1 { 2685 temperature = <95000>; 2686 hysteresis = <2000>; 2687 type = "passive"; 2688 }; 2689 2690 gpu_crit: gpu-crit { 2691 temperature = <110000>; 2692 hysteresis = <1000>; 2693 type = "critical"; 2694 }; 2695 }; 2696 }; 2697 2698 hm-center-thermal { 2699 thermal-sensors = <&tsens0 8>; 2700 2701 trips { 2702 hm_center_alert0: trip-point0 { 2703 temperature = <90000>; 2704 hysteresis = <2000>; 2705 type = "passive"; 2706 }; 2707 2708 hm_center_alert1: trip-point1 { 2709 temperature = <95000>; 2710 hysteresis = <2000>; 2711 type = "passive"; 2712 }; 2713 2714 hm_center_crit: hm-center-crit { 2715 temperature = <110000>; 2716 hysteresis = <1000>; 2717 type = "critical"; 2718 }; 2719 }; 2720 }; 2721 2722 camera-thermal { 2723 thermal-sensors = <&tsens0 9>; 2724 2725 trips { 2726 camera_alert0: trip-point0 { 2727 temperature = <90000>; 2728 hysteresis = <2000>; 2729 type = "passive"; 2730 }; 2731 2732 camera_alert1: trip-point1 { 2733 temperature = <95000>; 2734 hysteresis = <2000>; 2735 type = "passive"; 2736 }; 2737 2738 camera_crit: camera-crit { 2739 temperature = <110000>; 2740 hysteresis = <1000>; 2741 type = "critical"; 2742 }; 2743 }; 2744 }; 2745 }; 2746 2747 timer { 2748 compatible = "arm,armv8-timer"; 2749 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2750 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2751 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2752 <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2753 }; 2754};
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