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tegra210.dtsi
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linux-6.19.14/arch/arm64/boot/dts/nvidia/tegra210.dtsi
1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra210-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra210-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h> 7#include <dt-bindings/reset/tegra210-car.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/thermal/tegra124-soctherm.h> 10#include <dt-bindings/soc/tegra-pmc.h> 11 12#include "tegra210-peripherals-opp.dtsi" 13 14/ { 15 compatible = "nvidia,tegra210"; 16 interrupt-parent = <&lic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 pcie@1003000 { 21 compatible = "nvidia,tegra210-pcie"; 22 device_type = "pci"; 23 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 24 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 25 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 26 reg-names = "pads", "afi", "cs"; 27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 28 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 29 interrupt-names = "intr", "msi"; 30 31 #interrupt-cells = <1>; 32 interrupt-map-mask = <0 0 0 0>; 33 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 34 35 bus-range = <0x00 0xff>; 36 #address-cells = <3>; 37 #size-cells = <2>; 38 39 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 40 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 41 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 42 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 43 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 44 45 clocks = <&tegra_car TEGRA210_CLK_PCIE>, 46 <&tegra_car TEGRA210_CLK_AFI>, 47 <&tegra_car TEGRA210_CLK_PLL_E>, 48 <&tegra_car TEGRA210_CLK_CML0>; 49 clock-names = "pex", "afi", "pll_e", "cml"; 50 resets = <&tegra_car 70>, 51 <&tegra_car 72>, 52 <&tegra_car 74>; 53 reset-names = "pex", "afi", "pcie_x"; 54 55 pinctrl-names = "default", "idle"; 56 pinctrl-0 = <&pex_dpd_disable>; 57 pinctrl-1 = <&pex_dpd_enable>; 58 59 status = "disabled"; 60 61 pci@1,0 { 62 device_type = "pci"; 63 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 64 reg = <0x000800 0 0 0 0>; 65 bus-range = <0x00 0xff>; 66 status = "disabled"; 67 68 #address-cells = <3>; 69 #size-cells = <2>; 70 ranges; 71 72 nvidia,num-lanes = <4>; 73 }; 74 75 pci@2,0 { 76 device_type = "pci"; 77 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 78 reg = <0x001000 0 0 0 0>; 79 bus-range = <0x00 0xff>; 80 status = "disabled"; 81 82 #address-cells = <3>; 83 #size-cells = <2>; 84 ranges; 85 86 nvidia,num-lanes = <1>; 87 }; 88 }; 89 90 host1x@50000000 { 91 compatible = "nvidia,tegra210-host1x"; 92 reg = <0x0 0x50000000 0x0 0x00034000>; 93 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 94 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 95 interrupt-names = "syncpt", "host1x"; 96 clocks = <&tegra_car TEGRA210_CLK_HOST1X>; 97 clock-names = "host1x"; 98 resets = <&tegra_car 28>, <&mc TEGRA210_MC_RESET_HC>; 99 reset-names = "host1x", "mc"; 100 101 #address-cells = <2>; 102 #size-cells = <2>; 103 104 ranges = <0x0 0x54000000 0x0 0x54000000 0x0 0x01000000>; 105 106 iommus = <&mc TEGRA_SWGROUP_HC>; 107 108 dpaux1: dpaux@54040000 { 109 compatible = "nvidia,tegra210-dpaux"; 110 reg = <0x0 0x54040000 0x0 0x00040000>; 111 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 112 clocks = <&tegra_car TEGRA210_CLK_DPAUX1>, 113 <&tegra_car TEGRA210_CLK_PLL_DP>; 114 clock-names = "dpaux", "parent"; 115 resets = <&tegra_car 207>; 116 reset-names = "dpaux"; 117 power-domains = <&pd_sor>; 118 status = "disabled"; 119 120 state_dpaux1_aux: pinmux-aux { 121 groups = "dpaux-io"; 122 function = "aux"; 123 }; 124 125 state_dpaux1_i2c: pinmux-i2c { 126 groups = "dpaux-io"; 127 function = "i2c"; 128 }; 129 130 state_dpaux1_off: pinmux-off { 131 groups = "dpaux-io"; 132 function = "off"; 133 }; 134 135 i2c-bus { 136 #address-cells = <1>; 137 #size-cells = <0>; 138 }; 139 }; 140 141 vi@54080000 { 142 compatible = "nvidia,tegra210-vi"; 143 reg = <0x0 0x54080000 0x0 0x700>; 144 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 145 status = "disabled"; 146 assigned-clocks = <&tegra_car TEGRA210_CLK_VI>; 147 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 148 149 clocks = <&tegra_car TEGRA210_CLK_VI>; 150 power-domains = <&pd_venc>; 151 152 #address-cells = <1>; 153 #size-cells = <1>; 154 155 ranges = <0x0 0x0 0x54080000 0x2000>; 156 157 csi@838 { 158 compatible = "nvidia,tegra210-csi"; 159 reg = <0x838 0x1300>; 160 status = "disabled"; 161 assigned-clocks = <&tegra_car TEGRA210_CLK_CILAB>, 162 <&tegra_car TEGRA210_CLK_CILCD>, 163 <&tegra_car TEGRA210_CLK_CILE>, 164 <&tegra_car TEGRA210_CLK_CSI_TPG>; 165 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>, 166 <&tegra_car TEGRA210_CLK_PLL_P>, 167 <&tegra_car TEGRA210_CLK_PLL_P>; 168 assigned-clock-rates = <102000000>, 169 <102000000>, 170 <102000000>, 171 <972000000>; 172 173 clocks = <&tegra_car TEGRA210_CLK_CSI>, 174 <&tegra_car TEGRA210_CLK_CILAB>, 175 <&tegra_car TEGRA210_CLK_CILCD>, 176 <&tegra_car TEGRA210_CLK_CILE>, 177 <&tegra_car TEGRA210_CLK_CSI_TPG>; 178 clock-names = "csi", "cilab", "cilcd", "cile", "csi_tpg"; 179 power-domains = <&pd_sor>; 180 }; 181 }; 182 183 tsec@54100000 { 184 compatible = "nvidia,tegra210-tsec"; 185 reg = <0x0 0x54100000 0x0 0x00040000>; 186 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&tegra_car TEGRA210_CLK_TSEC>; 188 resets = <&tegra_car 83>; 189 status = "disabled"; 190 }; 191 192 dc@54200000 { 193 compatible = "nvidia,tegra210-dc"; 194 reg = <0x0 0x54200000 0x0 0x00040000>; 195 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 196 clocks = <&tegra_car TEGRA210_CLK_DISP1>; 197 clock-names = "dc"; 198 resets = <&tegra_car 27>; 199 reset-names = "dc"; 200 201 iommus = <&mc TEGRA_SWGROUP_DC>; 202 203 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 204 nvidia,head = <0>; 205 }; 206 207 dc@54240000 { 208 compatible = "nvidia,tegra210-dc"; 209 reg = <0x0 0x54240000 0x0 0x00040000>; 210 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&tegra_car TEGRA210_CLK_DISP2>; 212 clock-names = "dc"; 213 resets = <&tegra_car 26>; 214 reset-names = "dc"; 215 216 iommus = <&mc TEGRA_SWGROUP_DCB>; 217 218 nvidia,outputs = <&dsia &dsib &sor0 &sor1>; 219 nvidia,head = <1>; 220 }; 221 222 dsia: dsi@54300000 { 223 compatible = "nvidia,tegra210-dsi"; 224 reg = <0x0 0x54300000 0x0 0x00040000>; 225 clocks = <&tegra_car TEGRA210_CLK_DSIA>, 226 <&tegra_car TEGRA210_CLK_DSIALP>, 227 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 228 clock-names = "dsi", "lp", "parent"; 229 resets = <&tegra_car 48>; 230 reset-names = "dsi"; 231 power-domains = <&pd_sor>; 232 nvidia,mipi-calibrate = <&mipi 0x0c0>; /* DSIA & DSIB pads */ 233 234 status = "disabled"; 235 236 #address-cells = <1>; 237 #size-cells = <0>; 238 }; 239 240 vic@54340000 { 241 compatible = "nvidia,tegra210-vic"; 242 reg = <0x0 0x54340000 0x0 0x00040000>; 243 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 244 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 245 clock-names = "vic"; 246 resets = <&tegra_car 178>; 247 reset-names = "vic"; 248 249 iommus = <&mc TEGRA_SWGROUP_VIC>; 250 power-domains = <&pd_vic>; 251 }; 252 253 nvjpg@54380000 { 254 compatible = "nvidia,tegra210-nvjpg"; 255 reg = <0x0 0x54380000 0x0 0x00040000>; 256 clocks = <&tegra_car TEGRA210_CLK_NVJPG>; 257 clock-names = "nvjpg"; 258 resets = <&tegra_car 195>; 259 reset-names = "nvjpg"; 260 261 iommus = <&mc TEGRA_SWGROUP_NVJPG>; 262 power-domains = <&pd_nvjpg>; 263 }; 264 265 dsib: dsi@54400000 { 266 compatible = "nvidia,tegra210-dsi"; 267 reg = <0x0 0x54400000 0x0 0x00040000>; 268 clocks = <&tegra_car TEGRA210_CLK_DSIB>, 269 <&tegra_car TEGRA210_CLK_DSIBLP>, 270 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>; 271 clock-names = "dsi", "lp", "parent"; 272 resets = <&tegra_car 82>; 273 reset-names = "dsi"; 274 power-domains = <&pd_sor>; 275 nvidia,mipi-calibrate = <&mipi 0x300>; /* DSIC & DSID pads */ 276 277 status = "disabled"; 278 279 #address-cells = <1>; 280 #size-cells = <0>; 281 }; 282 283 nvdec@54480000 { 284 compatible = "nvidia,tegra210-nvdec"; 285 reg = <0x0 0x54480000 0x0 0x00040000>; 286 clocks = <&tegra_car TEGRA210_CLK_NVDEC>; 287 clock-names = "nvdec"; 288 resets = <&tegra_car 194>; 289 reset-names = "nvdec"; 290 291 iommus = <&mc TEGRA_SWGROUP_NVDEC>; 292 power-domains = <&pd_nvdec>; 293 }; 294 295 nvenc@544c0000 { 296 compatible = "nvidia,tegra210-nvenc"; 297 reg = <0x0 0x544c0000 0x0 0x00040000>; 298 clocks = <&tegra_car TEGRA210_CLK_NVENC>; 299 clock-names = "nvenc"; 300 resets = <&tegra_car 219>; 301 reset-names = "nvenc"; 302 303 iommus = <&mc TEGRA_SWGROUP_NVENC>; 304 power-domains = <&pd_nvenc>; 305 }; 306 307 tsec@54500000 { 308 compatible = "nvidia,tegra210-tsec"; 309 reg = <0x0 0x54500000 0x0 0x00040000>; 310 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 311 clocks = <&tegra_car TEGRA210_CLK_TSECB>; 312 clock-names = "tsec"; 313 resets = <&tegra_car 206>; 314 reset-names = "tsec"; 315 status = "disabled"; 316 }; 317 318 sor0: sor@54540000 { 319 compatible = "nvidia,tegra210-sor"; 320 reg = <0x0 0x54540000 0x0 0x00040000>; 321 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 323 <&tegra_car TEGRA210_CLK_SOR0_OUT>, 324 <&tegra_car TEGRA210_CLK_PLL_D_OUT0>, 325 <&tegra_car TEGRA210_CLK_PLL_DP>, 326 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 327 clock-names = "sor", "out", "parent", "dp", "safe"; 328 resets = <&tegra_car 182>; 329 reset-names = "sor"; 330 pinctrl-0 = <&state_dpaux_aux>; 331 pinctrl-1 = <&state_dpaux_i2c>; 332 pinctrl-2 = <&state_dpaux_off>; 333 pinctrl-names = "aux", "i2c", "off"; 334 power-domains = <&pd_sor>; 335 status = "disabled"; 336 }; 337 338 sor1: sor@54580000 { 339 compatible = "nvidia,tegra210-sor1"; 340 reg = <0x0 0x54580000 0x0 0x00040000>; 341 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 342 clocks = <&tegra_car TEGRA210_CLK_SOR1>, 343 <&tegra_car TEGRA210_CLK_SOR1_OUT>, 344 <&tegra_car TEGRA210_CLK_PLL_D2_OUT0>, 345 <&tegra_car TEGRA210_CLK_PLL_DP>, 346 <&tegra_car TEGRA210_CLK_SOR_SAFE>; 347 clock-names = "sor", "out", "parent", "dp", "safe"; 348 resets = <&tegra_car 183>; 349 reset-names = "sor"; 350 pinctrl-0 = <&state_dpaux1_aux>; 351 pinctrl-1 = <&state_dpaux1_i2c>; 352 pinctrl-2 = <&state_dpaux1_off>; 353 pinctrl-names = "aux", "i2c", "off"; 354 power-domains = <&pd_sor>; 355 status = "disabled"; 356 }; 357 358 dpaux: dpaux@545c0000 { 359 compatible = "nvidia,tegra210-dpaux"; 360 reg = <0x0 0x545c0000 0x0 0x00040000>; 361 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&tegra_car TEGRA210_CLK_DPAUX>, 363 <&tegra_car TEGRA210_CLK_PLL_DP>; 364 clock-names = "dpaux", "parent"; 365 resets = <&tegra_car 181>; 366 reset-names = "dpaux"; 367 power-domains = <&pd_sor>; 368 status = "disabled"; 369 370 state_dpaux_aux: pinmux-aux { 371 groups = "dpaux-io"; 372 function = "aux"; 373 }; 374 375 state_dpaux_i2c: pinmux-i2c { 376 groups = "dpaux-io"; 377 function = "i2c"; 378 }; 379 380 state_dpaux_off: pinmux-off { 381 groups = "dpaux-io"; 382 function = "off"; 383 }; 384 385 i2c-bus { 386 #address-cells = <1>; 387 #size-cells = <0>; 388 }; 389 }; 390 391 isp@54600000 { 392 compatible = "nvidia,tegra210-isp"; 393 reg = <0x0 0x54600000 0x0 0x00040000>; 394 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 395 clocks = <&tegra_car TEGRA210_CLK_ISPA>; 396 resets = <&tegra_car 23>; 397 reset-names = "isp"; 398 status = "disabled"; 399 }; 400 401 isp@54680000 { 402 compatible = "nvidia,tegra210-isp"; 403 reg = <0x0 0x54680000 0x0 0x00040000>; 404 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&tegra_car TEGRA210_CLK_ISPB>; 406 resets = <&tegra_car 3>; 407 reset-names = "isp"; 408 status = "disabled"; 409 }; 410 411 i2c@546c0000 { 412 compatible = "nvidia,tegra210-i2c-vi"; 413 reg = <0x0 0x546c0000 0x0 0x00040000>; 414 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 415 clocks = <&tegra_car TEGRA210_CLK_VI_I2C>, 416 <&tegra_car TEGRA210_CLK_I2CSLOW>; 417 clock-names = "div-clk", "slow"; 418 resets = <&tegra_car 208>; 419 reset-names = "i2c"; 420 power-domains = <&pd_venc>; 421 status = "disabled"; 422 423 #address-cells = <1>; 424 #size-cells = <0>; 425 }; 426 }; 427 428 gic: interrupt-controller@50041000 { 429 compatible = "arm,gic-400"; 430 #address-cells = <0>; 431 #interrupt-cells = <3>; 432 interrupt-controller; 433 reg = <0x0 0x50041000 0x0 0x1000>, 434 <0x0 0x50042000 0x0 0x2000>, 435 <0x0 0x50044000 0x0 0x2000>, 436 <0x0 0x50046000 0x0 0x2000>; 437 interrupts = <GIC_PPI 9 438 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 439 interrupt-parent = <&gic>; 440 }; 441 442 gpu@57000000 { 443 compatible = "nvidia,gm20b"; 444 reg = <0x0 0x57000000 0x0 0x01000000>, 445 <0x0 0x58000000 0x0 0x01000000>; 446 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 447 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 448 interrupt-names = "stall", "nonstall"; 449 clocks = <&tegra_car TEGRA210_CLK_GPU>, 450 <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, 451 <&tegra_car TEGRA210_CLK_PLL_G_REF>; 452 clock-names = "gpu", "pwr", "ref"; 453 resets = <&tegra_car 184>; 454 reset-names = "gpu"; 455 456 iommus = <&mc TEGRA_SWGROUP_GPU>; 457 458 status = "disabled"; 459 }; 460 461 lic: interrupt-controller@60004000 { 462 compatible = "nvidia,tegra210-ictlr"; 463 reg = <0x0 0x60004000 0x0 0x40>, /* primary controller */ 464 <0x0 0x60004100 0x0 0x40>, /* secondary controller */ 465 <0x0 0x60004200 0x0 0x40>, /* tertiary controller */ 466 <0x0 0x60004300 0x0 0x40>, /* quaternary controller */ 467 <0x0 0x60004400 0x0 0x40>, /* quinary controller */ 468 <0x0 0x60004500 0x0 0x40>; /* senary controller */ 469 interrupt-controller; 470 #interrupt-cells = <3>; 471 interrupt-parent = <&gic>; 472 }; 473 474 timer@60005000 { 475 compatible = "nvidia,tegra210-timer"; 476 reg = <0x0 0x60005000 0x0 0x400>; 477 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 491 clocks = <&tegra_car TEGRA210_CLK_TIMER>; 492 clock-names = "timer"; 493 }; 494 495 tegra_car: clock@60006000 { 496 compatible = "nvidia,tegra210-car"; 497 reg = <0x0 0x60006000 0x0 0x1000>; 498 #clock-cells = <1>; 499 #reset-cells = <1>; 500 }; 501 502 flow-controller@60007000 { 503 compatible = "nvidia,tegra210-flowctrl"; 504 reg = <0x0 0x60007000 0x0 0x1000>; 505 }; 506 507 actmon@6000c800 { 508 compatible = "nvidia,tegra210-actmon", "nvidia,tegra124-actmon"; 509 reg = <0x0 0x6000c800 0x0 0x400>; 510 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 511 clocks = <&tegra_car TEGRA210_CLK_ACTMON>, 512 <&tegra_car TEGRA210_CLK_EMC>; 513 clock-names = "actmon", "emc"; 514 resets = <&tegra_car 119>; 515 reset-names = "actmon"; 516 operating-points-v2 = <&emc_bw_dfs_opp_table>; 517 interconnects = <&mc TEGRA210_MC_MPCORER &emc>; 518 interconnect-names = "cpu-read"; 519 #cooling-cells = <2>; 520 }; 521 522 gpio: gpio@6000d000 { 523 compatible = "nvidia,tegra210-gpio", "nvidia,tegra30-gpio"; 524 reg = <0x0 0x6000d000 0x0 0x1000>; 525 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 526 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 527 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 528 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 529 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 530 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 531 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 532 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 533 #gpio-cells = <2>; 534 gpio-controller; 535 #interrupt-cells = <2>; 536 interrupt-controller; 537 }; 538 539 apbdma: dma-controller@60020000 { 540 compatible = "nvidia,tegra210-apbdma", "nvidia,tegra148-apbdma"; 541 reg = <0x0 0x60020000 0x0 0x1400>; 542 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 557 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 558 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 559 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 560 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 561 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 562 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 563 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 564 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 565 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 566 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 567 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 568 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 569 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 570 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 571 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 572 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 573 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 574 clocks = <&tegra_car TEGRA210_CLK_APBDMA>; 575 clock-names = "dma"; 576 resets = <&tegra_car 34>; 577 reset-names = "dma"; 578 #dma-cells = <1>; 579 }; 580 581 apbmisc@70000800 { 582 compatible = "nvidia,tegra210-apbmisc", "nvidia,tegra20-apbmisc"; 583 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 584 <0x0 0x70000008 0x0 0x04>; /* Strapping options */ 585 }; 586 587 pinmux: pinmux@700008d4 { 588 compatible = "nvidia,tegra210-pinmux"; 589 reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */ 590 <0x0 0x70003000 0x0 0x294>; /* Mux registers */ 591 592 sdmmc1_1v8_drv: pinmux-sdmmc1-1v8-drv { 593 sdmmc1 { 594 nvidia,pins = "drive_sdmmc1"; 595 nvidia,pull-down-strength = <0x4>; 596 nvidia,pull-up-strength = <0x3>; 597 }; 598 }; 599 600 sdmmc1_3v3_drv: pinmux-sdmmc1-3v3-drv { 601 sdmmc1 { 602 nvidia,pins = "drive_sdmmc1"; 603 nvidia,pull-down-strength = <0x8>; 604 nvidia,pull-up-strength = <0x8>; 605 }; 606 }; 607 608 sdmmc2_1v8_drv: pinmux-sdmmc2-1v8-drv { 609 sdmmc2 { 610 nvidia,pins = "drive_sdmmc2"; 611 nvidia,pull-down-strength = <0x10>; 612 nvidia,pull-up-strength = <0x10>; 613 }; 614 }; 615 616 sdmmc3_1v8_drv: pinmux-sdmmc3-1v8-drv { 617 sdmmc3 { 618 nvidia,pins = "drive_sdmmc3"; 619 nvidia,pull-down-strength = <0x4>; 620 nvidia,pull-up-strength = <0x3>; 621 }; 622 }; 623 624 sdmmc3_3v3_drv: pinmux-sdmmc3-3v3-drv { 625 sdmmc3 { 626 nvidia,pins = "drive_sdmmc3"; 627 nvidia,pull-down-strength = <0x8>; 628 nvidia,pull-up-strength = <0x8>; 629 }; 630 }; 631 632 sdmmc4_1v8_drv: pinmux-sdmmc4-1v8-drv { 633 sdmmc4 { 634 nvidia,pins = "drive_sdmmc4"; 635 nvidia,pull-down-strength = <0x10>; 636 nvidia,pull-up-strength = <0x10>; 637 }; 638 }; 639 }; 640 641 /* 642 * There are two serial driver i.e. 8250 based simple serial 643 * driver and APB DMA based serial driver for higher baudrate 644 * and performance. To enable the 8250 based driver, the compatible 645 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 646 * the APB DMA based serial driver, the compatible is 647 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 648 */ 649 uarta: serial@70006000 { 650 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 651 reg = <0x0 0x70006000 0x0 0x40>; 652 reg-shift = <2>; 653 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 654 clocks = <&tegra_car TEGRA210_CLK_UARTA>; 655 resets = <&tegra_car 6>; 656 dmas = <&apbdma 8>, <&apbdma 8>; 657 dma-names = "rx", "tx"; 658 status = "disabled"; 659 }; 660 661 uartb: serial@70006040 { 662 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 663 reg = <0x0 0x70006040 0x0 0x40>; 664 reg-shift = <2>; 665 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 666 clocks = <&tegra_car TEGRA210_CLK_UARTB>; 667 resets = <&tegra_car 7>; 668 dmas = <&apbdma 9>, <&apbdma 9>; 669 dma-names = "rx", "tx"; 670 status = "disabled"; 671 }; 672 673 uartc: serial@70006200 { 674 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 675 reg = <0x0 0x70006200 0x0 0x40>; 676 reg-shift = <2>; 677 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 678 clocks = <&tegra_car TEGRA210_CLK_UARTC>; 679 resets = <&tegra_car 55>; 680 dmas = <&apbdma 10>, <&apbdma 10>; 681 dma-names = "rx", "tx"; 682 status = "disabled"; 683 }; 684 685 uartd: serial@70006300 { 686 compatible = "nvidia,tegra210-uart", "nvidia,tegra20-uart"; 687 reg = <0x0 0x70006300 0x0 0x40>; 688 reg-shift = <2>; 689 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 690 clocks = <&tegra_car TEGRA210_CLK_UARTD>; 691 resets = <&tegra_car 65>; 692 dmas = <&apbdma 19>, <&apbdma 19>; 693 dma-names = "rx", "tx"; 694 status = "disabled"; 695 }; 696 697 pwm: pwm@7000a000 { 698 compatible = "nvidia,tegra210-pwm", "nvidia,tegra20-pwm"; 699 reg = <0x0 0x7000a000 0x0 0x100>; 700 #pwm-cells = <2>; 701 clocks = <&tegra_car TEGRA210_CLK_PWM>; 702 resets = <&tegra_car 17>; 703 reset-names = "pwm"; 704 status = "disabled"; 705 }; 706 707 i2c@7000c000 { 708 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 709 reg = <0x0 0x7000c000 0x0 0x100>; 710 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 711 #address-cells = <1>; 712 #size-cells = <0>; 713 clocks = <&tegra_car TEGRA210_CLK_I2C1>; 714 clock-names = "div-clk"; 715 resets = <&tegra_car 12>; 716 reset-names = "i2c"; 717 dmas = <&apbdma 21>, <&apbdma 21>; 718 dma-names = "rx", "tx"; 719 status = "disabled"; 720 }; 721 722 i2c@7000c400 { 723 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 724 reg = <0x0 0x7000c400 0x0 0x100>; 725 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 726 #address-cells = <1>; 727 #size-cells = <0>; 728 clocks = <&tegra_car TEGRA210_CLK_I2C2>; 729 clock-names = "div-clk"; 730 resets = <&tegra_car 54>; 731 reset-names = "i2c"; 732 dmas = <&apbdma 22>, <&apbdma 22>; 733 dma-names = "rx", "tx"; 734 status = "disabled"; 735 }; 736 737 i2c@7000c500 { 738 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 739 reg = <0x0 0x7000c500 0x0 0x100>; 740 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 741 #address-cells = <1>; 742 #size-cells = <0>; 743 clocks = <&tegra_car TEGRA210_CLK_I2C3>; 744 clock-names = "div-clk"; 745 resets = <&tegra_car 67>; 746 reset-names = "i2c"; 747 dmas = <&apbdma 23>, <&apbdma 23>; 748 dma-names = "rx", "tx"; 749 status = "disabled"; 750 }; 751 752 i2c@7000c700 { 753 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 754 reg = <0x0 0x7000c700 0x0 0x100>; 755 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 756 #address-cells = <1>; 757 #size-cells = <0>; 758 clocks = <&tegra_car TEGRA210_CLK_I2C4>; 759 clock-names = "div-clk"; 760 resets = <&tegra_car 103>; 761 reset-names = "i2c"; 762 dmas = <&apbdma 26>, <&apbdma 26>; 763 dma-names = "rx", "tx"; 764 pinctrl-0 = <&state_dpaux1_i2c>; 765 pinctrl-1 = <&state_dpaux1_off>; 766 pinctrl-names = "default", "idle"; 767 status = "disabled"; 768 }; 769 770 i2c@7000d000 { 771 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 772 reg = <0x0 0x7000d000 0x0 0x100>; 773 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 clocks = <&tegra_car TEGRA210_CLK_I2C5>; 777 clock-names = "div-clk"; 778 resets = <&tegra_car 47>; 779 reset-names = "i2c"; 780 dmas = <&apbdma 24>, <&apbdma 24>; 781 dma-names = "rx", "tx"; 782 status = "disabled"; 783 }; 784 785 i2c@7000d100 { 786 compatible = "nvidia,tegra210-i2c", "nvidia,tegra124-i2c"; 787 reg = <0x0 0x7000d100 0x0 0x100>; 788 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 clocks = <&tegra_car TEGRA210_CLK_I2C6>; 792 clock-names = "div-clk"; 793 resets = <&tegra_car 166>; 794 reset-names = "i2c"; 795 dmas = <&apbdma 30>, <&apbdma 30>; 796 dma-names = "rx", "tx"; 797 pinctrl-0 = <&state_dpaux_i2c>; 798 pinctrl-1 = <&state_dpaux_off>; 799 pinctrl-names = "default", "idle"; 800 status = "disabled"; 801 }; 802 803 spi@7000d400 { 804 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 805 reg = <0x0 0x7000d400 0x0 0x200>; 806 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 clocks = <&tegra_car TEGRA210_CLK_SBC1>; 810 clock-names = "spi"; 811 resets = <&tegra_car 41>; 812 reset-names = "spi"; 813 dmas = <&apbdma 15>, <&apbdma 15>; 814 dma-names = "rx", "tx"; 815 status = "disabled"; 816 }; 817 818 spi@7000d600 { 819 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 820 reg = <0x0 0x7000d600 0x0 0x200>; 821 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 822 #address-cells = <1>; 823 #size-cells = <0>; 824 clocks = <&tegra_car TEGRA210_CLK_SBC2>; 825 clock-names = "spi"; 826 resets = <&tegra_car 44>; 827 reset-names = "spi"; 828 dmas = <&apbdma 16>, <&apbdma 16>; 829 dma-names = "rx", "tx"; 830 status = "disabled"; 831 }; 832 833 spi@7000d800 { 834 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 835 reg = <0x0 0x7000d800 0x0 0x200>; 836 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 clocks = <&tegra_car TEGRA210_CLK_SBC3>; 840 clock-names = "spi"; 841 resets = <&tegra_car 46>; 842 reset-names = "spi"; 843 dmas = <&apbdma 17>, <&apbdma 17>; 844 dma-names = "rx", "tx"; 845 status = "disabled"; 846 }; 847 848 spi@7000da00 { 849 compatible = "nvidia,tegra210-spi", "nvidia,tegra114-spi"; 850 reg = <0x0 0x7000da00 0x0 0x200>; 851 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 852 #address-cells = <1>; 853 #size-cells = <0>; 854 clocks = <&tegra_car TEGRA210_CLK_SBC4>; 855 clock-names = "spi"; 856 resets = <&tegra_car 68>; 857 reset-names = "spi"; 858 dmas = <&apbdma 18>, <&apbdma 18>; 859 dma-names = "rx", "tx"; 860 status = "disabled"; 861 }; 862 863 rtc@7000e000 { 864 compatible = "nvidia,tegra210-rtc", "nvidia,tegra20-rtc"; 865 reg = <0x0 0x7000e000 0x0 0x100>; 866 interrupts = <16 IRQ_TYPE_LEVEL_HIGH>; 867 interrupt-parent = <&tegra_pmc>; 868 clocks = <&tegra_car TEGRA210_CLK_RTC>; 869 clock-names = "rtc"; 870 }; 871 872 tegra_pmc: pmc@7000e400 { 873 compatible = "nvidia,tegra210-pmc"; 874 reg = <0x0 0x7000e400 0x0 0x400>; 875 clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>; 876 clock-names = "pclk", "clk32k_in"; 877 #clock-cells = <1>; 878 #interrupt-cells = <2>; 879 interrupt-controller; 880 881 pinmux { 882 pex_dpd_disable: pex-dpd-disable { 883 pins = "pex-bias", "pex-clk1", "pex-clk2"; 884 low-power-disable; 885 }; 886 887 pex_dpd_enable: pex-dpd-enable { 888 pins = "pex-bias", "pex-clk1", "pex-clk2"; 889 low-power-enable; 890 }; 891 892 sdmmc1_1v8: sdmmc1-1v8 { 893 pins = "sdmmc1"; 894 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 895 }; 896 897 sdmmc1_3v3: sdmmc1-3v3 { 898 pins = "sdmmc1"; 899 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 900 }; 901 902 sdmmc3_1v8: sdmmc3-1v8 { 903 pins = "sdmmc3"; 904 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 905 }; 906 907 sdmmc3_3v3: sdmmc3-3v3 { 908 pins = "sdmmc3"; 909 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 910 }; 911 912 gpio_1v8: gpio-1v8 { 913 pins = "gpio"; 914 power-source = <TEGRA_IO_PAD_VOLTAGE_1V8>; 915 }; 916 917 gpio_3v3: gpio-3v3 { 918 pins = "gpio"; 919 power-source = <TEGRA_IO_PAD_VOLTAGE_3V3>; 920 }; 921 }; 922 923 powergates { 924 pd_audio: aud { 925 clocks = <&tegra_car TEGRA210_CLK_APE>, 926 <&tegra_car TEGRA210_CLK_APB2APE>; 927 resets = <&tegra_car 198>; 928 #power-domain-cells = <0>; 929 }; 930 931 pd_nvenc: mpe { 932 clocks = <&tegra_car TEGRA210_CLK_NVENC>; 933 resets = <&tegra_car 219>; 934 #power-domain-cells = <0>; 935 }; 936 937 pd_nvdec: nvdec { 938 clocks = <&tegra_car TEGRA210_CLK_NVDEC>; 939 resets = <&tegra_car 194>; 940 #power-domain-cells = <0>; 941 }; 942 943 pd_sor: sor { 944 clocks = <&tegra_car TEGRA210_CLK_SOR0>, 945 <&tegra_car TEGRA210_CLK_SOR1>, 946 <&tegra_car TEGRA210_CLK_CILAB>, 947 <&tegra_car TEGRA210_CLK_CILCD>, 948 <&tegra_car TEGRA210_CLK_CILE>, 949 <&tegra_car TEGRA210_CLK_DSIA>, 950 <&tegra_car TEGRA210_CLK_DSIB>, 951 <&tegra_car TEGRA210_CLK_DPAUX>, 952 <&tegra_car TEGRA210_CLK_DPAUX1>, 953 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 954 resets = <&tegra_car TEGRA210_CLK_SOR0>, 955 <&tegra_car TEGRA210_CLK_SOR1>, 956 <&tegra_car TEGRA210_CLK_DSIA>, 957 <&tegra_car TEGRA210_CLK_DSIB>, 958 <&tegra_car TEGRA210_CLK_DPAUX>, 959 <&tegra_car TEGRA210_CLK_DPAUX1>, 960 <&tegra_car TEGRA210_CLK_MIPI_CAL>; 961 #power-domain-cells = <0>; 962 }; 963 964 pd_venc: venc { 965 clocks = <&tegra_car TEGRA210_CLK_VI>, 966 <&tegra_car TEGRA210_CLK_CSI>; 967 resets = <&mc TEGRA210_MC_RESET_VI>, 968 <&tegra_car 20>, 969 <&tegra_car 52>; 970 #power-domain-cells = <0>; 971 }; 972 973 pd_vic: vic { 974 clocks = <&tegra_car TEGRA210_CLK_VIC03>; 975 resets = <&tegra_car 178>; 976 #power-domain-cells = <0>; 977 }; 978 979 pd_xusbss: xusba { 980 clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>; 981 resets = <&tegra_car TEGRA210_CLK_XUSB_SS>; 982 #power-domain-cells = <0>; 983 }; 984 985 pd_xusbdev: xusbb { 986 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>; 987 resets = <&tegra_car 95>; 988 #power-domain-cells = <0>; 989 }; 990 991 pd_xusbhost: xusbc { 992 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 993 resets = <&tegra_car TEGRA210_CLK_XUSB_HOST>; 994 #power-domain-cells = <0>; 995 }; 996 997 pd_nvjpg: nvjpg { 998 clocks = <&tegra_car TEGRA210_CLK_NVJPG>; 999 resets = <&tegra_car 195>; 1000 #power-domain-cells = <0>; 1001 }; 1002 }; 1003 }; 1004 1005 fuse@7000f800 { 1006 compatible = "nvidia,tegra210-efuse"; 1007 reg = <0x0 0x7000f800 0x0 0x400>; 1008 clocks = <&tegra_car TEGRA210_CLK_FUSE>; 1009 clock-names = "fuse"; 1010 resets = <&tegra_car 39>; 1011 reset-names = "fuse"; 1012 }; 1013 1014 cec@70015000 { 1015 compatible = "nvidia,tegra210-cec"; 1016 reg = <0x0 0x070015000 0x0 0x1000>; 1017 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1018 clocks = <&tegra_car TEGRA210_CLK_CEC>; 1019 clock-names = "cec"; 1020 status = "disabled"; 1021 }; 1022 1023 mc: memory-controller@70019000 { 1024 compatible = "nvidia,tegra210-mc"; 1025 reg = <0x0 0x70019000 0x0 0x1000>; 1026 clocks = <&tegra_car TEGRA210_CLK_MC>; 1027 clock-names = "mc"; 1028 1029 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1030 1031 #iommu-cells = <1>; 1032 #reset-cells = <1>; 1033 }; 1034 1035 emc: external-memory-controller@7001b000 { 1036 compatible = "nvidia,tegra210-emc"; 1037 reg = <0x0 0x7001b000 0x0 0x1000>, 1038 <0x0 0x7001e000 0x0 0x1000>, 1039 <0x0 0x7001f000 0x0 0x1000>; 1040 clocks = <&tegra_car TEGRA210_CLK_EMC>; 1041 clock-names = "emc"; 1042 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1043 nvidia,memory-controller = <&mc>; 1044 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 1045 1046 #cooling-cells = <2>; 1047 }; 1048 1049 sata@70020000 { 1050 compatible = "nvidia,tegra210-ahci"; 1051 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 1052 <0x0 0x70020000 0x0 0x7000>, /* SATA */ 1053 <0x0 0x70001100 0x0 0x1000>; /* SATA AUX */ 1054 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1055 clocks = <&tegra_car TEGRA210_CLK_SATA>, 1056 <&tegra_car TEGRA210_CLK_SATA_OOB>; 1057 clock-names = "sata", "sata-oob"; 1058 resets = <&tegra_car 124>, 1059 <&tegra_car 129>, 1060 <&tegra_car 123>; 1061 reset-names = "sata", "sata-cold", "sata-oob"; 1062 status = "disabled"; 1063 }; 1064 1065 hda@70030000 { 1066 compatible = "nvidia,tegra210-hda", "nvidia,tegra30-hda"; 1067 reg = <0x0 0x70030000 0x0 0x10000>; 1068 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1069 clocks = <&tegra_car TEGRA210_CLK_HDA>, 1070 <&tegra_car TEGRA210_CLK_HDA2HDMI>, 1071 <&tegra_car TEGRA210_CLK_HDA2CODEC_2X>; 1072 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 1073 resets = <&tegra_car 125>, /* hda */ 1074 <&tegra_car 128>, /* hda2hdmi */ 1075 <&tegra_car 111>; /* hda2codec_2x */ 1076 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 1077 power-domains = <&pd_sor>; 1078 status = "disabled"; 1079 }; 1080 1081 usb@70090000 { 1082 compatible = "nvidia,tegra210-xusb"; 1083 reg = <0x0 0x70090000 0x0 0x8000>, 1084 <0x0 0x70098000 0x0 0x1000>, 1085 <0x0 0x70099000 0x0 0x1000>; 1086 reg-names = "hcd", "fpci", "ipfs"; 1087 1088 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1090 1091 clocks = <&tegra_car TEGRA210_CLK_XUSB_HOST>, 1092 <&tegra_car TEGRA210_CLK_XUSB_HOST_SRC>, 1093 <&tegra_car TEGRA210_CLK_XUSB_FALCON_SRC>, 1094 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1095 <&tegra_car TEGRA210_CLK_XUSB_SS_DIV2>, 1096 <&tegra_car TEGRA210_CLK_XUSB_SS_SRC>, 1097 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>, 1098 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1099 <&tegra_car TEGRA210_CLK_PLL_U_480M>, 1100 <&tegra_car TEGRA210_CLK_CLK_M>, 1101 <&tegra_car TEGRA210_CLK_PLL_E>; 1102 clock-names = "xusb_host", "xusb_host_src", 1103 "xusb_falcon_src", "xusb_ss", 1104 "xusb_ss_div2", "xusb_ss_src", 1105 "xusb_hs_src", "xusb_fs_src", 1106 "pll_u_480m", "clk_m", "pll_e"; 1107 resets = <&tegra_car 89>, <&tegra_car 156>, 1108 <&tegra_car 143>; 1109 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 1110 power-domains = <&pd_xusbhost>, <&pd_xusbss>; 1111 power-domain-names = "xusb_host", "xusb_ss"; 1112 1113 nvidia,xusb-padctl = <&padctl>; 1114 1115 status = "disabled"; 1116 }; 1117 1118 padctl: padctl@7009f000 { 1119 compatible = "nvidia,tegra210-xusb-padctl"; 1120 reg = <0x0 0x7009f000 0x0 0x1000>; 1121 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1122 resets = <&tegra_car 142>; 1123 reset-names = "padctl"; 1124 nvidia,pmc = <&tegra_pmc>; 1125 1126 status = "disabled"; 1127 1128 pads { 1129 usb2 { 1130 clocks = <&tegra_car TEGRA210_CLK_USB2_TRK>; 1131 clock-names = "trk"; 1132 status = "disabled"; 1133 1134 lanes { 1135 usb2-0 { 1136 status = "disabled"; 1137 #phy-cells = <0>; 1138 }; 1139 1140 usb2-1 { 1141 status = "disabled"; 1142 #phy-cells = <0>; 1143 }; 1144 1145 usb2-2 { 1146 status = "disabled"; 1147 #phy-cells = <0>; 1148 }; 1149 1150 usb2-3 { 1151 status = "disabled"; 1152 #phy-cells = <0>; 1153 }; 1154 }; 1155 }; 1156 1157 hsic { 1158 clocks = <&tegra_car TEGRA210_CLK_HSIC_TRK>; 1159 clock-names = "trk"; 1160 status = "disabled"; 1161 1162 lanes { 1163 hsic-0 { 1164 status = "disabled"; 1165 #phy-cells = <0>; 1166 }; 1167 1168 hsic-1 { 1169 status = "disabled"; 1170 #phy-cells = <0>; 1171 }; 1172 }; 1173 }; 1174 1175 pcie { 1176 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1177 clock-names = "pll"; 1178 resets = <&tegra_car 205>; 1179 reset-names = "phy"; 1180 status = "disabled"; 1181 1182 lanes { 1183 pcie-0 { 1184 status = "disabled"; 1185 #phy-cells = <0>; 1186 }; 1187 1188 pcie-1 { 1189 status = "disabled"; 1190 #phy-cells = <0>; 1191 }; 1192 1193 pcie-2 { 1194 status = "disabled"; 1195 #phy-cells = <0>; 1196 }; 1197 1198 pcie-3 { 1199 status = "disabled"; 1200 #phy-cells = <0>; 1201 }; 1202 1203 pcie-4 { 1204 status = "disabled"; 1205 #phy-cells = <0>; 1206 }; 1207 1208 pcie-5 { 1209 status = "disabled"; 1210 #phy-cells = <0>; 1211 }; 1212 1213 pcie-6 { 1214 status = "disabled"; 1215 #phy-cells = <0>; 1216 }; 1217 }; 1218 }; 1219 1220 sata { 1221 clocks = <&tegra_car TEGRA210_CLK_PLL_E>; 1222 clock-names = "pll"; 1223 resets = <&tegra_car 204>; 1224 reset-names = "phy"; 1225 status = "disabled"; 1226 1227 lanes { 1228 sata-0 { 1229 status = "disabled"; 1230 #phy-cells = <0>; 1231 }; 1232 }; 1233 }; 1234 }; 1235 1236 ports { 1237 usb2-0 { 1238 status = "disabled"; 1239 }; 1240 1241 usb2-1 { 1242 status = "disabled"; 1243 }; 1244 1245 usb2-2 { 1246 status = "disabled"; 1247 }; 1248 1249 usb2-3 { 1250 status = "disabled"; 1251 }; 1252 1253 hsic-0 { 1254 status = "disabled"; 1255 }; 1256 1257 usb3-0 { 1258 status = "disabled"; 1259 }; 1260 1261 usb3-1 { 1262 status = "disabled"; 1263 }; 1264 1265 usb3-2 { 1266 status = "disabled"; 1267 }; 1268 1269 usb3-3 { 1270 status = "disabled"; 1271 }; 1272 }; 1273 }; 1274 1275 mmc@700b0000 { 1276 compatible = "nvidia,tegra210-sdhci"; 1277 reg = <0x0 0x700b0000 0x0 0x200>; 1278 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1279 clocks = <&tegra_car TEGRA210_CLK_SDMMC1>, 1280 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1281 clock-names = "sdhci", "tmclk"; 1282 resets = <&tegra_car 14>; 1283 reset-names = "sdhci"; 1284 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1285 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1286 pinctrl-0 = <&sdmmc1_3v3>; 1287 pinctrl-1 = <&sdmmc1_1v8>; 1288 pinctrl-2 = <&sdmmc1_3v3_drv>; 1289 pinctrl-3 = <&sdmmc1_1v8_drv>; 1290 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1291 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1292 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1293 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1294 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x0>; 1295 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x0>; 1296 nvidia,default-tap = <0x2>; 1297 nvidia,default-trim = <0x4>; 1298 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1299 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>, 1300 <&tegra_car TEGRA210_CLK_PLL_C4>; 1301 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1302 assigned-clock-rates = <200000000>, <1000000000>, <1000000000>; 1303 status = "disabled"; 1304 }; 1305 1306 mmc@700b0200 { 1307 compatible = "nvidia,tegra210-sdhci"; 1308 reg = <0x0 0x700b0200 0x0 0x200>; 1309 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1310 clocks = <&tegra_car TEGRA210_CLK_SDMMC2>, 1311 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1312 clock-names = "sdhci", "tmclk"; 1313 resets = <&tegra_car 9>; 1314 reset-names = "sdhci"; 1315 pinctrl-names = "sdmmc-1v8-drv"; 1316 pinctrl-0 = <&sdmmc2_1v8_drv>; 1317 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1318 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1319 nvidia,default-tap = <0x8>; 1320 nvidia,default-trim = <0x0>; 1321 status = "disabled"; 1322 }; 1323 1324 mmc@700b0400 { 1325 compatible = "nvidia,tegra210-sdhci"; 1326 reg = <0x0 0x700b0400 0x0 0x200>; 1327 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1328 clocks = <&tegra_car TEGRA210_CLK_SDMMC3>, 1329 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1330 clock-names = "sdhci", "tmclk"; 1331 resets = <&tegra_car 69>; 1332 reset-names = "sdhci"; 1333 pinctrl-names = "sdmmc-3v3", "sdmmc-1v8", 1334 "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1335 pinctrl-0 = <&sdmmc3_3v3>; 1336 pinctrl-1 = <&sdmmc3_1v8>; 1337 pinctrl-2 = <&sdmmc3_3v3_drv>; 1338 pinctrl-3 = <&sdmmc3_1v8_drv>; 1339 nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>; 1340 nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>; 1341 nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>; 1342 nvidia,pad-autocal-pull-down-offset-1v8 = <0x7b>; 1343 nvidia,default-tap = <0x3>; 1344 nvidia,default-trim = <0x3>; 1345 status = "disabled"; 1346 }; 1347 1348 mmc@700b0600 { 1349 compatible = "nvidia,tegra210-sdhci"; 1350 reg = <0x0 0x700b0600 0x0 0x200>; 1351 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1352 clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1353 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>; 1354 clock-names = "sdhci", "tmclk"; 1355 resets = <&tegra_car 15>; 1356 reset-names = "sdhci"; 1357 pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv"; 1358 pinctrl-0 = <&sdmmc4_1v8_drv>; 1359 pinctrl-1 = <&sdmmc4_1v8_drv>; 1360 nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>; 1361 nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>; 1362 nvidia,default-tap = <0x8>; 1363 nvidia,default-trim = <0x0>; 1364 assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>, 1365 <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1366 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT0>; 1367 nvidia,dqs-trim = <40>; 1368 mmc-hs400-1_8v; 1369 status = "disabled"; 1370 }; 1371 1372 usb@700d0000 { 1373 compatible = "nvidia,tegra210-xudc"; 1374 reg = <0x0 0x700d0000 0x0 0x8000>, 1375 <0x0 0x700d8000 0x0 0x1000>, 1376 <0x0 0x700d9000 0x0 0x1000>; 1377 reg-names = "base", "fpci", "ipfs"; 1378 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1379 clocks = <&tegra_car TEGRA210_CLK_XUSB_DEV>, 1380 <&tegra_car TEGRA210_CLK_XUSB_SS>, 1381 <&tegra_car TEGRA210_CLK_XUSB_SSP_SRC>, 1382 <&tegra_car TEGRA210_CLK_XUSB_FS_SRC>, 1383 <&tegra_car TEGRA210_CLK_XUSB_HS_SRC>; 1384 clock-names = "dev", "ss", "ss_src", "fs_src", "hs_src"; 1385 power-domains = <&pd_xusbdev>, <&pd_xusbss>; 1386 power-domain-names = "dev", "ss"; 1387 nvidia,xusb-padctl = <&padctl>; 1388 status = "disabled"; 1389 }; 1390 1391 soctherm: thermal-sensor@700e2000 { 1392 compatible = "nvidia,tegra210-soctherm"; 1393 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ 1394 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */ 1395 reg-names = "soctherm-reg", "car-reg"; 1396 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1397 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1398 interrupt-names = "thermal", "edp"; 1399 clocks = <&tegra_car TEGRA210_CLK_TSENSOR>, 1400 <&tegra_car TEGRA210_CLK_SOC_THERM>; 1401 clock-names = "tsensor", "soctherm"; 1402 resets = <&tegra_car 78>; 1403 reset-names = "soctherm"; 1404 #thermal-sensor-cells = <1>; 1405 1406 throttle-cfgs { 1407 throttle_heavy: heavy { 1408 nvidia,priority = <100>; 1409 nvidia,cpu-throt-percent = <85>; 1410 nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 1411 1412 #cooling-cells = <2>; 1413 }; 1414 }; 1415 }; 1416 1417 mipi: mipi@700e3000 { 1418 compatible = "nvidia,tegra210-mipi"; 1419 reg = <0x0 0x700e3000 0x0 0x100>; 1420 clocks = <&tegra_car TEGRA210_CLK_MIPI_CAL>; 1421 clock-names = "mipi-cal"; 1422 power-domains = <&pd_sor>; 1423 #nvidia,mipi-calibrate-cells = <1>; 1424 }; 1425 1426 dfll: clock@70110000 { 1427 compatible = "nvidia,tegra210-dfll"; 1428 reg = <0 0x70110000 0 0x100>, /* DFLL control */ 1429 <0 0x70110000 0 0x100>, /* I2C output control */ 1430 <0 0x70110100 0 0x100>, /* Integrated I2C controller */ 1431 <0 0x70110200 0 0x100>; /* Look-up table RAM */ 1432 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 1433 clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, 1434 <&tegra_car TEGRA210_CLK_DFLL_REF>, 1435 <&tegra_car TEGRA210_CLK_I2C5>; 1436 clock-names = "soc", "ref", "i2c"; 1437 resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>, 1438 <&tegra_car 155>; 1439 reset-names = "dvco", "dfll"; 1440 #clock-cells = <0>; 1441 clock-output-names = "dfllCPU_out"; 1442 status = "disabled"; 1443 }; 1444 1445 aconnect@702c0000 { 1446 compatible = "nvidia,tegra210-aconnect"; 1447 clocks = <&tegra_car TEGRA210_CLK_APE>, 1448 <&tegra_car TEGRA210_CLK_APB2APE>; 1449 clock-names = "ape", "apb2ape"; 1450 power-domains = <&pd_audio>; 1451 #address-cells = <1>; 1452 #size-cells = <1>; 1453 ranges = <0x702c0000 0x0 0x702c0000 0x00040000>; 1454 status = "disabled"; 1455 1456 tegra_ahub: ahub@702d0800 { 1457 compatible = "nvidia,tegra210-ahub"; 1458 reg = <0x702d0800 0x800>; 1459 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1460 clock-names = "ahub"; 1461 assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1462 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_P>; 1463 assigned-clock-rates = <81600000>; 1464 #address-cells = <1>; 1465 #size-cells = <1>; 1466 ranges = <0x702d0000 0x702d0000 0x0000e400>; 1467 status = "disabled"; 1468 1469 tegra_admaif: admaif@702d0000 { 1470 compatible = "nvidia,tegra210-admaif"; 1471 reg = <0x702d0000 0x800>; 1472 dmas = <&adma 1>, <&adma 1>, 1473 <&adma 2>, <&adma 2>, 1474 <&adma 3>, <&adma 3>, 1475 <&adma 4>, <&adma 4>, 1476 <&adma 5>, <&adma 5>, 1477 <&adma 6>, <&adma 6>, 1478 <&adma 7>, <&adma 7>, 1479 <&adma 8>, <&adma 8>, 1480 <&adma 9>, <&adma 9>, 1481 <&adma 10>, <&adma 10>; 1482 dma-names = "rx1", "tx1", 1483 "rx2", "tx2", 1484 "rx3", "tx3", 1485 "rx4", "tx4", 1486 "rx5", "tx5", 1487 "rx6", "tx6", 1488 "rx7", "tx7", 1489 "rx8", "tx8", 1490 "rx9", "tx9", 1491 "rx10", "tx10"; 1492 status = "disabled"; 1493 1494 ports { 1495 #address-cells = <1>; 1496 #size-cells = <0>; 1497 1498 admaif1_port: port@0 { 1499 reg = <0>; 1500 1501 admaif1_ep: endpoint { 1502 remote-endpoint = <&xbar_admaif1_ep>; 1503 }; 1504 }; 1505 1506 admaif2_port: port@1 { 1507 reg = <1>; 1508 1509 admaif2_ep: endpoint { 1510 remote-endpoint = <&xbar_admaif2_ep>; 1511 }; 1512 }; 1513 1514 admaif3_port: port@2 { 1515 reg = <2>; 1516 1517 admaif3_ep: endpoint { 1518 remote-endpoint = <&xbar_admaif3_ep>; 1519 }; 1520 }; 1521 1522 admaif4_port: port@3 { 1523 reg = <3>; 1524 1525 admaif4_ep: endpoint { 1526 remote-endpoint = <&xbar_admaif4_ep>; 1527 }; 1528 }; 1529 1530 admaif5_port: port@4 { 1531 reg = <4>; 1532 1533 admaif5_ep: endpoint { 1534 remote-endpoint = <&xbar_admaif5_ep>; 1535 }; 1536 }; 1537 1538 admaif6_port: port@5 { 1539 reg = <5>; 1540 1541 admaif6_ep: endpoint { 1542 remote-endpoint = <&xbar_admaif6_ep>; 1543 }; 1544 }; 1545 1546 admaif7_port: port@6 { 1547 reg = <6>; 1548 1549 admaif7_ep: endpoint { 1550 remote-endpoint = <&xbar_admaif7_ep>; 1551 }; 1552 }; 1553 1554 admaif8_port: port@7 { 1555 reg = <7>; 1556 1557 admaif8_ep: endpoint { 1558 remote-endpoint = <&xbar_admaif8_ep>; 1559 }; 1560 }; 1561 1562 admaif9_port: port@8 { 1563 reg = <8>; 1564 1565 admaif9_ep: endpoint { 1566 remote-endpoint = <&xbar_admaif9_ep>; 1567 }; 1568 }; 1569 1570 admaif10_port: port@9 { 1571 reg = <9>; 1572 1573 admaif10_ep: endpoint { 1574 remote-endpoint = <&xbar_admaif10_ep>; 1575 }; 1576 }; 1577 }; 1578 }; 1579 1580 tegra_i2s1: i2s@702d1000 { 1581 compatible = "nvidia,tegra210-i2s"; 1582 reg = <0x702d1000 0x100>; 1583 clocks = <&tegra_car TEGRA210_CLK_I2S0>, 1584 <&tegra_car TEGRA210_CLK_I2S0_SYNC>; 1585 clock-names = "i2s", "sync_input"; 1586 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>; 1587 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1588 assigned-clock-rates = <1536000>; 1589 sound-name-prefix = "I2S1"; 1590 status = "disabled"; 1591 }; 1592 1593 tegra_i2s2: i2s@702d1100 { 1594 compatible = "nvidia,tegra210-i2s"; 1595 reg = <0x702d1100 0x100>; 1596 clocks = <&tegra_car TEGRA210_CLK_I2S1>, 1597 <&tegra_car TEGRA210_CLK_I2S1_SYNC>; 1598 clock-names = "i2s", "sync_input"; 1599 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S1>; 1600 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1601 assigned-clock-rates = <1536000>; 1602 sound-name-prefix = "I2S2"; 1603 status = "disabled"; 1604 }; 1605 1606 tegra_i2s3: i2s@702d1200 { 1607 compatible = "nvidia,tegra210-i2s"; 1608 reg = <0x702d1200 0x100>; 1609 clocks = <&tegra_car TEGRA210_CLK_I2S2>, 1610 <&tegra_car TEGRA210_CLK_I2S2_SYNC>; 1611 clock-names = "i2s", "sync_input"; 1612 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S2>; 1613 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1614 assigned-clock-rates = <1536000>; 1615 sound-name-prefix = "I2S3"; 1616 status = "disabled"; 1617 }; 1618 1619 tegra_i2s4: i2s@702d1300 { 1620 compatible = "nvidia,tegra210-i2s"; 1621 reg = <0x702d1300 0x100>; 1622 clocks = <&tegra_car TEGRA210_CLK_I2S3>, 1623 <&tegra_car TEGRA210_CLK_I2S3_SYNC>; 1624 clock-names = "i2s", "sync_input"; 1625 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S3>; 1626 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1627 assigned-clock-rates = <1536000>; 1628 sound-name-prefix = "I2S4"; 1629 status = "disabled"; 1630 }; 1631 1632 tegra_i2s5: i2s@702d1400 { 1633 compatible = "nvidia,tegra210-i2s"; 1634 reg = <0x702d1400 0x100>; 1635 clocks = <&tegra_car TEGRA210_CLK_I2S4>, 1636 <&tegra_car TEGRA210_CLK_I2S4_SYNC>; 1637 clock-names = "i2s", "sync_input"; 1638 assigned-clocks = <&tegra_car TEGRA210_CLK_I2S4>; 1639 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1640 assigned-clock-rates = <1536000>; 1641 sound-name-prefix = "I2S5"; 1642 status = "disabled"; 1643 }; 1644 1645 tegra_sfc1: sfc@702d2000 { 1646 compatible = "nvidia,tegra210-sfc"; 1647 reg = <0x702d2000 0x200>; 1648 sound-name-prefix = "SFC1"; 1649 status = "disabled"; 1650 }; 1651 1652 tegra_sfc2: sfc@702d2200 { 1653 compatible = "nvidia,tegra210-sfc"; 1654 reg = <0x702d2200 0x200>; 1655 sound-name-prefix = "SFC2"; 1656 status = "disabled"; 1657 }; 1658 1659 tegra_sfc3: sfc@702d2400 { 1660 compatible = "nvidia,tegra210-sfc"; 1661 reg = <0x702d2400 0x200>; 1662 sound-name-prefix = "SFC3"; 1663 status = "disabled"; 1664 }; 1665 1666 tegra_sfc4: sfc@702d2600 { 1667 compatible = "nvidia,tegra210-sfc"; 1668 reg = <0x702d2600 0x200>; 1669 sound-name-prefix = "SFC4"; 1670 status = "disabled"; 1671 }; 1672 1673 tegra_amx1: amx@702d3000 { 1674 compatible = "nvidia,tegra210-amx"; 1675 reg = <0x702d3000 0x100>; 1676 sound-name-prefix = "AMX1"; 1677 status = "disabled"; 1678 }; 1679 1680 tegra_amx2: amx@702d3100 { 1681 compatible = "nvidia,tegra210-amx"; 1682 reg = <0x702d3100 0x100>; 1683 sound-name-prefix = "AMX2"; 1684 status = "disabled"; 1685 }; 1686 1687 tegra_adx1: adx@702d3800 { 1688 compatible = "nvidia,tegra210-adx"; 1689 reg = <0x702d3800 0x100>; 1690 sound-name-prefix = "ADX1"; 1691 status = "disabled"; 1692 }; 1693 1694 tegra_adx2: adx@702d3900 { 1695 compatible = "nvidia,tegra210-adx"; 1696 reg = <0x702d3900 0x100>; 1697 sound-name-prefix = "ADX2"; 1698 status = "disabled"; 1699 }; 1700 1701 tegra_dmic1: dmic@702d4000 { 1702 compatible = "nvidia,tegra210-dmic"; 1703 reg = <0x702d4000 0x100>; 1704 clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1705 clock-names = "dmic"; 1706 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC1>; 1707 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1708 assigned-clock-rates = <3072000>; 1709 sound-name-prefix = "DMIC1"; 1710 status = "disabled"; 1711 }; 1712 1713 tegra_dmic2: dmic@702d4100 { 1714 compatible = "nvidia,tegra210-dmic"; 1715 reg = <0x702d4100 0x100>; 1716 clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1717 clock-names = "dmic"; 1718 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC2>; 1719 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1720 assigned-clock-rates = <3072000>; 1721 sound-name-prefix = "DMIC2"; 1722 status = "disabled"; 1723 }; 1724 1725 tegra_dmic3: dmic@702d4200 { 1726 compatible = "nvidia,tegra210-dmic"; 1727 reg = <0x702d4200 0x100>; 1728 clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1729 clock-names = "dmic"; 1730 assigned-clocks = <&tegra_car TEGRA210_CLK_DMIC3>; 1731 assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 1732 assigned-clock-rates = <3072000>; 1733 sound-name-prefix = "DMIC3"; 1734 status = "disabled"; 1735 }; 1736 1737 tegra_ope1: processing-engine@702d8000 { 1738 compatible = "nvidia,tegra210-ope"; 1739 reg = <0x702d8000 0x100>; 1740 #address-cells = <1>; 1741 #size-cells = <1>; 1742 ranges; 1743 sound-name-prefix = "OPE1"; 1744 status = "disabled"; 1745 1746 equalizer@702d8100 { 1747 compatible = "nvidia,tegra210-peq"; 1748 reg = <0x702d8100 0x100>; 1749 }; 1750 1751 dynamic-range-compressor@702d8200 { 1752 compatible = "nvidia,tegra210-mbdrc"; 1753 reg = <0x702d8200 0x200>; 1754 }; 1755 }; 1756 1757 tegra_ope2: processing-engine@702d8400 { 1758 compatible = "nvidia,tegra210-ope"; 1759 reg = <0x702d8400 0x100>; 1760 #address-cells = <1>; 1761 #size-cells = <1>; 1762 ranges; 1763 sound-name-prefix = "OPE2"; 1764 status = "disabled"; 1765 1766 equalizer@702d8500 { 1767 compatible = "nvidia,tegra210-peq"; 1768 reg = <0x702d8500 0x100>; 1769 }; 1770 1771 dynamic-range-compressor@702d8600 { 1772 compatible = "nvidia,tegra210-mbdrc"; 1773 reg = <0x702d8600 0x200>; 1774 }; 1775 }; 1776 1777 tegra_mvc1: mvc@702da000 { 1778 compatible = "nvidia,tegra210-mvc"; 1779 reg = <0x702da000 0x200>; 1780 sound-name-prefix = "MVC1"; 1781 status = "disabled"; 1782 }; 1783 1784 tegra_mvc2: mvc@702da200 { 1785 compatible = "nvidia,tegra210-mvc"; 1786 reg = <0x702da200 0x200>; 1787 sound-name-prefix = "MVC2"; 1788 status = "disabled"; 1789 }; 1790 1791 tegra_amixer: amixer@702dbb00 { 1792 compatible = "nvidia,tegra210-amixer"; 1793 reg = <0x702dbb00 0x800>; 1794 sound-name-prefix = "MIXER1"; 1795 status = "disabled"; 1796 }; 1797 1798 ports { 1799 #address-cells = <1>; 1800 #size-cells = <0>; 1801 1802 port@0 { 1803 reg = <0x0>; 1804 1805 xbar_admaif1_ep: endpoint { 1806 remote-endpoint = <&admaif1_ep>; 1807 }; 1808 }; 1809 1810 port@1 { 1811 reg = <0x1>; 1812 1813 xbar_admaif2_ep: endpoint { 1814 remote-endpoint = <&admaif2_ep>; 1815 }; 1816 }; 1817 1818 port@2 { 1819 reg = <0x2>; 1820 1821 xbar_admaif3_ep: endpoint { 1822 remote-endpoint = <&admaif3_ep>; 1823 }; 1824 }; 1825 1826 port@3 { 1827 reg = <0x3>; 1828 1829 xbar_admaif4_ep: endpoint { 1830 remote-endpoint = <&admaif4_ep>; 1831 }; 1832 }; 1833 1834 port@4 { 1835 reg = <0x4>; 1836 xbar_admaif5_ep: endpoint { 1837 remote-endpoint = <&admaif5_ep>; 1838 }; 1839 }; 1840 port@5 { 1841 reg = <0x5>; 1842 1843 xbar_admaif6_ep: endpoint { 1844 remote-endpoint = <&admaif6_ep>; 1845 }; 1846 }; 1847 1848 port@6 { 1849 reg = <0x6>; 1850 1851 xbar_admaif7_ep: endpoint { 1852 remote-endpoint = <&admaif7_ep>; 1853 }; 1854 }; 1855 1856 port@7 { 1857 reg = <0x7>; 1858 1859 xbar_admaif8_ep: endpoint { 1860 remote-endpoint = <&admaif8_ep>; 1861 }; 1862 }; 1863 1864 port@8 { 1865 reg = <0x8>; 1866 1867 xbar_admaif9_ep: endpoint { 1868 remote-endpoint = <&admaif9_ep>; 1869 }; 1870 }; 1871 1872 port@9 { 1873 reg = <0x9>; 1874 1875 xbar_admaif10_ep: endpoint { 1876 remote-endpoint = <&admaif10_ep>; 1877 }; 1878 }; 1879 }; 1880 }; 1881 1882 adma: dma-controller@702e2000 { 1883 compatible = "nvidia,tegra210-adma"; 1884 reg = <0x702e2000 0x2000>; 1885 interrupt-parent = <&agic>; 1886 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 1887 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 1888 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 1889 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 1890 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 1891 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 1892 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1893 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1894 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1895 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1896 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1897 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1898 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1899 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1900 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1901 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1902 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1903 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1904 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1905 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1906 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1907 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1908 #dma-cells = <1>; 1909 clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>; 1910 clock-names = "d_audio"; 1911 status = "disabled"; 1912 }; 1913 1914 agic: interrupt-controller@702f9000 { 1915 compatible = "nvidia,tegra210-agic"; 1916 #interrupt-cells = <3>; 1917 interrupt-controller; 1918 reg = <0x702f9000 0x1000>, 1919 <0x702fa000 0x2000>; 1920 interrupts = <GIC_SPI 102 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 1921 clocks = <&tegra_car TEGRA210_CLK_APE>; 1922 clock-names = "clk"; 1923 status = "disabled"; 1924 }; 1925 }; 1926 1927 spi@70410000 { 1928 compatible = "nvidia,tegra210-qspi"; 1929 reg = <0x0 0x70410000 0x0 0x1000>; 1930 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1931 #address-cells = <1>; 1932 #size-cells = <0>; 1933 clocks = <&tegra_car TEGRA210_CLK_QSPI>, 1934 <&tegra_car TEGRA210_CLK_QSPI_PM>; 1935 clock-names = "qspi", "qspi_out"; 1936 resets = <&tegra_car 211>; 1937 dmas = <&apbdma 5>, <&apbdma 5>; 1938 dma-names = "rx", "tx"; 1939 status = "disabled"; 1940 }; 1941 1942 usb@7d000000 { 1943 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1944 reg = <0x0 0x7d000000 0x0 0x4000>; 1945 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1946 phy_type = "utmi"; 1947 clocks = <&tegra_car TEGRA210_CLK_USBD>; 1948 clock-names = "usb"; 1949 resets = <&tegra_car 22>; 1950 reset-names = "usb"; 1951 nvidia,phy = <&phy1>; 1952 status = "disabled"; 1953 }; 1954 1955 phy1: usb-phy@7d000000 { 1956 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1957 reg = <0x0 0x7d000000 0x0 0x4000>, 1958 <0x0 0x7d000000 0x0 0x4000>; 1959 phy_type = "utmi"; 1960 clocks = <&tegra_car TEGRA210_CLK_USBD>, 1961 <&tegra_car TEGRA210_CLK_PLL_U>, 1962 <&tegra_car TEGRA210_CLK_USBD>; 1963 clock-names = "reg", "pll_u", "utmi-pads"; 1964 resets = <&tegra_car 22>, <&tegra_car 22>; 1965 reset-names = "usb", "utmi-pads"; 1966 nvidia,hssync-start-delay = <0>; 1967 nvidia,idle-wait-delay = <17>; 1968 nvidia,elastic-limit = <16>; 1969 nvidia,term-range-adj = <6>; 1970 nvidia,xcvr-setup = <9>; 1971 nvidia,xcvr-lsfslew = <0>; 1972 nvidia,xcvr-lsrslew = <3>; 1973 nvidia,hssquelch-level = <2>; 1974 nvidia,hsdiscon-level = <5>; 1975 nvidia,xcvr-hsslew = <12>; 1976 nvidia,has-utmi-pad-registers; 1977 status = "disabled"; 1978 }; 1979 1980 usb@7d004000 { 1981 compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci"; 1982 reg = <0x0 0x7d004000 0x0 0x4000>; 1983 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1984 phy_type = "utmi"; 1985 clocks = <&tegra_car TEGRA210_CLK_USB2>; 1986 clock-names = "usb"; 1987 resets = <&tegra_car 58>; 1988 reset-names = "usb"; 1989 nvidia,phy = <&phy2>; 1990 status = "disabled"; 1991 }; 1992 1993 phy2: usb-phy@7d004000 { 1994 compatible = "nvidia,tegra210-usb-phy", "nvidia,tegra30-usb-phy"; 1995 reg = <0x0 0x7d004000 0x0 0x4000>, 1996 <0x0 0x7d000000 0x0 0x4000>; 1997 phy_type = "utmi"; 1998 clocks = <&tegra_car TEGRA210_CLK_USB2>, 1999 <&tegra_car TEGRA210_CLK_PLL_U>, 2000 <&tegra_car TEGRA210_CLK_USBD>; 2001 clock-names = "reg", "pll_u", "utmi-pads"; 2002 resets = <&tegra_car 58>, <&tegra_car 22>; 2003 reset-names = "usb", "utmi-pads"; 2004 nvidia,hssync-start-delay = <0>; 2005 nvidia,idle-wait-delay = <17>; 2006 nvidia,elastic-limit = <16>; 2007 nvidia,term-range-adj = <6>; 2008 nvidia,xcvr-setup = <9>; 2009 nvidia,xcvr-lsfslew = <0>; 2010 nvidia,xcvr-lsrslew = <3>; 2011 nvidia,hssquelch-level = <2>; 2012 nvidia,hsdiscon-level = <5>; 2013 nvidia,xcvr-hsslew = <12>; 2014 status = "disabled"; 2015 }; 2016 2017 cpus { 2018 #address-cells = <1>; 2019 #size-cells = <0>; 2020 2021 cpu@0 { 2022 device_type = "cpu"; 2023 compatible = "arm,cortex-a57"; 2024 reg = <0>; 2025 clocks = <&tegra_car TEGRA210_CLK_CCLK_G>, 2026 <&tegra_car TEGRA210_CLK_PLL_X>, 2027 <&tegra_car TEGRA210_CLK_PLL_P_OUT4>, 2028 <&dfll>; 2029 clock-names = "cpu_g", "pll_x", "pll_p", "dfll"; 2030 clock-latency = <300000>; 2031 cpu-idle-states = <&CPU_SLEEP>; 2032 next-level-cache = <&L2>; 2033 }; 2034 2035 cpu@1 { 2036 device_type = "cpu"; 2037 compatible = "arm,cortex-a57"; 2038 reg = <1>; 2039 cpu-idle-states = <&CPU_SLEEP>; 2040 next-level-cache = <&L2>; 2041 }; 2042 2043 cpu@2 { 2044 device_type = "cpu"; 2045 compatible = "arm,cortex-a57"; 2046 reg = <2>; 2047 cpu-idle-states = <&CPU_SLEEP>; 2048 next-level-cache = <&L2>; 2049 }; 2050 2051 cpu@3 { 2052 device_type = "cpu"; 2053 compatible = "arm,cortex-a57"; 2054 reg = <3>; 2055 cpu-idle-states = <&CPU_SLEEP>; 2056 next-level-cache = <&L2>; 2057 }; 2058 2059 idle-states { 2060 entry-method = "psci"; 2061 2062 CPU_SLEEP: cpu-sleep { 2063 compatible = "arm,idle-state"; 2064 arm,psci-suspend-param = <0x40000007>; 2065 entry-latency-us = <100>; 2066 exit-latency-us = <30>; 2067 min-residency-us = <1000>; 2068 wakeup-latency-us = <130>; 2069 idle-state-name = "cpu-sleep"; 2070 status = "disabled"; 2071 }; 2072 }; 2073 2074 L2: l2-cache { 2075 compatible = "cache"; 2076 cache-level = <2>; 2077 cache-unified; 2078 }; 2079 }; 2080 2081 pmu { 2082 compatible = "arm,cortex-a57-pmu"; 2083 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2084 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2085 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2086 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2087 interrupt-affinity = <&{/cpus/cpu@0} &{/cpus/cpu@1} 2088 &{/cpus/cpu@2} &{/cpus/cpu@3}>; 2089 }; 2090 2091 sound { 2092 status = "disabled"; 2093 2094 clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2095 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2096 clock-names = "pll_a", "plla_out0"; 2097 2098 assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>, 2099 <&tegra_car TEGRA210_CLK_PLL_A_OUT0>, 2100 <&tegra_car TEGRA210_CLK_EXTERN1>; 2101 assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>; 2102 assigned-clock-rates = <368640000>, <49152000>, <12288000>; 2103 }; 2104 2105 thermal-zones { 2106 cpu-thermal { 2107 polling-delay-passive = <1000>; 2108 polling-delay = <0>; 2109 2110 thermal-sensors = 2111 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 2112 2113 trips { 2114 cpu-shutdown-trip { 2115 temperature = <102500>; 2116 hysteresis = <0>; 2117 type = "critical"; 2118 }; 2119 2120 cpu_throttle_trip: throttle-trip { 2121 temperature = <98500>; 2122 hysteresis = <1000>; 2123 type = "hot"; 2124 }; 2125 }; 2126 2127 cooling-maps { 2128 map0 { 2129 trip = <&cpu_throttle_trip>; 2130 cooling-device = <&throttle_heavy 1 1>; 2131 }; 2132 }; 2133 }; 2134 2135 mem-thermal { 2136 polling-delay-passive = <0>; 2137 polling-delay = <0>; 2138 2139 thermal-sensors = 2140 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 2141 2142 trips { 2143 dram_nominal: mem-nominal-trip { 2144 temperature = <50000>; 2145 hysteresis = <1000>; 2146 type = "passive"; 2147 }; 2148 2149 dram_throttle: mem-throttle-trip { 2150 temperature = <70000>; 2151 hysteresis = <1000>; 2152 type = "active"; 2153 }; 2154 2155 mem-hot-trip { 2156 temperature = <100000>; 2157 hysteresis = <1000>; 2158 type = "hot"; 2159 }; 2160 2161 mem-shutdown-trip { 2162 temperature = <103000>; 2163 hysteresis = <0>; 2164 type = "critical"; 2165 }; 2166 }; 2167 2168 cooling-maps { 2169 dram-passive { 2170 cooling-device = <&emc 0 0>; 2171 trip = <&dram_nominal>; 2172 }; 2173 2174 dram-active { 2175 cooling-device = <&emc 1 1>; 2176 trip = <&dram_throttle>; 2177 }; 2178 }; 2179 }; 2180 2181 gpu-thermal { 2182 polling-delay-passive = <1000>; 2183 polling-delay = <0>; 2184 2185 thermal-sensors = 2186 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 2187 2188 trips { 2189 gpu-shutdown-trip { 2190 temperature = <103000>; 2191 hysteresis = <0>; 2192 type = "critical"; 2193 }; 2194 2195 gpu_throttle_trip: throttle-trip { 2196 temperature = <100000>; 2197 hysteresis = <1000>; 2198 type = "hot"; 2199 }; 2200 }; 2201 2202 cooling-maps { 2203 map0 { 2204 trip = <&gpu_throttle_trip>; 2205 cooling-device = <&throttle_heavy 1 1>; 2206 }; 2207 }; 2208 }; 2209 2210 pllx-thermal { 2211 polling-delay-passive = <0>; 2212 polling-delay = <0>; 2213 2214 thermal-sensors = 2215 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 2216 2217 trips { 2218 pllx-shutdown-trip { 2219 temperature = <103000>; 2220 hysteresis = <0>; 2221 type = "critical"; 2222 }; 2223 2224 pllx-throttle-trip { 2225 temperature = <100000>; 2226 hysteresis = <1000>; 2227 type = "hot"; 2228 }; 2229 }; 2230 2231 cooling-maps { 2232 /* 2233 * There are currently no cooling maps, 2234 * because there are no cooling devices. 2235 */ 2236 }; 2237 }; 2238 }; 2239 2240 timer { 2241 compatible = "arm,armv8-timer"; 2242 interrupts = <GIC_PPI 13 2243 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2244 <GIC_PPI 14 2245 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2246 <GIC_PPI 11 2247 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 2248 <GIC_PPI 10 2249 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 2250 interrupt-parent = <&gic>; 2251 arm,no-tick-in-suspend; 2252 }; 2253};
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