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tegra132.dtsi
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linux-6.19.14/arch/arm64/boot/dts/nvidia/tegra132.dtsi
1// SPDX-License-Identifier: GPL-2.0 2#include <dt-bindings/clock/tegra124-car.h> 3#include <dt-bindings/gpio/tegra-gpio.h> 4#include <dt-bindings/memory/tegra124-mc.h> 5#include <dt-bindings/pinctrl/pinctrl-tegra.h> 6#include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h> 7#include <dt-bindings/interrupt-controller/arm-gic.h> 8#include <dt-bindings/thermal/tegra124-soctherm.h> 9#include <dt-bindings/soc/tegra-pmc.h> 10 11#include "tegra132-peripherals-opp.dtsi" 12 13/ { 14 compatible = "nvidia,tegra132", "nvidia,tegra124"; 15 interrupt-parent = <&lic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 pcie@1003000 { 20 compatible = "nvidia,tegra124-pcie"; 21 device_type = "pci"; 22 reg = <0x0 0x01003000 0x0 0x00000800>, /* PADS registers */ 23 <0x0 0x01003800 0x0 0x00000800>, /* AFI registers */ 24 <0x0 0x02000000 0x0 0x10000000>; /* configuration space */ 25 reg-names = "pads", "afi", "cs"; 26 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 27 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 28 interrupt-names = "intr", "msi"; 29 30 #interrupt-cells = <1>; 31 interrupt-map-mask = <0 0 0 0>; 32 interrupt-map = <0 0 0 0 &gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 33 34 bus-range = <0x00 0xff>; 35 #address-cells = <3>; 36 #size-cells = <2>; 37 38 ranges = <0x02000000 0 0x01000000 0x0 0x01000000 0 0x00001000>, /* port 0 configuration space */ 39 <0x02000000 0 0x01001000 0x0 0x01001000 0 0x00001000>, /* port 1 configuration space */ 40 <0x01000000 0 0x0 0x0 0x12000000 0 0x00010000>, /* downstream I/O (64 KiB) */ 41 <0x02000000 0 0x13000000 0x0 0x13000000 0 0x0d000000>, /* non-prefetchable memory (208 MiB) */ 42 <0x42000000 0 0x20000000 0x0 0x20000000 0 0x20000000>; /* prefetchable memory (512 MiB) */ 43 44 clocks = <&tegra_car TEGRA124_CLK_PCIE>, 45 <&tegra_car TEGRA124_CLK_AFI>, 46 <&tegra_car TEGRA124_CLK_PLL_E>, 47 <&tegra_car TEGRA124_CLK_CML0>; 48 clock-names = "pex", "afi", "pll_e", "cml"; 49 resets = <&tegra_car 70>, 50 <&tegra_car 72>, 51 <&tegra_car 74>; 52 reset-names = "pex", "afi", "pcie_x"; 53 status = "disabled"; 54 55 pci@1,0 { 56 device_type = "pci"; 57 assigned-addresses = <0x82000800 0 0x01000000 0 0x1000>; 58 reg = <0x000800 0 0 0 0>; 59 bus-range = <0x00 0xff>; 60 status = "disabled"; 61 62 #address-cells = <3>; 63 #size-cells = <2>; 64 ranges; 65 66 nvidia,num-lanes = <2>; 67 }; 68 69 pci@2,0 { 70 device_type = "pci"; 71 assigned-addresses = <0x82001000 0 0x01001000 0 0x1000>; 72 reg = <0x001000 0 0 0 0>; 73 bus-range = <0x00 0xff>; 74 status = "disabled"; 75 76 #address-cells = <3>; 77 #size-cells = <2>; 78 ranges; 79 80 nvidia,num-lanes = <1>; 81 }; 82 }; 83 84 host1x@50000000 { 85 compatible = "nvidia,tegra132-host1x", 86 "nvidia,tegra124-host1x"; 87 reg = <0x0 0x50000000 0x0 0x00034000>; 88 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ 89 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ 90 interrupt-names = "syncpt", "host1x"; 91 clocks = <&tegra_car TEGRA124_CLK_HOST1X>; 92 clock-names = "host1x"; 93 resets = <&tegra_car 28>; 94 reset-names = "host1x"; 95 96 iommus = <&mc TEGRA_SWGROUP_HC>; 97 98 #address-cells = <2>; 99 #size-cells = <2>; 100 101 ranges = <0 0x54000000 0 0x54000000 0 0x01000000>; 102 103 dc@54200000 { 104 compatible = "nvidia,tegra124-dc"; 105 reg = <0x0 0x54200000 0x0 0x00040000>; 106 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 107 clocks = <&tegra_car TEGRA124_CLK_DISP1>; 108 clock-names = "dc"; 109 resets = <&tegra_car 27>; 110 reset-names = "dc"; 111 112 iommus = <&mc TEGRA_SWGROUP_DC>; 113 114 nvidia,head = <0>; 115 }; 116 117 dc@54240000 { 118 compatible = "nvidia,tegra124-dc"; 119 reg = <0x0 0x54240000 0x0 0x00040000>; 120 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&tegra_car TEGRA124_CLK_DISP2>; 122 clock-names = "dc"; 123 resets = <&tegra_car 26>; 124 reset-names = "dc"; 125 126 iommus = <&mc TEGRA_SWGROUP_DCB>; 127 128 nvidia,head = <1>; 129 }; 130 131 hdmi@54280000 { 132 compatible = "nvidia,tegra124-hdmi"; 133 reg = <0x0 0x54280000 0x0 0x00040000>; 134 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 135 clocks = <&tegra_car TEGRA124_CLK_HDMI>, 136 <&tegra_car TEGRA124_CLK_PLL_D2_OUT0>; 137 clock-names = "hdmi", "parent"; 138 resets = <&tegra_car 51>; 139 reset-names = "hdmi"; 140 status = "disabled"; 141 }; 142 143 sor@54540000 { 144 compatible = "nvidia,tegra124-sor"; 145 reg = <0x0 0x54540000 0x0 0x00040000>; 146 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 147 clocks = <&tegra_car TEGRA124_CLK_SOR0>, 148 <&tegra_car TEGRA124_CLK_SOR0_OUT>, 149 <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, 150 <&tegra_car TEGRA124_CLK_PLL_DP>, 151 <&tegra_car TEGRA124_CLK_CLK_M>; 152 clock-names = "sor", "out", "parent", "dp", "safe"; 153 resets = <&tegra_car 182>; 154 reset-names = "sor"; 155 status = "disabled"; 156 }; 157 158 dpaux: dpaux@545c0000 { 159 compatible = "nvidia,tegra124-dpaux"; 160 reg = <0x0 0x545c0000 0x0 0x00040000>; 161 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 162 clocks = <&tegra_car TEGRA124_CLK_DPAUX>, 163 <&tegra_car TEGRA124_CLK_PLL_DP>; 164 clock-names = "dpaux", "parent"; 165 resets = <&tegra_car 181>; 166 reset-names = "dpaux"; 167 status = "disabled"; 168 169 i2c-bus { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 }; 173 }; 174 }; 175 176 gic: interrupt-controller@50041000 { 177 compatible = "arm,cortex-a15-gic"; 178 #address-cells = <0>; 179 #interrupt-cells = <3>; 180 interrupt-controller; 181 reg = <0x0 0x50041000 0x0 0x1000>, 182 <0x0 0x50042000 0x0 0x2000>, 183 <0x0 0x50044000 0x0 0x2000>, 184 <0x0 0x50046000 0x0 0x2000>; 185 interrupts = <GIC_PPI 9 186 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 187 interrupt-parent = <&gic>; 188 }; 189 190 gpu@57000000 { 191 compatible = "nvidia,gk20a"; 192 reg = <0x0 0x57000000 0x0 0x01000000>, 193 <0x0 0x58000000 0x0 0x01000000>; 194 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 196 interrupt-names = "stall", "nonstall"; 197 clocks = <&tegra_car TEGRA124_CLK_GPU>, 198 <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; 199 clock-names = "gpu", "pwr"; 200 resets = <&tegra_car 184>; 201 reset-names = "gpu"; 202 status = "disabled"; 203 }; 204 205 lic: interrupt-controller@60004000 { 206 compatible = "nvidia,tegra124-ictlr", "nvidia,tegra30-ictlr"; 207 reg = <0x0 0x60004000 0x0 0x100>, 208 <0x0 0x60004100 0x0 0x100>, 209 <0x0 0x60004200 0x0 0x100>, 210 <0x0 0x60004300 0x0 0x100>, 211 <0x0 0x60004400 0x0 0x100>; 212 interrupt-controller; 213 #interrupt-cells = <3>; 214 interrupt-parent = <&gic>; 215 }; 216 217 timer@60005000 { 218 compatible = "nvidia,tegra124-timer", "nvidia,tegra30-timer"; 219 reg = <0x0 0x60005000 0x0 0x400>; 220 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 221 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 222 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 224 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 225 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 226 clocks = <&tegra_car TEGRA124_CLK_TIMER>; 227 clock-names = "timer"; 228 }; 229 230 tegra_car: clock@60006000 { 231 compatible = "nvidia,tegra132-car"; 232 reg = <0x0 0x60006000 0x0 0x1000>; 233 #clock-cells = <1>; 234 #reset-cells = <1>; 235 nvidia,external-memory-controller = <&emc>; 236 }; 237 238 flow-controller@60007000 { 239 compatible = "nvidia,tegra132-flowctrl", "nvidia,tegra124-flowctrl"; 240 reg = <0x0 0x60007000 0x0 0x1000>; 241 }; 242 243 actmon@6000c800 { 244 compatible = "nvidia,tegra124-actmon"; 245 reg = <0x0 0x6000c800 0x0 0x400>; 246 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 247 clocks = <&tegra_car TEGRA124_CLK_ACTMON>, 248 <&tegra_car TEGRA124_CLK_EMC>; 249 clock-names = "actmon", "emc"; 250 resets = <&tegra_car 119>; 251 reset-names = "actmon"; 252 operating-points-v2 = <&emc_bw_dfs_opp_table>; 253 interconnects = <&mc TEGRA124_MC_MPCORER &emc>; 254 interconnect-names = "cpu-read"; 255 #cooling-cells = <2>; 256 }; 257 258 gpio: gpio@6000d000 { 259 compatible = "nvidia,tegra124-gpio", "nvidia,tegra30-gpio"; 260 reg = <0x0 0x6000d000 0x0 0x1000>; 261 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 265 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 266 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, 267 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, 268 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 269 #gpio-cells = <2>; 270 gpio-controller; 271 #interrupt-cells = <2>; 272 interrupt-controller; 273 }; 274 275 apbdma: dma-controller@60020000 { 276 compatible = "nvidia,tegra124-apbdma", "nvidia,tegra148-apbdma"; 277 reg = <0x0 0x60020000 0x0 0x1400>; 278 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 283 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 284 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 285 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 286 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 287 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 288 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 289 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 290 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 291 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 292 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 293 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 294 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 308 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 309 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 310 clocks = <&tegra_car TEGRA124_CLK_APBDMA>; 311 clock-names = "dma"; 312 resets = <&tegra_car 34>; 313 reset-names = "dma"; 314 #dma-cells = <1>; 315 }; 316 317 apbmisc@70000800 { 318 compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; 319 reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ 320 <0x0 0x7000e864 0x0 0x04>; /* Strapping options */ 321 }; 322 323 pinmux: pinmux@70000868 { 324 compatible = "nvidia,tegra124-pinmux"; 325 reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ 326 <0x0 0x70003000 0x0 0x434>, /* Mux registers */ 327 <0x0 0x70000820 0x0 0x008>; /* MIPI pad control */ 328 }; 329 330 /* 331 * There are two serial driver i.e. 8250 based simple serial 332 * driver and APB DMA based serial driver for higher baudrate 333 * and performance. To enable the 8250 based driver, the compatible 334 * is "nvidia,tegra124-uart", "nvidia,tegra20-uart" and to enable 335 * the APB DMA based serial driver, the compatible is 336 * "nvidia,tegra124-hsuart", "nvidia,tegra30-hsuart". 337 */ 338 uarta: serial@70006000 { 339 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 340 reg = <0x0 0x70006000 0x0 0x40>; 341 reg-shift = <2>; 342 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 343 clocks = <&tegra_car TEGRA124_CLK_UARTA>; 344 resets = <&tegra_car 6>; 345 dmas = <&apbdma 8>, <&apbdma 8>; 346 dma-names = "rx", "tx"; 347 status = "disabled"; 348 }; 349 350 uartb: serial@70006040 { 351 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 352 reg = <0x0 0x70006040 0x0 0x40>; 353 reg-shift = <2>; 354 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&tegra_car TEGRA124_CLK_UARTB>; 356 resets = <&tegra_car 7>; 357 dmas = <&apbdma 9>, <&apbdma 9>; 358 dma-names = "rx", "tx"; 359 status = "disabled"; 360 }; 361 362 uartc: serial@70006200 { 363 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 364 reg = <0x0 0x70006200 0x0 0x40>; 365 reg-shift = <2>; 366 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&tegra_car TEGRA124_CLK_UARTC>; 368 resets = <&tegra_car 55>; 369 dmas = <&apbdma 10>, <&apbdma 10>; 370 dma-names = "rx", "tx"; 371 status = "disabled"; 372 }; 373 374 uartd: serial@70006300 { 375 compatible = "nvidia,tegra124-uart", "nvidia,tegra20-uart"; 376 reg = <0x0 0x70006300 0x0 0x40>; 377 reg-shift = <2>; 378 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&tegra_car TEGRA124_CLK_UARTD>; 380 resets = <&tegra_car 65>; 381 dmas = <&apbdma 19>, <&apbdma 19>; 382 dma-names = "rx", "tx"; 383 status = "disabled"; 384 }; 385 386 pwm: pwm@7000a000 { 387 compatible = "nvidia,tegra124-pwm", "nvidia,tegra20-pwm"; 388 reg = <0x0 0x7000a000 0x0 0x100>; 389 #pwm-cells = <2>; 390 clocks = <&tegra_car TEGRA124_CLK_PWM>; 391 resets = <&tegra_car 17>; 392 reset-names = "pwm"; 393 status = "disabled"; 394 }; 395 396 i2c@7000c000 { 397 compatible = "nvidia,tegra124-i2c"; 398 reg = <0x0 0x7000c000 0x0 0x100>; 399 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 clocks = <&tegra_car TEGRA124_CLK_I2C1>; 403 clock-names = "div-clk"; 404 resets = <&tegra_car 12>; 405 reset-names = "i2c"; 406 dmas = <&apbdma 21>, <&apbdma 21>; 407 dma-names = "rx", "tx"; 408 status = "disabled"; 409 }; 410 411 i2c@7000c400 { 412 compatible = "nvidia,tegra124-i2c"; 413 reg = <0x0 0x7000c400 0x0 0x100>; 414 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 415 #address-cells = <1>; 416 #size-cells = <0>; 417 clocks = <&tegra_car TEGRA124_CLK_I2C2>; 418 clock-names = "div-clk"; 419 resets = <&tegra_car 54>; 420 reset-names = "i2c"; 421 dmas = <&apbdma 22>, <&apbdma 22>; 422 dma-names = "rx", "tx"; 423 status = "disabled"; 424 }; 425 426 i2c@7000c500 { 427 compatible = "nvidia,tegra124-i2c"; 428 reg = <0x0 0x7000c500 0x0 0x100>; 429 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 430 #address-cells = <1>; 431 #size-cells = <0>; 432 clocks = <&tegra_car TEGRA124_CLK_I2C3>; 433 clock-names = "div-clk"; 434 resets = <&tegra_car 67>; 435 reset-names = "i2c"; 436 dmas = <&apbdma 23>, <&apbdma 23>; 437 dma-names = "rx", "tx"; 438 status = "disabled"; 439 }; 440 441 i2c@7000c700 { 442 compatible = "nvidia,tegra124-i2c"; 443 reg = <0x0 0x7000c700 0x0 0x100>; 444 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 445 #address-cells = <1>; 446 #size-cells = <0>; 447 clocks = <&tegra_car TEGRA124_CLK_I2C4>; 448 clock-names = "div-clk"; 449 resets = <&tegra_car 103>; 450 reset-names = "i2c"; 451 dmas = <&apbdma 26>, <&apbdma 26>; 452 dma-names = "rx", "tx"; 453 status = "disabled"; 454 }; 455 456 i2c@7000d000 { 457 compatible = "nvidia,tegra124-i2c"; 458 reg = <0x0 0x7000d000 0x0 0x100>; 459 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 clocks = <&tegra_car TEGRA124_CLK_I2C5>; 463 clock-names = "div-clk"; 464 resets = <&tegra_car 47>; 465 reset-names = "i2c"; 466 dmas = <&apbdma 24>, <&apbdma 24>; 467 dma-names = "rx", "tx"; 468 status = "disabled"; 469 }; 470 471 i2c@7000d100 { 472 compatible = "nvidia,tegra124-i2c"; 473 reg = <0x0 0x7000d100 0x0 0x100>; 474 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 475 #address-cells = <1>; 476 #size-cells = <0>; 477 clocks = <&tegra_car TEGRA124_CLK_I2C6>; 478 clock-names = "div-clk"; 479 resets = <&tegra_car 166>; 480 reset-names = "i2c"; 481 dmas = <&apbdma 30>, <&apbdma 30>; 482 dma-names = "rx", "tx"; 483 status = "disabled"; 484 }; 485 486 spi@7000d400 { 487 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 488 reg = <0x0 0x7000d400 0x0 0x200>; 489 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 490 #address-cells = <1>; 491 #size-cells = <0>; 492 clocks = <&tegra_car TEGRA124_CLK_SBC1>; 493 clock-names = "spi"; 494 resets = <&tegra_car 41>; 495 reset-names = "spi"; 496 dmas = <&apbdma 15>, <&apbdma 15>; 497 dma-names = "rx", "tx"; 498 status = "disabled"; 499 }; 500 501 spi@7000d600 { 502 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 503 reg = <0x0 0x7000d600 0x0 0x200>; 504 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 505 #address-cells = <1>; 506 #size-cells = <0>; 507 clocks = <&tegra_car TEGRA124_CLK_SBC2>; 508 clock-names = "spi"; 509 resets = <&tegra_car 44>; 510 reset-names = "spi"; 511 dmas = <&apbdma 16>, <&apbdma 16>; 512 dma-names = "rx", "tx"; 513 status = "disabled"; 514 }; 515 516 spi@7000d800 { 517 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 518 reg = <0x0 0x7000d800 0x0 0x200>; 519 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 520 #address-cells = <1>; 521 #size-cells = <0>; 522 clocks = <&tegra_car TEGRA124_CLK_SBC3>; 523 clock-names = "spi"; 524 resets = <&tegra_car 46>; 525 reset-names = "spi"; 526 dmas = <&apbdma 17>, <&apbdma 17>; 527 dma-names = "rx", "tx"; 528 status = "disabled"; 529 }; 530 531 spi@7000da00 { 532 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 533 reg = <0x0 0x7000da00 0x0 0x200>; 534 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 535 #address-cells = <1>; 536 #size-cells = <0>; 537 clocks = <&tegra_car TEGRA124_CLK_SBC4>; 538 clock-names = "spi"; 539 resets = <&tegra_car 68>; 540 reset-names = "spi"; 541 dmas = <&apbdma 18>, <&apbdma 18>; 542 dma-names = "rx", "tx"; 543 status = "disabled"; 544 }; 545 546 spi@7000dc00 { 547 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 548 reg = <0x0 0x7000dc00 0x0 0x200>; 549 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 550 #address-cells = <1>; 551 #size-cells = <0>; 552 clocks = <&tegra_car TEGRA124_CLK_SBC5>; 553 clock-names = "spi"; 554 resets = <&tegra_car 104>; 555 reset-names = "spi"; 556 dmas = <&apbdma 27>, <&apbdma 27>; 557 dma-names = "rx", "tx"; 558 status = "disabled"; 559 }; 560 561 spi@7000de00 { 562 compatible = "nvidia,tegra124-spi", "nvidia,tegra114-spi"; 563 reg = <0x0 0x7000de00 0x0 0x200>; 564 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 565 #address-cells = <1>; 566 #size-cells = <0>; 567 clocks = <&tegra_car TEGRA124_CLK_SBC6>; 568 clock-names = "spi"; 569 resets = <&tegra_car 105>; 570 reset-names = "spi"; 571 dmas = <&apbdma 28>, <&apbdma 28>; 572 dma-names = "rx", "tx"; 573 status = "disabled"; 574 }; 575 576 tegra_rtc: rtc@7000e000 { 577 compatible = "nvidia,tegra124-rtc", "nvidia,tegra20-rtc"; 578 reg = <0x0 0x7000e000 0x0 0x100>; 579 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&tegra_car TEGRA124_CLK_RTC>; 581 clock-names = "rtc"; 582 }; 583 584 tegra_pmc: pmc@7000e400 { 585 compatible = "nvidia,tegra124-pmc"; 586 reg = <0x0 0x7000e400 0x0 0x400>; 587 clocks = <&tegra_car TEGRA124_CLK_PCLK>, <&clk32k_in>; 588 clock-names = "pclk", "clk32k_in"; 589 #clock-cells = <1>; 590 }; 591 592 fuse@7000f800 { 593 compatible = "nvidia,tegra124-efuse"; 594 reg = <0x0 0x7000f800 0x0 0x400>; 595 clocks = <&tegra_car TEGRA124_CLK_FUSE>; 596 clock-names = "fuse"; 597 resets = <&tegra_car 39>; 598 reset-names = "fuse"; 599 }; 600 601 mc: memory-controller@70019000 { 602 compatible = "nvidia,tegra132-mc"; 603 reg = <0x0 0x70019000 0x0 0x1000>; 604 clocks = <&tegra_car TEGRA124_CLK_MC>; 605 clock-names = "mc"; 606 607 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 608 609 #iommu-cells = <1>; 610 #reset-cells = <1>; 611 #interconnect-cells = <1>; 612 }; 613 614 emc: external-memory-controller@7001b000 { 615 compatible = "nvidia,tegra132-emc", "nvidia,tegra124-emc"; 616 reg = <0x0 0x7001b000 0x0 0x1000>; 617 clocks = <&tegra_car TEGRA124_CLK_EMC>; 618 clock-names = "emc"; 619 620 nvidia,memory-controller = <&mc>; 621 operating-points-v2 = <&emc_icc_dvfs_opp_table>; 622 623 #interconnect-cells = <0>; 624 }; 625 626 sata@70020000 { 627 compatible = "nvidia,tegra124-ahci"; 628 reg = <0x0 0x70027000 0x0 0x2000>, /* AHCI */ 629 <0x0 0x70020000 0x0 0x7000>; /* SATA */ 630 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&tegra_car TEGRA124_CLK_SATA>, 632 <&tegra_car TEGRA124_CLK_SATA_OOB>; 633 clock-names = "sata", "sata-oob"; 634 resets = <&tegra_car 124>, 635 <&tegra_car 129>, 636 <&tegra_car 123>; 637 reset-names = "sata", "sata-cold", "sata-oob"; 638 status = "disabled"; 639 }; 640 641 hda@70030000 { 642 compatible = "nvidia,tegra132-hda", "nvidia,tegra124-hda", 643 "nvidia,tegra30-hda"; 644 reg = <0x0 0x70030000 0x0 0x10000>; 645 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 646 clocks = <&tegra_car TEGRA124_CLK_HDA>, 647 <&tegra_car TEGRA124_CLK_HDA2HDMI>, 648 <&tegra_car TEGRA124_CLK_HDA2CODEC_2X>; 649 clock-names = "hda", "hda2hdmi", "hda2codec_2x"; 650 resets = <&tegra_car 125>, /* hda */ 651 <&tegra_car 128>, /* hda2hdmi */ 652 <&tegra_car 111>; /* hda2codec_2x */ 653 reset-names = "hda", "hda2hdmi", "hda2codec_2x"; 654 status = "disabled"; 655 }; 656 657 usb@70090000 { 658 compatible = "nvidia,tegra132-xusb", "nvidia,tegra124-xusb"; 659 reg = <0x0 0x70090000 0x0 0x8000>, 660 <0x0 0x70098000 0x0 0x1000>, 661 <0x0 0x70099000 0x0 0x1000>; 662 reg-names = "hcd", "fpci", "ipfs"; 663 664 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 666 667 clocks = <&tegra_car TEGRA124_CLK_XUSB_HOST>, 668 <&tegra_car TEGRA124_CLK_XUSB_HOST_SRC>, 669 <&tegra_car TEGRA124_CLK_XUSB_FALCON_SRC>, 670 <&tegra_car TEGRA124_CLK_XUSB_SS>, 671 <&tegra_car TEGRA124_CLK_XUSB_SS_DIV2>, 672 <&tegra_car TEGRA124_CLK_XUSB_SS_SRC>, 673 <&tegra_car TEGRA124_CLK_XUSB_HS_SRC>, 674 <&tegra_car TEGRA124_CLK_XUSB_FS_SRC>, 675 <&tegra_car TEGRA124_CLK_PLL_U_480M>, 676 <&tegra_car TEGRA124_CLK_CLK_M>, 677 <&tegra_car TEGRA124_CLK_PLL_E>; 678 clock-names = "xusb_host", "xusb_host_src", 679 "xusb_falcon_src", "xusb_ss", 680 "xusb_ss_div2", "xusb_ss_src", 681 "xusb_hs_src", "xusb_fs_src", 682 "pll_u_480m", "clk_m", "pll_e"; 683 resets = <&tegra_car 89>, <&tegra_car 156>, 684 <&tegra_car 143>; 685 reset-names = "xusb_host", "xusb_ss", "xusb_src"; 686 687 nvidia,xusb-padctl = <&padctl>; 688 689 status = "disabled"; 690 }; 691 692 padctl: padctl@7009f000 { 693 compatible = "nvidia,tegra132-xusb-padctl", 694 "nvidia,tegra124-xusb-padctl"; 695 reg = <0x0 0x7009f000 0x0 0x1000>; 696 resets = <&tegra_car 142>; 697 reset-names = "padctl"; 698 699 pads { 700 usb2 { 701 status = "disabled"; 702 703 lanes { 704 usb2-0 { 705 status = "disabled"; 706 #phy-cells = <0>; 707 }; 708 709 usb2-1 { 710 status = "disabled"; 711 #phy-cells = <0>; 712 }; 713 714 usb2-2 { 715 status = "disabled"; 716 #phy-cells = <0>; 717 }; 718 }; 719 }; 720 721 ulpi { 722 status = "disabled"; 723 724 lanes { 725 ulpi-0 { 726 status = "disabled"; 727 #phy-cells = <0>; 728 }; 729 }; 730 }; 731 732 hsic { 733 status = "disabled"; 734 735 lanes { 736 hsic-0 { 737 status = "disabled"; 738 #phy-cells = <0>; 739 }; 740 741 hsic-1 { 742 status = "disabled"; 743 #phy-cells = <0>; 744 }; 745 }; 746 }; 747 748 pcie { 749 status = "disabled"; 750 751 lanes { 752 pcie-0 { 753 status = "disabled"; 754 #phy-cells = <0>; 755 }; 756 757 pcie-1 { 758 status = "disabled"; 759 #phy-cells = <0>; 760 }; 761 762 pcie-2 { 763 status = "disabled"; 764 #phy-cells = <0>; 765 }; 766 767 pcie-3 { 768 status = "disabled"; 769 #phy-cells = <0>; 770 }; 771 772 pcie-4 { 773 status = "disabled"; 774 #phy-cells = <0>; 775 }; 776 }; 777 }; 778 779 sata { 780 status = "disabled"; 781 782 lanes { 783 sata-0 { 784 status = "disabled"; 785 #phy-cells = <0>; 786 }; 787 }; 788 }; 789 }; 790 791 ports { 792 usb2-0 { 793 status = "disabled"; 794 }; 795 796 usb2-1 { 797 status = "disabled"; 798 }; 799 800 usb2-2 { 801 status = "disabled"; 802 }; 803 804 hsic-0 { 805 status = "disabled"; 806 }; 807 808 hsic-1 { 809 status = "disabled"; 810 }; 811 812 usb3-0 { 813 status = "disabled"; 814 }; 815 816 usb3-1 { 817 status = "disabled"; 818 }; 819 }; 820 }; 821 822 mmc@700b0000 { 823 compatible = "nvidia,tegra124-sdhci"; 824 reg = <0x0 0x700b0000 0x0 0x200>; 825 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 826 clocks = <&tegra_car TEGRA124_CLK_SDMMC1>; 827 clock-names = "sdhci"; 828 resets = <&tegra_car 14>; 829 reset-names = "sdhci"; 830 status = "disabled"; 831 }; 832 833 mmc@700b0200 { 834 compatible = "nvidia,tegra124-sdhci"; 835 reg = <0x0 0x700b0200 0x0 0x200>; 836 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&tegra_car TEGRA124_CLK_SDMMC2>; 838 clock-names = "sdhci"; 839 resets = <&tegra_car 9>; 840 reset-names = "sdhci"; 841 status = "disabled"; 842 }; 843 844 mmc@700b0400 { 845 compatible = "nvidia,tegra124-sdhci"; 846 reg = <0x0 0x700b0400 0x0 0x200>; 847 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 848 clocks = <&tegra_car TEGRA124_CLK_SDMMC3>; 849 clock-names = "sdhci"; 850 resets = <&tegra_car 69>; 851 reset-names = "sdhci"; 852 status = "disabled"; 853 }; 854 855 mmc@700b0600 { 856 compatible = "nvidia,tegra124-sdhci"; 857 reg = <0x0 0x700b0600 0x0 0x200>; 858 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 859 clocks = <&tegra_car TEGRA124_CLK_SDMMC4>; 860 clock-names = "sdhci"; 861 resets = <&tegra_car 15>; 862 reset-names = "sdhci"; 863 status = "disabled"; 864 }; 865 866 soctherm: thermal-sensor@700e2000 { 867 compatible = "nvidia,tegra132-soctherm"; 868 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */ 869 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */ 870 reg-names = "soctherm-reg", "ccroc-reg"; 871 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 872 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 873 interrupt-names = "thermal", "edp"; 874 clocks = <&tegra_car TEGRA124_CLK_TSENSOR>, 875 <&tegra_car TEGRA124_CLK_SOC_THERM>; 876 clock-names = "tsensor", "soctherm"; 877 resets = <&tegra_car 78>; 878 reset-names = "soctherm"; 879 #thermal-sensor-cells = <1>; 880 881 throttle-cfgs { 882 throttle_heavy: heavy { 883 nvidia,priority = <100>; 884 nvidia,cpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_HIGH>; 885 886 #cooling-cells = <2>; 887 }; 888 }; 889 }; 890 891 ahub@70300000 { 892 compatible = "nvidia,tegra124-ahub"; 893 reg = <0x0 0x70300000 0x0 0x200>, 894 <0x0 0x70300800 0x0 0x800>, 895 <0x0 0x70300200 0x0 0x600>; 896 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&tegra_car TEGRA124_CLK_D_AUDIO>, 898 <&tegra_car TEGRA124_CLK_APBIF>; 899 clock-names = "d_audio", "apbif"; 900 resets = <&tegra_car 106>, /* d_audio */ 901 <&tegra_car 107>, /* apbif */ 902 <&tegra_car 30>, /* i2s0 */ 903 <&tegra_car 11>, /* i2s1 */ 904 <&tegra_car 18>, /* i2s2 */ 905 <&tegra_car 101>, /* i2s3 */ 906 <&tegra_car 102>, /* i2s4 */ 907 <&tegra_car 108>, /* dam0 */ 908 <&tegra_car 109>, /* dam1 */ 909 <&tegra_car 110>, /* dam2 */ 910 <&tegra_car 10>, /* spdif */ 911 <&tegra_car 153>, /* amx */ 912 <&tegra_car 185>, /* amx1 */ 913 <&tegra_car 154>, /* adx */ 914 <&tegra_car 180>, /* adx1 */ 915 <&tegra_car 186>, /* afc0 */ 916 <&tegra_car 187>, /* afc1 */ 917 <&tegra_car 188>, /* afc2 */ 918 <&tegra_car 189>, /* afc3 */ 919 <&tegra_car 190>, /* afc4 */ 920 <&tegra_car 191>; /* afc5 */ 921 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", 922 "i2s3", "i2s4", "dam0", "dam1", "dam2", 923 "spdif", "amx", "amx1", "adx", "adx1", 924 "afc0", "afc1", "afc2", "afc3", "afc4", "afc5"; 925 dmas = <&apbdma 1>, <&apbdma 1>, 926 <&apbdma 2>, <&apbdma 2>, 927 <&apbdma 3>, <&apbdma 3>, 928 <&apbdma 4>, <&apbdma 4>, 929 <&apbdma 6>, <&apbdma 6>, 930 <&apbdma 7>, <&apbdma 7>, 931 <&apbdma 12>, <&apbdma 12>, 932 <&apbdma 13>, <&apbdma 13>, 933 <&apbdma 14>, <&apbdma 14>, 934 <&apbdma 29>, <&apbdma 29>; 935 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2", 936 "rx3", "tx3", "rx4", "tx4", "rx5", "tx5", 937 "rx6", "tx6", "rx7", "tx7", "rx8", "tx8", 938 "rx9", "tx9"; 939 ranges; 940 #address-cells = <2>; 941 #size-cells = <2>; 942 943 tegra_i2s0: i2s@70301000 { 944 compatible = "nvidia,tegra124-i2s"; 945 reg = <0x0 0x70301000 0x0 0x100>; 946 nvidia,ahub-cif-ids = <4 4>; 947 clocks = <&tegra_car TEGRA124_CLK_I2S0>; 948 clock-names = "i2s"; 949 resets = <&tegra_car 30>; 950 reset-names = "i2s"; 951 status = "disabled"; 952 }; 953 954 tegra_i2s1: i2s@70301100 { 955 compatible = "nvidia,tegra124-i2s"; 956 reg = <0x0 0x70301100 0x0 0x100>; 957 nvidia,ahub-cif-ids = <5 5>; 958 clocks = <&tegra_car TEGRA124_CLK_I2S1>; 959 clock-names = "i2s"; 960 resets = <&tegra_car 11>; 961 reset-names = "i2s"; 962 status = "disabled"; 963 }; 964 965 tegra_i2s2: i2s@70301200 { 966 compatible = "nvidia,tegra124-i2s"; 967 reg = <0x0 0x70301200 0x0 0x100>; 968 nvidia,ahub-cif-ids = <6 6>; 969 clocks = <&tegra_car TEGRA124_CLK_I2S2>; 970 clock-names = "i2s"; 971 resets = <&tegra_car 18>; 972 reset-names = "i2s"; 973 status = "disabled"; 974 }; 975 976 tegra_i2s3: i2s@70301300 { 977 compatible = "nvidia,tegra124-i2s"; 978 reg = <0x0 0x70301300 0x0 0x100>; 979 nvidia,ahub-cif-ids = <7 7>; 980 clocks = <&tegra_car TEGRA124_CLK_I2S3>; 981 clock-names = "i2s"; 982 resets = <&tegra_car 101>; 983 reset-names = "i2s"; 984 status = "disabled"; 985 }; 986 987 tegra_i2s4: i2s@70301400 { 988 compatible = "nvidia,tegra124-i2s"; 989 reg = <0x0 0x70301400 0x0 0x100>; 990 nvidia,ahub-cif-ids = <8 8>; 991 clocks = <&tegra_car TEGRA124_CLK_I2S4>; 992 clock-names = "i2s"; 993 resets = <&tegra_car 102>; 994 reset-names = "i2s"; 995 status = "disabled"; 996 }; 997 }; 998 999 usb@7d000000 { 1000 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1001 reg = <0x0 0x7d000000 0x0 0x4000>; 1002 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1003 phy_type = "utmi"; 1004 clocks = <&tegra_car TEGRA124_CLK_USBD>; 1005 clock-names = "usb"; 1006 resets = <&tegra_car 22>; 1007 reset-names = "usb"; 1008 nvidia,phy = <&phy1>; 1009 status = "disabled"; 1010 }; 1011 1012 phy1: usb-phy@7d000000 { 1013 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1014 reg = <0x0 0x7d000000 0x0 0x4000>, 1015 <0x0 0x7d000000 0x0 0x4000>; 1016 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1017 phy_type = "utmi"; 1018 clocks = <&tegra_car TEGRA124_CLK_USBD>, 1019 <&tegra_car TEGRA124_CLK_PLL_U>, 1020 <&tegra_car TEGRA124_CLK_USBD>; 1021 clock-names = "reg", "pll_u", "utmi-pads"; 1022 resets = <&tegra_car 22>, <&tegra_car 22>; 1023 reset-names = "usb", "utmi-pads"; 1024 #phy-cells = <0>; 1025 nvidia,hssync-start-delay = <0>; 1026 nvidia,idle-wait-delay = <17>; 1027 nvidia,elastic-limit = <16>; 1028 nvidia,term-range-adj = <6>; 1029 nvidia,xcvr-setup = <9>; 1030 nvidia,xcvr-lsfslew = <0>; 1031 nvidia,xcvr-lsrslew = <3>; 1032 nvidia,hssquelch-level = <2>; 1033 nvidia,hsdiscon-level = <5>; 1034 nvidia,xcvr-hsslew = <12>; 1035 nvidia,has-utmi-pad-registers; 1036 nvidia,pmc = <&tegra_pmc 0>; 1037 status = "disabled"; 1038 }; 1039 1040 usb@7d004000 { 1041 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1042 reg = <0x0 0x7d004000 0x0 0x4000>; 1043 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1044 phy_type = "utmi"; 1045 clocks = <&tegra_car TEGRA124_CLK_USB2>; 1046 clock-names = "usb"; 1047 resets = <&tegra_car 58>; 1048 reset-names = "usb"; 1049 nvidia,phy = <&phy2>; 1050 status = "disabled"; 1051 }; 1052 1053 phy2: usb-phy@7d004000 { 1054 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1055 reg = <0x0 0x7d004000 0x0 0x4000>, 1056 <0x0 0x7d000000 0x0 0x4000>; 1057 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1058 phy_type = "utmi"; 1059 clocks = <&tegra_car TEGRA124_CLK_USB2>, 1060 <&tegra_car TEGRA124_CLK_PLL_U>, 1061 <&tegra_car TEGRA124_CLK_USBD>; 1062 clock-names = "reg", "pll_u", "utmi-pads"; 1063 resets = <&tegra_car 58>, <&tegra_car 22>; 1064 reset-names = "usb", "utmi-pads"; 1065 #phy-cells = <0>; 1066 nvidia,hssync-start-delay = <0>; 1067 nvidia,idle-wait-delay = <17>; 1068 nvidia,elastic-limit = <16>; 1069 nvidia,term-range-adj = <6>; 1070 nvidia,xcvr-setup = <9>; 1071 nvidia,xcvr-lsfslew = <0>; 1072 nvidia,xcvr-lsrslew = <3>; 1073 nvidia,hssquelch-level = <2>; 1074 nvidia,hsdiscon-level = <5>; 1075 nvidia,xcvr-hsslew = <12>; 1076 nvidia,pmc = <&tegra_pmc 1>; 1077 status = "disabled"; 1078 }; 1079 1080 usb@7d008000 { 1081 compatible = "nvidia,tegra124-ehci", "nvidia,tegra30-ehci"; 1082 reg = <0x0 0x7d008000 0x0 0x4000>; 1083 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1084 phy_type = "utmi"; 1085 clocks = <&tegra_car TEGRA124_CLK_USB3>; 1086 clock-names = "usb"; 1087 resets = <&tegra_car 59>; 1088 reset-names = "usb"; 1089 nvidia,phy = <&phy3>; 1090 status = "disabled"; 1091 }; 1092 1093 phy3: usb-phy@7d008000 { 1094 compatible = "nvidia,tegra124-usb-phy", "nvidia,tegra30-usb-phy"; 1095 reg = <0x0 0x7d008000 0x0 0x4000>, 1096 <0x0 0x7d000000 0x0 0x4000>; 1097 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 1098 phy_type = "utmi"; 1099 clocks = <&tegra_car TEGRA124_CLK_USB3>, 1100 <&tegra_car TEGRA124_CLK_PLL_U>, 1101 <&tegra_car TEGRA124_CLK_USBD>; 1102 clock-names = "reg", "pll_u", "utmi-pads"; 1103 resets = <&tegra_car 59>, <&tegra_car 22>; 1104 reset-names = "usb", "utmi-pads"; 1105 #phy-cells = <0>; 1106 nvidia,hssync-start-delay = <0>; 1107 nvidia,idle-wait-delay = <17>; 1108 nvidia,elastic-limit = <16>; 1109 nvidia,term-range-adj = <6>; 1110 nvidia,xcvr-setup = <9>; 1111 nvidia,xcvr-lsfslew = <0>; 1112 nvidia,xcvr-lsrslew = <3>; 1113 nvidia,hssquelch-level = <2>; 1114 nvidia,hsdiscon-level = <5>; 1115 nvidia,xcvr-hsslew = <12>; 1116 nvidia,pmc = <&tegra_pmc 2>; 1117 status = "disabled"; 1118 }; 1119 1120 cpus { 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 1124 cpu@0 { 1125 device_type = "cpu"; 1126 compatible = "nvidia,tegra132-denver"; 1127 reg = <0>; 1128 }; 1129 1130 cpu@1 { 1131 device_type = "cpu"; 1132 compatible = "nvidia,tegra132-denver"; 1133 reg = <1>; 1134 }; 1135 }; 1136 1137 thermal-zones { 1138 cpu-thermal { 1139 polling-delay-passive = <1000>; 1140 polling-delay = <0>; 1141 1142 thermal-sensors = 1143 <&soctherm TEGRA124_SOCTHERM_SENSOR_CPU>; 1144 1145 trips { 1146 cpu_shutdown_trip { 1147 temperature = <105000>; 1148 hysteresis = <1000>; 1149 type = "critical"; 1150 }; 1151 1152 cpu_throttle_trip: throttle-trip { 1153 temperature = <102000>; 1154 hysteresis = <1000>; 1155 type = "hot"; 1156 }; 1157 }; 1158 1159 cooling-maps { 1160 map0 { 1161 trip = <&cpu_throttle_trip>; 1162 cooling-device = <&throttle_heavy 1 1>; 1163 }; 1164 }; 1165 }; 1166 1167 mem-thermal { 1168 polling-delay-passive = <0>; 1169 polling-delay = <0>; 1170 1171 thermal-sensors = 1172 <&soctherm TEGRA124_SOCTHERM_SENSOR_MEM>; 1173 1174 trips { 1175 mem_shutdown_trip { 1176 temperature = <101000>; 1177 hysteresis = <1000>; 1178 type = "critical"; 1179 }; 1180 mem_throttle_trip { 1181 temperature = <99000>; 1182 hysteresis = <1000>; 1183 type = "hot"; 1184 }; 1185 }; 1186 1187 cooling-maps { 1188 /* 1189 * There are currently no cooling maps, 1190 * because there are no cooling devices. 1191 */ 1192 }; 1193 }; 1194 1195 gpu-thermal { 1196 polling-delay-passive = <1000>; 1197 polling-delay = <0>; 1198 1199 thermal-sensors = 1200 <&soctherm TEGRA124_SOCTHERM_SENSOR_GPU>; 1201 1202 trips { 1203 gpu_shutdown_trip { 1204 temperature = <101000>; 1205 hysteresis = <1000>; 1206 type = "critical"; 1207 }; 1208 1209 gpu_throttle_trip: throttle-trip { 1210 temperature = <99000>; 1211 hysteresis = <1000>; 1212 type = "hot"; 1213 }; 1214 }; 1215 1216 cooling-maps { 1217 map0 { 1218 trip = <&gpu_throttle_trip>; 1219 cooling-device = <&throttle_heavy 1 1>; 1220 }; 1221 }; 1222 }; 1223 1224 pllx-thermal { 1225 polling-delay-passive = <0>; 1226 polling-delay = <0>; 1227 1228 thermal-sensors = 1229 <&soctherm TEGRA124_SOCTHERM_SENSOR_PLLX>; 1230 1231 trips { 1232 pllx_shutdown_trip { 1233 temperature = <105000>; 1234 hysteresis = <1000>; 1235 type = "critical"; 1236 }; 1237 pllx_throttle_trip { 1238 temperature = <99000>; 1239 hysteresis = <1000>; 1240 type = "hot"; 1241 }; 1242 }; 1243 1244 cooling-maps { 1245 /* 1246 * There are currently no cooling maps, 1247 * because there are no cooling devices. 1248 */ 1249 }; 1250 }; 1251 }; 1252 1253 timer { 1254 compatible = "arm,armv7-timer"; 1255 interrupts = <GIC_PPI 13 1256 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1257 <GIC_PPI 14 1258 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1259 <GIC_PPI 11 1260 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 1261 <GIC_PPI 10 1262 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 1263 interrupt-parent = <&gic>; 1264 }; 1265};
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