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ma35d1.dtsi
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linux-6.19.14/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2023 Nuvoton Technology Corp. 4 * Author: Shan-Chun Hung <schung@nuvoton.com> 5 * Jacky huang <ychuang3@nuvoton.com> 6 */ 7 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/clock/nuvoton,ma35d1-clk.h> 12#include <dt-bindings/reset/nuvoton,ma35d1-reset.h> 13 14/ { 15 compatible = "nuvoton,ma35d1"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 cpus { 21 #address-cells = <2>; 22 #size-cells = <0>; 23 24 cpu0: cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a35"; 27 reg = <0x0 0x0>; 28 enable-method = "psci"; 29 next-level-cache = <&L2_0>; 30 }; 31 32 cpu1: cpu@1 { 33 device_type = "cpu"; 34 compatible = "arm,cortex-a35"; 35 reg = <0x0 0x1>; 36 enable-method = "psci"; 37 next-level-cache = <&L2_0>; 38 }; 39 40 L2_0: l2-cache { 41 compatible = "cache"; 42 cache-level = <2>; 43 cache-unified; 44 cache-size = <0x80000>; 45 }; 46 }; 47 48 psci { 49 compatible = "arm,psci-0.2"; 50 method = "smc"; 51 }; 52 53 gic: interrupt-controller@50801000 { 54 compatible = "arm,gic-400"; 55 reg = <0x0 0x50801000 0 0x1000>, /* GICD */ 56 <0x0 0x50802000 0 0x2000>, /* GICC */ 57 <0x0 0x50804000 0 0x2000>, /* GICH */ 58 <0x0 0x50806000 0 0x2000>; /* GICV */ 59 #interrupt-cells = <3>; 60 interrupt-parent = <&gic>; 61 interrupt-controller; 62 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0x13) | 63 IRQ_TYPE_LEVEL_HIGH)>; 64 }; 65 66 timer { 67 compatible = "arm,armv8-timer"; 68 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | 69 IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */ 70 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | 71 IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */ 72 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | 73 IRQ_TYPE_LEVEL_LOW)>, /* Virtual */ 74 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | 75 IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */ 76 interrupt-parent = <&gic>; 77 }; 78 79 soc { 80 compatible = "simple-bus"; 81 #address-cells = <2>; 82 #size-cells = <2>; 83 ranges; 84 85 sys: system-management@40460000 { 86 compatible = "nuvoton,ma35d1-reset", "syscon"; 87 reg = <0x0 0x40460000 0x0 0x200>; 88 #reset-cells = <1>; 89 }; 90 91 clk: clock-controller@40460200 { 92 compatible = "nuvoton,ma35d1-clk"; 93 reg = <0x00000000 0x40460200 0x0 0x100>; 94 #clock-cells = <1>; 95 clocks = <&clk_hxt>; 96 }; 97 98 pinctrl: pinctrl@40040000 { 99 compatible = "nuvoton,ma35d1-pinctrl"; 100 reg = <0x0 0x40040000 0x0 0xc00>; 101 #address-cells = <1>; 102 #size-cells = <1>; 103 nuvoton,sys = <&sys>; 104 ranges = <0x0 0x0 0x40040000 0x400>; 105 106 gpioa: gpio@0 { 107 reg = <0x0 0x40>; 108 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 109 clocks = <&clk GPA_GATE>; 110 gpio-controller; 111 #gpio-cells = <2>; 112 interrupt-controller; 113 #interrupt-cells = <2>; 114 }; 115 116 gpiob: gpio@40 { 117 reg = <0x40 0x40>; 118 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 119 clocks = <&clk GPB_GATE>; 120 gpio-controller; 121 #gpio-cells = <2>; 122 interrupt-controller; 123 #interrupt-cells = <2>; 124 }; 125 126 gpioc: gpio@80 { 127 reg = <0x80 0x40>; 128 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 129 clocks = <&clk GPC_GATE>; 130 gpio-controller; 131 #gpio-cells = <2>; 132 interrupt-controller; 133 #interrupt-cells = <2>; 134 }; 135 136 gpiod: gpio@c0 { 137 reg = <0xc0 0x40>; 138 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 139 clocks = <&clk GPD_GATE>; 140 gpio-controller; 141 #gpio-cells = <2>; 142 interrupt-controller; 143 #interrupt-cells = <2>; 144 }; 145 146 gpioe: gpio@100 { 147 reg = <0x100 0x40>; 148 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 149 clocks = <&clk GPE_GATE>; 150 #gpio-cells = <2>; 151 gpio-controller; 152 interrupt-controller; 153 #interrupt-cells = <2>; 154 }; 155 156 gpiof: gpio@140 { 157 reg = <0x140 0x40>; 158 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&clk GPF_GATE>; 160 gpio-controller; 161 #gpio-cells = <2>; 162 interrupt-controller; 163 #interrupt-cells = <2>; 164 }; 165 166 gpiog: gpio@180 { 167 reg = <0x180 0x40>; 168 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 169 clocks = <&clk GPG_GATE>; 170 #gpio-cells = <2>; 171 gpio-controller; 172 interrupt-controller; 173 #interrupt-cells = <2>; 174 }; 175 176 gpioh: gpio@1c0 { 177 reg = <0x1c0 0x40>; 178 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 179 clocks = <&clk GPH_GATE>; 180 gpio-controller; 181 #gpio-cells = <2>; 182 interrupt-controller; 183 #interrupt-cells = <2>; 184 }; 185 186 gpioi: gpio@200 { 187 reg = <0x200 0x40>; 188 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 189 clocks = <&clk GPI_GATE>; 190 gpio-controller; 191 #gpio-cells = <2>; 192 interrupt-controller; 193 #interrupt-cells = <2>; 194 }; 195 196 gpioj: gpio@240 { 197 reg = <0x240 0x40>; 198 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&clk GPJ_GATE>; 200 gpio-controller; 201 #gpio-cells = <2>; 202 interrupt-controller; 203 #interrupt-cells = <2>; 204 }; 205 206 gpiok: gpio@280 { 207 reg = <0x280 0x40>; 208 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&clk GPK_GATE>; 210 gpio-controller; 211 #gpio-cells = <2>; 212 interrupt-controller; 213 #interrupt-cells = <2>; 214 }; 215 216 gpiol: gpio@2c0 { 217 reg = <0x2c0 0x40>; 218 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 219 clocks = <&clk GPL_GATE>; 220 gpio-controller; 221 #gpio-cells = <2>; 222 interrupt-controller; 223 #interrupt-cells = <2>; 224 }; 225 226 gpiom: gpio@300 { 227 reg = <0x300 0x40>; 228 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&clk GPM_GATE>; 230 gpio-controller; 231 #gpio-cells = <2>; 232 interrupt-controller; 233 #interrupt-cells = <2>; 234 }; 235 236 gpion: gpio@340 { 237 reg = <0x340 0x40>; 238 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 239 clocks = <&clk GPN_GATE>; 240 gpio-controller; 241 #gpio-cells = <2>; 242 interrupt-controller; 243 #interrupt-cells = <2>; 244 }; 245 }; 246 247 uart0: serial@40700000 { 248 compatible = "nuvoton,ma35d1-uart"; 249 reg = <0x0 0x40700000 0x0 0x100>; 250 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 251 clocks = <&clk UART0_GATE>; 252 status = "disabled"; 253 }; 254 255 uart1: serial@40710000 { 256 compatible = "nuvoton,ma35d1-uart"; 257 reg = <0x0 0x40710000 0x0 0x100>; 258 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 259 clocks = <&clk UART1_GATE>; 260 status = "disabled"; 261 }; 262 263 uart2: serial@40720000 { 264 compatible = "nuvoton,ma35d1-uart"; 265 reg = <0x0 0x40720000 0x0 0x100>; 266 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&clk UART2_GATE>; 268 status = "disabled"; 269 }; 270 271 uart3: serial@40730000 { 272 compatible = "nuvoton,ma35d1-uart"; 273 reg = <0x0 0x40730000 0x0 0x100>; 274 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&clk UART3_GATE>; 276 status = "disabled"; 277 }; 278 279 uart4: serial@40740000 { 280 compatible = "nuvoton,ma35d1-uart"; 281 reg = <0x0 0x40740000 0x0 0x100>; 282 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&clk UART4_GATE>; 284 status = "disabled"; 285 }; 286 287 uart5: serial@40750000 { 288 compatible = "nuvoton,ma35d1-uart"; 289 reg = <0x0 0x40750000 0x0 0x100>; 290 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&clk UART5_GATE>; 292 status = "disabled"; 293 }; 294 295 uart6: serial@40760000 { 296 compatible = "nuvoton,ma35d1-uart"; 297 reg = <0x0 0x40760000 0x0 0x100>; 298 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 299 clocks = <&clk UART6_GATE>; 300 status = "disabled"; 301 }; 302 303 uart7: serial@40770000 { 304 compatible = "nuvoton,ma35d1-uart"; 305 reg = <0x0 0x40770000 0x0 0x100>; 306 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 307 clocks = <&clk UART7_GATE>; 308 status = "disabled"; 309 }; 310 311 uart8: serial@40780000 { 312 compatible = "nuvoton,ma35d1-uart"; 313 reg = <0x0 0x40780000 0x0 0x100>; 314 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 315 clocks = <&clk UART8_GATE>; 316 status = "disabled"; 317 }; 318 319 uart9: serial@40790000 { 320 compatible = "nuvoton,ma35d1-uart"; 321 reg = <0x0 0x40790000 0x0 0x100>; 322 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 323 clocks = <&clk UART9_GATE>; 324 status = "disabled"; 325 }; 326 327 uart10: serial@407a0000 { 328 compatible = "nuvoton,ma35d1-uart"; 329 reg = <0x0 0x407a0000 0x0 0x100>; 330 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 331 clocks = <&clk UART10_GATE>; 332 status = "disabled"; 333 }; 334 335 uart11: serial@407b0000 { 336 compatible = "nuvoton,ma35d1-uart"; 337 reg = <0x0 0x407b0000 0x0 0x100>; 338 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&clk UART11_GATE>; 340 status = "disabled"; 341 }; 342 343 uart12: serial@407c0000 { 344 compatible = "nuvoton,ma35d1-uart"; 345 reg = <0x0 0x407c0000 0x0 0x100>; 346 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 347 clocks = <&clk UART12_GATE>; 348 status = "disabled"; 349 }; 350 351 uart13: serial@407d0000 { 352 compatible = "nuvoton,ma35d1-uart"; 353 reg = <0x0 0x407d0000 0x0 0x100>; 354 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 355 clocks = <&clk UART13_GATE>; 356 status = "disabled"; 357 }; 358 359 uart14: serial@407e0000 { 360 compatible = "nuvoton,ma35d1-uart"; 361 reg = <0x0 0x407e0000 0x0 0x100>; 362 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&clk UART14_GATE>; 364 status = "disabled"; 365 }; 366 367 uart15: serial@407f0000 { 368 compatible = "nuvoton,ma35d1-uart"; 369 reg = <0x0 0x407f0000 0x0 0x100>; 370 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 371 clocks = <&clk UART15_GATE>; 372 status = "disabled"; 373 }; 374 375 uart16: serial@40880000 { 376 compatible = "nuvoton,ma35d1-uart"; 377 reg = <0x0 0x40880000 0x0 0x100>; 378 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&clk UART16_GATE>; 380 status = "disabled"; 381 }; 382 }; 383};
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