mt8395-genio-common.dtsi

   1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2/*
   3 * Copyright (C) 2023 MediaTek Inc.
   4 * Author: Ben Lok <ben.lok@mediatek.com>
   5 *	   Macpaul Lin <macpaul.lin@mediatek.com>
   6 */
   7/dts-v1/;
   8
   9#include "mt8195.dtsi"
  10#include "mt6359.dtsi"
  11#include <dt-bindings/gpio/gpio.h>
  12#include <dt-bindings/input/input.h>
  13#include <dt-bindings/interrupt-controller/irq.h>
  14#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
  15#include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
  16#include <dt-bindings/spmi/spmi.h>
  17#include <dt-bindings/usb/pd.h>
  18
  19/ {
  20	aliases {
  21		serial0 = &uart0;
  22		ethernet0 = &eth;
  23	};
  24
  25	chosen {
  26		stdout-path = "serial0:921600n8";
  27	};
  28
  29	firmware {
  30		optee {
  31			compatible = "linaro,optee-tz";
  32			method = "smc";
  33		};
  34	};
  35
  36	memory@40000000 {
  37		device_type = "memory";
  38		reg = <0 0x40000000 0x2 0x00000000>;
  39	};
  40
  41	reserved-memory {
  42		#address-cells = <2>;
  43		#size-cells = <2>;
  44		ranges;
  45
  46		/*
  47		 * 12 MiB reserved for OP-TEE (BL32)
  48		 * +-----------------------+ 0x43e0_0000
  49		 * |      SHMEM 2MiB       |
  50		 * +-----------------------+ 0x43c0_0000
  51		 * |        | TA_RAM  8MiB |
  52		 * + TZDRAM +--------------+ 0x4340_0000
  53		 * |        | TEE_RAM 2MiB |
  54		 * +-----------------------+ 0x4320_0000
  55		 */
  56		optee_reserved: optee@43200000 {
  57			no-map;
  58			reg = <0 0x43200000 0 0x00c00000>;
  59		};
  60
  61		scp_mem: memory@50000000 {
  62			compatible = "shared-dma-pool";
  63			reg = <0 0x50000000 0 0x2900000>;
  64			no-map;
  65		};
  66
  67		vpu_mem: memory@53000000 {
  68			compatible = "shared-dma-pool";
  69			reg = <0 0x53000000 0 0x1400000>; /* 20 MB */
  70		};
  71
  72		/* 2 MiB reserved for ARM Trusted Firmware (BL31) */
  73		bl31_secmon_mem: memory@54600000 {
  74			no-map;
  75			reg = <0 0x54600000 0x0 0x200000>;
  76		};
  77
  78		adsp_mem: memory@60000000 {
  79			compatible = "shared-dma-pool";
  80			reg = <0 0x60000000 0 0xf00000>;
  81			no-map;
  82		};
  83
  84		afe_dma_mem: memory@60f00000 {
  85			compatible = "shared-dma-pool";
  86			reg = <0 0x60f00000 0 0x100000>;
  87			no-map;
  88		};
  89
  90		adsp_dma_mem: memory@61000000 {
  91			compatible = "shared-dma-pool";
  92			reg = <0 0x61000000 0 0x100000>;
  93			no-map;
  94		};
  95
  96		apu_mem: memory@62000000 {
  97			compatible = "shared-dma-pool";
  98			reg = <0 0x62000000 0 0x1400000>; /* 20 MB */
  99		};
 100	};
 101
 102	backlight_lcm0: backlight-lcm0 {
 103		compatible = "pwm-backlight";
 104		brightness-levels = <0 1023>;
 105		default-brightness-level = <576>;
 106		num-interpolated-steps = <1023>;
 107		pwms = <&disp_pwm0 0 500000>;
 108	};
 109
 110	backlight_lcd1: backlight-lcd1 {
 111		compatible = "pwm-backlight";
 112		pwms = <&disp_pwm1 0 500000>;
 113		enable-gpios = <&pio 46 GPIO_ACTIVE_HIGH>;
 114		brightness-levels = <0 1023>;
 115		num-interpolated-steps = <1023>;
 116		default-brightness-level = <576>;
 117		status = "disabled";
 118	};
 119
 120	can_clk: can-clk {
 121		compatible = "fixed-clock";
 122		#clock-cells = <0>;
 123		clock-frequency = <20000000>;
 124		clock-output-names = "can-clk";
 125	};
 126
 127	edp_panel_fixed_3v3: regulator-0 {
 128		compatible = "regulator-fixed";
 129		regulator-name = "edp_panel_3v3";
 130		regulator-min-microvolt = <3300000>;
 131		regulator-max-microvolt = <3300000>;
 132		enable-active-high;
 133		gpio = <&pio 6 GPIO_ACTIVE_HIGH>;
 134		pinctrl-names = "default";
 135		pinctrl-0 = <&edp_panel_3v3_en_pins>;
 136	};
 137
 138	edp_panel_fixed_12v: regulator-1 {
 139		compatible = "regulator-fixed";
 140		regulator-name = "edp_backlight_12v";
 141		regulator-min-microvolt = <12000000>;
 142		regulator-max-microvolt = <12000000>;
 143		enable-active-high;
 144		gpio = <&pio 96 GPIO_ACTIVE_HIGH>;
 145		pinctrl-names = "default";
 146		pinctrl-0 = <&edp_panel_12v_en_pins>;
 147	};
 148
 149	keys: gpio-keys {
 150		compatible = "gpio-keys";
 151
 152		button-volume-up {
 153			wakeup-source;
 154			debounce-interval = <100>;
 155			gpios = <&pio 106 GPIO_ACTIVE_LOW>;
 156			label = "volume_up";
 157			linux,code = <KEY_VOLUMEUP>;
 158		};
 159	};
 160
 161	lcm0_iovcc: regulator-vio18-lcm0 {
 162		compatible = "regulator-fixed";
 163		regulator-name = "vio18_lcm0";
 164		enable-active-high;
 165		gpio = <&pio 47 GPIO_ACTIVE_HIGH>;
 166		pinctrl-names = "default";
 167		pinctrl-0 = <&dsi0_vreg_en_pins>;
 168		vin-supply = <&mt6360_ldo2>;
 169	};
 170
 171	lcm0_vddp: regulator-vsys-lcm0 {
 172		compatible = "regulator-fixed";
 173		regulator-name = "vsys_lcm0";
 174		regulator-always-on;
 175		regulator-boot-on;
 176		vin-supply = <&mt6360_ldo1>;
 177	};
 178
 179	wifi_fixed_3v3: regulator-2 {
 180		compatible = "regulator-fixed";
 181		regulator-name = "wifi_3v3";
 182		regulator-min-microvolt = <3300000>;
 183		regulator-max-microvolt = <3300000>;
 184		gpio = <&pio 135 GPIO_ACTIVE_HIGH>;
 185		enable-active-high;
 186		regulator-always-on;
 187	};
 188};
 189
 190&adsp {
 191	memory-region = <&adsp_dma_mem>, <&adsp_mem>;
 192	status = "okay";
 193};
 194
 195&afe {
 196	memory-region = <&afe_dma_mem>;
 197	status = "okay";
 198};
 199
 200&cpu0 {
 201	cpu-supply = <&mt6359_vcore_buck_reg>;
 202};
 203
 204&cpu1 {
 205	cpu-supply = <&mt6359_vcore_buck_reg>;
 206};
 207
 208&cpu2 {
 209	cpu-supply = <&mt6359_vcore_buck_reg>;
 210};
 211
 212&cpu3 {
 213	cpu-supply = <&mt6359_vcore_buck_reg>;
 214};
 215
 216&cpu4 {
 217	cpu-supply = <&mt6315_6_vbuck1>;
 218};
 219
 220&cpu5 {
 221	cpu-supply = <&mt6315_6_vbuck1>;
 222};
 223
 224&cpu6 {
 225	cpu-supply = <&mt6315_6_vbuck1>;
 226};
 227
 228&cpu7 {
 229	cpu-supply = <&mt6315_6_vbuck1>;
 230};
 231
 232&disp_pwm0 {
 233	pinctrl-names = "default";
 234	pinctrl-0 = <&disp_pwm0_pins>;
 235	status = "okay";
 236};
 237
 238&dither0_in {
 239	remote-endpoint = <&gamma0_out>;
 240};
 241
 242&dither0_out {
 243	remote-endpoint = <&dsi0_in>;
 244};
 245
 246&dmic_codec {
 247	wakeup-delay-ms = <200>;
 248};
 249
 250&dsi0 {
 251	#address-cells = <1>;
 252	#size-cells = <0>;
 253	status = "okay";
 254
 255	panel@0 {
 256		compatible = "startek,kd070fhfid078", "himax,hx8279";
 257		reg = <0>;
 258		backlight = <&backlight_lcm0>;
 259		enable-gpios = <&pio 48 GPIO_ACTIVE_HIGH>;
 260		reset-gpios = <&pio 108 GPIO_ACTIVE_HIGH>;
 261		iovcc-supply = <&lcm0_iovcc>;
 262		vdd-supply = <&lcm0_vddp>;
 263		pinctrl-names = "default";
 264		pinctrl-0 = <&panel_default_pins>;
 265
 266		port {
 267			dsi_panel_in: endpoint {
 268				remote-endpoint = <&dsi0_out>;
 269			};
 270		};
 271	};
 272
 273	ports {
 274		#address-cells = <1>;
 275		#size-cells = <0>;
 276
 277		port@0 {
 278			reg = <0>;
 279			dsi0_in: endpoint {
 280				remote-endpoint = <&dither0_out>;
 281			};
 282		};
 283
 284		port@1 {
 285			reg = <1>;
 286			dsi0_out: endpoint {
 287				remote-endpoint = <&dsi_panel_in>;
 288			};
 289		};
 290	};
 291};
 292
 293&eth {
 294	phy-mode ="rgmii-rxid";
 295	phy-handle = <&eth_phy0>;
 296	snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>;
 297	snps,reset-delays-us = <0 10000 10000>;
 298	mediatek,tx-delay-ps = <2030>;
 299	mediatek,mac-wol;
 300	pinctrl-names = "default", "sleep";
 301	pinctrl-0 = <&eth_default_pins>;
 302	pinctrl-1 = <&eth_sleep_pins>;
 303	status = "okay";
 304
 305	mdio {
 306		compatible = "snps,dwmac-mdio";
 307		#address-cells = <1>;
 308		#size-cells = <0>;
 309		eth_phy0: ethernet-phy@1 {
 310			compatible = "ethernet-phy-id001c.c916";
 311			reg = <0x1>;
 312		};
 313	};
 314};
 315
 316&gamma0_out {
 317	remote-endpoint = <&dither0_in>;
 318};
 319
 320&gpu {
 321	mali-supply = <&mt6315_7_vbuck1>;
 322	status = "okay";
 323};
 324
 325&i2c0 {
 326	clock-frequency = <400000>;
 327	pinctrl-0 = <&i2c0_pins>;
 328	pinctrl-names = "default";
 329	status = "okay";
 330};
 331
 332&i2c1 {
 333	clock-frequency = <400000>;
 334	pinctrl-0 = <&i2c1_pins>;
 335	pinctrl-names = "default";
 336	status = "okay";
 337
 338	touchscreen@5d {
 339		compatible = "goodix,gt9271";
 340		reg = <0x5d>;
 341		interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>;
 342		irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>;
 343		reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>;
 344		AVDD28-supply = <&mt6360_ldo1>;
 345		pinctrl-names = "default";
 346		pinctrl-0 = <&touch_pins>;
 347	};
 348};
 349
 350&i2c2 {
 351	clock-frequency = <400000>;
 352	pinctrl-0 = <&i2c2_pins>;
 353	pinctrl-names = "default";
 354	status = "okay";
 355
 356	typec-mux@48 {
 357		compatible = "ite,it5205";
 358		reg = <0x48>;
 359		vcc-supply = <&mt6359_vibr_ldo_reg>;
 360		mode-switch;
 361		orientation-switch;
 362		status = "okay";
 363
 364		port {
 365			it5205_sbu_ep: endpoint {
 366				remote-endpoint = <&mt6360_ssusb_sbu_ep>;
 367			};
 368		};
 369	};
 370};
 371
 372&i2c6 {
 373	clock-frequency = <400000>;
 374	pinctrl-0 = <&i2c6_pins>;
 375	pinctrl-names = "default";
 376	#address-cells = <1>;
 377	#size-cells = <0>;
 378	status = "okay";
 379
 380	mt6360: pmic@34 {
 381		compatible = "mediatek,mt6360";
 382		reg = <0x34>;
 383		interrupt-parent = <&pio>;
 384		interrupts = <128 IRQ_TYPE_EDGE_FALLING>;
 385		interrupt-names = "IRQB";
 386		interrupt-controller;
 387		#interrupt-cells = <1>;
 388		pinctrl-0 = <&mt6360_pins>;
 389
 390		charger {
 391			compatible = "mediatek,mt6360-chg";
 392			richtek,vinovp-microvolt = <14500000>;
 393
 394			otg_vbus_regulator: usb-otg-vbus-regulator {
 395				regulator-name = "usb-otg-vbus";
 396				regulator-min-microvolt = <4425000>;
 397				regulator-max-microvolt = <5825000>;
 398			};
 399		};
 400
 401		regulator {
 402			compatible = "mediatek,mt6360-regulator";
 403			LDO_VIN3-supply = <&mt6360_buck2>;
 404
 405			mt6360_buck1: buck1 {
 406				regulator-name = "emi_vdd2";
 407				regulator-min-microvolt = <300000>;
 408				regulator-max-microvolt = <1300000>;
 409				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 410							   MT6360_OPMODE_LP
 411							   MT6360_OPMODE_ULP>;
 412				regulator-always-on;
 413			};
 414
 415			mt6360_buck2: buck2 {
 416				regulator-name = "emi_vddq";
 417				regulator-min-microvolt = <300000>;
 418				regulator-max-microvolt = <1300000>;
 419				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 420							   MT6360_OPMODE_LP
 421							   MT6360_OPMODE_ULP>;
 422				regulator-always-on;
 423			};
 424
 425			mt6360_ldo1: ldo1 {
 426				regulator-name = "tp1_p3v0";
 427				regulator-min-microvolt = <3300000>;
 428				regulator-max-microvolt = <3300000>;
 429				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 430							   MT6360_OPMODE_LP>;
 431				regulator-always-on;
 432			};
 433
 434			mt6360_ldo2: ldo2 {
 435				regulator-name = "panel1_p1v8";
 436				regulator-min-microvolt = <1800000>;
 437				regulator-max-microvolt = <1800000>;
 438				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 439							   MT6360_OPMODE_LP>;
 440			};
 441
 442			mt6360_ldo3: ldo3 {
 443				regulator-name = "vmc_pmu";
 444				regulator-min-microvolt = <1200000>;
 445				regulator-max-microvolt = <3600000>;
 446				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 447							   MT6360_OPMODE_LP>;
 448			};
 449
 450			mt6360_ldo5: ldo5 {
 451				regulator-name = "vmch_pmu";
 452				regulator-min-microvolt = <2700000>;
 453				regulator-max-microvolt = <3600000>;
 454				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 455							   MT6360_OPMODE_LP>;
 456			};
 457
 458			/* This is a measure point, which name is mt6360_ldo1 on schematic */
 459			mt6360_ldo6: ldo6 {
 460				regulator-name = "mt6360_ldo1";
 461				regulator-min-microvolt = <500000>;
 462				regulator-max-microvolt = <2100000>;
 463				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 464							   MT6360_OPMODE_LP>;
 465			};
 466
 467			mt6360_ldo7: ldo7 {
 468				regulator-name = "emi_vmddr_en";
 469				regulator-min-microvolt = <500000>;
 470				regulator-max-microvolt = <2100000>;
 471				regulator-allowed-modes = <MT6360_OPMODE_NORMAL
 472							   MT6360_OPMODE_LP>;
 473				regulator-always-on;
 474			};
 475		};
 476
 477		tcpc {
 478			compatible = "mediatek,mt6360-tcpc";
 479			interrupts-extended = <&pio 17 IRQ_TYPE_LEVEL_LOW>;
 480			interrupt-names = "PD_IRQB";
 481
 482			connector {
 483				compatible = "usb-c-connector";
 484				label = "USB-C";
 485				data-role = "dual";
 486				op-sink-microwatt = <10000000>;
 487				power-role = "dual";
 488				try-power-role = "sink";
 489
 490				source-pdos = <PDO_FIXED(5000, 1000,
 491							 PDO_FIXED_DUAL_ROLE |
 492							 PDO_FIXED_DATA_SWAP)>;
 493				sink-pdos = <PDO_FIXED(5000, 2000,
 494						       PDO_FIXED_DUAL_ROLE |
 495						       PDO_FIXED_DATA_SWAP)>;
 496
 497				pd-revision = /bits/ 8 <0x03 0x01 0x01 0x06>;
 498
 499				altmodes {
 500					displayport {
 501						svid = /bits/ 16 <0xff01>;
 502						vdo = <0x00001c46>;
 503					};
 504				};
 505
 506				ports {
 507					#address-cells = <1>;
 508					#size-cells = <0>;
 509
 510					port@0 {
 511						reg = <0>;
 512						typec_con_hs: endpoint {
 513							remote-endpoint = <&mtu3_hs0_role_sw>;
 514						};
 515					};
 516
 517					port@1 {
 518						reg = <1>;
 519						typec_con_ss: endpoint {
 520							remote-endpoint = <&mtu3_ss0_role_sw>;
 521						};
 522					};
 523
 524					port@2 {
 525						reg = <2>;
 526						mt6360_ssusb_sbu_ep: endpoint {
 527							remote-endpoint = <&it5205_sbu_ep>;
 528						};
 529					};
 530				};
 531			};
 532		};
 533	};
 534};
 535
 536&mfg0 {
 537	domain-supply = <&mt6315_7_vbuck1>;
 538};
 539
 540&mfg1 {
 541	domain-supply = <&mt6359_vsram_others_ldo_reg>;
 542};
 543
 544&mipi_tx0 {
 545	status = "okay";
 546};
 547
 548&mmc0 {
 549	status = "okay";
 550	pinctrl-names = "default", "state_uhs";
 551	pinctrl-0 = <&mmc0_default_pins>;
 552	pinctrl-1 = <&mmc0_uhs_pins>;
 553	bus-width = <8>;
 554	max-frequency = <200000000>;
 555	cap-mmc-highspeed;
 556	mmc-hs200-1_8v;
 557	mmc-hs400-1_8v;
 558	cap-mmc-hw-reset;
 559	no-sdio;
 560	no-sd;
 561	hs400-ds-delay = <0x14c11>;
 562	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
 563	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
 564	non-removable;
 565};
 566
 567&mmc1 {
 568	pinctrl-names = "default", "state_uhs";
 569	pinctrl-0 = <&mmc1_default_pins>;
 570	pinctrl-1 = <&mmc1_uhs_pins>;
 571	bus-width = <4>;
 572	max-frequency = <200000000>;
 573	cap-sd-highspeed;
 574	sd-uhs-sdr50;
 575	sd-uhs-sdr104;
 576	no-mmc;
 577	no-sdio;
 578	vmmc-supply = <&mt6360_ldo5>;
 579	vqmmc-supply = <&mt6360_ldo3>;
 580	status = "okay";
 581	non-removable;
 582};
 583
 584&mt6359_vaud18_ldo_reg {
 585	regulator-always-on;
 586};
 587
 588&mt6359_vbbck_ldo_reg {
 589	regulator-always-on;
 590};
 591
 592/* For USB Hub */
 593&mt6359_vcamio_ldo_reg {
 594	regulator-always-on;
 595};
 596
 597&mt6359_vcn33_2_bt_ldo_reg {
 598	regulator-min-microvolt = <3300000>;
 599	regulator-max-microvolt = <3300000>;
 600};
 601
 602&mt6359_vcore_buck_reg {
 603	regulator-always-on;
 604};
 605
 606&mt6359_vgpu11_buck_reg {
 607	regulator-always-on;
 608};
 609
 610&mt6359_vpu_buck_reg {
 611	regulator-always-on;
 612};
 613
 614&mt6359_vrf12_ldo_reg {
 615	regulator-always-on;
 616};
 617
 618/* for GPU SRAM */
 619&mt6359_vsram_others_ldo_reg {
 620	regulator-min-microvolt = <750000>;
 621	regulator-max-microvolt = <750000>;
 622};
 623
 624&mt6359codec {
 625	mediatek,mic-type-0 = <1>; /* ACC */
 626	mediatek,mic-type-1 = <3>; /* DCC */
 627	mediatek,mic-type-2 = <1>; /* ACC */
 628};
 629
 630&ovl0_in {
 631	remote-endpoint = <&vdosys0_ep_main>;
 632};
 633
 634&pcie0 {
 635	pinctrl-names = "default", "idle";
 636	pinctrl-0 = <&pcie0_default_pins>;
 637	pinctrl-1 = <&pcie0_idle_pins>;
 638	status = "okay";
 639};
 640
 641&pcie1 {
 642	pinctrl-names = "default";
 643	pinctrl-0 = <&pcie1_default_pins>;
 644	status = "disabled";
 645};
 646
 647&pciephy {
 648	status = "okay";
 649};
 650
 651&pio {
 652	audio_default_pins: audio-default-pins {
 653		pins-cmd-dat {
 654			pinmux = <PINMUX_GPIO61__FUNC_DMIC1_CLK>,
 655				 <PINMUX_GPIO62__FUNC_DMIC1_DAT>,
 656				 <PINMUX_GPIO65__FUNC_PCM_DO>,
 657				 <PINMUX_GPIO66__FUNC_PCM_CLK>,
 658				 <PINMUX_GPIO67__FUNC_PCM_DI>,
 659				 <PINMUX_GPIO68__FUNC_PCM_SYNC>,
 660				 <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>,
 661				 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>,
 662				 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>,
 663				 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>,
 664				 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>,
 665				 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>,
 666				 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>;
 667		};
 668	};
 669
 670	disp_pwm1_default_pins: disp-pwm1-default-pins {
 671		pins1 {
 672			pinmux = <PINMUX_GPIO104__FUNC_DISP_PWM1>;
 673		};
 674	};
 675
 676	edp_panel_12v_en_pins: edp-panel-12v-en-pins {
 677		pins1 {
 678			pinmux = <PINMUX_GPIO96__FUNC_GPIO96>;
 679			output-high;
 680		};
 681	};
 682
 683	edp_panel_3v3_en_pins: edp-panel-3v3-en-pins {
 684		pins1 {
 685			pinmux = <PINMUX_GPIO6__FUNC_GPIO6>;
 686			output-high;
 687		};
 688	};
 689
 690	eth_default_pins: eth-default-pins {
 691		pins-cc {
 692			pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>,
 693				 <PINMUX_GPIO86__FUNC_GBE_RXC>,
 694				 <PINMUX_GPIO87__FUNC_GBE_RXDV>,
 695				 <PINMUX_GPIO88__FUNC_GBE_TXEN>;
 696			drive-strength = <8>;
 697		};
 698
 699		pins-mdio {
 700			pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>,
 701				 <PINMUX_GPIO90__FUNC_GBE_MDIO>;
 702			input-enable;
 703		};
 704
 705		pins-power {
 706			pinmux = <PINMUX_GPIO91__FUNC_GPIO91>,
 707				 <PINMUX_GPIO92__FUNC_GPIO92>;
 708			output-high;
 709		};
 710
 711		pins-rxd {
 712			pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>,
 713				 <PINMUX_GPIO82__FUNC_GBE_RXD2>,
 714				 <PINMUX_GPIO83__FUNC_GBE_RXD1>,
 715				 <PINMUX_GPIO84__FUNC_GBE_RXD0>;
 716		};
 717
 718		pins-txd {
 719			pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>,
 720				 <PINMUX_GPIO78__FUNC_GBE_TXD2>,
 721				 <PINMUX_GPIO79__FUNC_GBE_TXD1>,
 722				 <PINMUX_GPIO80__FUNC_GBE_TXD0>;
 723			drive-strength = <8>;
 724		};
 725	};
 726
 727	eth_sleep_pins: eth-sleep-pins {
 728		pins-cc {
 729			pinmux = <PINMUX_GPIO85__FUNC_GPIO85>,
 730				 <PINMUX_GPIO86__FUNC_GPIO86>,
 731				 <PINMUX_GPIO87__FUNC_GPIO87>,
 732				 <PINMUX_GPIO88__FUNC_GPIO88>;
 733		};
 734
 735		pins-mdio {
 736			pinmux = <PINMUX_GPIO89__FUNC_GPIO89>,
 737				 <PINMUX_GPIO90__FUNC_GPIO90>;
 738			input-disable;
 739			bias-disable;
 740		};
 741
 742		pins-rxd {
 743			pinmux = <PINMUX_GPIO81__FUNC_GPIO81>,
 744				 <PINMUX_GPIO82__FUNC_GPIO82>,
 745				 <PINMUX_GPIO83__FUNC_GPIO83>,
 746				 <PINMUX_GPIO84__FUNC_GPIO84>;
 747		};
 748
 749		pins-txd {
 750			pinmux = <PINMUX_GPIO77__FUNC_GPIO77>,
 751				 <PINMUX_GPIO78__FUNC_GPIO78>,
 752				 <PINMUX_GPIO79__FUNC_GPIO79>,
 753				 <PINMUX_GPIO80__FUNC_GPIO80>;
 754		};
 755	};
 756
 757	gpio_key_pins: gpio-keys-pins {
 758		pins {
 759			pinmux = <PINMUX_GPIO106__FUNC_GPIO106>;
 760			bias-pull-up;
 761			input-enable;
 762		};
 763	};
 764
 765	i2c0_pins: i2c0-pins {
 766		pins {
 767			pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
 768				 <PINMUX_GPIO9__FUNC_SCL0>;
 769			bias-pull-up = <MTK_PULL_SET_RSEL_111>;
 770			drive-strength-microamp = <1000>;
 771		};
 772	};
 773
 774	i2c1_pins: i2c1-pins {
 775		pins {
 776			pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
 777				 <PINMUX_GPIO11__FUNC_SCL1>;
 778			bias-pull-up = <MTK_PULL_SET_RSEL_111>;
 779			drive-strength-microamp = <1000>;
 780		};
 781	};
 782
 783	i2c2_pins: i2c2-pins {
 784		pins {
 785			pinmux = <PINMUX_GPIO12__FUNC_SDA2>,
 786				 <PINMUX_GPIO13__FUNC_SCL2>;
 787			bias-pull-up = <MTK_PULL_SET_RSEL_111>;
 788			drive-strength = <6>;
 789		};
 790	};
 791
 792	i2c6_pins: i2c6-pins {
 793		pins {
 794			pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
 795				 <PINMUX_GPIO26__FUNC_SCL6>;
 796			bias-pull-up;
 797		};
 798	};
 799
 800	mmc0_default_pins: mmc0-default-pins {
 801		pins-clk {
 802			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
 803			drive-strength = <6>;
 804			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 805		};
 806
 807		pins-cmd-dat {
 808			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
 809				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
 810				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
 811				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
 812				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
 813				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
 814				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
 815				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
 816				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
 817			input-enable;
 818			drive-strength = <6>;
 819			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 820		};
 821
 822		pins-rst {
 823			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
 824			drive-strength = <6>;
 825			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 826		};
 827	};
 828
 829	mmc0_uhs_pins: mmc0-uhs-pins {
 830		pins-clk {
 831			pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>;
 832			drive-strength = <8>;
 833			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 834		};
 835
 836		pins-cmd-dat {
 837			pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>,
 838				 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>,
 839				 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>,
 840				 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>,
 841				 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>,
 842				 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>,
 843				 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>,
 844				 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>,
 845				 <PINMUX_GPIO121__FUNC_MSDC0_CMD>;
 846			input-enable;
 847			drive-strength = <8>;
 848			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 849		};
 850
 851		pins-ds {
 852			pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>;
 853			drive-strength = <8>;
 854			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 855		};
 856
 857		pins-rst {
 858			pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>;
 859			drive-strength = <8>;
 860			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 861		};
 862	};
 863
 864	mmc1_default_pins: mmc1-default-pins {
 865		pins-clk {
 866			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
 867			drive-strength = <8>;
 868			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 869		};
 870
 871		pins-cmd-dat {
 872			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
 873				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
 874				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
 875				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
 876				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
 877			input-enable;
 878			drive-strength = <8>;
 879			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 880		};
 881	};
 882
 883	mmc1_uhs_pins: mmc1-uhs-pins {
 884		pins-clk {
 885			pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>;
 886			drive-strength = <8>;
 887			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
 888		};
 889
 890		pins-cmd-dat {
 891			pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>,
 892				 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>,
 893				 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>,
 894				 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>,
 895				 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>;
 896			input-enable;
 897			drive-strength = <8>;
 898			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
 899		};
 900	};
 901
 902	mt6360_pins: mt6360-pins {
 903		pins {
 904			pinmux = <PINMUX_GPIO17__FUNC_GPIO17>,
 905				 <PINMUX_GPIO128__FUNC_GPIO128>;
 906			input-enable;
 907			bias-pull-up;
 908		};
 909	};
 910
 911	dsi0_vreg_en_pins: dsi0-vreg-en-pins {
 912		pins-pwr-en {
 913			pinmux = <PINMUX_GPIO47__FUNC_GPIO47>;
 914			output-low;
 915		};
 916	};
 917
 918	panel_default_pins: panel-default-pins {
 919		pins-rst {
 920			pinmux = <PINMUX_GPIO108__FUNC_GPIO108>;
 921			output-high;
 922		};
 923
 924		pins-en {
 925			pinmux = <PINMUX_GPIO48__FUNC_GPIO48>;
 926			output-low;
 927		};
 928	};
 929
 930	pcie0_default_pins: pcie0-default-pins {
 931		pins {
 932			pinmux = <PINMUX_GPIO19__FUNC_WAKEN>,
 933				 <PINMUX_GPIO20__FUNC_PERSTN>,
 934				 <PINMUX_GPIO21__FUNC_CLKREQN>;
 935			bias-pull-up;
 936		};
 937	};
 938
 939	pcie0_idle_pins: pcie0-idle-pins {
 940		pins {
 941			pinmux = <PINMUX_GPIO20__FUNC_GPIO20>;
 942			bias-disable;
 943			output-low;
 944		};
 945	};
 946
 947	pcie1_default_pins: pcie1-default-pins {
 948		pins {
 949			pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>,
 950				 <PINMUX_GPIO23__FUNC_CLKREQN_1>,
 951				 <PINMUX_GPIO24__FUNC_WAKEN_1>;
 952			bias-pull-up;
 953		};
 954	};
 955
 956	disp_pwm0_pins: disp-pwm0-pins {
 957		pins-disp-pwm {
 958			pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>;
 959		};
 960	};
 961
 962	spi1_pins: spi1-pins {
 963		pins {
 964			pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>,
 965				 <PINMUX_GPIO137__FUNC_SPIM1_CLK>,
 966				 <PINMUX_GPIO138__FUNC_SPIM1_MO>,
 967				 <PINMUX_GPIO139__FUNC_SPIM1_MI>;
 968			bias-disable;
 969		};
 970	};
 971
 972	spi2_pins: spi-pins {
 973		pins {
 974			pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>,
 975				 <PINMUX_GPIO141__FUNC_SPIM2_CLK>,
 976				 <PINMUX_GPIO142__FUNC_SPIM2_MO>,
 977				 <PINMUX_GPIO143__FUNC_SPIM2_MI>;
 978			bias-disable;
 979		};
 980	};
 981
 982	touch_pins: touch-pins {
 983		pins-irq {
 984			pinmux = <PINMUX_GPIO132__FUNC_GPIO132>;
 985			input-enable;
 986			bias-disable;
 987		};
 988
 989		pins-reset {
 990			pinmux = <PINMUX_GPIO133__FUNC_GPIO133>;
 991			output-high;
 992		};
 993	};
 994
 995	u3_p0_vbus: u3-p0-vbus-default-pins {
 996		pins-vbus {
 997			pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>;
 998			input-enable;
 999		};
1000	};
1001
1002	uart0_pins: uart0-pins {
1003		pins {
1004			pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
1005				 <PINMUX_GPIO99__FUNC_URXD0>;
1006		};
1007	};
1008
1009	uart1_pins: uart1-pins {
1010		pins {
1011			pinmux = <PINMUX_GPIO100__FUNC_URTS1>,
1012				 <PINMUX_GPIO101__FUNC_UCTS1>,
1013				 <PINMUX_GPIO102__FUNC_UTXD1>,
1014				 <PINMUX_GPIO103__FUNC_URXD1>;
1015		};
1016	};
1017};
1018
1019&pmic {
1020	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
1021
1022	mt6359keys: keys {
1023		compatible = "mediatek,mt6359-keys";
1024		mediatek,long-press-mode = <1>;
1025		power-off-time-sec = <0>;
1026
1027		power-key {
1028			linux,keycodes = <KEY_POWER>;
1029			wakeup-source;
1030		};
1031
1032		home {
1033			linux,keycodes = <KEY_HOME>;
1034		};
1035	};
1036};
1037
1038&scp {
1039	memory-region = <&scp_mem>;
1040	firmware-name = "mediatek/mt8195/scp.img";
1041	status = "okay";
1042};
1043
1044&sound {
1045	compatible = "mediatek,mt8195_mt6359";
1046	model = "mt8395-evk";
1047	pinctrl-names = "default";
1048	pinctrl-0 = <&audio_default_pins>;
1049	audio-routing =
1050		"Headphone", "Headphone L",
1051		"Headphone", "Headphone R";
1052	mediatek,adsp = <&adsp>;
1053	status = "okay";
1054
1055	headphone-dai-link {
1056		link-name = "DL_SRC_BE";
1057
1058		codec {
1059			sound-dai = <&pmic 0>;
1060		};
1061	};
1062};
1063
1064&spi1 {
1065	pinctrl-0 = <&spi1_pins>;
1066	pinctrl-names = "default";
1067	mediatek,pad-select = <0>;
1068	#address-cells = <1>;
1069	#size-cells = <0>;
1070	status = "okay";
1071	cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>;
1072
1073	can0: can@0 {
1074		compatible = "microchip,mcp2518fd";
1075		reg = <0>;
1076		clocks = <&can_clk>;
1077		spi-max-frequency = <20000000>;
1078		interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>;
1079		vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>;
1080		xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>;
1081	};
1082};
1083
1084&spi2 {
1085	pinctrl-0 = <&spi2_pins>;
1086	pinctrl-names = "default";
1087	mediatek,pad-select = <0>;
1088	#address-cells = <1>;
1089	#size-cells = <0>;
1090	status = "okay";
1091};
1092
1093&spmi {
1094	#address-cells = <2>;
1095	#size-cells = <0>;
1096
1097	mt6315_6: pmic@6 {
1098		compatible = "mediatek,mt6315-regulator";
1099		reg = <0x6 SPMI_USID>;
1100
1101		regulators {
1102			mt6315_6_vbuck1: vbuck1 {
1103				regulator-name = "Vbcpu";
1104				regulator-min-microvolt = <300000>;
1105				regulator-max-microvolt = <1193750>;
1106				regulator-enable-ramp-delay = <256>;
1107				regulator-allowed-modes = <0 1 2>;
1108				regulator-always-on;
1109			};
1110		};
1111	};
1112
1113	mt6315_7: pmic@7 {
1114		compatible = "mediatek,mt6315-regulator";
1115		reg = <0x7 SPMI_USID>;
1116
1117		regulators {
1118			mt6315_7_vbuck1: vbuck1 {
1119				regulator-name = "Vgpu";
1120				regulator-min-microvolt = <546000>;
1121				regulator-max-microvolt = <787000>;
1122				regulator-enable-ramp-delay = <256>;
1123				regulator-allowed-modes = <0 1 2>;
1124			};
1125		};
1126	};
1127};
1128
1129&u3phy0 {
1130	status = "okay";
1131};
1132
1133&u3phy1 {
1134	status = "okay";
1135
1136	u3port1: usb-phy@700 {
1137		mediatek,force-mode;
1138	};
1139};
1140
1141&u3phy2 {
1142	status = "okay";
1143};
1144
1145&u3phy3 {
1146	status = "okay";
1147};
1148
1149&uart0 {
1150	pinctrl-0 = <&uart0_pins>;
1151	pinctrl-names = "default";
1152	status = "okay";
1153};
1154
1155&uart1 {
1156	pinctrl-0 = <&uart1_pins>;
1157	pinctrl-names = "default";
1158	status = "okay";
1159};
1160
1161&ufsphy {
1162	status = "disabled";
1163};
1164
1165&ssusb0 {
1166	dr_mode = "otg";
1167	pinctrl-names = "default";
1168	pinctrl-0 = <&u3_p0_vbus>;
1169	usb-role-switch;
1170	vusb33-supply = <&mt6359_vusb_ldo_reg>;
1171	status = "okay";
1172
1173	ports {
1174		#address-cells = <1>;
1175		#size-cells = <0>;
1176
1177		port@0 {
1178			reg = <0>;
1179			mtu3_hs0_role_sw: endpoint {
1180				remote-endpoint = <&typec_con_hs>;
1181			};
1182		};
1183
1184		port@1 {
1185			reg = <1>;
1186			mtu3_ss0_role_sw: endpoint {
1187				remote-endpoint = <&typec_con_ss>;
1188			};
1189		};
1190	};
1191};
1192
1193&ssusb2 {
1194	vusb33-supply = <&mt6359_vusb_ldo_reg>;
1195	status = "okay";
1196};
1197
1198&ssusb3 {
1199	vusb33-supply = <&mt6359_vusb_ldo_reg>;
1200	status = "okay";
1201};
1202
1203&vdosys0 {
1204	port {
1205		#address-cells = <1>;
1206		#size-cells = <0>;
1207
1208		vdosys0_ep_main: endpoint@0 {
1209			reg = <0>;
1210			remote-endpoint = <&ovl0_in>;
1211		};
1212	};
1213};
1214
1215&xhci0 {
1216	status = "okay";
1217};
1218
1219&xhci1 {
1220	vusb33-supply = <&mt6359_vusb_ldo_reg>;
1221	status = "okay";
1222};
1223
1224&xhci2 {
1225	status = "okay";
1226};
1227
1228&xhci3 {
1229	status = "okay";
1230};