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mt8365.dtsi
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linux-6.19.14/arch/arm64/boot/dts/mediatek/mt8365.dtsi
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * (C) 2018 MediaTek Inc. 4 * Copyright (C) 2022 BayLibre SAS 5 * Authors: Fabien Parent <fparent@baylibre.com> 6 * Bernhard Rosenkränzer <bero@baylibre.com> 7 * Alexandre Mergnat <amergnat@baylibre.com> 8 */ 9 10#include <dt-bindings/clock/mediatek,mt8365-clk.h> 11#include <dt-bindings/interrupt-controller/arm-gic.h> 12#include <dt-bindings/interrupt-controller/irq.h> 13#include <dt-bindings/memory/mediatek,mt8365-larb-port.h> 14#include <dt-bindings/phy/phy.h> 15#include <dt-bindings/power/mediatek,mt8365-power.h> 16 17/ { 18 compatible = "mediatek,mt8365"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 aal0 = &aal0; 25 ccorr0 = &ccorr0; 26 color0 = &color0; 27 dither0 = &dither0; 28 dpi0 = &dpi0; 29 dsi0 = &dsi0; 30 gamma0 = &gamma0; 31 ovl0 = &ovl0; 32 rdma0 = &rdma0; 33 rdma1 = &rdma1; 34 }; 35 36 cpus { 37 #address-cells = <1>; 38 #size-cells = <0>; 39 40 cluster0_opp: opp-table-0 { 41 compatible = "operating-points-v2"; 42 opp-shared; 43 44 opp-850000000 { 45 opp-hz = /bits/ 64 <850000000>; 46 opp-microvolt = <650000>; 47 }; 48 49 opp-918000000 { 50 opp-hz = /bits/ 64 <918000000>; 51 opp-microvolt = <668750>; 52 }; 53 54 opp-987000000 { 55 opp-hz = /bits/ 64 <987000000>; 56 opp-microvolt = <687500>; 57 }; 58 59 opp-1056000000 { 60 opp-hz = /bits/ 64 <1056000000>; 61 opp-microvolt = <706250>; 62 }; 63 64 opp-1125000000 { 65 opp-hz = /bits/ 64 <1125000000>; 66 opp-microvolt = <725000>; 67 }; 68 69 opp-1216000000 { 70 opp-hz = /bits/ 64 <1216000000>; 71 opp-microvolt = <750000>; 72 }; 73 74 opp-1308000000 { 75 opp-hz = /bits/ 64 <1308000000>; 76 opp-microvolt = <775000>; 77 }; 78 79 opp-1400000000 { 80 opp-hz = /bits/ 64 <1400000000>; 81 opp-microvolt = <800000>; 82 }; 83 84 opp-1466000000 { 85 opp-hz = /bits/ 64 <1466000000>; 86 opp-microvolt = <825000>; 87 }; 88 89 opp-1533000000 { 90 opp-hz = /bits/ 64 <1533000000>; 91 opp-microvolt = <850000>; 92 }; 93 94 opp-1633000000 { 95 opp-hz = /bits/ 64 <1633000000>; 96 opp-microvolt = <887500>; 97 }; 98 99 opp-1700000000 { 100 opp-hz = /bits/ 64 <1700000000>; 101 opp-microvolt = <912500>; 102 }; 103 104 opp-1767000000 { 105 opp-hz = /bits/ 64 <1767000000>; 106 opp-microvolt = <937500>; 107 }; 108 109 opp-1834000000 { 110 opp-hz = /bits/ 64 <1834000000>; 111 opp-microvolt = <962500>; 112 }; 113 114 opp-1917000000 { 115 opp-hz = /bits/ 64 <1917000000>; 116 opp-microvolt = <993750>; 117 }; 118 119 opp-2001000000 { 120 opp-hz = /bits/ 64 <2001000000>; 121 opp-microvolt = <1025000>; 122 }; 123 }; 124 125 cpu-map { 126 cluster0 { 127 core0 { 128 cpu = <&cpu0>; 129 }; 130 core1 { 131 cpu = <&cpu1>; 132 }; 133 core2 { 134 cpu = <&cpu2>; 135 }; 136 core3 { 137 cpu = <&cpu3>; 138 }; 139 }; 140 }; 141 142 cpu0: cpu@0 { 143 device_type = "cpu"; 144 compatible = "arm,cortex-a53"; 145 reg = <0x0>; 146 #cooling-cells = <2>; 147 enable-method = "psci"; 148 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 149 i-cache-size = <0x8000>; 150 i-cache-line-size = <64>; 151 i-cache-sets = <256>; 152 d-cache-size = <0x8000>; 153 d-cache-line-size = <64>; 154 d-cache-sets = <256>; 155 next-level-cache = <&l2>; 156 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 157 <&apmixedsys CLK_APMIXED_MAINPLL>; 158 clock-names = "cpu", "intermediate"; 159 operating-points-v2 = <&cluster0_opp>; 160 }; 161 162 cpu1: cpu@1 { 163 device_type = "cpu"; 164 compatible = "arm,cortex-a53"; 165 reg = <0x1>; 166 #cooling-cells = <2>; 167 enable-method = "psci"; 168 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 169 i-cache-size = <0x8000>; 170 i-cache-line-size = <64>; 171 i-cache-sets = <256>; 172 d-cache-size = <0x8000>; 173 d-cache-line-size = <64>; 174 d-cache-sets = <256>; 175 next-level-cache = <&l2>; 176 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 177 <&apmixedsys CLK_APMIXED_MAINPLL>; 178 clock-names = "cpu", "intermediate", "armpll"; 179 operating-points-v2 = <&cluster0_opp>; 180 }; 181 182 cpu2: cpu@2 { 183 device_type = "cpu"; 184 compatible = "arm,cortex-a53"; 185 reg = <0x2>; 186 #cooling-cells = <2>; 187 enable-method = "psci"; 188 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 189 i-cache-size = <0x8000>; 190 i-cache-line-size = <64>; 191 i-cache-sets = <256>; 192 d-cache-size = <0x8000>; 193 d-cache-line-size = <64>; 194 d-cache-sets = <256>; 195 next-level-cache = <&l2>; 196 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 197 <&apmixedsys CLK_APMIXED_MAINPLL>; 198 clock-names = "cpu", "intermediate", "armpll"; 199 operating-points-v2 = <&cluster0_opp>; 200 }; 201 202 cpu3: cpu@3 { 203 device_type = "cpu"; 204 compatible = "arm,cortex-a53"; 205 reg = <0x3>; 206 #cooling-cells = <2>; 207 enable-method = "psci"; 208 cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>; 209 i-cache-size = <0x8000>; 210 i-cache-line-size = <64>; 211 i-cache-sets = <256>; 212 d-cache-size = <0x8000>; 213 d-cache-line-size = <64>; 214 d-cache-sets = <256>; 215 next-level-cache = <&l2>; 216 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 217 <&apmixedsys CLK_APMIXED_MAINPLL>; 218 clock-names = "cpu", "intermediate", "armpll"; 219 operating-points-v2 = <&cluster0_opp>; 220 }; 221 222 idle-states { 223 entry-method = "psci"; 224 225 CPU_MCDI: cpu-mcdi { 226 compatible = "arm,idle-state"; 227 local-timer-stop; 228 arm,psci-suspend-param = <0x00010001>; 229 entry-latency-us = <300>; 230 exit-latency-us = <200>; 231 min-residency-us = <1000>; 232 }; 233 234 CLUSTER_MCDI: cluster-mcdi { 235 compatible = "arm,idle-state"; 236 local-timer-stop; 237 arm,psci-suspend-param = <0x01010001>; 238 entry-latency-us = <350>; 239 exit-latency-us = <250>; 240 min-residency-us = <1200>; 241 }; 242 243 CLUSTER_DPIDLE: cluster-dpidle { 244 compatible = "arm,idle-state"; 245 local-timer-stop; 246 arm,psci-suspend-param = <0x01010004>; 247 entry-latency-us = <300>; 248 exit-latency-us = <800>; 249 min-residency-us = <3300>; 250 }; 251 }; 252 253 l2: l2-cache { 254 compatible = "cache"; 255 cache-level = <2>; 256 cache-size = <0x80000>; 257 cache-line-size = <64>; 258 cache-sets = <512>; 259 cache-unified; 260 }; 261 }; 262 263 clk26m: oscillator { 264 compatible = "fixed-clock"; 265 #clock-cells = <0>; 266 clock-frequency = <26000000>; 267 clock-output-names = "clk26m"; 268 }; 269 270 gpu_opp_table: opp-table-gpu { 271 compatible = "operating-points-v2"; 272 opp-shared; 273 274 opp-450000000 { 275 opp-hz = /bits/ 64 <450000000>; 276 opp-microvolt = <650000>; 277 }; 278 279 opp-560000000 { 280 opp-hz = /bits/ 64 <560000000>; 281 opp-microvolt = <700000>; 282 }; 283 284 opp-800000000 { 285 opp-hz = /bits/ 64 <800000000>; 286 opp-microvolt = <800000>; 287 }; 288 }; 289 290 psci { 291 compatible = "arm,psci-1.0"; 292 method = "smc"; 293 }; 294 295 soc { 296 #address-cells = <2>; 297 #size-cells = <2>; 298 compatible = "simple-bus"; 299 ranges; 300 301 gic: interrupt-controller@c000000 { 302 compatible = "arm,gic-v3"; 303 #interrupt-cells = <3>; 304 interrupt-parent = <&gic>; 305 interrupt-controller; 306 reg = <0 0x0c000000 0 0x10000>, /* GICD */ 307 <0 0x0c080000 0 0x80000>, /* GICR */ 308 <0 0x0c400000 0 0x2000>, /* GICC */ 309 <0 0x0c410000 0 0x1000>, /* GICH */ 310 <0 0x0c420000 0 0x2000>; /* GICV */ 311 312 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 313 }; 314 315 mfgcfg: syscon@13000000 { 316 compatible = "mediatek,mt8365-mfgcfg", "syscon"; 317 reg = <0 0x13000000 0 0x1000>; 318 #clock-cells = <1>; 319 }; 320 321 gpu: gpu@13040000 { 322 compatible = "mediatek,mt8365-mali", "arm,mali-bifrost"; 323 reg = <0 0x13040000 0 0x4000>; 324 325 clocks = <&mfgcfg CLK_MFG_BG3D>; 326 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>, 327 <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>, 328 <GIC_SPI 201 IRQ_TYPE_LEVEL_LOW>, 329 <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 330 interrupt-names = "job", "mmu", "gpu", "event"; 331 operating-points-v2 = <&gpu_opp_table>; 332 power-domains = <&spm MT8365_POWER_DOMAIN_MFG>; 333 status = "disabled"; 334 }; 335 336 topckgen: syscon@10000000 { 337 compatible = "mediatek,mt8365-topckgen", "syscon"; 338 reg = <0 0x10000000 0 0x1000>; 339 #clock-cells = <1>; 340 }; 341 342 infracfg: syscon@10001000 { 343 compatible = "mediatek,mt8365-infracfg", "syscon"; 344 reg = <0 0x10001000 0 0x1000>; 345 #clock-cells = <1>; 346 }; 347 348 pericfg: syscon@10003000 { 349 compatible = "mediatek,mt8365-pericfg", "syscon"; 350 reg = <0 0x10003000 0 0x1000>; 351 #clock-cells = <1>; 352 }; 353 354 syscfg_pctl: syscfg-pctl@10005000 { 355 compatible = "mediatek,mt8365-syscfg", "syscon"; 356 reg = <0 0x10005000 0 0x1000>; 357 }; 358 359 scpsys: syscon@10006000 { 360 compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd"; 361 reg = <0 0x10006000 0 0x1000>; 362 363 /* System Power Manager */ 364 spm: power-controller { 365 compatible = "mediatek,mt8365-power-controller"; 366 #address-cells = <1>; 367 #size-cells = <0>; 368 #power-domain-cells = <1>; 369 370 /* power domains of the SoC */ 371 power-domain@MT8365_POWER_DOMAIN_MM { 372 reg = <MT8365_POWER_DOMAIN_MM>; 373 clocks = <&topckgen CLK_TOP_MM_SEL>, 374 <&mmsys CLK_MM_MM_SMI_COMMON>, 375 <&mmsys CLK_MM_MM_SMI_COMM0>, 376 <&mmsys CLK_MM_MM_SMI_COMM1>, 377 <&mmsys CLK_MM_MM_SMI_LARB0>; 378 clock-names = "mm", "mm-0", "mm-1", 379 "mm-2", "mm-3"; 380 #power-domain-cells = <0>; 381 mediatek,infracfg = <&infracfg>; 382 mediatek,infracfg-nao = <&infracfg_nao>; 383 #address-cells = <1>; 384 #size-cells = <0>; 385 386 power-domain@MT8365_POWER_DOMAIN_CAM { 387 reg = <MT8365_POWER_DOMAIN_CAM>; 388 clocks = <&camsys CLK_CAM_LARB2>, 389 <&camsys CLK_CAM_SENIF>, 390 <&camsys CLK_CAMSV0>, 391 <&camsys CLK_CAMSV1>, 392 <&camsys CLK_CAM_FDVT>, 393 <&camsys CLK_CAM_WPE>; 394 clock-names = "cam-0", "cam-1", 395 "cam-2", "cam-3", 396 "cam-4", "cam-5"; 397 #power-domain-cells = <0>; 398 mediatek,infracfg = <&infracfg>; 399 mediatek,smi = <&smi_common>; 400 }; 401 402 power-domain@MT8365_POWER_DOMAIN_VDEC { 403 reg = <MT8365_POWER_DOMAIN_VDEC>; 404 #power-domain-cells = <0>; 405 mediatek,smi = <&smi_common>; 406 }; 407 408 power-domain@MT8365_POWER_DOMAIN_VENC { 409 reg = <MT8365_POWER_DOMAIN_VENC>; 410 #power-domain-cells = <0>; 411 mediatek,smi = <&smi_common>; 412 }; 413 414 power-domain@MT8365_POWER_DOMAIN_APU { 415 reg = <MT8365_POWER_DOMAIN_APU>; 416 clocks = <&infracfg CLK_IFR_APU_AXI>, 417 <&apu CLK_APU_IPU_CK>, 418 <&apu CLK_APU_AXI>, 419 <&apu CLK_APU_JTAG>, 420 <&apu CLK_APU_IF_CK>, 421 <&apu CLK_APU_EDMA>, 422 <&apu CLK_APU_AHB>; 423 clock-names = "apu", "apu-0", 424 "apu-1", "apu-2", 425 "apu-3", "apu-4", 426 "apu-5"; 427 #power-domain-cells = <0>; 428 mediatek,infracfg = <&infracfg>; 429 mediatek,smi = <&smi_common>; 430 }; 431 }; 432 433 power-domain@MT8365_POWER_DOMAIN_CONN { 434 reg = <MT8365_POWER_DOMAIN_CONN>; 435 clocks = <&topckgen CLK_TOP_CONN_32K>, 436 <&topckgen CLK_TOP_CONN_26M>; 437 clock-names = "conn", "conn1"; 438 #power-domain-cells = <0>; 439 mediatek,infracfg = <&infracfg>; 440 }; 441 442 mfg: power-domain@MT8365_POWER_DOMAIN_MFG { 443 reg = <MT8365_POWER_DOMAIN_MFG>; 444 clocks = <&topckgen CLK_TOP_MFG_SEL>; 445 clock-names = "mfg"; 446 #power-domain-cells = <0>; 447 mediatek,infracfg = <&infracfg>; 448 }; 449 450 power-domain@MT8365_POWER_DOMAIN_AUDIO { 451 reg = <MT8365_POWER_DOMAIN_AUDIO>; 452 clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 453 <&infracfg CLK_IFR_AUDIO>, 454 <&infracfg CLK_IFR_AUD_26M_BK>; 455 clock-names = "audio", "audio1", "audio2"; 456 #power-domain-cells = <0>; 457 mediatek,infracfg = <&infracfg>; 458 }; 459 460 power-domain@MT8365_POWER_DOMAIN_DSP { 461 reg = <MT8365_POWER_DOMAIN_DSP>; 462 clocks = <&topckgen CLK_TOP_DSP_SEL>, 463 <&topckgen CLK_TOP_DSP_26M>; 464 clock-names = "dsp", "dsp1"; 465 #power-domain-cells = <0>; 466 mediatek,infracfg = <&infracfg>; 467 }; 468 }; 469 }; 470 471 watchdog: watchdog@10007000 { 472 compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt"; 473 reg = <0 0x10007000 0 0x100>; 474 #reset-cells = <1>; 475 }; 476 477 pio: pinctrl@1000b000 { 478 compatible = "mediatek,mt8365-pinctrl"; 479 reg = <0 0x1000b000 0 0x1000>; 480 mediatek,pctl-regmap = <&syscfg_pctl>; 481 gpio-controller; 482 #gpio-cells = <2>; 483 interrupt-controller; 484 #interrupt-cells = <2>; 485 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 486 }; 487 488 apmixedsys: syscon@1000c000 { 489 compatible = "mediatek,mt8365-apmixedsys", "syscon"; 490 reg = <0 0x1000c000 0 0x1000>; 491 #clock-cells = <1>; 492 }; 493 494 pwrap: pwrap@1000d000 { 495 compatible = "mediatek,mt8365-pwrap"; 496 reg = <0 0x1000d000 0 0x1000>; 497 reg-names = "pwrap"; 498 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 499 clocks = <&infracfg CLK_IFR_PWRAP_SPI>, 500 <&infracfg CLK_IFR_PMIC_AP>, 501 <&infracfg CLK_IFR_PWRAP_SYS>, 502 <&infracfg CLK_IFR_PWRAP_TMR>; 503 clock-names = "spi", "wrap", "sys", "tmr"; 504 }; 505 506 keypad: keypad@10010000 { 507 compatible = "mediatek,mt8365-keypad", 508 "mediatek,mt6779-keypad"; 509 reg = <0 0x10010000 0 0x1000>; 510 wakeup-source; 511 interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>; 512 clocks = <&clk26m>; 513 clock-names = "kpd"; 514 status = "disabled"; 515 }; 516 517 mcucfg: syscon@10200000 { 518 compatible = "mediatek,mt8365-mcucfg", "syscon"; 519 reg = <0 0x10200000 0 0x2000>; 520 #clock-cells = <1>; 521 }; 522 523 sysirq: interrupt-controller@10200a80 { 524 compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq"; 525 interrupt-controller; 526 #interrupt-cells = <3>; 527 interrupt-parent = <&gic>; 528 reg = <0 0x10200a80 0 0x20>; 529 }; 530 531 iommu: iommu@10205000 { 532 compatible = "mediatek,mt8365-m4u"; 533 reg = <0 0x10205000 0 0x1000>; 534 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_LOW>; 535 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>; 536 #iommu-cells = <1>; 537 }; 538 539 infracfg_nao: infracfg@1020e000 { 540 compatible = "mediatek,mt8365-infracfg", "syscon"; 541 reg = <0 0x1020e000 0 0x1000>; 542 #clock-cells = <1>; 543 }; 544 545 rng: rng@1020f000 { 546 compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng"; 547 reg = <0 0x1020f000 0 0x100>; 548 clocks = <&infracfg CLK_IFR_TRNG>; 549 clock-names = "rng"; 550 }; 551 552 apdma: dma-controller@11000280 { 553 compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma"; 554 reg = <0 0x11000280 0 0x80>, 555 <0 0x11000300 0 0x80>, 556 <0 0x11000380 0 0x80>, 557 <0 0x11000400 0 0x80>, 558 <0 0x11000580 0 0x80>, 559 <0 0x11000600 0 0x80>; 560 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>, 561 <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>, 562 <GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>, 563 <GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>, 564 <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>, 565 <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>; 566 dma-requests = <6>; 567 clocks = <&infracfg CLK_IFR_AP_DMA>; 568 clock-names = "apdma"; 569 #dma-cells = <1>; 570 }; 571 572 uart0: serial@11002000 { 573 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 574 reg = <0 0x11002000 0 0x1000>; 575 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>; 576 clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; 577 clock-names = "baud", "bus"; 578 dmas = <&apdma 0>, <&apdma 1>; 579 dma-names = "tx", "rx"; 580 status = "disabled"; 581 }; 582 583 uart1: serial@11003000 { 584 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 585 reg = <0 0x11003000 0 0x1000>; 586 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>; 587 clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; 588 clock-names = "baud", "bus"; 589 dmas = <&apdma 2>, <&apdma 3>; 590 dma-names = "tx", "rx"; 591 status = "disabled"; 592 }; 593 594 uart2: serial@11004000 { 595 compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart"; 596 reg = <0 0x11004000 0 0x1000>; 597 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>; 598 clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; 599 clock-names = "baud", "bus"; 600 dmas = <&apdma 4>, <&apdma 5>; 601 dma-names = "tx", "rx"; 602 status = "disabled"; 603 }; 604 605 pwm: pwm@11006000 { 606 compatible = "mediatek,mt8365-pwm"; 607 reg = <0 0x11006000 0 0x1000>; 608 #pwm-cells = <2>; 609 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 610 clocks = <&infracfg CLK_IFR_PWM_HCLK>, 611 <&infracfg CLK_IFR_PWM>, 612 <&infracfg CLK_IFR_PWM1>, 613 <&infracfg CLK_IFR_PWM2>, 614 <&infracfg CLK_IFR_PWM3>; 615 clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; 616 }; 617 618 i2c0: i2c@11007000 { 619 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 620 reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>; 621 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>; 622 clock-div = <1>; 623 clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>; 624 clock-names = "main", "dma"; 625 #address-cells = <1>; 626 #size-cells = <0>; 627 status = "disabled"; 628 }; 629 630 i2c1: i2c@11008000 { 631 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 632 reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>; 633 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>; 634 clock-div = <1>; 635 clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>; 636 clock-names = "main", "dma"; 637 #address-cells = <1>; 638 #size-cells = <0>; 639 status = "disabled"; 640 }; 641 642 i2c2: i2c@11009000 { 643 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 644 reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>; 645 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>; 646 clock-div = <1>; 647 clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>; 648 clock-names = "main", "dma"; 649 #address-cells = <1>; 650 #size-cells = <0>; 651 status = "disabled"; 652 }; 653 654 spi: spi@1100a000 { 655 compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi"; 656 reg = <0 0x1100a000 0 0x100>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>; 660 clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 661 <&topckgen CLK_TOP_SPI_SEL>, 662 <&infracfg CLK_IFR_SPI0>; 663 clock-names = "parent-clk", "sel-clk", "spi-clk"; 664 status = "disabled"; 665 }; 666 667 disp_pwm: pwm@1100e000 { 668 compatible = "mediatek,mt8365-disp-pwm", "mediatek,mt8183-disp-pwm"; 669 reg = <0 0x1100e000 0 0x1000>; 670 clock-names = "main", "mm"; 671 clocks = <&topckgen CLK_TOP_DISP_PWM_SEL>, <&infracfg CLK_IFR_DISP_PWM>; 672 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 673 #pwm-cells = <2>; 674 }; 675 676 i2c3: i2c@1100f000 { 677 compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c"; 678 reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>; 679 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>; 680 clock-div = <1>; 681 clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>; 682 clock-names = "main", "dma"; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 status = "disabled"; 686 }; 687 688 ssusb: usb@11201000 { 689 compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; 690 reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>; 691 reg-names = "mac", "ippc"; 692 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>; 693 phys = <&u2port0 PHY_TYPE_USB2>, 694 <&u2port1 PHY_TYPE_USB2>; 695 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 696 <&infracfg CLK_IFR_SSUSB_REF>, 697 <&infracfg CLK_IFR_SSUSB_SYS>, 698 <&infracfg CLK_IFR_ICUSB>; 699 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 700 #address-cells = <2>; 701 #size-cells = <2>; 702 ranges; 703 status = "disabled"; 704 705 usb_host: usb@11200000 { 706 compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci"; 707 reg = <0 0x11200000 0 0x1000>; 708 reg-names = "mac"; 709 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>; 710 clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, 711 <&infracfg CLK_IFR_SSUSB_REF>, 712 <&infracfg CLK_IFR_SSUSB_SYS>, 713 <&infracfg CLK_IFR_ICUSB>, 714 <&infracfg CLK_IFR_SSUSB_XHCI>; 715 clock-names = "sys_ck", "ref_ck", "mcu_ck", 716 "dma_ck", "xhci_ck"; 717 status = "disabled"; 718 }; 719 }; 720 721 mmc0: mmc@11230000 { 722 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 723 reg = <0 0x11230000 0 0x1000>, 724 <0 0x11cd0000 0 0x1000>; 725 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>; 726 clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, 727 <&infracfg CLK_IFR_MSDC0_HCLK>, 728 <&infracfg CLK_IFR_MSDC0_SRC>; 729 clock-names = "source", "hclk", "source_cg"; 730 status = "disabled"; 731 }; 732 733 mmc1: mmc@11240000 { 734 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 735 reg = <0 0x11240000 0 0x1000>, 736 <0 0x11c90000 0 0x1000>; 737 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>; 738 clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, 739 <&infracfg CLK_IFR_MSDC1_HCLK>, 740 <&infracfg CLK_IFR_MSDC1_SRC>; 741 clock-names = "source", "hclk", "source_cg"; 742 status = "disabled"; 743 }; 744 745 mmc2: mmc@11250000 { 746 compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; 747 reg = <0 0x11250000 0 0x1000>, 748 <0 0x11c60000 0 0x1000>; 749 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>; 750 clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>, 751 <&infracfg CLK_IFR_MSDC2_HCLK>, 752 <&infracfg CLK_IFR_MSDC2_SRC>, 753 <&infracfg CLK_IFR_MSDC2_BK>, 754 <&infracfg CLK_IFR_AP_MSDC0>; 755 clock-names = "source", "hclk", "source_cg", 756 "bus_clk", "sys_cg"; 757 status = "disabled"; 758 }; 759 760 ethernet: ethernet@112a0000 { 761 compatible = "mediatek,mt8365-eth"; 762 reg = <0 0x112a0000 0 0x1000>; 763 mediatek,pericfg = <&infracfg>; 764 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 765 clocks = <&topckgen CLK_TOP_ETH_SEL>, 766 <&infracfg CLK_IFR_NIC_AXI>, 767 <&infracfg CLK_IFR_NIC_SLV_AXI>; 768 clock-names = "core", "reg", "trans"; 769 status = "disabled"; 770 }; 771 772 mipi_tx0: dsi-phy@11c00000 { 773 compatible = "mediatek,mt8365-mipi-tx", "mediatek,mt8183-mipi-tx"; 774 reg = <0 0x11c00000 0 0x800>; 775 clock-output-names = "mipi_tx0_pll"; 776 clocks = <&clk26m>; 777 #clock-cells = <0>; 778 #phy-cells = <0>; 779 }; 780 781 u3phy: t-phy@11cc0000 { 782 compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2"; 783 #address-cells = <1>; 784 #size-cells = <1>; 785 ranges = <0 0 0x11cc0000 0x9000>; 786 787 u2port0: usb-phy@0 { 788 reg = <0x0 0x400>; 789 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 790 <&topckgen CLK_TOP_USB20_48M_EN>; 791 clock-names = "ref", "da_ref"; 792 #phy-cells = <1>; 793 }; 794 795 u2port1: usb-phy@1000 { 796 reg = <0x1000 0x400>; 797 clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, 798 <&topckgen CLK_TOP_USB20_48M_EN>; 799 clock-names = "ref", "da_ref"; 800 #phy-cells = <1>; 801 }; 802 }; 803 804 mmsys: syscon@14000000 { 805 compatible = "mediatek,mt8365-mmsys", "syscon"; 806 reg = <0 0x14000000 0 0x1000>; 807 #clock-cells = <1>; 808 port { 809 #address-cells = <1>; 810 #size-cells = <0>; 811 812 mmsys_main: endpoint@0 { 813 reg = <0>; 814 remote-endpoint = <&ovl0_in>; 815 }; 816 mmsys_ext: endpoint@1 { 817 reg = <1>; 818 remote-endpoint = <&rdma1_in>; 819 }; 820 }; 821 }; 822 823 mutex: mutex@14001000 { 824 compatible = "mediatek,mt8365-disp-mutex"; 825 reg = <0 0x14001000 0 0x1000>; 826 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_LOW>; 827 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 828 }; 829 830 smi_common: smi@14002000 { 831 compatible = "mediatek,mt8365-smi-common"; 832 reg = <0 0x14002000 0 0x1000>; 833 clocks = <&mmsys CLK_MM_MM_SMI_COMMON>, 834 <&mmsys CLK_MM_MM_SMI_COMMON>, 835 <&mmsys CLK_MM_MM_SMI_COMM0>, 836 <&mmsys CLK_MM_MM_SMI_COMM1>; 837 clock-names = "apb", "smi", "gals0", "gals1"; 838 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 839 }; 840 841 larb0: larb@14003000 { 842 compatible = "mediatek,mt8365-smi-larb", 843 "mediatek,mt8186-smi-larb"; 844 reg = <0 0x14003000 0 0x1000>; 845 mediatek,smi = <&smi_common>; 846 clocks = <&mmsys CLK_MM_MM_SMI_LARB0>, 847 <&mmsys CLK_MM_MM_SMI_LARB0>; 848 clock-names = "apb", "smi"; 849 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 850 mediatek,larb-id = <0>; 851 }; 852 853 ovl0: ovl@1400b000 { 854 compatible = "mediatek,mt8365-disp-ovl", "mediatek,mt8192-disp-ovl"; 855 reg = <0 0x1400b000 0 0x1000>; 856 clocks = <&mmsys CLK_MM_MM_DISP_OVL0>; 857 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 858 iommus = <&iommu M4U_PORT_DISP_OVL0>; 859 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 860 ports { 861 #address-cells = <1>; 862 #size-cells = <0>; 863 864 port@0 { 865 #address-cells = <1>; 866 #size-cells = <0>; 867 reg = <0>; 868 ovl0_in: endpoint@0 { 869 reg = <0>; 870 remote-endpoint = <&mmsys_main>; 871 }; 872 }; 873 874 port@1 { 875 #address-cells = <1>; 876 #size-cells = <0>; 877 reg = <1>; 878 ovl0_out: endpoint@0 { 879 reg = <0>; 880 remote-endpoint = <&rdma0_in>; 881 }; 882 }; 883 }; 884 }; 885 886 rdma0: rdma@1400d000 { 887 compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; 888 reg = <0 0x1400d000 0 0x1000>; 889 clocks = <&mmsys CLK_MM_MM_DISP_RDMA0>; 890 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 891 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 892 mediatek,rdma-fifo-size = <5120>; 893 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 894 ports { 895 #address-cells = <1>; 896 #size-cells = <0>; 897 898 port@0 { 899 #address-cells = <1>; 900 #size-cells = <0>; 901 reg = <0>; 902 rdma0_in: endpoint@0 { 903 reg = <0>; 904 remote-endpoint = <&ovl0_out>; 905 }; 906 }; 907 908 port@1 { 909 #address-cells = <1>; 910 #size-cells = <0>; 911 reg = <1>; 912 rdma0_out: endpoint@0 { 913 reg = <0>; 914 remote-endpoint = <&color0_in>; 915 }; 916 }; 917 }; 918 }; 919 920 color0: color@1400f000 { 921 compatible = "mediatek,mt8365-disp-color", "mediatek,mt8173-disp-color"; 922 reg = <0 0x1400f000 0 0x1000>; 923 clocks = <&mmsys CLK_MM_MM_DISP_COLOR0>; 924 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>; 925 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 926 ports { 927 #address-cells = <1>; 928 #size-cells = <0>; 929 930 port@0 { 931 #address-cells = <1>; 932 #size-cells = <0>; 933 reg = <0>; 934 color0_in: endpoint@0 { 935 reg = <0>; 936 remote-endpoint = <&rdma0_out>; 937 }; 938 }; 939 940 port@1 { 941 #address-cells = <1>; 942 #size-cells = <0>; 943 reg = <1>; 944 color0_out: endpoint@0 { 945 reg = <0>; 946 remote-endpoint = <&ccorr0_in>; 947 }; 948 }; 949 }; 950 }; 951 952 ccorr0: ccorr@14010000 { 953 compatible = "mediatek,mt8365-disp-ccorr", "mediatek,mt8183-disp-ccorr"; 954 reg = <0 0x14010000 0 0x1000>; 955 clocks = <&mmsys CLK_MM_MM_DISP_CCORR0>; 956 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>; 957 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 958 ports { 959 #address-cells = <1>; 960 #size-cells = <0>; 961 962 port@0 { 963 #address-cells = <1>; 964 #size-cells = <0>; 965 reg = <0>; 966 ccorr0_in: endpoint@0 { 967 reg = <0>; 968 remote-endpoint = <&color0_out>; 969 }; 970 }; 971 972 port@1 { 973 #address-cells = <1>; 974 #size-cells = <0>; 975 reg = <1>; 976 ccorr0_out: endpoint@0 { 977 reg = <0>; 978 remote-endpoint = <&aal0_in>; 979 }; 980 }; 981 }; 982 }; 983 984 aal0: aal@14011000 { 985 compatible = "mediatek,mt8365-disp-aal", "mediatek,mt8183-disp-aal"; 986 reg = <0 0x14011000 0 0x1000>; 987 clocks = <&mmsys CLK_MM_MM_DISP_AAL0>; 988 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 989 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 990 ports { 991 #address-cells = <1>; 992 #size-cells = <0>; 993 994 port@0 { 995 #address-cells = <1>; 996 #size-cells = <0>; 997 reg = <0>; 998 aal0_in: endpoint@0 { 999 reg = <0>; 1000 remote-endpoint = <&ccorr0_out>; 1001 }; 1002 }; 1003 1004 port@1 { 1005 #address-cells = <1>; 1006 #size-cells = <0>; 1007 reg = <1>; 1008 aal0_out: endpoint@0 { 1009 reg = <0>; 1010 remote-endpoint = <&gamma0_in>; 1011 }; 1012 }; 1013 }; 1014 }; 1015 1016 gamma0: gamma@14012000 { 1017 compatible = "mediatek,mt8365-disp-gamma", "mediatek,mt8183-disp-gamma"; 1018 reg = <0 0x14012000 0 0x1000>; 1019 clocks = <&mmsys CLK_MM_MM_DISP_GAMMA0>; 1020 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 1021 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1022 ports { 1023 #address-cells = <1>; 1024 #size-cells = <0>; 1025 1026 port@0 { 1027 #address-cells = <1>; 1028 #size-cells = <0>; 1029 reg = <0>; 1030 gamma0_in: endpoint@0 { 1031 reg = <0>; 1032 remote-endpoint = <&aal0_out>; 1033 }; 1034 }; 1035 1036 port@1 { 1037 #address-cells = <1>; 1038 #size-cells = <0>; 1039 reg = <1>; 1040 gamma0_out: endpoint@0 { 1041 reg = <0>; 1042 remote-endpoint = <&dither0_in>; 1043 }; 1044 }; 1045 }; 1046 }; 1047 1048 dither0: dither@14013000 { 1049 compatible = "mediatek,mt8365-disp-dither", "mediatek,mt8183-disp-dither"; 1050 reg = <0 0x14013000 0 0x1000>; 1051 clocks = <&mmsys CLK_MM_MM_DISP_DITHER0>; 1052 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; 1053 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1054 ports { 1055 #address-cells = <1>; 1056 #size-cells = <0>; 1057 1058 port@0 { 1059 #address-cells = <1>; 1060 #size-cells = <0>; 1061 reg = <0>; 1062 dither0_in: endpoint@0 { 1063 reg = <0>; 1064 remote-endpoint = <&gamma0_out>; 1065 }; 1066 }; 1067 1068 port@1 { 1069 #address-cells = <1>; 1070 #size-cells = <0>; 1071 reg = <1>; 1072 dither0_out: endpoint@0 { 1073 reg = <0>; 1074 }; 1075 }; 1076 }; 1077 }; 1078 1079 dsi0: dsi@14014000 { 1080 compatible = "mediatek,mt8365-dsi", "mediatek,mt8183-dsi"; 1081 reg = <0 0x14014000 0 0x1000>; 1082 clock-names = "engine", "digital", "hs"; 1083 clocks = <&mmsys CLK_MM_MM_DSI0>, 1084 <&mmsys CLK_MM_DSI0_DIG_DSI>, 1085 <&mipi_tx0>; 1086 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1087 phy-names = "dphy"; 1088 phys = <&mipi_tx0>; 1089 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1090 }; 1091 1092 rdma1: rdma@14016000 { 1093 compatible = "mediatek,mt8365-disp-rdma", "mediatek,mt8183-disp-rdma"; 1094 reg = <0 0x14016000 0 0x1000>; 1095 clocks = <&mmsys CLK_MM_MM_DISP_RDMA1>; 1096 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 1097 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1098 mediatek,rdma-fifo-size = <2048>; 1099 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1100 ports { 1101 #address-cells = <1>; 1102 #size-cells = <0>; 1103 1104 port@0 { 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 reg = <0>; 1108 rdma1_in: endpoint@1 { 1109 reg = <1>; 1110 remote-endpoint = <&mmsys_ext>; 1111 }; 1112 }; 1113 1114 port@1 { 1115 #address-cells = <1>; 1116 #size-cells = <0>; 1117 reg = <1>; 1118 rdma1_out: endpoint@1 { 1119 reg = <1>; 1120 }; 1121 }; 1122 }; 1123 }; 1124 1125 dpi0: dpi@14018000 { 1126 compatible = "mediatek,mt8365-dpi", "mediatek,mt8192-dpi"; 1127 reg = <0 0x14018000 0 0x1000>; 1128 clocks = <&mmsys CLK_MM_DPI0_DPI0>, 1129 <&mmsys CLK_MM_MM_DPI0>, 1130 <&apmixedsys CLK_APMIXED_LVDSPLL>; 1131 clock-names = "pixel", "engine", "pll"; 1132 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; 1133 power-domains = <&spm MT8365_POWER_DOMAIN_MM>; 1134 status = "disabled"; 1135 }; 1136 1137 camsys: syscon@15000000 { 1138 compatible = "mediatek,mt8365-imgsys", "syscon"; 1139 reg = <0 0x15000000 0 0x1000>; 1140 #clock-cells = <1>; 1141 }; 1142 1143 larb2: larb@15001000 { 1144 compatible = "mediatek,mt8365-smi-larb", 1145 "mediatek,mt8186-smi-larb"; 1146 reg = <0 0x15001000 0 0x1000>; 1147 mediatek,smi = <&smi_common>; 1148 clocks = <&mmsys CLK_MM_MM_SMI_IMG>, 1149 <&camsys CLK_CAM_LARB2>; 1150 clock-names = "apb", "smi"; 1151 power-domains = <&spm MT8365_POWER_DOMAIN_CAM>; 1152 mediatek,larb-id = <2>; 1153 }; 1154 1155 vdecsys: syscon@16000000 { 1156 compatible = "mediatek,mt8365-vdecsys", "syscon"; 1157 reg = <0 0x16000000 0 0x1000>; 1158 #clock-cells = <1>; 1159 }; 1160 1161 larb3: larb@16010000 { 1162 compatible = "mediatek,mt8365-smi-larb", 1163 "mediatek,mt8186-smi-larb"; 1164 reg = <0 0x16010000 0 0x1000>; 1165 mediatek,smi = <&smi_common>; 1166 clocks = <&vdecsys CLK_VDEC_LARB1>, 1167 <&vdecsys CLK_VDEC_LARB1>; 1168 clock-names = "apb", "smi"; 1169 power-domains = <&spm MT8365_POWER_DOMAIN_VDEC>; 1170 mediatek,larb-id = <3>; 1171 }; 1172 1173 vencsys: syscon@17000000 { 1174 compatible = "mediatek,mt8365-vencsys", "syscon"; 1175 reg = <0 0x17000000 0 0x1000>; 1176 #clock-cells = <1>; 1177 }; 1178 1179 larb1: larb@17010000 { 1180 compatible = "mediatek,mt8365-smi-larb", 1181 "mediatek,mt8186-smi-larb"; 1182 reg = <0 0x17010000 0 0x1000>; 1183 mediatek,smi = <&smi_common>; 1184 clocks = <&vencsys CLK_VENC>, <&vencsys CLK_VENC>; 1185 clock-names = "apb", "smi"; 1186 power-domains = <&spm MT8365_POWER_DOMAIN_VENC>; 1187 mediatek,larb-id = <1>; 1188 }; 1189 1190 apu: syscon@19020000 { 1191 compatible = "mediatek,mt8365-apu", "syscon"; 1192 reg = <0 0x19020000 0 0x1000>; 1193 #clock-cells = <1>; 1194 }; 1195 1196 afe: audio-controller@11220000 { 1197 compatible = "mediatek,mt8365-afe-pcm"; 1198 reg = <0 0x11220000 0 0x1000>; 1199 #sound-dai-cells = <0>; 1200 clocks = <&clk26m>, 1201 <&topckgen CLK_TOP_AUDIO_SEL>, 1202 <&topckgen CLK_TOP_AUD_I2S0_M>, 1203 <&topckgen CLK_TOP_AUD_I2S1_M>, 1204 <&topckgen CLK_TOP_AUD_I2S2_M>, 1205 <&topckgen CLK_TOP_AUD_I2S3_M>, 1206 <&topckgen CLK_TOP_AUD_ENGEN1_SEL>, 1207 <&topckgen CLK_TOP_AUD_ENGEN2_SEL>, 1208 <&topckgen CLK_TOP_AUD_1_SEL>, 1209 <&topckgen CLK_TOP_AUD_2_SEL>, 1210 <&topckgen CLK_TOP_APLL_I2S0_SEL>, 1211 <&topckgen CLK_TOP_APLL_I2S1_SEL>, 1212 <&topckgen CLK_TOP_APLL_I2S2_SEL>, 1213 <&topckgen CLK_TOP_APLL_I2S3_SEL>; 1214 clock-names = "top_clk26m_clk", 1215 "top_audio_sel", 1216 "audio_i2s0_m", 1217 "audio_i2s1_m", 1218 "audio_i2s2_m", 1219 "audio_i2s3_m", 1220 "engen1", 1221 "engen2", 1222 "aud1", 1223 "aud2", 1224 "i2s0_m_sel", 1225 "i2s1_m_sel", 1226 "i2s2_m_sel", 1227 "i2s3_m_sel"; 1228 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_LOW>; 1229 power-domains = <&spm MT8365_POWER_DOMAIN_AUDIO>; 1230 status = "disabled"; 1231 }; 1232 }; 1233 1234 timer { 1235 compatible = "arm,armv8-timer"; 1236 interrupt-parent = <&gic>; 1237 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1238 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1239 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1240 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1241 }; 1242 1243 system_clk: dummy13m { 1244 compatible = "fixed-clock"; 1245 clock-frequency = <13000000>; 1246 #clock-cells = <0>; 1247 }; 1248 1249 systimer: timer@10017000 { 1250 compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer"; 1251 reg = <0 0x10017000 0 0x100>; 1252 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 1253 clocks = <&system_clk>; 1254 clock-names = "clk13m"; 1255 }; 1256};
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