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mt8195.dtsi
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linux-6.19.14/arch/arm64/boot/dts/mediatek/mt8195.dtsi
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2021 MediaTek Inc. 4 * Author: Seiya Wang <seiya.wang@mediatek.com> 5 */ 6 7/dts-v1/; 8#include <dt-bindings/clock/mt8195-clk.h> 9#include <dt-bindings/gce/mt8195-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8195-memory-port.h> 13#include <dt-bindings/phy/phy.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/power/mt8195-power.h> 16#include <dt-bindings/reset/mt8195-resets.h> 17#include <dt-bindings/thermal/thermal.h> 18#include <dt-bindings/thermal/mediatek,lvts-thermal.h> 19 20/ { 21 compatible = "mediatek,mt8195"; 22 interrupt-parent = <&gic>; 23 #address-cells = <2>; 24 #size-cells = <2>; 25 26 aliases { 27 dp-intf0 = &dp_intf0; 28 dp-intf1 = &dp_intf1; 29 gce0 = &gce0; 30 gce1 = &gce1; 31 ethdr0 = ðdr0; 32 mutex0 = &mutex; 33 mutex1 = &mutex1; 34 merge1 = &merge1; 35 merge2 = &merge2; 36 merge3 = &merge3; 37 merge4 = &merge4; 38 merge5 = &merge5; 39 vdo1-rdma0 = &vdo1_rdma0; 40 vdo1-rdma1 = &vdo1_rdma1; 41 vdo1-rdma2 = &vdo1_rdma2; 42 vdo1-rdma3 = &vdo1_rdma3; 43 vdo1-rdma4 = &vdo1_rdma4; 44 vdo1-rdma5 = &vdo1_rdma5; 45 vdo1-rdma6 = &vdo1_rdma6; 46 vdo1-rdma7 = &vdo1_rdma7; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 cpu0: cpu@0 { 54 device_type = "cpu"; 55 compatible = "arm,cortex-a55"; 56 reg = <0x000>; 57 enable-method = "psci"; 58 performance-domains = <&performance 0>; 59 clock-frequency = <1701000000>; 60 capacity-dmips-mhz = <308>; 61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 62 i-cache-size = <32768>; 63 i-cache-line-size = <64>; 64 i-cache-sets = <128>; 65 d-cache-size = <32768>; 66 d-cache-line-size = <64>; 67 d-cache-sets = <128>; 68 next-level-cache = <&l2_0>; 69 #cooling-cells = <2>; 70 }; 71 72 cpu1: cpu@100 { 73 device_type = "cpu"; 74 compatible = "arm,cortex-a55"; 75 reg = <0x100>; 76 enable-method = "psci"; 77 performance-domains = <&performance 0>; 78 clock-frequency = <1701000000>; 79 capacity-dmips-mhz = <308>; 80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 81 i-cache-size = <32768>; 82 i-cache-line-size = <64>; 83 i-cache-sets = <128>; 84 d-cache-size = <32768>; 85 d-cache-line-size = <64>; 86 d-cache-sets = <128>; 87 next-level-cache = <&l2_0>; 88 #cooling-cells = <2>; 89 }; 90 91 cpu2: cpu@200 { 92 device_type = "cpu"; 93 compatible = "arm,cortex-a55"; 94 reg = <0x200>; 95 enable-method = "psci"; 96 performance-domains = <&performance 0>; 97 clock-frequency = <1701000000>; 98 capacity-dmips-mhz = <308>; 99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 100 i-cache-size = <32768>; 101 i-cache-line-size = <64>; 102 i-cache-sets = <128>; 103 d-cache-size = <32768>; 104 d-cache-line-size = <64>; 105 d-cache-sets = <128>; 106 next-level-cache = <&l2_0>; 107 #cooling-cells = <2>; 108 }; 109 110 cpu3: cpu@300 { 111 device_type = "cpu"; 112 compatible = "arm,cortex-a55"; 113 reg = <0x300>; 114 enable-method = "psci"; 115 performance-domains = <&performance 0>; 116 clock-frequency = <1701000000>; 117 capacity-dmips-mhz = <308>; 118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>; 119 i-cache-size = <32768>; 120 i-cache-line-size = <64>; 121 i-cache-sets = <128>; 122 d-cache-size = <32768>; 123 d-cache-line-size = <64>; 124 d-cache-sets = <128>; 125 next-level-cache = <&l2_0>; 126 #cooling-cells = <2>; 127 }; 128 129 cpu4: cpu@400 { 130 device_type = "cpu"; 131 compatible = "arm,cortex-a78"; 132 reg = <0x400>; 133 enable-method = "psci"; 134 performance-domains = <&performance 1>; 135 clock-frequency = <2171000000>; 136 capacity-dmips-mhz = <1024>; 137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 138 i-cache-size = <65536>; 139 i-cache-line-size = <64>; 140 i-cache-sets = <256>; 141 d-cache-size = <65536>; 142 d-cache-line-size = <64>; 143 d-cache-sets = <256>; 144 next-level-cache = <&l2_1>; 145 #cooling-cells = <2>; 146 }; 147 148 cpu5: cpu@500 { 149 device_type = "cpu"; 150 compatible = "arm,cortex-a78"; 151 reg = <0x500>; 152 enable-method = "psci"; 153 performance-domains = <&performance 1>; 154 clock-frequency = <2171000000>; 155 capacity-dmips-mhz = <1024>; 156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 157 i-cache-size = <65536>; 158 i-cache-line-size = <64>; 159 i-cache-sets = <256>; 160 d-cache-size = <65536>; 161 d-cache-line-size = <64>; 162 d-cache-sets = <256>; 163 next-level-cache = <&l2_1>; 164 #cooling-cells = <2>; 165 }; 166 167 cpu6: cpu@600 { 168 device_type = "cpu"; 169 compatible = "arm,cortex-a78"; 170 reg = <0x600>; 171 enable-method = "psci"; 172 performance-domains = <&performance 1>; 173 clock-frequency = <2171000000>; 174 capacity-dmips-mhz = <1024>; 175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 176 i-cache-size = <65536>; 177 i-cache-line-size = <64>; 178 i-cache-sets = <256>; 179 d-cache-size = <65536>; 180 d-cache-line-size = <64>; 181 d-cache-sets = <256>; 182 next-level-cache = <&l2_1>; 183 #cooling-cells = <2>; 184 }; 185 186 cpu7: cpu@700 { 187 device_type = "cpu"; 188 compatible = "arm,cortex-a78"; 189 reg = <0x700>; 190 enable-method = "psci"; 191 performance-domains = <&performance 1>; 192 clock-frequency = <2171000000>; 193 capacity-dmips-mhz = <1024>; 194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>; 195 i-cache-size = <65536>; 196 i-cache-line-size = <64>; 197 i-cache-sets = <256>; 198 d-cache-size = <65536>; 199 d-cache-line-size = <64>; 200 d-cache-sets = <256>; 201 next-level-cache = <&l2_1>; 202 #cooling-cells = <2>; 203 }; 204 205 cpu-map { 206 cluster0 { 207 core0 { 208 cpu = <&cpu0>; 209 }; 210 211 core1 { 212 cpu = <&cpu1>; 213 }; 214 215 core2 { 216 cpu = <&cpu2>; 217 }; 218 219 core3 { 220 cpu = <&cpu3>; 221 }; 222 223 core4 { 224 cpu = <&cpu4>; 225 }; 226 227 core5 { 228 cpu = <&cpu5>; 229 }; 230 231 core6 { 232 cpu = <&cpu6>; 233 }; 234 235 core7 { 236 cpu = <&cpu7>; 237 }; 238 }; 239 }; 240 241 idle-states { 242 entry-method = "psci"; 243 244 cpu_ret_l: cpu-retention-l { 245 compatible = "arm,idle-state"; 246 arm,psci-suspend-param = <0x00010001>; 247 local-timer-stop; 248 entry-latency-us = <50>; 249 exit-latency-us = <95>; 250 min-residency-us = <580>; 251 }; 252 253 cpu_ret_b: cpu-retention-b { 254 compatible = "arm,idle-state"; 255 arm,psci-suspend-param = <0x00010001>; 256 local-timer-stop; 257 entry-latency-us = <45>; 258 exit-latency-us = <140>; 259 min-residency-us = <740>; 260 }; 261 262 cpu_off_l: cpu-off-l { 263 compatible = "arm,idle-state"; 264 arm,psci-suspend-param = <0x01010002>; 265 local-timer-stop; 266 entry-latency-us = <55>; 267 exit-latency-us = <155>; 268 min-residency-us = <840>; 269 }; 270 271 cpu_off_b: cpu-off-b { 272 compatible = "arm,idle-state"; 273 arm,psci-suspend-param = <0x01010002>; 274 local-timer-stop; 275 entry-latency-us = <50>; 276 exit-latency-us = <200>; 277 min-residency-us = <1000>; 278 }; 279 }; 280 281 l2_0: l2-cache0 { 282 compatible = "cache"; 283 cache-level = <2>; 284 cache-size = <131072>; 285 cache-line-size = <64>; 286 cache-sets = <512>; 287 next-level-cache = <&l3_0>; 288 cache-unified; 289 }; 290 291 l2_1: l2-cache1 { 292 compatible = "cache"; 293 cache-level = <2>; 294 cache-size = <262144>; 295 cache-line-size = <64>; 296 cache-sets = <512>; 297 next-level-cache = <&l3_0>; 298 cache-unified; 299 }; 300 301 l3_0: l3-cache { 302 compatible = "cache"; 303 cache-level = <3>; 304 cache-size = <2097152>; 305 cache-line-size = <64>; 306 cache-sets = <2048>; 307 cache-unified; 308 }; 309 }; 310 311 dsu-pmu { 312 compatible = "arm,dsu-pmu"; 313 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>; 314 cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, 315 <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>; 316 status = "fail"; 317 }; 318 319 dmic_codec: dmic-codec { 320 compatible = "dmic-codec"; 321 num-channels = <2>; 322 wakeup-delay-ms = <50>; 323 }; 324 325 sound: mt8195-sound { 326 mediatek,platform = <&afe>; 327 status = "disabled"; 328 }; 329 330 clk13m: fixed-factor-clock-13m { 331 compatible = "fixed-factor-clock"; 332 #clock-cells = <0>; 333 clocks = <&clk26m>; 334 clock-div = <2>; 335 clock-mult = <1>; 336 clock-output-names = "clk13m"; 337 }; 338 339 clk26m: oscillator-26m { 340 compatible = "fixed-clock"; 341 #clock-cells = <0>; 342 clock-frequency = <26000000>; 343 clock-output-names = "clk26m"; 344 }; 345 346 clk32k: oscillator-32k { 347 compatible = "fixed-clock"; 348 #clock-cells = <0>; 349 clock-frequency = <32768>; 350 clock-output-names = "clk32k"; 351 }; 352 353 performance: performance-controller@11bc10 { 354 compatible = "mediatek,cpufreq-hw"; 355 reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>; 356 #performance-domain-cells = <1>; 357 }; 358 359 gpu_opp_table: opp-table-gpu { 360 compatible = "operating-points-v2"; 361 opp-shared; 362 363 opp-390000000 { 364 opp-hz = /bits/ 64 <390000000>; 365 opp-microvolt = <625000>; 366 }; 367 opp-410000000 { 368 opp-hz = /bits/ 64 <410000000>; 369 opp-microvolt = <631250>; 370 }; 371 opp-431000000 { 372 opp-hz = /bits/ 64 <431000000>; 373 opp-microvolt = <631250>; 374 }; 375 opp-473000000 { 376 opp-hz = /bits/ 64 <473000000>; 377 opp-microvolt = <637500>; 378 }; 379 opp-515000000 { 380 opp-hz = /bits/ 64 <515000000>; 381 opp-microvolt = <637500>; 382 }; 383 opp-556000000 { 384 opp-hz = /bits/ 64 <556000000>; 385 opp-microvolt = <643750>; 386 }; 387 opp-598000000 { 388 opp-hz = /bits/ 64 <598000000>; 389 opp-microvolt = <650000>; 390 }; 391 opp-640000000 { 392 opp-hz = /bits/ 64 <640000000>; 393 opp-microvolt = <650000>; 394 }; 395 opp-670000000 { 396 opp-hz = /bits/ 64 <670000000>; 397 opp-microvolt = <662500>; 398 }; 399 opp-700000000 { 400 opp-hz = /bits/ 64 <700000000>; 401 opp-microvolt = <675000>; 402 }; 403 opp-730000000 { 404 opp-hz = /bits/ 64 <730000000>; 405 opp-microvolt = <687500>; 406 }; 407 opp-760000000 { 408 opp-hz = /bits/ 64 <760000000>; 409 opp-microvolt = <700000>; 410 }; 411 opp-790000000 { 412 opp-hz = /bits/ 64 <790000000>; 413 opp-microvolt = <712500>; 414 }; 415 opp-820000000 { 416 opp-hz = /bits/ 64 <820000000>; 417 opp-microvolt = <725000>; 418 }; 419 opp-850000000 { 420 opp-hz = /bits/ 64 <850000000>; 421 opp-microvolt = <737500>; 422 }; 423 opp-880000000 { 424 opp-hz = /bits/ 64 <880000000>; 425 opp-microvolt = <750000>; 426 }; 427 }; 428 429 pmu-a55 { 430 compatible = "arm,cortex-a55-pmu"; 431 interrupt-parent = <&gic>; 432 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>; 433 }; 434 435 pmu-a78 { 436 compatible = "arm,cortex-a78-pmu"; 437 interrupt-parent = <&gic>; 438 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>; 439 }; 440 441 psci { 442 compatible = "arm,psci-1.0"; 443 method = "smc"; 444 }; 445 446 timer: timer { 447 compatible = "arm,armv8-timer"; 448 interrupt-parent = <&gic>; 449 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>, 450 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>, 451 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>, 452 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>; 453 }; 454 455 soc { 456 #address-cells = <2>; 457 #size-cells = <2>; 458 compatible = "simple-bus"; 459 ranges; 460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>; 461 462 gic: interrupt-controller@c000000 { 463 compatible = "arm,gic-v3"; 464 #interrupt-cells = <4>; 465 #redistributor-regions = <1>; 466 interrupt-parent = <&gic>; 467 interrupt-controller; 468 reg = <0 0x0c000000 0 0x40000>, 469 <0 0x0c040000 0 0x200000>; 470 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 471 472 ppi-partitions { 473 ppi_cluster0: interrupt-partition-0 { 474 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 475 }; 476 477 ppi_cluster1: interrupt-partition-1 { 478 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 479 }; 480 }; 481 }; 482 483 topckgen: syscon@10000000 { 484 compatible = "mediatek,mt8195-topckgen", "syscon"; 485 reg = <0 0x10000000 0 0x1000>; 486 #clock-cells = <1>; 487 }; 488 489 infracfg_ao: syscon@10001000 { 490 compatible = "mediatek,mt8195-infracfg_ao", "syscon"; 491 reg = <0 0x10001000 0 0x1000>; 492 #clock-cells = <1>; 493 #reset-cells = <1>; 494 }; 495 496 pericfg: syscon@10003000 { 497 compatible = "mediatek,mt8195-pericfg", "syscon"; 498 reg = <0 0x10003000 0 0x1000>; 499 #clock-cells = <1>; 500 }; 501 502 pio: pinctrl@10005000 { 503 compatible = "mediatek,mt8195-pinctrl"; 504 reg = <0 0x10005000 0 0x1000>, 505 <0 0x11d10000 0 0x1000>, 506 <0 0x11d30000 0 0x1000>, 507 <0 0x11d40000 0 0x1000>, 508 <0 0x11e20000 0 0x1000>, 509 <0 0x11eb0000 0 0x1000>, 510 <0 0x11f40000 0 0x1000>, 511 <0 0x1000b000 0 0x1000>; 512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl", 513 "iocfg_br", "iocfg_lm", "iocfg_rb", 514 "iocfg_tl", "eint"; 515 gpio-controller; 516 #gpio-cells = <2>; 517 gpio-ranges = <&pio 0 0 144>; 518 interrupt-controller; 519 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>; 520 #interrupt-cells = <2>; 521 }; 522 523 scpsys: syscon@10006000 { 524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd"; 525 reg = <0 0x10006000 0 0x1000>; 526 527 /* System Power Manager */ 528 spm: power-controller { 529 compatible = "mediatek,mt8195-power-controller"; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 #power-domain-cells = <1>; 533 534 /* power domain of the SoC */ 535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 { 536 reg = <MT8195_POWER_DOMAIN_MFG0>; 537 #address-cells = <1>; 538 #size-cells = <0>; 539 #power-domain-cells = <1>; 540 541 mfg1: power-domain@MT8195_POWER_DOMAIN_MFG1 { 542 reg = <MT8195_POWER_DOMAIN_MFG1>; 543 clocks = <&apmixedsys CLK_APMIXED_MFGPLL>, 544 <&topckgen CLK_TOP_MFG_CORE_TMP>; 545 clock-names = "mfg", "alt"; 546 mediatek,infracfg = <&infracfg_ao>; 547 #address-cells = <1>; 548 #size-cells = <0>; 549 #power-domain-cells = <1>; 550 551 power-domain@MT8195_POWER_DOMAIN_MFG2 { 552 reg = <MT8195_POWER_DOMAIN_MFG2>; 553 #power-domain-cells = <0>; 554 }; 555 556 power-domain@MT8195_POWER_DOMAIN_MFG3 { 557 reg = <MT8195_POWER_DOMAIN_MFG3>; 558 #power-domain-cells = <0>; 559 }; 560 561 power-domain@MT8195_POWER_DOMAIN_MFG4 { 562 reg = <MT8195_POWER_DOMAIN_MFG4>; 563 #power-domain-cells = <0>; 564 }; 565 566 power-domain@MT8195_POWER_DOMAIN_MFG5 { 567 reg = <MT8195_POWER_DOMAIN_MFG5>; 568 #power-domain-cells = <0>; 569 }; 570 571 power-domain@MT8195_POWER_DOMAIN_MFG6 { 572 reg = <MT8195_POWER_DOMAIN_MFG6>; 573 #power-domain-cells = <0>; 574 }; 575 }; 576 }; 577 578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 { 579 reg = <MT8195_POWER_DOMAIN_VPPSYS0>; 580 clocks = <&topckgen CLK_TOP_VPP>, 581 <&topckgen CLK_TOP_CAM>, 582 <&topckgen CLK_TOP_CCU>, 583 <&topckgen CLK_TOP_IMG>, 584 <&topckgen CLK_TOP_VENC>, 585 <&topckgen CLK_TOP_VDEC>, 586 <&topckgen CLK_TOP_WPE_VPP>, 587 <&topckgen CLK_TOP_CFG_VPP0>, 588 <&vppsys0 CLK_VPP0_SMI_COMMON>, 589 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>, 590 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>, 591 <&vppsys0 CLK_VPP0_GALS_VENCSYS>, 592 <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>, 593 <&vppsys0 CLK_VPP0_GALS_INFRA>, 594 <&vppsys0 CLK_VPP0_GALS_CAMSYS>, 595 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>, 596 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>, 597 <&vppsys0 CLK_VPP0_SMI_REORDER>, 598 <&vppsys0 CLK_VPP0_SMI_IOMMU>, 599 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, 600 <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, 601 <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, 602 <&vppsys0 CLK_VPP0_SMI_RSI>, 603 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 604 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 605 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 606 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3", 608 "vppsys4", "vppsys5", "vppsys6", "vppsys7", 609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3", 610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7", 611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11", 612 "vppsys0-12", "vppsys0-13", "vppsys0-14", 613 "vppsys0-15", "vppsys0-16", "vppsys0-17", 614 "vppsys0-18"; 615 mediatek,infracfg = <&infracfg_ao>; 616 #address-cells = <1>; 617 #size-cells = <0>; 618 #power-domain-cells = <1>; 619 620 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 { 621 reg = <MT8195_POWER_DOMAIN_VDOSYS0>; 622 clocks = <&topckgen CLK_TOP_CFG_VDO0>, 623 <&vdosys0 CLK_VDO0_SMI_GALS>, 624 <&vdosys0 CLK_VDO0_SMI_COMMON>, 625 <&vdosys0 CLK_VDO0_SMI_EMI>, 626 <&vdosys0 CLK_VDO0_SMI_IOMMU>, 627 <&vdosys0 CLK_VDO0_SMI_LARB>, 628 <&vdosys0 CLK_VDO0_SMI_RSI>; 629 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1", 630 "vdosys0-2", "vdosys0-3", 631 "vdosys0-4", "vdosys0-5"; 632 mediatek,infracfg = <&infracfg_ao>; 633 #address-cells = <1>; 634 #size-cells = <0>; 635 #power-domain-cells = <1>; 636 637 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 { 638 reg = <MT8195_POWER_DOMAIN_VPPSYS1>; 639 clocks = <&topckgen CLK_TOP_CFG_VPP1>, 640 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 641 <&vppsys1 CLK_VPP1_VPPSYS1_LARB>; 642 clock-names = "vppsys1", "vppsys1-0", 643 "vppsys1-1"; 644 mediatek,infracfg = <&infracfg_ao>; 645 #power-domain-cells = <0>; 646 }; 647 648 power-domain@MT8195_POWER_DOMAIN_WPESYS { 649 reg = <MT8195_POWER_DOMAIN_WPESYS>; 650 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 651 <&wpesys CLK_WPE_SMI_LARB8>, 652 <&wpesys CLK_WPE_SMI_LARB7_P>, 653 <&wpesys CLK_WPE_SMI_LARB8_P>; 654 clock-names = "wepsys-0", "wepsys-1", "wepsys-2", 655 "wepsys-3"; 656 mediatek,infracfg = <&infracfg_ao>; 657 #power-domain-cells = <0>; 658 }; 659 660 power-domain@MT8195_POWER_DOMAIN_VDEC0 { 661 reg = <MT8195_POWER_DOMAIN_VDEC0>; 662 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 663 clock-names = "vdec0-0"; 664 mediatek,infracfg = <&infracfg_ao>; 665 #address-cells = <1>; 666 #size-cells = <0>; 667 #power-domain-cells = <0>; 668 669 power-domain@MT8195_POWER_DOMAIN_VDEC1 { 670 reg = <MT8195_POWER_DOMAIN_VDEC1>; 671 clocks = <&vdecsys CLK_VDEC_LARB1>; 672 clock-names = "vdec1-0"; 673 mediatek,infracfg = <&infracfg_ao>; 674 #power-domain-cells = <0>; 675 }; 676 677 power-domain@MT8195_POWER_DOMAIN_VDEC2 { 678 reg = <MT8195_POWER_DOMAIN_VDEC2>; 679 clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 680 clock-names = "vdec2-0"; 681 mediatek,infracfg = <&infracfg_ao>; 682 #power-domain-cells = <0>; 683 }; 684 }; 685 686 power-domain@MT8195_POWER_DOMAIN_VENC { 687 reg = <MT8195_POWER_DOMAIN_VENC>; 688 clocks = <&vencsys CLK_VENC_LARB>; 689 clock-names = "venc0-larb"; 690 mediatek,infracfg = <&infracfg_ao>; 691 #address-cells = <1>; 692 #size-cells = <0>; 693 #power-domain-cells = <0>; 694 695 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 { 696 reg = <MT8195_POWER_DOMAIN_VENC_CORE1>; 697 clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>; 698 clock-names = "venc1-larb"; 699 mediatek,infracfg = <&infracfg_ao>; 700 #power-domain-cells = <0>; 701 }; 702 }; 703 704 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 { 705 reg = <MT8195_POWER_DOMAIN_VDOSYS1>; 706 clocks = <&topckgen CLK_TOP_CFG_VDO1>, 707 <&vdosys1 CLK_VDO1_SMI_LARB2>, 708 <&vdosys1 CLK_VDO1_SMI_LARB3>, 709 <&vdosys1 CLK_VDO1_GALS>; 710 clock-names = "vdosys1", "vdosys1-0", 711 "vdosys1-1", "vdosys1-2"; 712 mediatek,infracfg = <&infracfg_ao>; 713 #address-cells = <1>; 714 #size-cells = <0>; 715 #power-domain-cells = <1>; 716 717 power-domain@MT8195_POWER_DOMAIN_DP_TX { 718 reg = <MT8195_POWER_DOMAIN_DP_TX>; 719 mediatek,infracfg = <&infracfg_ao>; 720 #power-domain-cells = <0>; 721 }; 722 723 power-domain@MT8195_POWER_DOMAIN_EPD_TX { 724 reg = <MT8195_POWER_DOMAIN_EPD_TX>; 725 mediatek,infracfg = <&infracfg_ao>; 726 #power-domain-cells = <0>; 727 }; 728 729 power-domain@MT8195_POWER_DOMAIN_HDMI_TX { 730 reg = <MT8195_POWER_DOMAIN_HDMI_TX>; 731 clocks = <&topckgen CLK_TOP_HDMI_APB>; 732 clock-names = "hdmi_tx"; 733 #power-domain-cells = <0>; 734 }; 735 }; 736 737 power-domain@MT8195_POWER_DOMAIN_IMG { 738 reg = <MT8195_POWER_DOMAIN_IMG>; 739 clocks = <&imgsys CLK_IMG_LARB9>, 740 <&imgsys CLK_IMG_GALS>; 741 clock-names = "img-0", "img-1"; 742 mediatek,infracfg = <&infracfg_ao>; 743 #address-cells = <1>; 744 #size-cells = <0>; 745 #power-domain-cells = <1>; 746 747 power-domain@MT8195_POWER_DOMAIN_DIP { 748 reg = <MT8195_POWER_DOMAIN_DIP>; 749 #power-domain-cells = <0>; 750 }; 751 752 power-domain@MT8195_POWER_DOMAIN_IPE { 753 reg = <MT8195_POWER_DOMAIN_IPE>; 754 clocks = <&topckgen CLK_TOP_IPE>, 755 <&imgsys CLK_IMG_IPE>, 756 <&ipesys CLK_IPE_SMI_LARB12>; 757 clock-names = "ipe", "ipe-0", "ipe-1"; 758 mediatek,infracfg = <&infracfg_ao>; 759 #power-domain-cells = <0>; 760 }; 761 }; 762 763 power-domain@MT8195_POWER_DOMAIN_CAM { 764 reg = <MT8195_POWER_DOMAIN_CAM>; 765 clocks = <&camsys CLK_CAM_LARB13>, 766 <&camsys CLK_CAM_LARB14>, 767 <&camsys CLK_CAM_CAM2MM0_GALS>, 768 <&camsys CLK_CAM_CAM2MM1_GALS>, 769 <&camsys CLK_CAM_CAM2SYS_GALS>; 770 clock-names = "cam-0", "cam-1", "cam-2", "cam-3", 771 "cam-4"; 772 mediatek,infracfg = <&infracfg_ao>; 773 #address-cells = <1>; 774 #size-cells = <0>; 775 #power-domain-cells = <1>; 776 777 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA { 778 reg = <MT8195_POWER_DOMAIN_CAM_RAWA>; 779 #power-domain-cells = <0>; 780 }; 781 782 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB { 783 reg = <MT8195_POWER_DOMAIN_CAM_RAWB>; 784 #power-domain-cells = <0>; 785 }; 786 787 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW { 788 reg = <MT8195_POWER_DOMAIN_CAM_MRAW>; 789 #power-domain-cells = <0>; 790 }; 791 }; 792 }; 793 }; 794 795 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 { 796 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 797 mediatek,infracfg = <&infracfg_ao>; 798 #power-domain-cells = <0>; 799 }; 800 801 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 { 802 reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 803 mediatek,infracfg = <&infracfg_ao>; 804 #power-domain-cells = <0>; 805 }; 806 807 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY { 808 reg = <MT8195_POWER_DOMAIN_PCIE_PHY>; 809 #power-domain-cells = <0>; 810 }; 811 812 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY { 813 reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 814 #power-domain-cells = <0>; 815 }; 816 817 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP { 818 reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>; 819 clocks = <&topckgen CLK_TOP_SENINF>, 820 <&topckgen CLK_TOP_SENINF2>; 821 clock-names = "csi_rx_top", "csi_rx_top1"; 822 #power-domain-cells = <0>; 823 }; 824 825 power-domain@MT8195_POWER_DOMAIN_ETHER { 826 reg = <MT8195_POWER_DOMAIN_ETHER>; 827 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 828 clock-names = "ether"; 829 #power-domain-cells = <0>; 830 }; 831 832 power-domain@MT8195_POWER_DOMAIN_ADSP { 833 reg = <MT8195_POWER_DOMAIN_ADSP>; 834 clocks = <&topckgen CLK_TOP_ADSP>, 835 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>; 836 clock-names = "adsp", "adsp1"; 837 #address-cells = <1>; 838 #size-cells = <0>; 839 mediatek,infracfg = <&infracfg_ao>; 840 #power-domain-cells = <1>; 841 842 power-domain@MT8195_POWER_DOMAIN_AUDIO { 843 reg = <MT8195_POWER_DOMAIN_AUDIO>; 844 clocks = <&topckgen CLK_TOP_A1SYS_HP>, 845 <&topckgen CLK_TOP_AUD_INTBUS>, 846 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 847 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>; 848 clock-names = "audio", "audio1", "audio2", 849 "audio3"; 850 mediatek,infracfg = <&infracfg_ao>; 851 #power-domain-cells = <0>; 852 }; 853 }; 854 }; 855 }; 856 857 watchdog: watchdog@10007000 { 858 compatible = "mediatek,mt8195-wdt"; 859 mediatek,disable-extrst; 860 reg = <0 0x10007000 0 0x100>; 861 #reset-cells = <1>; 862 }; 863 864 apmixedsys: syscon@1000c000 { 865 compatible = "mediatek,mt8195-apmixedsys", "syscon"; 866 reg = <0 0x1000c000 0 0x1000>; 867 #clock-cells = <1>; 868 }; 869 870 systimer: timer@10017000 { 871 compatible = "mediatek,mt8195-timer", 872 "mediatek,mt6765-timer"; 873 reg = <0 0x10017000 0 0x1000>; 874 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>; 875 clocks = <&clk13m>; 876 }; 877 878 pwrap: pwrap@10024000 { 879 compatible = "mediatek,mt8195-pwrap", "syscon"; 880 reg = <0 0x10024000 0 0x1000>; 881 reg-names = "pwrap"; 882 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>; 883 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 884 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>; 885 clock-names = "spi", "wrap"; 886 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 887 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 888 }; 889 890 spmi: spmi@10027000 { 891 compatible = "mediatek,mt8195-spmi"; 892 reg = <0 0x10027000 0 0x000e00>, 893 <0 0x10029000 0 0x000100>; 894 reg-names = "pmif", "spmimst"; 895 clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>, 896 <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>, 897 <&topckgen CLK_TOP_SPMI_M_MST>; 898 clock-names = "pmif_sys_ck", 899 "pmif_tmr_ck", 900 "spmimst_clk_mux"; 901 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>; 902 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>; 903 }; 904 905 iommu_infra: infra-iommu@10315000 { 906 compatible = "mediatek,mt8195-iommu-infra"; 907 reg = <0 0x10315000 0 0x5000>; 908 interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>, 909 <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>, 910 <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>, 911 <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>, 912 <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>; 913 #iommu-cells = <1>; 914 }; 915 916 gce0: mailbox@10320000 { 917 compatible = "mediatek,mt8195-gce"; 918 reg = <0 0x10320000 0 0x4000>; 919 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; 920 #mbox-cells = <2>; 921 clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; 922 }; 923 924 gce1: mailbox@10330000 { 925 compatible = "mediatek,mt8195-gce"; 926 reg = <0 0x10330000 0 0x4000>; 927 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; 928 #mbox-cells = <2>; 929 clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; 930 }; 931 932 scp: scp@10500000 { 933 compatible = "mediatek,mt8195-scp"; 934 reg = <0 0x10500000 0 0x100000>, 935 <0 0x10720000 0 0xe0000>, 936 <0 0x10700000 0 0x8000>; 937 reg-names = "sram", "cfg", "l1tcm"; 938 interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>; 939 status = "disabled"; 940 }; 941 942 scp_adsp: clock-controller@10720000 { 943 compatible = "mediatek,mt8195-scp_adsp"; 944 reg = <0 0x10720000 0 0x1000>; 945 #clock-cells = <1>; 946 }; 947 948 adsp: dsp@10803000 { 949 compatible = "mediatek,mt8195-dsp"; 950 reg = <0 0x10803000 0 0x1000>, 951 <0 0x10840000 0 0x40000>; 952 reg-names = "cfg", "sram"; 953 clocks = <&topckgen CLK_TOP_ADSP>, 954 <&clk26m>, 955 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 956 <&topckgen CLK_TOP_MAINPLL_D7_D2>, 957 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>, 958 <&topckgen CLK_TOP_AUDIO_H>; 959 clock-names = "adsp_sel", 960 "clk26m_ck", 961 "audio_local_bus", 962 "mainpll_d7_d2", 963 "scp_adsp_audiodsp", 964 "audio_h"; 965 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>; 966 mbox-names = "rx", "tx"; 967 mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>; 968 status = "disabled"; 969 }; 970 971 adsp_mailbox0: mailbox@10816000 { 972 compatible = "mediatek,mt8195-adsp-mbox"; 973 #mbox-cells = <0>; 974 reg = <0 0x10816000 0 0x1000>; 975 interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>; 976 }; 977 978 adsp_mailbox1: mailbox@10817000 { 979 compatible = "mediatek,mt8195-adsp-mbox"; 980 #mbox-cells = <0>; 981 reg = <0 0x10817000 0 0x1000>; 982 interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>; 983 }; 984 985 afe: mt8195-afe-pcm@10890000 { 986 compatible = "mediatek,mt8195-audio"; 987 reg = <0 0x10890000 0 0x10000>; 988 mediatek,topckgen = <&topckgen>; 989 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>; 990 interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>; 991 resets = <&watchdog 14>; 992 reset-names = "audiosys"; 993 clocks = <&clk26m>, 994 <&apmixedsys CLK_APMIXED_APLL1>, 995 <&apmixedsys CLK_APMIXED_APLL2>, 996 <&topckgen CLK_TOP_APLL12_DIV0>, 997 <&topckgen CLK_TOP_APLL12_DIV1>, 998 <&topckgen CLK_TOP_APLL12_DIV2>, 999 <&topckgen CLK_TOP_APLL12_DIV3>, 1000 <&topckgen CLK_TOP_APLL12_DIV9>, 1001 <&topckgen CLK_TOP_A1SYS_HP>, 1002 <&topckgen CLK_TOP_AUD_INTBUS>, 1003 <&topckgen CLK_TOP_AUDIO_H>, 1004 <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, 1005 <&topckgen CLK_TOP_DPTX_MCK>, 1006 <&topckgen CLK_TOP_I2SO1_MCK>, 1007 <&topckgen CLK_TOP_I2SO2_MCK>, 1008 <&topckgen CLK_TOP_I2SI1_MCK>, 1009 <&topckgen CLK_TOP_I2SI2_MCK>, 1010 <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>, 1011 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>; 1012 clock-names = "clk26m", 1013 "apll1_ck", 1014 "apll2_ck", 1015 "apll12_div0", 1016 "apll12_div1", 1017 "apll12_div2", 1018 "apll12_div3", 1019 "apll12_div9", 1020 "a1sys_hp_sel", 1021 "aud_intbus_sel", 1022 "audio_h_sel", 1023 "audio_local_bus_sel", 1024 "dptx_m_sel", 1025 "i2so1_m_sel", 1026 "i2so2_m_sel", 1027 "i2si1_m_sel", 1028 "i2si2_m_sel", 1029 "infra_ao_audio_26m_b", 1030 "scp_adsp_audiodsp"; 1031 status = "disabled"; 1032 }; 1033 1034 uart0: serial@11001100 { 1035 compatible = "mediatek,mt8195-uart", 1036 "mediatek,mt6577-uart"; 1037 reg = <0 0x11001100 0 0x100>; 1038 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>; 1039 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>; 1040 clock-names = "baud", "bus"; 1041 status = "disabled"; 1042 }; 1043 1044 uart1: serial@11001200 { 1045 compatible = "mediatek,mt8195-uart", 1046 "mediatek,mt6577-uart"; 1047 reg = <0 0x11001200 0 0x100>; 1048 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>; 1049 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>; 1050 clock-names = "baud", "bus"; 1051 status = "disabled"; 1052 }; 1053 1054 uart2: serial@11001300 { 1055 compatible = "mediatek,mt8195-uart", 1056 "mediatek,mt6577-uart"; 1057 reg = <0 0x11001300 0 0x100>; 1058 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>; 1059 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>; 1060 clock-names = "baud", "bus"; 1061 status = "disabled"; 1062 }; 1063 1064 uart3: serial@11001400 { 1065 compatible = "mediatek,mt8195-uart", 1066 "mediatek,mt6577-uart"; 1067 reg = <0 0x11001400 0 0x100>; 1068 interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>; 1069 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>; 1070 clock-names = "baud", "bus"; 1071 status = "disabled"; 1072 }; 1073 1074 uart4: serial@11001500 { 1075 compatible = "mediatek,mt8195-uart", 1076 "mediatek,mt6577-uart"; 1077 reg = <0 0x11001500 0 0x100>; 1078 interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>; 1079 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>; 1080 clock-names = "baud", "bus"; 1081 status = "disabled"; 1082 }; 1083 1084 uart5: serial@11001600 { 1085 compatible = "mediatek,mt8195-uart", 1086 "mediatek,mt6577-uart"; 1087 reg = <0 0x11001600 0 0x100>; 1088 interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>; 1089 clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>; 1090 clock-names = "baud", "bus"; 1091 status = "disabled"; 1092 }; 1093 1094 auxadc: auxadc@11002000 { 1095 compatible = "mediatek,mt8195-auxadc", 1096 "mediatek,mt8173-auxadc"; 1097 reg = <0 0x11002000 0 0x1000>; 1098 clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>; 1099 clock-names = "main"; 1100 #io-channel-cells = <1>; 1101 status = "disabled"; 1102 }; 1103 1104 pericfg_ao: syscon@11003000 { 1105 compatible = "mediatek,mt8195-pericfg_ao", "syscon"; 1106 reg = <0 0x11003000 0 0x1000>; 1107 #clock-cells = <1>; 1108 }; 1109 1110 spi0: spi@1100a000 { 1111 compatible = "mediatek,mt8195-spi", 1112 "mediatek,mt6765-spi"; 1113 #address-cells = <1>; 1114 #size-cells = <0>; 1115 reg = <0 0x1100a000 0 0x1000>; 1116 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>; 1117 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1118 <&topckgen CLK_TOP_SPI>, 1119 <&infracfg_ao CLK_INFRA_AO_SPI0>; 1120 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1121 status = "disabled"; 1122 }; 1123 1124 lvts_ap: thermal-sensor@1100b000 { 1125 compatible = "mediatek,mt8195-lvts-ap"; 1126 reg = <0 0x1100b000 0 0xc00>; 1127 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH 0>; 1128 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1129 resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; 1130 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1131 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1132 #thermal-sensor-cells = <1>; 1133 }; 1134 1135 svs: svs@1100bc00 { 1136 compatible = "mediatek,mt8195-svs"; 1137 reg = <0 0x1100bc00 0 0x400>; 1138 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH 0>; 1139 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1140 clock-names = "main"; 1141 nvmem-cells = <&svs_calib_data &lvts_efuse_data1>; 1142 nvmem-cell-names = "svs-calibration-data", "t-calibration-data"; 1143 resets = <&infracfg_ao MT8195_INFRA_RST3_THERM_CTRL_PTP_SWRST>; 1144 reset-names = "svs_rst"; 1145 }; 1146 1147 disp_pwm0: pwm@1100e000 { 1148 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1149 reg = <0 0x1100e000 0 0x1000>; 1150 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW 0>; 1151 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 1152 #pwm-cells = <2>; 1153 clocks = <&topckgen CLK_TOP_DISP_PWM0>, 1154 <&infracfg_ao CLK_INFRA_AO_DISP_PWM>; 1155 clock-names = "main", "mm"; 1156 status = "disabled"; 1157 }; 1158 1159 disp_pwm1: pwm@1100f000 { 1160 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm"; 1161 reg = <0 0x1100f000 0 0x1000>; 1162 interrupts = <GIC_SPI 793 IRQ_TYPE_LEVEL_HIGH 0>; 1163 #pwm-cells = <2>; 1164 clocks = <&topckgen CLK_TOP_DISP_PWM1>, 1165 <&infracfg_ao CLK_INFRA_AO_DISP_PWM1>; 1166 clock-names = "main", "mm"; 1167 status = "disabled"; 1168 }; 1169 1170 spi1: spi@11010000 { 1171 compatible = "mediatek,mt8195-spi", 1172 "mediatek,mt6765-spi"; 1173 #address-cells = <1>; 1174 #size-cells = <0>; 1175 reg = <0 0x11010000 0 0x1000>; 1176 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>; 1177 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1178 <&topckgen CLK_TOP_SPI>, 1179 <&infracfg_ao CLK_INFRA_AO_SPI1>; 1180 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1181 status = "disabled"; 1182 }; 1183 1184 spi2: spi@11012000 { 1185 compatible = "mediatek,mt8195-spi", 1186 "mediatek,mt6765-spi"; 1187 #address-cells = <1>; 1188 #size-cells = <0>; 1189 reg = <0 0x11012000 0 0x1000>; 1190 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>; 1191 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1192 <&topckgen CLK_TOP_SPI>, 1193 <&infracfg_ao CLK_INFRA_AO_SPI2>; 1194 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1195 status = "disabled"; 1196 }; 1197 1198 spi3: spi@11013000 { 1199 compatible = "mediatek,mt8195-spi", 1200 "mediatek,mt6765-spi"; 1201 #address-cells = <1>; 1202 #size-cells = <0>; 1203 reg = <0 0x11013000 0 0x1000>; 1204 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>; 1205 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1206 <&topckgen CLK_TOP_SPI>, 1207 <&infracfg_ao CLK_INFRA_AO_SPI3>; 1208 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1209 status = "disabled"; 1210 }; 1211 1212 spi4: spi@11018000 { 1213 compatible = "mediatek,mt8195-spi", 1214 "mediatek,mt6765-spi"; 1215 #address-cells = <1>; 1216 #size-cells = <0>; 1217 reg = <0 0x11018000 0 0x1000>; 1218 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>; 1219 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1220 <&topckgen CLK_TOP_SPI>, 1221 <&infracfg_ao CLK_INFRA_AO_SPI4>; 1222 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1223 status = "disabled"; 1224 }; 1225 1226 spi5: spi@11019000 { 1227 compatible = "mediatek,mt8195-spi", 1228 "mediatek,mt6765-spi"; 1229 #address-cells = <1>; 1230 #size-cells = <0>; 1231 reg = <0 0x11019000 0 0x1000>; 1232 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>; 1233 clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>, 1234 <&topckgen CLK_TOP_SPI>, 1235 <&infracfg_ao CLK_INFRA_AO_SPI5>; 1236 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1237 status = "disabled"; 1238 }; 1239 1240 spis0: spi@1101d000 { 1241 compatible = "mediatek,mt8195-spi-slave"; 1242 reg = <0 0x1101d000 0 0x1000>; 1243 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>; 1244 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>; 1245 clock-names = "spi"; 1246 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1247 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1248 status = "disabled"; 1249 }; 1250 1251 spis1: spi@1101e000 { 1252 compatible = "mediatek,mt8195-spi-slave"; 1253 reg = <0 0x1101e000 0 0x1000>; 1254 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>; 1255 clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>; 1256 clock-names = "spi"; 1257 assigned-clocks = <&topckgen CLK_TOP_SPIS>; 1258 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>; 1259 status = "disabled"; 1260 }; 1261 1262 eth: ethernet@11021000 { 1263 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a"; 1264 reg = <0 0x11021000 0 0x4000>; 1265 interrupts = <GIC_SPI 716 IRQ_TYPE_LEVEL_HIGH 0>; 1266 interrupt-names = "macirq"; 1267 clock-names = "axi", 1268 "apb", 1269 "mac_main", 1270 "ptp_ref", 1271 "rmii_internal", 1272 "mac_cg"; 1273 clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET>, 1274 <&pericfg_ao CLK_PERI_AO_ETHERNET_BUS>, 1275 <&topckgen CLK_TOP_SNPS_ETH_250M>, 1276 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1277 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>, 1278 <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; 1279 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>, 1280 <&topckgen CLK_TOP_SNPS_ETH_62P4M_PTP>, 1281 <&topckgen CLK_TOP_SNPS_ETH_50M_RMII>; 1282 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>, 1283 <&topckgen CLK_TOP_ETHPLL_D8>, 1284 <&topckgen CLK_TOP_ETHPLL_D10>; 1285 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>; 1286 mediatek,pericfg = <&infracfg_ao>; 1287 snps,axi-config = <&stmmac_axi_setup>; 1288 snps,mtl-rx-config = <&mtl_rx_setup>; 1289 snps,mtl-tx-config = <&mtl_tx_setup>; 1290 snps,txpbl = <16>; 1291 snps,rxpbl = <16>; 1292 snps,clk-csr = <0>; 1293 status = "disabled"; 1294 1295 mdio { 1296 compatible = "snps,dwmac-mdio"; 1297 #address-cells = <1>; 1298 #size-cells = <0>; 1299 }; 1300 1301 stmmac_axi_setup: stmmac-axi-config { 1302 snps,wr_osr_lmt = <0x7>; 1303 snps,rd_osr_lmt = <0x7>; 1304 snps,blen = <0 0 0 0 16 8 4>; 1305 }; 1306 1307 mtl_rx_setup: rx-queues-config { 1308 snps,rx-queues-to-use = <4>; 1309 snps,rx-sched-sp; 1310 queue0 { 1311 snps,dcb-algorithm; 1312 snps,map-to-dma-channel = <0x0>; 1313 }; 1314 queue1 { 1315 snps,dcb-algorithm; 1316 snps,map-to-dma-channel = <0x0>; 1317 }; 1318 queue2 { 1319 snps,dcb-algorithm; 1320 snps,map-to-dma-channel = <0x0>; 1321 }; 1322 queue3 { 1323 snps,dcb-algorithm; 1324 snps,map-to-dma-channel = <0x0>; 1325 }; 1326 }; 1327 1328 mtl_tx_setup: tx-queues-config { 1329 snps,tx-queues-to-use = <4>; 1330 snps,tx-sched-wrr; 1331 queue0 { 1332 snps,weight = <0x10>; 1333 snps,dcb-algorithm; 1334 snps,priority = <0x0>; 1335 }; 1336 queue1 { 1337 snps,weight = <0x11>; 1338 snps,dcb-algorithm; 1339 snps,priority = <0x1>; 1340 }; 1341 queue2 { 1342 snps,weight = <0x12>; 1343 snps,dcb-algorithm; 1344 snps,priority = <0x2>; 1345 }; 1346 queue3 { 1347 snps,weight = <0x13>; 1348 snps,dcb-algorithm; 1349 snps,priority = <0x3>; 1350 }; 1351 }; 1352 }; 1353 1354 ssusb0: usb@11201000 { 1355 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1356 reg = <0 0x11201000 0 0x2dff>, <0 0x11203e00 0 0x0100>; 1357 reg-names = "mac", "ippc"; 1358 ranges = <0 0 0 0x11200000 0 0x3f00>; 1359 #address-cells = <2>; 1360 #size-cells = <2>; 1361 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>; 1362 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1363 <&topckgen CLK_TOP_SSUSB_REF>, 1364 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1365 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1366 phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>; 1367 wakeup-source; 1368 mediatek,syscon-wakeup = <&pericfg 0x400 103>; 1369 status = "disabled"; 1370 1371 xhci0: usb@0 { 1372 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1373 reg = <0 0 0 0x1000>; 1374 reg-names = "mac"; 1375 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>; 1376 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>, 1377 <&topckgen CLK_TOP_SSUSB_XHCI>; 1378 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1379 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1380 clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>, 1381 <&topckgen CLK_TOP_SSUSB_REF>, 1382 <&apmixedsys CLK_APMIXED_USB1PLL>, 1383 <&clk26m>, 1384 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>; 1385 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 1386 status = "disabled"; 1387 }; 1388 }; 1389 1390 mmc0: mmc@11230000 { 1391 compatible = "mediatek,mt8195-mmc", 1392 "mediatek,mt8183-mmc"; 1393 reg = <0 0x11230000 0 0x10000>, 1394 <0 0x11f50000 0 0x1000>; 1395 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>; 1396 clocks = <&topckgen CLK_TOP_MSDC50_0>, 1397 <&infracfg_ao CLK_INFRA_AO_MSDC0>, 1398 <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>; 1399 clock-names = "source", "hclk", "source_cg"; 1400 status = "disabled"; 1401 }; 1402 1403 mmc1: mmc@11240000 { 1404 compatible = "mediatek,mt8195-mmc", 1405 "mediatek,mt8183-mmc"; 1406 reg = <0 0x11240000 0 0x1000>, 1407 <0 0x11c70000 0 0x1000>; 1408 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>; 1409 clocks = <&topckgen CLK_TOP_MSDC30_1>, 1410 <&infracfg_ao CLK_INFRA_AO_MSDC1>, 1411 <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>; 1412 clock-names = "source", "hclk", "source_cg"; 1413 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>; 1414 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1415 status = "disabled"; 1416 }; 1417 1418 mmc2: mmc@11250000 { 1419 compatible = "mediatek,mt8195-mmc", 1420 "mediatek,mt8183-mmc"; 1421 reg = <0 0x11250000 0 0x1000>, 1422 <0 0x11e60000 0 0x1000>; 1423 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>; 1424 clocks = <&topckgen CLK_TOP_MSDC30_2>, 1425 <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>, 1426 <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>; 1427 clock-names = "source", "hclk", "source_cg"; 1428 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>; 1429 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>; 1430 status = "disabled"; 1431 }; 1432 1433 ufshci: ufshci@11270000 { 1434 compatible = "mediatek,mt8195-ufshci"; 1435 reg = <0 0x11270000 0 0x2300>; 1436 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH 0>; 1437 phys = <&ufsphy>; 1438 clocks = <&infracfg_ao CLK_INFRA_AO_AES_UFSFDE>, 1439 <&infracfg_ao CLK_INFRA_AO_AES>, 1440 <&infracfg_ao CLK_INFRA_AO_UFS_TICK>, 1441 <&infracfg_ao CLK_INFRA_AO_UNIPRO_SYS>, 1442 <&infracfg_ao CLK_INFRA_AO_UNIPRO_TICK>, 1443 <&infracfg_ao CLK_INFRA_AO_UFS_MP_SAP_B>, 1444 <&infracfg_ao CLK_INFRA_AO_UFS_TX_SYMBOL>, 1445 <&infracfg_ao CLK_INFRA_AO_PERI_UFS_MEM_SUB>; 1446 clock-names = "ufs", "ufs_aes", "ufs_tick", 1447 "unipro_sysclk", "unipro_tick", 1448 "unipro_mp_bclk", "ufs_tx_symbol", 1449 "ufs_mem_sub"; 1450 freq-table-hz = <0 0>, <0 0>, <0 0>, 1451 <0 0>, <0 0>, <0 0>, 1452 <0 0>, <0 0>; 1453 1454 mediatek,ufs-disable-mcq; 1455 status = "disabled"; 1456 }; 1457 1458 lvts_mcu: thermal-sensor@11278000 { 1459 compatible = "mediatek,mt8195-lvts-mcu"; 1460 reg = <0 0x11278000 0 0x1000>; 1461 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>; 1462 clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; 1463 resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; 1464 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; 1465 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; 1466 #thermal-sensor-cells = <1>; 1467 }; 1468 1469 xhci1: usb@11290000 { 1470 compatible = "mediatek,mt8195-xhci", 1471 "mediatek,mtk-xhci"; 1472 reg = <0 0x11290000 0 0x1000>, 1473 <0 0x11293e00 0 0x0100>; 1474 reg-names = "mac", "ippc"; 1475 interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>; 1476 phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>; 1477 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>, 1478 <&topckgen CLK_TOP_SSUSB_XHCI_1P>; 1479 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>, 1480 <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1481 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>, 1482 <&topckgen CLK_TOP_SSUSB_P1_REF>, 1483 <&apmixedsys CLK_APMIXED_USB1PLL>, 1484 <&clk26m>, 1485 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>; 1486 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", 1487 "xhci_ck"; 1488 mediatek,syscon-wakeup = <&pericfg 0x400 104>; 1489 wakeup-source; 1490 status = "disabled"; 1491 }; 1492 1493 ssusb2: usb@112a1000 { 1494 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1495 reg = <0 0x112a1000 0 0x2dff>, <0 0x112a3e00 0 0x0100>; 1496 reg-names = "mac", "ippc"; 1497 ranges = <0 0 0 0x112a0000 0 0x3f00>; 1498 #address-cells = <2>; 1499 #size-cells = <2>; 1500 interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>; 1501 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>; 1502 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1503 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>, 1504 <&topckgen CLK_TOP_SSUSB_P2_REF>, 1505 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1506 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1507 phys = <&u2port2 PHY_TYPE_USB2>; 1508 wakeup-source; 1509 mediatek,syscon-wakeup = <&pericfg 0x400 105>; 1510 status = "disabled"; 1511 1512 xhci2: usb@0 { 1513 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1514 reg = <0 0 0 0x1000>; 1515 reg-names = "mac"; 1516 interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>; 1517 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>; 1518 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1519 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>; 1520 clock-names = "sys_ck"; 1521 status = "disabled"; 1522 }; 1523 }; 1524 1525 ssusb3: usb@112b1000 { 1526 compatible = "mediatek,mt8195-mtu3", "mediatek,mtu3"; 1527 reg = <0 0x112b1000 0 0x2dff>, <0 0x112b3e00 0 0x0100>; 1528 reg-names = "mac", "ippc"; 1529 ranges = <0 0 0 0x112b0000 0 0x3f00>; 1530 #address-cells = <2>; 1531 #size-cells = <2>; 1532 interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>; 1533 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>; 1534 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1535 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>, 1536 <&topckgen CLK_TOP_SSUSB_P3_REF>, 1537 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1538 clock-names = "sys_ck", "ref_ck", "mcu_ck"; 1539 phys = <&u2port3 PHY_TYPE_USB2>; 1540 wakeup-source; 1541 mediatek,syscon-wakeup = <&pericfg 0x400 106>; 1542 status = "disabled"; 1543 1544 xhci3: usb@0 { 1545 compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci"; 1546 reg = <0 0 0 0x1000>; 1547 reg-names = "mac"; 1548 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>; 1549 assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_3P>; 1550 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>; 1551 clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>; 1552 clock-names = "sys_ck"; 1553 status = "disabled"; 1554 }; 1555 }; 1556 1557 pcie0: pcie@112f0000 { 1558 compatible = "mediatek,mt8195-pcie", 1559 "mediatek,mt8192-pcie"; 1560 device_type = "pci"; 1561 #address-cells = <3>; 1562 #size-cells = <2>; 1563 reg = <0 0x112f0000 0 0x4000>; 1564 reg-names = "pcie-mac"; 1565 interrupts = <GIC_SPI 791 IRQ_TYPE_LEVEL_HIGH 0>; 1566 bus-range = <0x00 0xff>; 1567 ranges = <0x81000000 0 0x20000000 1568 0x0 0x20000000 0 0x200000>, 1569 <0x82000000 0 0x20200000 1570 0x0 0x20200000 0 0x3e00000>; 1571 1572 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>; 1573 iommu-map-mask = <0x0>; 1574 1575 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P0>, 1576 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_26M>, 1577 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_96M>, 1578 <&infracfg_ao CLK_INFRA_AO_PCIE_TL_32K>, 1579 <&infracfg_ao CLK_INFRA_AO_PCIE_PERI_26M>, 1580 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1581 clock-names = "pl_250m", "tl_26m", "tl_96m", 1582 "tl_32k", "peri_26m", "peri_mem"; 1583 assigned-clocks = <&topckgen CLK_TOP_TL>; 1584 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1585 1586 phys = <&pciephy>; 1587 phy-names = "pcie-phy"; 1588 1589 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>; 1590 1591 #interrupt-cells = <1>; 1592 interrupt-map-mask = <0 0 0 7>; 1593 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 1594 <0 0 0 2 &pcie_intc0 1>, 1595 <0 0 0 3 &pcie_intc0 2>, 1596 <0 0 0 4 &pcie_intc0 3>; 1597 status = "disabled"; 1598 1599 pcie_intc0: interrupt-controller { 1600 interrupt-controller; 1601 #address-cells = <0>; 1602 #interrupt-cells = <1>; 1603 }; 1604 }; 1605 1606 pcie1: pcie@112f8000 { 1607 compatible = "mediatek,mt8195-pcie", 1608 "mediatek,mt8192-pcie"; 1609 device_type = "pci"; 1610 #address-cells = <3>; 1611 #size-cells = <2>; 1612 reg = <0 0x112f8000 0 0x4000>; 1613 reg-names = "pcie-mac"; 1614 interrupts = <GIC_SPI 792 IRQ_TYPE_LEVEL_HIGH 0>; 1615 bus-range = <0x00 0xff>; 1616 ranges = <0x81000000 0 0x24000000 1617 0x0 0x24000000 0 0x200000>, 1618 <0x82000000 0 0x24200000 1619 0x0 0x24200000 0 0x3e00000>; 1620 1621 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>; 1622 iommu-map-mask = <0x0>; 1623 1624 clocks = <&infracfg_ao CLK_INFRA_AO_PCIE_PL_P_250M_P1>, 1625 <&clk26m>, 1626 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_TL_96M>, 1627 <&clk26m>, 1628 <&infracfg_ao CLK_INFRA_AO_PCIE_P1_PERI_26M>, 1629 /* Designer has connect pcie1 with peri_mem_p0 clock */ 1630 <&pericfg_ao CLK_PERI_AO_PCIE_P0_MEM>; 1631 clock-names = "pl_250m", "tl_26m", "tl_96m", 1632 "tl_32k", "peri_26m", "peri_mem"; 1633 assigned-clocks = <&topckgen CLK_TOP_TL_P1>; 1634 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>; 1635 1636 phys = <&u3port1 PHY_TYPE_PCIE>; 1637 phy-names = "pcie-phy"; 1638 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>; 1639 1640 #interrupt-cells = <1>; 1641 interrupt-map-mask = <0 0 0 7>; 1642 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 1643 <0 0 0 2 &pcie_intc1 1>, 1644 <0 0 0 3 &pcie_intc1 2>, 1645 <0 0 0 4 &pcie_intc1 3>; 1646 status = "disabled"; 1647 1648 pcie_intc1: interrupt-controller { 1649 interrupt-controller; 1650 #address-cells = <0>; 1651 #interrupt-cells = <1>; 1652 }; 1653 }; 1654 1655 nor_flash: spi@1132c000 { 1656 compatible = "mediatek,mt8195-nor", 1657 "mediatek,mt8173-nor"; 1658 reg = <0 0x1132c000 0 0x1000>; 1659 interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>; 1660 clocks = <&topckgen CLK_TOP_SPINOR>, 1661 <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>, 1662 <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>; 1663 clock-names = "spi", "sf", "axi"; 1664 #address-cells = <1>; 1665 #size-cells = <0>; 1666 status = "disabled"; 1667 }; 1668 1669 efuse: efuse@11c10000 { 1670 compatible = "mediatek,mt8195-efuse", "mediatek,efuse"; 1671 reg = <0 0x11c10000 0 0x1000>; 1672 #address-cells = <1>; 1673 #size-cells = <1>; 1674 u3_tx_imp_p0: usb3-tx-imp@184,1 { 1675 reg = <0x184 0x1>; 1676 bits = <0 5>; 1677 }; 1678 u3_rx_imp_p0: usb3-rx-imp@184,2 { 1679 reg = <0x184 0x2>; 1680 bits = <5 5>; 1681 }; 1682 u3_intr_p0: usb3-intr@185 { 1683 reg = <0x185 0x1>; 1684 bits = <2 6>; 1685 }; 1686 comb_tx_imp_p1: usb3-tx-imp@186,1 { 1687 reg = <0x186 0x1>; 1688 bits = <0 5>; 1689 }; 1690 comb_rx_imp_p1: usb3-rx-imp@186,2 { 1691 reg = <0x186 0x2>; 1692 bits = <5 5>; 1693 }; 1694 comb_intr_p1: usb3-intr@187 { 1695 reg = <0x187 0x1>; 1696 bits = <2 6>; 1697 }; 1698 u2_intr_p0: usb2-intr-p0@188,1 { 1699 reg = <0x188 0x1>; 1700 bits = <0 5>; 1701 }; 1702 u2_intr_p1: usb2-intr-p1@188,2 { 1703 reg = <0x188 0x2>; 1704 bits = <5 5>; 1705 }; 1706 u2_intr_p2: usb2-intr-p2@189,1 { 1707 reg = <0x189 0x1>; 1708 bits = <2 5>; 1709 }; 1710 u2_intr_p3: usb2-intr-p3@189,2 { 1711 reg = <0x189 0x2>; 1712 bits = <7 5>; 1713 }; 1714 pciephy_rx_ln1: pciephy-rx-ln1@190,1 { 1715 reg = <0x190 0x1>; 1716 bits = <0 4>; 1717 }; 1718 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 { 1719 reg = <0x190 0x1>; 1720 bits = <4 4>; 1721 }; 1722 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 { 1723 reg = <0x191 0x1>; 1724 bits = <0 4>; 1725 }; 1726 pciephy_rx_ln0: pciephy-rx-ln0@191,2 { 1727 reg = <0x191 0x1>; 1728 bits = <4 4>; 1729 }; 1730 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 { 1731 reg = <0x192 0x1>; 1732 bits = <0 4>; 1733 }; 1734 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 { 1735 reg = <0x192 0x1>; 1736 bits = <4 4>; 1737 }; 1738 pciephy_glb_intr: pciephy-glb-intr@193 { 1739 reg = <0x193 0x1>; 1740 bits = <0 4>; 1741 }; 1742 dp_calibration: dp-data@1ac { 1743 reg = <0x1ac 0x10>; 1744 }; 1745 lvts_efuse_data1: lvts1-calib@1bc { 1746 reg = <0x1bc 0x14>; 1747 }; 1748 lvts_efuse_data2: lvts2-calib@1d0 { 1749 reg = <0x1d0 0x38>; 1750 }; 1751 svs_calib_data: svs-calib@580 { 1752 reg = <0x580 0x64>; 1753 }; 1754 socinfo-data1@7a0 { 1755 reg = <0x7a0 0x4>; 1756 }; 1757 }; 1758 1759 u3phy2: t-phy@11c40000 { 1760 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1761 #address-cells = <1>; 1762 #size-cells = <1>; 1763 ranges = <0 0 0x11c40000 0x700>; 1764 status = "disabled"; 1765 1766 u2port2: usb-phy@0 { 1767 reg = <0x0 0x700>; 1768 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>; 1769 clock-names = "ref"; 1770 #phy-cells = <1>; 1771 }; 1772 }; 1773 1774 u3phy3: t-phy@11c50000 { 1775 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1776 #address-cells = <1>; 1777 #size-cells = <1>; 1778 ranges = <0 0 0x11c50000 0x700>; 1779 status = "disabled"; 1780 1781 u2port3: usb-phy@0 { 1782 reg = <0x0 0x700>; 1783 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>; 1784 clock-names = "ref"; 1785 #phy-cells = <1>; 1786 }; 1787 }; 1788 1789 mipi_tx0: dsi-phy@11c80000 { 1790 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1791 reg = <0 0x11c80000 0 0x1000>; 1792 clocks = <&clk26m>; 1793 clock-output-names = "mipi_tx0_pll"; 1794 #clock-cells = <0>; 1795 #phy-cells = <0>; 1796 status = "disabled"; 1797 }; 1798 1799 mipi_tx1: dsi-phy@11c90000 { 1800 compatible = "mediatek,mt8195-mipi-tx", "mediatek,mt8183-mipi-tx"; 1801 reg = <0 0x11c90000 0 0x1000>; 1802 clocks = <&clk26m>; 1803 clock-output-names = "mipi_tx1_pll"; 1804 #clock-cells = <0>; 1805 #phy-cells = <0>; 1806 status = "disabled"; 1807 }; 1808 1809 i2c5: i2c@11d00000 { 1810 compatible = "mediatek,mt8195-i2c", 1811 "mediatek,mt8192-i2c"; 1812 reg = <0 0x11d00000 0 0x1000>, 1813 <0 0x10220580 0 0x80>; 1814 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>; 1815 clock-div = <1>; 1816 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>, 1817 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1818 clock-names = "main", "dma"; 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 status = "disabled"; 1822 }; 1823 1824 i2c6: i2c@11d01000 { 1825 compatible = "mediatek,mt8195-i2c", 1826 "mediatek,mt8192-i2c"; 1827 reg = <0 0x11d01000 0 0x1000>, 1828 <0 0x10220600 0 0x80>; 1829 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>; 1830 clock-div = <1>; 1831 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>, 1832 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1833 clock-names = "main", "dma"; 1834 #address-cells = <1>; 1835 #size-cells = <0>; 1836 status = "disabled"; 1837 }; 1838 1839 i2c7: i2c@11d02000 { 1840 compatible = "mediatek,mt8195-i2c", 1841 "mediatek,mt8192-i2c"; 1842 reg = <0 0x11d02000 0 0x1000>, 1843 <0 0x10220680 0 0x80>; 1844 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>; 1845 clock-div = <1>; 1846 clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>, 1847 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1848 clock-names = "main", "dma"; 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 status = "disabled"; 1852 }; 1853 1854 imp_iic_wrap_s: clock-controller@11d03000 { 1855 compatible = "mediatek,mt8195-imp_iic_wrap_s"; 1856 reg = <0 0x11d03000 0 0x1000>; 1857 #clock-cells = <1>; 1858 }; 1859 1860 i2c0: i2c@11e00000 { 1861 compatible = "mediatek,mt8195-i2c", 1862 "mediatek,mt8192-i2c"; 1863 reg = <0 0x11e00000 0 0x1000>, 1864 <0 0x10220080 0 0x80>; 1865 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>; 1866 clock-div = <1>; 1867 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>, 1868 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1869 clock-names = "main", "dma"; 1870 #address-cells = <1>; 1871 #size-cells = <0>; 1872 status = "disabled"; 1873 }; 1874 1875 i2c1: i2c@11e01000 { 1876 compatible = "mediatek,mt8195-i2c", 1877 "mediatek,mt8192-i2c"; 1878 reg = <0 0x11e01000 0 0x1000>, 1879 <0 0x10220200 0 0x80>; 1880 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>; 1881 clock-div = <1>; 1882 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>, 1883 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1884 clock-names = "main", "dma"; 1885 #address-cells = <1>; 1886 #size-cells = <0>; 1887 status = "disabled"; 1888 }; 1889 1890 i2c2: i2c@11e02000 { 1891 compatible = "mediatek,mt8195-i2c", 1892 "mediatek,mt8192-i2c"; 1893 reg = <0 0x11e02000 0 0x1000>, 1894 <0 0x10220380 0 0x80>; 1895 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>; 1896 clock-div = <1>; 1897 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>, 1898 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1899 clock-names = "main", "dma"; 1900 #address-cells = <1>; 1901 #size-cells = <0>; 1902 status = "disabled"; 1903 }; 1904 1905 i2c3: i2c@11e03000 { 1906 compatible = "mediatek,mt8195-i2c", 1907 "mediatek,mt8192-i2c"; 1908 reg = <0 0x11e03000 0 0x1000>, 1909 <0 0x10220480 0 0x80>; 1910 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>; 1911 clock-div = <1>; 1912 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>, 1913 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1914 clock-names = "main", "dma"; 1915 #address-cells = <1>; 1916 #size-cells = <0>; 1917 status = "disabled"; 1918 }; 1919 1920 i2c4: i2c@11e04000 { 1921 compatible = "mediatek,mt8195-i2c", 1922 "mediatek,mt8192-i2c"; 1923 reg = <0 0x11e04000 0 0x1000>, 1924 <0 0x10220500 0 0x80>; 1925 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>; 1926 clock-div = <1>; 1927 clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>, 1928 <&infracfg_ao CLK_INFRA_AO_APDMA_B>; 1929 clock-names = "main", "dma"; 1930 #address-cells = <1>; 1931 #size-cells = <0>; 1932 status = "disabled"; 1933 }; 1934 1935 imp_iic_wrap_w: clock-controller@11e05000 { 1936 compatible = "mediatek,mt8195-imp_iic_wrap_w"; 1937 reg = <0 0x11e05000 0 0x1000>; 1938 #clock-cells = <1>; 1939 }; 1940 1941 u3phy1: t-phy@11e30000 { 1942 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1943 #address-cells = <1>; 1944 #size-cells = <1>; 1945 ranges = <0 0 0x11e30000 0xe00>; 1946 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>; 1947 status = "disabled"; 1948 1949 u2port1: usb-phy@0 { 1950 reg = <0x0 0x700>; 1951 clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>, 1952 <&clk26m>; 1953 clock-names = "ref", "da_ref"; 1954 #phy-cells = <1>; 1955 }; 1956 1957 u3port1: usb-phy@700 { 1958 reg = <0x700 0x700>; 1959 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1960 <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>; 1961 clock-names = "ref", "da_ref"; 1962 nvmem-cells = <&comb_intr_p1>, 1963 <&comb_rx_imp_p1>, 1964 <&comb_tx_imp_p1>; 1965 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1966 #phy-cells = <1>; 1967 }; 1968 }; 1969 1970 u3phy0: t-phy@11e40000 { 1971 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3"; 1972 #address-cells = <1>; 1973 #size-cells = <1>; 1974 ranges = <0 0 0x11e40000 0xe00>; 1975 status = "disabled"; 1976 1977 u2port0: usb-phy@0 { 1978 reg = <0x0 0x700>; 1979 clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>, 1980 <&clk26m>; 1981 clock-names = "ref", "da_ref"; 1982 #phy-cells = <1>; 1983 }; 1984 1985 u3port0: usb-phy@700 { 1986 reg = <0x700 0x700>; 1987 clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>, 1988 <&topckgen CLK_TOP_SSUSB_PHY_REF>; 1989 clock-names = "ref", "da_ref"; 1990 nvmem-cells = <&u3_intr_p0>, 1991 <&u3_rx_imp_p0>, 1992 <&u3_tx_imp_p0>; 1993 nvmem-cell-names = "intr", "rx_imp", "tx_imp"; 1994 #phy-cells = <1>; 1995 }; 1996 }; 1997 1998 pciephy: phy@11e80000 { 1999 compatible = "mediatek,mt8195-pcie-phy"; 2000 reg = <0 0x11e80000 0 0x10000>; 2001 reg-names = "sif"; 2002 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>, 2003 <&pciephy_tx_ln0_nmos>, <&pciephy_rx_ln0>, 2004 <&pciephy_tx_ln1_pmos>, <&pciephy_tx_ln1_nmos>, 2005 <&pciephy_rx_ln1>; 2006 nvmem-cell-names = "glb_intr", "tx_ln0_pmos", 2007 "tx_ln0_nmos", "rx_ln0", 2008 "tx_ln1_pmos", "tx_ln1_nmos", 2009 "rx_ln1"; 2010 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>; 2011 #phy-cells = <0>; 2012 status = "disabled"; 2013 }; 2014 2015 ufsphy: ufs-phy@11fa0000 { 2016 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy"; 2017 reg = <0 0x11fa0000 0 0xc000>; 2018 clocks = <&clk26m>, <&clk26m>; 2019 clock-names = "unipro", "mp"; 2020 #phy-cells = <0>; 2021 status = "disabled"; 2022 }; 2023 2024 gpu: gpu@13000000 { 2025 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali", 2026 "arm,mali-valhall-jm"; 2027 reg = <0 0x13000000 0 0x4000>; 2028 2029 clocks = <&mfgcfg CLK_MFG_BG3D>; 2030 interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>, 2031 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>, 2032 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH 0>; 2033 interrupt-names = "job", "mmu", "gpu"; 2034 operating-points-v2 = <&gpu_opp_table>; 2035 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>, 2036 <&spm MT8195_POWER_DOMAIN_MFG3>, 2037 <&spm MT8195_POWER_DOMAIN_MFG4>, 2038 <&spm MT8195_POWER_DOMAIN_MFG5>, 2039 <&spm MT8195_POWER_DOMAIN_MFG6>; 2040 power-domain-names = "core0", "core1", "core2", "core3", "core4"; 2041 status = "disabled"; 2042 }; 2043 2044 mfgcfg: clock-controller@13fbf000 { 2045 compatible = "mediatek,mt8195-mfgcfg"; 2046 reg = <0 0x13fbf000 0 0x1000>; 2047 #clock-cells = <1>; 2048 }; 2049 2050 vppsys0: syscon@14000000 { 2051 compatible = "mediatek,mt8195-vppsys0", "syscon"; 2052 reg = <0 0x14000000 0 0x1000>; 2053 #clock-cells = <1>; 2054 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0 0x1000>; 2055 }; 2056 2057 dma-controller@14001000 { 2058 compatible = "mediatek,mt8195-mdp3-rdma"; 2059 reg = <0 0x14001000 0 0x1000>; 2060 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x1000 0x1000>; 2061 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RDMA_SOF>, 2062 <CMDQ_EVENT_VPP0_MDP_RDMA_FRAME_DONE>; 2063 mediatek,scp = <&scp>; 2064 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2065 iommus = <&iommu_vpp M4U_PORT_L4_MDP_RDMA>; 2066 clocks = <&vppsys0 CLK_VPP0_MDP_RDMA>; 2067 mboxes = <&gce1 12 CMDQ_THR_PRIO_1>, 2068 <&gce1 13 CMDQ_THR_PRIO_1>, 2069 <&gce1 14 CMDQ_THR_PRIO_1>, 2070 <&gce1 21 CMDQ_THR_PRIO_1>, 2071 <&gce1 22 CMDQ_THR_PRIO_1>; 2072 #dma-cells = <1>; 2073 }; 2074 2075 display@14002000 { 2076 compatible = "mediatek,mt8195-mdp3-fg"; 2077 reg = <0 0x14002000 0 0x1000>; 2078 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; 2079 clocks = <&vppsys0 CLK_VPP0_MDP_FG>; 2080 }; 2081 2082 display@14003000 { 2083 compatible = "mediatek,mt8195-mdp3-stitch"; 2084 reg = <0 0x14003000 0 0x1000>; 2085 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; 2086 clocks = <&vppsys0 CLK_VPP0_STITCH>; 2087 }; 2088 2089 display@14004000 { 2090 compatible = "mediatek,mt8195-mdp3-hdr"; 2091 reg = <0 0x14004000 0 0x1000>; 2092 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; 2093 clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; 2094 }; 2095 2096 display@14005000 { 2097 compatible = "mediatek,mt8195-mdp3-aal"; 2098 reg = <0 0x14005000 0 0x1000>; 2099 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH 0>; 2100 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x5000 0x1000>; 2101 clocks = <&vppsys0 CLK_VPP0_MDP_AAL>; 2102 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2103 }; 2104 2105 display@14006000 { 2106 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2107 reg = <0 0x14006000 0 0x1000>; 2108 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x6000 0x1000>; 2109 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_RSZ_IN_RSZ_SOF>, 2110 <CMDQ_EVENT_VPP0_MDP_RSZ_FRAME_DONE>; 2111 clocks = <&vppsys0 CLK_VPP0_MDP_RSZ>; 2112 }; 2113 2114 display@14007000 { 2115 compatible = "mediatek,mt8195-mdp3-tdshp"; 2116 reg = <0 0x14007000 0 0x1000>; 2117 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; 2118 clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; 2119 }; 2120 2121 display@14008000 { 2122 compatible = "mediatek,mt8195-mdp3-color"; 2123 reg = <0 0x14008000 0 0x1000>; 2124 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH 0>; 2125 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x8000 0x1000>; 2126 clocks = <&vppsys0 CLK_VPP0_MDP_COLOR>; 2127 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2128 }; 2129 2130 display@14009000 { 2131 compatible = "mediatek,mt8195-mdp3-ovl"; 2132 reg = <0 0x14009000 0 0x1000>; 2133 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>; 2134 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x9000 0x1000>; 2135 clocks = <&vppsys0 CLK_VPP0_MDP_OVL>; 2136 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2137 iommus = <&iommu_vpp M4U_PORT_L4_MDP_OVL>; 2138 }; 2139 2140 display@1400a000 { 2141 compatible = "mediatek,mt8195-mdp3-padding"; 2142 reg = <0 0x1400a000 0 0x1000>; 2143 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xa000 0x1000>; 2144 clocks = <&vppsys0 CLK_VPP0_PADDING>; 2145 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2146 }; 2147 2148 display@1400b000 { 2149 compatible = "mediatek,mt8195-mdp3-tcc"; 2150 reg = <0 0x1400b000 0 0x1000>; 2151 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; 2152 clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; 2153 }; 2154 2155 dma-controller@1400c000 { 2156 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2157 reg = <0 0x1400c000 0 0x1000>; 2158 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xc000 0x1000>; 2159 mediatek,gce-events = <CMDQ_EVENT_VPP0_MDP_WROT_SOF>, 2160 <CMDQ_EVENT_VPP0_MDP_WROT_VIDO_WDONE>; 2161 clocks = <&vppsys0 CLK_VPP0_MDP_WROT>; 2162 iommus = <&iommu_vpp M4U_PORT_L4_MDP_WROT>; 2163 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2164 #dma-cells = <1>; 2165 }; 2166 2167 mutex@1400f000 { 2168 compatible = "mediatek,mt8195-vpp-mutex"; 2169 reg = <0 0x1400f000 0 0x1000>; 2170 interrupts = <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH 0>; 2171 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>; 2172 clocks = <&vppsys0 CLK_VPP0_MUTEX>; 2173 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2174 }; 2175 2176 smi_sub_common_vpp0_vpp1_2x1: smi@14010000 { 2177 compatible = "mediatek,mt8195-smi-sub-common"; 2178 reg = <0 0x14010000 0 0x1000>; 2179 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2180 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2181 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2182 clock-names = "apb", "smi", "gals0"; 2183 mediatek,smi = <&smi_common_vpp>; 2184 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2185 }; 2186 2187 smi_sub_common_vdec_vpp0_2x1: smi@14011000 { 2188 compatible = "mediatek,mt8195-smi-sub-common"; 2189 reg = <0 0x14011000 0 0x1000>; 2190 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2191 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2192 <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>; 2193 clock-names = "apb", "smi", "gals0"; 2194 mediatek,smi = <&smi_common_vpp>; 2195 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2196 }; 2197 2198 smi_common_vpp: smi@14012000 { 2199 compatible = "mediatek,mt8195-smi-common-vpp"; 2200 reg = <0 0x14012000 0 0x1000>; 2201 clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2202 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, 2203 <&vppsys0 CLK_VPP0_SMI_RSI>, 2204 <&vppsys0 CLK_VPP0_SMI_RSI>; 2205 clock-names = "apb", "smi", "gals0", "gals1"; 2206 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2207 }; 2208 2209 larb4: larb@14013000 { 2210 compatible = "mediatek,mt8195-smi-larb"; 2211 reg = <0 0x14013000 0 0x1000>; 2212 mediatek,larb-id = <4>; 2213 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2214 clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>, 2215 <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>; 2216 clock-names = "apb", "smi"; 2217 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2218 }; 2219 2220 iommu_vpp: iommu@14018000 { 2221 compatible = "mediatek,mt8195-iommu-vpp"; 2222 reg = <0 0x14018000 0 0x1000>; 2223 mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8 2224 &larb12 &larb14 &larb16 &larb18 2225 &larb20 &larb22 &larb23 &larb26 2226 &larb27>; 2227 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>; 2228 clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>; 2229 clock-names = "bclk"; 2230 #iommu-cells = <1>; 2231 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>; 2232 }; 2233 2234 wpesys: clock-controller@14e00000 { 2235 compatible = "mediatek,mt8195-wpesys"; 2236 reg = <0 0x14e00000 0 0x1000>; 2237 #clock-cells = <1>; 2238 }; 2239 2240 wpesys_vpp0: clock-controller@14e02000 { 2241 compatible = "mediatek,mt8195-wpesys_vpp0"; 2242 reg = <0 0x14e02000 0 0x1000>; 2243 #clock-cells = <1>; 2244 }; 2245 2246 wpesys_vpp1: clock-controller@14e03000 { 2247 compatible = "mediatek,mt8195-wpesys_vpp1"; 2248 reg = <0 0x14e03000 0 0x1000>; 2249 #clock-cells = <1>; 2250 }; 2251 2252 larb7: larb@14e04000 { 2253 compatible = "mediatek,mt8195-smi-larb"; 2254 reg = <0 0x14e04000 0 0x1000>; 2255 mediatek,larb-id = <7>; 2256 mediatek,smi = <&smi_common_vdo>; 2257 clocks = <&wpesys CLK_WPE_SMI_LARB7>, 2258 <&wpesys CLK_WPE_SMI_LARB7>; 2259 clock-names = "apb", "smi"; 2260 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2261 }; 2262 2263 larb8: larb@14e05000 { 2264 compatible = "mediatek,mt8195-smi-larb"; 2265 reg = <0 0x14e05000 0 0x1000>; 2266 mediatek,larb-id = <8>; 2267 mediatek,smi = <&smi_common_vpp>; 2268 clocks = <&wpesys CLK_WPE_SMI_LARB8>, 2269 <&wpesys CLK_WPE_SMI_LARB8>, 2270 <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>; 2271 clock-names = "apb", "smi", "gals"; 2272 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>; 2273 }; 2274 2275 vppsys1: syscon@14f00000 { 2276 compatible = "mediatek,mt8195-vppsys1", "syscon"; 2277 reg = <0 0x14f00000 0 0x1000>; 2278 #clock-cells = <1>; 2279 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0 0x1000>; 2280 }; 2281 2282 mutex@14f01000 { 2283 compatible = "mediatek,mt8195-vpp-mutex"; 2284 reg = <0 0x14f01000 0 0x1000>; 2285 interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL_HIGH 0>; 2286 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>; 2287 clocks = <&vppsys1 CLK_VPP1_DISP_MUTEX>; 2288 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2289 }; 2290 2291 larb5: larb@14f02000 { 2292 compatible = "mediatek,mt8195-smi-larb"; 2293 reg = <0 0x14f02000 0 0x1000>; 2294 mediatek,larb-id = <5>; 2295 mediatek,smi = <&smi_common_vdo>; 2296 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2297 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2298 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>; 2299 clock-names = "apb", "smi", "gals"; 2300 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2301 }; 2302 2303 larb6: larb@14f03000 { 2304 compatible = "mediatek,mt8195-smi-larb"; 2305 reg = <0 0x14f03000 0 0x1000>; 2306 mediatek,larb-id = <6>; 2307 mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>; 2308 clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>, 2309 <&vppsys1 CLK_VPP1_VPPSYS1_GALS>, 2310 <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>; 2311 clock-names = "apb", "smi", "gals"; 2312 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2313 }; 2314 2315 display@14f06000 { 2316 compatible = "mediatek,mt8195-mdp3-split"; 2317 reg = <0 0x14f06000 0 0x1000>; 2318 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x6000 0x1000>; 2319 clocks = <&vppsys1 CLK_VPP1_VPP_SPLIT>, 2320 <&vppsys1 CLK_VPP1_HDMI_META>, 2321 <&vppsys1 CLK_VPP1_VPP_SPLIT_HDMI>; 2322 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2323 }; 2324 2325 display@14f07000 { 2326 compatible = "mediatek,mt8195-mdp3-tcc"; 2327 reg = <0 0x14f07000 0 0x1000>; 2328 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x7000 0x1000>; 2329 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TCC>; 2330 }; 2331 2332 dma-controller@14f08000 { 2333 compatible = "mediatek,mt8195-mdp3-rdma"; 2334 reg = <0 0x14f08000 0 0x1000>; 2335 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x8000 0x1000>; 2336 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_SOF>, 2337 <CMDQ_EVENT_VPP1_SVPP1_MDP_RDMA_FRAME_DONE>; 2338 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RDMA>; 2339 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_RDMA>; 2340 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2341 #dma-cells = <1>; 2342 }; 2343 2344 dma-controller@14f09000 { 2345 compatible = "mediatek,mt8195-mdp3-rdma"; 2346 reg = <0 0x14f09000 0 0x1000>; 2347 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x9000 0x1000>; 2348 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_SOF>, 2349 <CMDQ_EVENT_VPP1_SVPP2_MDP_RDMA_FRAME_DONE>; 2350 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RDMA>; 2351 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_RDMA>; 2352 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2353 #dma-cells = <1>; 2354 }; 2355 2356 dma-controller@14f0a000 { 2357 compatible = "mediatek,mt8195-mdp3-rdma"; 2358 reg = <0 0x14f0a000 0 0x1000>; 2359 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xa000 0x1000>; 2360 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_SOF>, 2361 <CMDQ_EVENT_VPP1_SVPP3_MDP_RDMA_FRAME_DONE>; 2362 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RDMA>; 2363 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_RDMA>; 2364 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2365 #dma-cells = <1>; 2366 }; 2367 2368 display@14f0b000 { 2369 compatible = "mediatek,mt8195-mdp3-fg"; 2370 reg = <0 0x14f0b000 0 0x1000>; 2371 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xb000 0x1000>; 2372 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_FG>; 2373 }; 2374 2375 display@14f0c000 { 2376 compatible = "mediatek,mt8195-mdp3-fg"; 2377 reg = <0 0x14f0c000 0 0x1000>; 2378 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xc000 0x1000>; 2379 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_FG>; 2380 }; 2381 2382 display@14f0d000 { 2383 compatible = "mediatek,mt8195-mdp3-fg"; 2384 reg = <0 0x14f0d000 0 0x1000>; 2385 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xd000 0x1000>; 2386 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_FG>; 2387 }; 2388 2389 display@14f0e000 { 2390 compatible = "mediatek,mt8195-mdp3-hdr"; 2391 reg = <0 0x14f0e000 0 0x1000>; 2392 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xe000 0x1000>; 2393 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_HDR>; 2394 }; 2395 2396 display@14f0f000 { 2397 compatible = "mediatek,mt8195-mdp3-hdr"; 2398 reg = <0 0x14f0f000 0 0x1000>; 2399 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0xf000 0x1000>; 2400 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_HDR>; 2401 }; 2402 2403 display@14f10000 { 2404 compatible = "mediatek,mt8195-mdp3-hdr"; 2405 reg = <0 0x14f10000 0 0x1000>; 2406 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0 0x1000>; 2407 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_HDR>; 2408 }; 2409 2410 display@14f11000 { 2411 compatible = "mediatek,mt8195-mdp3-aal"; 2412 reg = <0 0x14f11000 0 0x1000>; 2413 interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH 0>; 2414 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x1000 0x1000>; 2415 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_AAL>; 2416 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2417 }; 2418 2419 display@14f12000 { 2420 compatible = "mediatek,mt8195-mdp3-aal"; 2421 reg = <0 0x14f12000 0 0x1000>; 2422 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH 0>; 2423 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x2000 0x1000>; 2424 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_AAL>; 2425 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2426 }; 2427 2428 display@14f13000 { 2429 compatible = "mediatek,mt8195-mdp3-aal"; 2430 reg = <0 0x14f13000 0 0x1000>; 2431 interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH 0>; 2432 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x3000 0x1000>; 2433 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_AAL>; 2434 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2435 }; 2436 2437 display@14f14000 { 2438 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2439 reg = <0 0x14f14000 0 0x1000>; 2440 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x4000 0x1000>; 2441 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_SOF>, 2442 <CMDQ_EVENT_VPP1_SVPP1_MDP_RSZ_FRAME_DONE>; 2443 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_RSZ>; 2444 }; 2445 2446 display@14f15000 { 2447 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2448 reg = <0 0x14f15000 0 0x1000>; 2449 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x5000 0x1000>; 2450 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_SOF>, 2451 <CMDQ_EVENT_VPP1_SVPP2_MDP_RSZ_FRAME_DONE>; 2452 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_RSZ>; 2453 }; 2454 2455 display@14f16000 { 2456 compatible = "mediatek,mt8195-mdp3-rsz", "mediatek,mt8183-mdp3-rsz"; 2457 reg = <0 0x14f16000 0 0x1000>; 2458 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x6000 0x1000>; 2459 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_SOF>, 2460 <CMDQ_EVENT_VPP1_SVPP3_MDP_RSZ_FRAME_DONE>; 2461 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_RSZ>; 2462 }; 2463 2464 display@14f17000 { 2465 compatible = "mediatek,mt8195-mdp3-tdshp"; 2466 reg = <0 0x14f17000 0 0x1000>; 2467 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x7000 0x1000>; 2468 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_TDSHP>; 2469 }; 2470 2471 display@14f18000 { 2472 compatible = "mediatek,mt8195-mdp3-tdshp"; 2473 reg = <0 0x14f18000 0 0x1000>; 2474 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x8000 0x1000>; 2475 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_TDSHP>; 2476 }; 2477 2478 display@14f19000 { 2479 compatible = "mediatek,mt8195-mdp3-tdshp"; 2480 reg = <0 0x14f19000 0 0x1000>; 2481 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0x9000 0x1000>; 2482 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_TDSHP>; 2483 }; 2484 2485 display@14f1a000 { 2486 compatible = "mediatek,mt8195-mdp3-merge"; 2487 reg = <0 0x14f1a000 0 0x1000>; 2488 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xa000 0x1000>; 2489 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_MERGE>; 2490 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2491 }; 2492 2493 display@14f1b000 { 2494 compatible = "mediatek,mt8195-mdp3-merge"; 2495 reg = <0 0x14f1b000 0 0x1000>; 2496 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xb000 0x1000>; 2497 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_MERGE>; 2498 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2499 }; 2500 2501 display@14f1c000 { 2502 compatible = "mediatek,mt8195-mdp3-color"; 2503 reg = <0 0x14f1c000 0 0x1000>; 2504 interrupts = <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH 0>; 2505 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xc000 0x1000>; 2506 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_COLOR>; 2507 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2508 }; 2509 2510 display@14f1d000 { 2511 compatible = "mediatek,mt8195-mdp3-color"; 2512 reg = <0 0x14f1d000 0 0x1000>; 2513 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xd000 0x1000>; 2514 interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH 0>; 2515 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_COLOR>; 2516 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2517 }; 2518 2519 display@14f1e000 { 2520 compatible = "mediatek,mt8195-mdp3-color"; 2521 reg = <0 0x14f1e000 0 0x1000>; 2522 interrupts = <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH 0>; 2523 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xe000 0x1000>; 2524 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_COLOR>; 2525 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2526 }; 2527 2528 display@14f1f000 { 2529 compatible = "mediatek,mt8195-mdp3-ovl"; 2530 reg = <0 0x14f1f000 0 0x1000>; 2531 interrupts = <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH 0>; 2532 mediatek,gce-client-reg = <&gce1 SUBSYS_14f1XXXX 0xf000 0x1000>; 2533 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_OVL>; 2534 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2535 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_OVL>; 2536 }; 2537 2538 display@14f20000 { 2539 compatible = "mediatek,mt8195-mdp3-padding"; 2540 reg = <0 0x14f20000 0 0x1000>; 2541 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0 0x1000>; 2542 clocks = <&vppsys1 CLK_VPP1_SVPP1_VPP_PAD>; 2543 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2544 }; 2545 2546 display@14f21000 { 2547 compatible = "mediatek,mt8195-mdp3-padding"; 2548 reg = <0 0x14f21000 0 0x1000>; 2549 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x1000 0x1000>; 2550 clocks = <&vppsys1 CLK_VPP1_SVPP2_VPP_PAD>; 2551 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2552 }; 2553 2554 display@14f22000 { 2555 compatible = "mediatek,mt8195-mdp3-padding"; 2556 reg = <0 0x14f22000 0 0x1000>; 2557 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x2000 0x1000>; 2558 clocks = <&vppsys1 CLK_VPP1_SVPP3_VPP_PAD>; 2559 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2560 }; 2561 2562 dma-controller@14f23000 { 2563 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2564 reg = <0 0x14f23000 0 0x1000>; 2565 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x3000 0x1000>; 2566 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_SOF>, 2567 <CMDQ_EVENT_VPP1_SVPP1_MDP_WROT_FRAME_DONE>; 2568 clocks = <&vppsys1 CLK_VPP1_SVPP1_MDP_WROT>; 2569 iommus = <&iommu_vdo M4U_PORT_L5_SVPP1_MDP_WROT>; 2570 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2571 #dma-cells = <1>; 2572 }; 2573 2574 dma-controller@14f24000 { 2575 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2576 reg = <0 0x14f24000 0 0x1000>; 2577 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x4000 0x1000>; 2578 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_SOF>, 2579 <CMDQ_EVENT_VPP1_SVPP2_MDP_WROT_FRAME_DONE>; 2580 clocks = <&vppsys1 CLK_VPP1_SVPP2_MDP_WROT>; 2581 iommus = <&iommu_vdo M4U_PORT_L5_SVPP2_MDP_WROT>; 2582 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2583 #dma-cells = <1>; 2584 }; 2585 2586 dma-controller@14f25000 { 2587 compatible = "mediatek,mt8195-mdp3-wrot", "mediatek,mt8183-mdp3-wrot"; 2588 reg = <0 0x14f25000 0 0x1000>; 2589 mediatek,gce-client-reg = <&gce1 SUBSYS_14f2XXXX 0x5000 0x1000>; 2590 mediatek,gce-events = <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_SOF>, 2591 <CMDQ_EVENT_VPP1_SVPP3_MDP_WROT_FRAME_DONE>; 2592 clocks = <&vppsys1 CLK_VPP1_SVPP3_MDP_WROT>; 2593 iommus = <&iommu_vpp M4U_PORT_L6_SVPP3_MDP_WROT>; 2594 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>; 2595 #dma-cells = <1>; 2596 }; 2597 2598 imgsys: clock-controller@15000000 { 2599 compatible = "mediatek,mt8195-imgsys"; 2600 reg = <0 0x15000000 0 0x1000>; 2601 #clock-cells = <1>; 2602 }; 2603 2604 larb9: larb@15001000 { 2605 compatible = "mediatek,mt8195-smi-larb"; 2606 reg = <0 0x15001000 0 0x1000>; 2607 mediatek,larb-id = <9>; 2608 mediatek,smi = <&smi_sub_common_img1_3x1>; 2609 clocks = <&imgsys CLK_IMG_LARB9>, 2610 <&imgsys CLK_IMG_LARB9>, 2611 <&imgsys CLK_IMG_GALS>; 2612 clock-names = "apb", "smi", "gals"; 2613 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2614 }; 2615 2616 smi_sub_common_img0_3x1: smi@15002000 { 2617 compatible = "mediatek,mt8195-smi-sub-common"; 2618 reg = <0 0x15002000 0 0x1000>; 2619 clocks = <&imgsys CLK_IMG_IPE>, 2620 <&imgsys CLK_IMG_IPE>, 2621 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2622 clock-names = "apb", "smi", "gals0"; 2623 mediatek,smi = <&smi_common_vpp>; 2624 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2625 }; 2626 2627 smi_sub_common_img1_3x1: smi@15003000 { 2628 compatible = "mediatek,mt8195-smi-sub-common"; 2629 reg = <0 0x15003000 0 0x1000>; 2630 clocks = <&imgsys CLK_IMG_LARB9>, 2631 <&imgsys CLK_IMG_LARB9>, 2632 <&imgsys CLK_IMG_GALS>; 2633 clock-names = "apb", "smi", "gals0"; 2634 mediatek,smi = <&smi_common_vdo>; 2635 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>; 2636 }; 2637 2638 imgsys1_dip_top: clock-controller@15110000 { 2639 compatible = "mediatek,mt8195-imgsys1_dip_top"; 2640 reg = <0 0x15110000 0 0x1000>; 2641 #clock-cells = <1>; 2642 }; 2643 2644 larb10: larb@15120000 { 2645 compatible = "mediatek,mt8195-smi-larb"; 2646 reg = <0 0x15120000 0 0x1000>; 2647 mediatek,larb-id = <10>; 2648 mediatek,smi = <&smi_sub_common_img1_3x1>; 2649 clocks = <&imgsys CLK_IMG_DIP0>, 2650 <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>; 2651 clock-names = "apb", "smi"; 2652 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2653 }; 2654 2655 imgsys1_dip_nr: clock-controller@15130000 { 2656 compatible = "mediatek,mt8195-imgsys1_dip_nr"; 2657 reg = <0 0x15130000 0 0x1000>; 2658 #clock-cells = <1>; 2659 }; 2660 2661 imgsys1_wpe: clock-controller@15220000 { 2662 compatible = "mediatek,mt8195-imgsys1_wpe"; 2663 reg = <0 0x15220000 0 0x1000>; 2664 #clock-cells = <1>; 2665 }; 2666 2667 larb11: larb@15230000 { 2668 compatible = "mediatek,mt8195-smi-larb"; 2669 reg = <0 0x15230000 0 0x1000>; 2670 mediatek,larb-id = <11>; 2671 mediatek,smi = <&smi_sub_common_img1_3x1>; 2672 clocks = <&imgsys CLK_IMG_WPE0>, 2673 <&imgsys1_wpe CLK_IMG1_WPE_LARB11>; 2674 clock-names = "apb", "smi"; 2675 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>; 2676 }; 2677 2678 ipesys: clock-controller@15330000 { 2679 compatible = "mediatek,mt8195-ipesys"; 2680 reg = <0 0x15330000 0 0x1000>; 2681 #clock-cells = <1>; 2682 }; 2683 2684 larb12: larb@15340000 { 2685 compatible = "mediatek,mt8195-smi-larb"; 2686 reg = <0 0x15340000 0 0x1000>; 2687 mediatek,larb-id = <12>; 2688 mediatek,smi = <&smi_sub_common_img0_3x1>; 2689 clocks = <&ipesys CLK_IPE_SMI_LARB12>, 2690 <&ipesys CLK_IPE_SMI_LARB12>; 2691 clock-names = "apb", "smi"; 2692 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>; 2693 }; 2694 2695 camsys: clock-controller@16000000 { 2696 compatible = "mediatek,mt8195-camsys"; 2697 reg = <0 0x16000000 0 0x1000>; 2698 #clock-cells = <1>; 2699 }; 2700 2701 larb13: larb@16001000 { 2702 compatible = "mediatek,mt8195-smi-larb"; 2703 reg = <0 0x16001000 0 0x1000>; 2704 mediatek,larb-id = <13>; 2705 mediatek,smi = <&smi_sub_common_cam_4x1>; 2706 clocks = <&camsys CLK_CAM_LARB13>, 2707 <&camsys CLK_CAM_LARB13>, 2708 <&camsys CLK_CAM_CAM2MM0_GALS>; 2709 clock-names = "apb", "smi", "gals"; 2710 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2711 }; 2712 2713 larb14: larb@16002000 { 2714 compatible = "mediatek,mt8195-smi-larb"; 2715 reg = <0 0x16002000 0 0x1000>; 2716 mediatek,larb-id = <14>; 2717 mediatek,smi = <&smi_sub_common_cam_7x1>; 2718 clocks = <&camsys CLK_CAM_LARB14>, 2719 <&camsys CLK_CAM_LARB14>; 2720 clock-names = "apb", "smi"; 2721 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2722 }; 2723 2724 smi_sub_common_cam_4x1: smi@16004000 { 2725 compatible = "mediatek,mt8195-smi-sub-common"; 2726 reg = <0 0x16004000 0 0x1000>; 2727 clocks = <&camsys CLK_CAM_LARB13>, 2728 <&camsys CLK_CAM_LARB13>, 2729 <&camsys CLK_CAM_CAM2MM0_GALS>; 2730 clock-names = "apb", "smi", "gals0"; 2731 mediatek,smi = <&smi_common_vdo>; 2732 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2733 }; 2734 2735 smi_sub_common_cam_7x1: smi@16005000 { 2736 compatible = "mediatek,mt8195-smi-sub-common"; 2737 reg = <0 0x16005000 0 0x1000>; 2738 clocks = <&camsys CLK_CAM_LARB14>, 2739 <&camsys CLK_CAM_CAM2MM1_GALS>, 2740 <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>; 2741 clock-names = "apb", "smi", "gals0"; 2742 mediatek,smi = <&smi_common_vpp>; 2743 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2744 }; 2745 2746 larb16: larb@16012000 { 2747 compatible = "mediatek,mt8195-smi-larb"; 2748 reg = <0 0x16012000 0 0x1000>; 2749 mediatek,larb-id = <16>; 2750 mediatek,smi = <&smi_sub_common_cam_7x1>; 2751 clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>, 2752 <&camsys_rawa CLK_CAM_RAWA_LARBX>; 2753 clock-names = "apb", "smi"; 2754 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2755 }; 2756 2757 larb17: larb@16013000 { 2758 compatible = "mediatek,mt8195-smi-larb"; 2759 reg = <0 0x16013000 0 0x1000>; 2760 mediatek,larb-id = <17>; 2761 mediatek,smi = <&smi_sub_common_cam_4x1>; 2762 clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>, 2763 <&camsys_yuva CLK_CAM_YUVA_LARBX>; 2764 clock-names = "apb", "smi"; 2765 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>; 2766 }; 2767 2768 larb27: larb@16014000 { 2769 compatible = "mediatek,mt8195-smi-larb"; 2770 reg = <0 0x16014000 0 0x1000>; 2771 mediatek,larb-id = <27>; 2772 mediatek,smi = <&smi_sub_common_cam_7x1>; 2773 clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>, 2774 <&camsys_rawb CLK_CAM_RAWB_LARBX>; 2775 clock-names = "apb", "smi"; 2776 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2777 }; 2778 2779 larb28: larb@16015000 { 2780 compatible = "mediatek,mt8195-smi-larb"; 2781 reg = <0 0x16015000 0 0x1000>; 2782 mediatek,larb-id = <28>; 2783 mediatek,smi = <&smi_sub_common_cam_4x1>; 2784 clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>, 2785 <&camsys_yuvb CLK_CAM_YUVB_LARBX>; 2786 clock-names = "apb", "smi"; 2787 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>; 2788 }; 2789 2790 camsys_rawa: clock-controller@1604f000 { 2791 compatible = "mediatek,mt8195-camsys_rawa"; 2792 reg = <0 0x1604f000 0 0x1000>; 2793 #clock-cells = <1>; 2794 }; 2795 2796 camsys_yuva: clock-controller@1606f000 { 2797 compatible = "mediatek,mt8195-camsys_yuva"; 2798 reg = <0 0x1606f000 0 0x1000>; 2799 #clock-cells = <1>; 2800 }; 2801 2802 camsys_rawb: clock-controller@1608f000 { 2803 compatible = "mediatek,mt8195-camsys_rawb"; 2804 reg = <0 0x1608f000 0 0x1000>; 2805 #clock-cells = <1>; 2806 }; 2807 2808 camsys_yuvb: clock-controller@160af000 { 2809 compatible = "mediatek,mt8195-camsys_yuvb"; 2810 reg = <0 0x160af000 0 0x1000>; 2811 #clock-cells = <1>; 2812 }; 2813 2814 camsys_mraw: clock-controller@16140000 { 2815 compatible = "mediatek,mt8195-camsys_mraw"; 2816 reg = <0 0x16140000 0 0x1000>; 2817 #clock-cells = <1>; 2818 }; 2819 2820 larb25: larb@16141000 { 2821 compatible = "mediatek,mt8195-smi-larb"; 2822 reg = <0 0x16141000 0 0x1000>; 2823 mediatek,larb-id = <25>; 2824 mediatek,smi = <&smi_sub_common_cam_4x1>; 2825 clocks = <&camsys CLK_CAM_LARB13>, 2826 <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2827 <&camsys CLK_CAM_CAM2MM0_GALS>; 2828 clock-names = "apb", "smi", "gals"; 2829 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2830 }; 2831 2832 larb26: larb@16142000 { 2833 compatible = "mediatek,mt8195-smi-larb"; 2834 reg = <0 0x16142000 0 0x1000>; 2835 mediatek,larb-id = <26>; 2836 mediatek,smi = <&smi_sub_common_cam_7x1>; 2837 clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>, 2838 <&camsys_mraw CLK_CAM_MRAW_LARBX>; 2839 clock-names = "apb", "smi"; 2840 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>; 2841 2842 }; 2843 2844 ccusys: clock-controller@17200000 { 2845 compatible = "mediatek,mt8195-ccusys"; 2846 reg = <0 0x17200000 0 0x1000>; 2847 #clock-cells = <1>; 2848 }; 2849 2850 larb18: larb@17201000 { 2851 compatible = "mediatek,mt8195-smi-larb"; 2852 reg = <0 0x17201000 0 0x1000>; 2853 mediatek,larb-id = <18>; 2854 mediatek,smi = <&smi_sub_common_cam_7x1>; 2855 clocks = <&ccusys CLK_CCU_LARB18>, 2856 <&ccusys CLK_CCU_LARB18>; 2857 clock-names = "apb", "smi"; 2858 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; 2859 }; 2860 2861 video-codec@18000000 { 2862 compatible = "mediatek,mt8195-vcodec-dec"; 2863 mediatek,scp = <&scp>; 2864 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; 2865 #address-cells = <2>; 2866 #size-cells = <2>; 2867 reg = <0 0x18000000 0 0x1000>, 2868 <0 0x18004000 0 0x1000>; 2869 ranges = <0 0 0 0x18000000 0 0x26000>; 2870 2871 video-codec@2000 { 2872 compatible = "mediatek,mtk-vcodec-lat-soc"; 2873 reg = <0 0x2000 0 0x800>; 2874 iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, 2875 <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; 2876 clocks = <&topckgen CLK_TOP_VDEC>, 2877 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2878 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2879 <&topckgen CLK_TOP_UNIVPLL_D4>; 2880 clock-names = "sel", "vdec", "lat", "top"; 2881 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2882 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2883 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2884 }; 2885 2886 video-codec@10000 { 2887 compatible = "mediatek,mtk-vcodec-lat"; 2888 reg = <0 0x10000 0 0x800>; 2889 interrupts = <GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH 0>; 2890 iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, 2891 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, 2892 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, 2893 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, 2894 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, 2895 <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; 2896 clocks = <&topckgen CLK_TOP_VDEC>, 2897 <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 2898 <&vdecsys_soc CLK_VDEC_SOC_LAT>, 2899 <&topckgen CLK_TOP_UNIVPLL_D4>; 2900 clock-names = "sel", "vdec", "lat", "top"; 2901 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2902 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2903 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2904 }; 2905 2906 video-codec@25000 { 2907 compatible = "mediatek,mtk-vcodec-core"; 2908 reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ 2909 interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH 0>; 2910 iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, 2911 <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, 2912 <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, 2913 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, 2914 <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, 2915 <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, 2916 <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, 2917 <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, 2918 <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, 2919 <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; 2920 clocks = <&topckgen CLK_TOP_VDEC>, 2921 <&vdecsys CLK_VDEC_VDEC>, 2922 <&vdecsys CLK_VDEC_LAT>, 2923 <&topckgen CLK_TOP_UNIVPLL_D4>; 2924 clock-names = "sel", "vdec", "lat", "top"; 2925 assigned-clocks = <&topckgen CLK_TOP_VDEC>; 2926 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 2927 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2928 }; 2929 }; 2930 2931 larb24: larb@1800d000 { 2932 compatible = "mediatek,mt8195-smi-larb"; 2933 reg = <0 0x1800d000 0 0x1000>; 2934 mediatek,larb-id = <24>; 2935 mediatek,smi = <&smi_common_vdo>; 2936 clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 2937 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2938 clock-names = "apb", "smi"; 2939 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2940 }; 2941 2942 larb23: larb@1800e000 { 2943 compatible = "mediatek,mt8195-smi-larb"; 2944 reg = <0 0x1800e000 0 0x1000>; 2945 mediatek,larb-id = <23>; 2946 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2947 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2948 <&vdecsys_soc CLK_VDEC_SOC_LARB1>; 2949 clock-names = "apb", "smi"; 2950 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 2951 }; 2952 2953 vdecsys_soc: clock-controller@1800f000 { 2954 compatible = "mediatek,mt8195-vdecsys_soc"; 2955 reg = <0 0x1800f000 0 0x1000>; 2956 #clock-cells = <1>; 2957 }; 2958 2959 larb21: larb@1802e000 { 2960 compatible = "mediatek,mt8195-smi-larb"; 2961 reg = <0 0x1802e000 0 0x1000>; 2962 mediatek,larb-id = <21>; 2963 mediatek,smi = <&smi_common_vdo>; 2964 clocks = <&vdecsys CLK_VDEC_LARB1>, 2965 <&vdecsys CLK_VDEC_LARB1>; 2966 clock-names = "apb", "smi"; 2967 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 2968 }; 2969 2970 vdecsys: clock-controller@1802f000 { 2971 compatible = "mediatek,mt8195-vdecsys"; 2972 reg = <0 0x1802f000 0 0x1000>; 2973 #clock-cells = <1>; 2974 }; 2975 2976 larb22: larb@1803e000 { 2977 compatible = "mediatek,mt8195-smi-larb"; 2978 reg = <0 0x1803e000 0 0x1000>; 2979 mediatek,larb-id = <22>; 2980 mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>; 2981 clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, 2982 <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>; 2983 clock-names = "apb", "smi"; 2984 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 2985 }; 2986 2987 vdecsys_core1: clock-controller@1803f000 { 2988 compatible = "mediatek,mt8195-vdecsys_core1"; 2989 reg = <0 0x1803f000 0 0x1000>; 2990 #clock-cells = <1>; 2991 }; 2992 2993 apusys_pll: clock-controller@190f3000 { 2994 compatible = "mediatek,mt8195-apusys_pll"; 2995 reg = <0 0x190f3000 0 0x1000>; 2996 #clock-cells = <1>; 2997 }; 2998 2999 vencsys: clock-controller@1a000000 { 3000 compatible = "mediatek,mt8195-vencsys"; 3001 reg = <0 0x1a000000 0 0x1000>; 3002 #clock-cells = <1>; 3003 }; 3004 3005 larb19: larb@1a010000 { 3006 compatible = "mediatek,mt8195-smi-larb"; 3007 reg = <0 0x1a010000 0 0x1000>; 3008 mediatek,larb-id = <19>; 3009 mediatek,smi = <&smi_common_vdo>; 3010 clocks = <&vencsys CLK_VENC_VENC>, 3011 <&vencsys CLK_VENC_GALS>; 3012 clock-names = "apb", "smi"; 3013 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3014 }; 3015 3016 venc: video-codec@1a020000 { 3017 compatible = "mediatek,mt8195-vcodec-enc"; 3018 reg = <0 0x1a020000 0 0x10000>; 3019 iommus = <&iommu_vdo M4U_PORT_L19_VENC_RCPU>, 3020 <&iommu_vdo M4U_PORT_L19_VENC_REC>, 3021 <&iommu_vdo M4U_PORT_L19_VENC_BSDMA>, 3022 <&iommu_vdo M4U_PORT_L19_VENC_SV_COMV>, 3023 <&iommu_vdo M4U_PORT_L19_VENC_RD_COMV>, 3024 <&iommu_vdo M4U_PORT_L19_VENC_CUR_LUMA>, 3025 <&iommu_vdo M4U_PORT_L19_VENC_CUR_CHROMA>, 3026 <&iommu_vdo M4U_PORT_L19_VENC_REF_LUMA>, 3027 <&iommu_vdo M4U_PORT_L19_VENC_REF_CHROMA>; 3028 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH 0>; 3029 mediatek,scp = <&scp>; 3030 clocks = <&vencsys CLK_VENC_VENC>; 3031 clock-names = "venc_sel"; 3032 assigned-clocks = <&topckgen CLK_TOP_VENC>; 3033 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; 3034 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3035 #address-cells = <2>; 3036 #size-cells = <2>; 3037 }; 3038 3039 jpeg-decoder@1a040000 { 3040 compatible = "mediatek,mt8195-jpgdec"; 3041 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 3042 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3043 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3044 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3045 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3046 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3047 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3048 #address-cells = <2>; 3049 #size-cells = <2>; 3050 ranges = <0 0 0 0x1a040000 0 0x20000>, 3051 <1 0 0 0x1b040000 0 0x10000>; 3052 3053 jpgdec@0,0 { 3054 compatible = "mediatek,mt8195-jpgdec-hw"; 3055 reg = <0 0 0 0x10000>;/* JPGDEC_C0 */ 3056 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3057 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3058 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3059 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3060 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3061 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3062 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>; 3063 clocks = <&vencsys CLK_VENC_JPGDEC>; 3064 clock-names = "jpgdec"; 3065 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; 3066 }; 3067 3068 jpgdec@0,10000 { 3069 compatible = "mediatek,mt8195-jpgdec-hw"; 3070 reg = <0 0x10000 0 0x10000>;/* JPGDEC_C1 */ 3071 iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>, 3072 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>, 3073 <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>, 3074 <&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>, 3075 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>, 3076 <&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>; 3077 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>; 3078 clocks = <&vencsys CLK_VENC_JPGDEC_C1>; 3079 clock-names = "jpgdec"; 3080 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; 3081 }; 3082 3083 jpgdec@1,0 { 3084 compatible = "mediatek,mt8195-jpgdec-hw"; 3085 reg = <1 0 0 0x10000>;/* JPGDEC_C2 */ 3086 iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>, 3087 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>, 3088 <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>, 3089 <&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>, 3090 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>, 3091 <&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>; 3092 interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>; 3093 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>; 3094 clock-names = "jpgdec"; 3095 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>; 3096 }; 3097 }; 3098 3099 vencsys_core1: clock-controller@1b000000 { 3100 compatible = "mediatek,mt8195-vencsys_core1"; 3101 reg = <0 0x1b000000 0 0x1000>; 3102 #clock-cells = <1>; 3103 }; 3104 3105 vdosys0: syscon@1c01a000 { 3106 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon"; 3107 reg = <0 0x1c01a000 0 0x1000>; 3108 mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; 3109 #clock-cells = <1>; 3110 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xa000 0x1000>; 3111 }; 3112 3113 3114 jpeg-encoder@1a030000 { 3115 compatible = "mediatek,mt8195-jpgenc"; 3116 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3117 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3118 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3119 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3120 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3121 #address-cells = <2>; 3122 #size-cells = <2>; 3123 ranges = <0 0 0 0x1a030000 0 0x10000>, 3124 <1 0 0 0x1b030000 0 0x10000>; 3125 3126 jpgenc@0,0 { 3127 compatible = "mediatek,mt8195-jpgenc-hw"; 3128 reg = <0 0 0 0x10000>; 3129 iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>, 3130 <&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>, 3131 <&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>, 3132 <&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>; 3133 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>; 3134 clocks = <&vencsys CLK_VENC_JPGENC>; 3135 clock-names = "jpgenc"; 3136 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>; 3137 }; 3138 3139 jpgenc@1,0 { 3140 compatible = "mediatek,mt8195-jpgenc-hw"; 3141 reg = <1 0 0 0x10000>; 3142 iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>, 3143 <&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>, 3144 <&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>, 3145 <&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>; 3146 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>; 3147 clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>; 3148 clock-names = "jpgenc"; 3149 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3150 }; 3151 }; 3152 3153 larb20: larb@1b010000 { 3154 compatible = "mediatek,mt8195-smi-larb"; 3155 reg = <0 0x1b010000 0 0x1000>; 3156 mediatek,larb-id = <20>; 3157 mediatek,smi = <&smi_common_vpp>; 3158 clocks = <&vencsys_core1 CLK_VENC_CORE1_VENC>, 3159 <&vencsys_core1 CLK_VENC_CORE1_GALS>, 3160 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3161 clock-names = "apb", "smi", "gals"; 3162 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>; 3163 }; 3164 3165 ovl0: ovl@1c000000 { 3166 compatible = "mediatek,mt8195-disp-ovl"; 3167 reg = <0 0x1c000000 0 0x1000>; 3168 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>; 3169 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3170 clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>; 3171 iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>; 3172 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>; 3173 3174 ports { 3175 #address-cells = <1>; 3176 #size-cells = <0>; 3177 3178 port@0 { 3179 reg = <0>; 3180 ovl0_in: endpoint { }; 3181 }; 3182 3183 port@1 { 3184 reg = <1>; 3185 ovl0_out: endpoint { 3186 remote-endpoint = <&rdma0_in>; 3187 }; 3188 }; 3189 }; 3190 }; 3191 3192 rdma0: rdma@1c002000 { 3193 compatible = "mediatek,mt8195-disp-rdma"; 3194 reg = <0 0x1c002000 0 0x1000>; 3195 interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>; 3196 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3197 clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>; 3198 iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>; 3199 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>; 3200 3201 ports { 3202 #address-cells = <1>; 3203 #size-cells = <0>; 3204 3205 port@0 { 3206 reg = <0>; 3207 rdma0_in: endpoint { 3208 remote-endpoint = <&ovl0_out>; 3209 }; 3210 }; 3211 3212 port@1 { 3213 reg = <1>; 3214 rdma0_out: endpoint { 3215 remote-endpoint = <&color0_in>; 3216 }; 3217 }; 3218 }; 3219 }; 3220 3221 color0: color@1c003000 { 3222 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color"; 3223 reg = <0 0x1c003000 0 0x1000>; 3224 interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>; 3225 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3226 clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>; 3227 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>; 3228 3229 ports { 3230 #address-cells = <1>; 3231 #size-cells = <0>; 3232 3233 port@0 { 3234 reg = <0>; 3235 color0_in: endpoint { 3236 remote-endpoint = <&rdma0_out>; 3237 }; 3238 }; 3239 3240 port@1 { 3241 reg = <1>; 3242 color0_out: endpoint { 3243 remote-endpoint = <&ccorr0_in>; 3244 }; 3245 }; 3246 }; 3247 }; 3248 3249 ccorr0: ccorr@1c004000 { 3250 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr"; 3251 reg = <0 0x1c004000 0 0x1000>; 3252 interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>; 3253 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3254 clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>; 3255 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>; 3256 3257 ports { 3258 #address-cells = <1>; 3259 #size-cells = <0>; 3260 3261 port@0 { 3262 reg = <0>; 3263 ccorr0_in: endpoint { 3264 remote-endpoint = <&color0_out>; 3265 }; 3266 }; 3267 3268 port@1 { 3269 reg = <1>; 3270 ccorr0_out: endpoint { 3271 remote-endpoint = <&aal0_in>; 3272 }; 3273 }; 3274 }; 3275 }; 3276 3277 aal0: aal@1c005000 { 3278 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal"; 3279 reg = <0 0x1c005000 0 0x1000>; 3280 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>; 3281 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3282 clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>; 3283 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>; 3284 3285 ports { 3286 #address-cells = <1>; 3287 #size-cells = <0>; 3288 3289 port@0 { 3290 reg = <0>; 3291 aal0_in: endpoint { 3292 remote-endpoint = <&ccorr0_out>; 3293 }; 3294 }; 3295 3296 port@1 { 3297 reg = <1>; 3298 aal0_out: endpoint { 3299 remote-endpoint = <&gamma0_in>; 3300 }; 3301 }; 3302 }; 3303 }; 3304 3305 gamma0: gamma@1c006000 { 3306 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma"; 3307 reg = <0 0x1c006000 0 0x1000>; 3308 interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>; 3309 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3310 clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>; 3311 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>; 3312 3313 ports { 3314 #address-cells = <1>; 3315 #size-cells = <0>; 3316 3317 port@0 { 3318 reg = <0>; 3319 gamma0_in: endpoint { 3320 remote-endpoint = <&aal0_out>; 3321 }; 3322 }; 3323 3324 port@1 { 3325 reg = <1>; 3326 gamma0_out: endpoint { 3327 remote-endpoint = <&dither0_in>; 3328 }; 3329 }; 3330 }; 3331 }; 3332 3333 dither0: dither@1c007000 { 3334 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither"; 3335 reg = <0 0x1c007000 0 0x1000>; 3336 interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>; 3337 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3338 clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>; 3339 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>; 3340 3341 ports { 3342 #address-cells = <1>; 3343 #size-cells = <0>; 3344 3345 port@0 { 3346 reg = <0>; 3347 dither0_in: endpoint { 3348 remote-endpoint = <&gamma0_out>; 3349 }; 3350 }; 3351 3352 port@1 { 3353 reg = <1>; 3354 dither0_out: endpoint { }; 3355 }; 3356 }; 3357 }; 3358 3359 dsi0: dsi@1c008000 { 3360 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3361 reg = <0 0x1c008000 0 0x1000>; 3362 interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH 0>; 3363 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3364 clocks = <&vdosys0 CLK_VDO0_DSI0>, 3365 <&vdosys0 CLK_VDO0_DSI0_DSI>, 3366 <&mipi_tx0>; 3367 clock-names = "engine", "digital", "hs"; 3368 phys = <&mipi_tx0>; 3369 phy-names = "dphy"; 3370 status = "disabled"; 3371 }; 3372 3373 dsc0: dsc@1c009000 { 3374 compatible = "mediatek,mt8195-disp-dsc"; 3375 reg = <0 0x1c009000 0 0x1000>; 3376 interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>; 3377 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3378 clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>; 3379 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>; 3380 }; 3381 3382 dsi1: dsi@1c012000 { 3383 compatible = "mediatek,mt8195-dsi", "mediatek,mt8183-dsi"; 3384 reg = <0 0x1c012000 0 0x1000>; 3385 interrupts = <GIC_SPI 654 IRQ_TYPE_LEVEL_HIGH 0>; 3386 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3387 clocks = <&vdosys0 CLK_VDO0_DSI1>, 3388 <&vdosys0 CLK_VDO0_DSI1_DSI>, 3389 <&mipi_tx1>; 3390 clock-names = "engine", "digital", "hs"; 3391 phys = <&mipi_tx1>; 3392 phy-names = "dphy"; 3393 status = "disabled"; 3394 }; 3395 3396 merge0: merge@1c014000 { 3397 compatible = "mediatek,mt8195-disp-merge"; 3398 reg = <0 0x1c014000 0 0x1000>; 3399 interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>; 3400 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3401 clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>; 3402 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; 3403 }; 3404 3405 dp_intf0: dp-intf@1c015000 { 3406 compatible = "mediatek,mt8195-dp-intf"; 3407 reg = <0 0x1c015000 0 0x1000>; 3408 interrupts = <GIC_SPI 657 IRQ_TYPE_LEVEL_HIGH 0>; 3409 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3410 clocks = <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, 3411 <&vdosys0 CLK_VDO0_DP_INTF0>, 3412 <&apmixedsys CLK_APMIXED_TVDPLL1>; 3413 clock-names = "pixel", "engine", "pll"; 3414 status = "disabled"; 3415 }; 3416 3417 mutex: mutex@1c016000 { 3418 compatible = "mediatek,mt8195-disp-mutex"; 3419 reg = <0 0x1c016000 0 0x1000>; 3420 interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>; 3421 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3422 clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>; 3423 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x6000 0x1000>; 3424 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>; 3425 }; 3426 3427 larb0: larb@1c018000 { 3428 compatible = "mediatek,mt8195-smi-larb"; 3429 reg = <0 0x1c018000 0 0x1000>; 3430 mediatek,larb-id = <0>; 3431 mediatek,smi = <&smi_common_vdo>; 3432 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3433 <&vdosys0 CLK_VDO0_SMI_LARB>, 3434 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>; 3435 clock-names = "apb", "smi", "gals"; 3436 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3437 }; 3438 3439 larb1: larb@1c019000 { 3440 compatible = "mediatek,mt8195-smi-larb"; 3441 reg = <0 0x1c019000 0 0x1000>; 3442 mediatek,larb-id = <1>; 3443 mediatek,smi = <&smi_common_vpp>; 3444 clocks = <&vdosys0 CLK_VDO0_SMI_LARB>, 3445 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>, 3446 <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>; 3447 clock-names = "apb", "smi", "gals"; 3448 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3449 }; 3450 3451 vdosys1: syscon@1c100000 { 3452 compatible = "mediatek,mt8195-vdosys1", "syscon"; 3453 reg = <0 0x1c100000 0 0x1000>; 3454 mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; 3455 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>; 3456 #clock-cells = <1>; 3457 #reset-cells = <1>; 3458 }; 3459 3460 smi_common_vdo: smi@1c01b000 { 3461 compatible = "mediatek,mt8195-smi-common-vdo"; 3462 reg = <0 0x1c01b000 0 0x1000>; 3463 clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>, 3464 <&vdosys0 CLK_VDO0_SMI_EMI>, 3465 <&vdosys0 CLK_VDO0_SMI_RSI>, 3466 <&vdosys0 CLK_VDO0_SMI_GALS>; 3467 clock-names = "apb", "smi", "gals0", "gals1"; 3468 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3469 3470 }; 3471 3472 iommu_vdo: iommu@1c01f000 { 3473 compatible = "mediatek,mt8195-iommu-vdo"; 3474 reg = <0 0x1c01f000 0 0x1000>; 3475 mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9 3476 &larb10 &larb11 &larb13 &larb17 3477 &larb19 &larb21 &larb24 &larb25 3478 &larb28>; 3479 interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>; 3480 #iommu-cells = <1>; 3481 clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>; 3482 clock-names = "bclk"; 3483 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>; 3484 }; 3485 3486 mutex1: mutex@1c101000 { 3487 compatible = "mediatek,mt8195-disp-mutex"; 3488 reg = <0 0x1c101000 0 0x1000>; 3489 interrupts = <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>; 3490 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3491 clocks = <&vdosys1 CLK_VDO1_DISP_MUTEX>; 3492 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x1000 0x1000>; 3493 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>; 3494 }; 3495 3496 larb2: larb@1c102000 { 3497 compatible = "mediatek,mt8195-smi-larb"; 3498 reg = <0 0x1c102000 0 0x1000>; 3499 mediatek,larb-id = <2>; 3500 mediatek,smi = <&smi_common_vdo>; 3501 clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>, 3502 <&vdosys1 CLK_VDO1_SMI_LARB2>, 3503 <&vdosys1 CLK_VDO1_GALS>; 3504 clock-names = "apb", "smi", "gals"; 3505 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3506 }; 3507 3508 larb3: larb@1c103000 { 3509 compatible = "mediatek,mt8195-smi-larb"; 3510 reg = <0 0x1c103000 0 0x1000>; 3511 mediatek,larb-id = <3>; 3512 mediatek,smi = <&smi_common_vpp>; 3513 clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>, 3514 <&vdosys1 CLK_VDO1_GALS>, 3515 <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; 3516 clock-names = "apb", "smi", "gals"; 3517 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3518 }; 3519 3520 vdo1_rdma0: dma-controller@1c104000 { 3521 compatible = "mediatek,mt8195-vdo1-rdma"; 3522 reg = <0 0x1c104000 0 0x1000>; 3523 interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>; 3524 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; 3525 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3526 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; 3527 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; 3528 #dma-cells = <1>; 3529 }; 3530 3531 vdo1_rdma1: dma-controller@1c105000 { 3532 compatible = "mediatek,mt8195-vdo1-rdma"; 3533 reg = <0 0x1c105000 0 0x1000>; 3534 interrupts = <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>; 3535 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA1>; 3536 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3537 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>; 3538 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>; 3539 #dma-cells = <1>; 3540 }; 3541 3542 vdo1_rdma2: dma-controller@1c106000 { 3543 compatible = "mediatek,mt8195-vdo1-rdma"; 3544 reg = <0 0x1c106000 0 0x1000>; 3545 interrupts = <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>; 3546 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA2>; 3547 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3548 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>; 3549 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>; 3550 #dma-cells = <1>; 3551 }; 3552 3553 vdo1_rdma3: dma-controller@1c107000 { 3554 compatible = "mediatek,mt8195-vdo1-rdma"; 3555 reg = <0 0x1c107000 0 0x1000>; 3556 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>; 3557 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA3>; 3558 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3559 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>; 3560 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>; 3561 #dma-cells = <1>; 3562 }; 3563 3564 vdo1_rdma4: dma-controller@1c108000 { 3565 compatible = "mediatek,mt8195-vdo1-rdma"; 3566 reg = <0 0x1c108000 0 0x1000>; 3567 interrupts = <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>; 3568 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA4>; 3569 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3570 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>; 3571 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>; 3572 #dma-cells = <1>; 3573 }; 3574 3575 vdo1_rdma5: dma-controller@1c109000 { 3576 compatible = "mediatek,mt8195-vdo1-rdma"; 3577 reg = <0 0x1c109000 0 0x1000>; 3578 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>; 3579 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA5>; 3580 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3581 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>; 3582 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>; 3583 #dma-cells = <1>; 3584 }; 3585 3586 vdo1_rdma6: dma-controller@1c10a000 { 3587 compatible = "mediatek,mt8195-vdo1-rdma"; 3588 reg = <0 0x1c10a000 0 0x1000>; 3589 interrupts = <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>; 3590 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA6>; 3591 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3592 iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>; 3593 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>; 3594 #dma-cells = <1>; 3595 }; 3596 3597 vdo1_rdma7: dma-controller@1c10b000 { 3598 compatible = "mediatek,mt8195-vdo1-rdma"; 3599 reg = <0 0x1c10b000 0 0x1000>; 3600 interrupts = <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>; 3601 clocks = <&vdosys1 CLK_VDO1_MDP_RDMA7>; 3602 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3603 iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>; 3604 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>; 3605 #dma-cells = <1>; 3606 }; 3607 3608 merge1: vpp-merge@1c10c000 { 3609 compatible = "mediatek,mt8195-disp-merge"; 3610 reg = <0 0x1c10c000 0 0x1000>; 3611 interrupts = <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>; 3612 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE0>, 3613 <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>; 3614 clock-names = "merge","merge_async"; 3615 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3616 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>; 3617 mediatek,merge-mute; 3618 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC>; 3619 }; 3620 3621 merge2: vpp-merge@1c10d000 { 3622 compatible = "mediatek,mt8195-disp-merge"; 3623 reg = <0 0x1c10d000 0 0x1000>; 3624 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>; 3625 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE1>, 3626 <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>; 3627 clock-names = "merge","merge_async"; 3628 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3629 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>; 3630 mediatek,merge-mute; 3631 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC>; 3632 }; 3633 3634 merge3: vpp-merge@1c10e000 { 3635 compatible = "mediatek,mt8195-disp-merge"; 3636 reg = <0 0x1c10e000 0 0x1000>; 3637 interrupts = <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>; 3638 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE2>, 3639 <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>; 3640 clock-names = "merge","merge_async"; 3641 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3642 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>; 3643 mediatek,merge-mute; 3644 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC>; 3645 }; 3646 3647 merge4: vpp-merge@1c10f000 { 3648 compatible = "mediatek,mt8195-disp-merge"; 3649 reg = <0 0x1c10f000 0 0x1000>; 3650 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; 3651 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE3>, 3652 <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>; 3653 clock-names = "merge","merge_async"; 3654 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3655 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>; 3656 mediatek,merge-mute; 3657 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC>; 3658 }; 3659 3660 merge5: vpp-merge@1c110000 { 3661 compatible = "mediatek,mt8195-disp-merge"; 3662 reg = <0 0x1c110000 0 0x1000>; 3663 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>; 3664 clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>, 3665 <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>; 3666 clock-names = "merge","merge_async"; 3667 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3668 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>; 3669 mediatek,merge-fifo-en; 3670 resets = <&vdosys1 MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC>; 3671 }; 3672 3673 dp_intf1: dp-intf@1c113000 { 3674 compatible = "mediatek,mt8195-dp-intf"; 3675 reg = <0 0x1c113000 0 0x1000>; 3676 interrupts = <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>; 3677 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3678 clocks = <&vdosys1 CLK_VDO1_DPINTF>, 3679 <&vdosys1 CLK_VDO1_DP_INTF0_MM>, 3680 <&apmixedsys CLK_APMIXED_TVDPLL2>; 3681 clock-names = "pixel", "engine", "pll"; 3682 status = "disabled"; 3683 }; 3684 3685 ethdr0: hdr-engine@1c114000 { 3686 compatible = "mediatek,mt8195-disp-ethdr"; 3687 reg = <0 0x1c114000 0 0x1000>, 3688 <0 0x1c115000 0 0x1000>, 3689 <0 0x1c117000 0 0x1000>, 3690 <0 0x1c119000 0 0x1000>, 3691 <0 0x1c11a000 0 0x1000>, 3692 <0 0x1c11b000 0 0x1000>, 3693 <0 0x1c11c000 0 0x1000>; 3694 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3695 "vdo_be", "adl_ds"; 3696 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, 3697 <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, 3698 <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, 3699 <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, 3700 <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, 3701 <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, 3702 <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; 3703 clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, 3704 <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, 3705 <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, 3706 <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, 3707 <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, 3708 <&vdosys1 CLK_VDO1_HDR_VDO_BE>, 3709 <&vdosys1 CLK_VDO1_26M_SLOW>, 3710 <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, 3711 <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, 3712 <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, 3713 <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, 3714 <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, 3715 <&topckgen CLK_TOP_ETHDR>; 3716 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", 3717 "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", 3718 "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", 3719 "ethdr_top"; 3720 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; 3721 iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, 3722 <&iommu_vpp M4U_PORT_L3_HDR_ADL>; 3723 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */ 3724 resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, 3725 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, 3726 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, 3727 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, 3728 <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; 3729 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async", 3730 "gfx_fe1_async", "vdo_be_async"; 3731 }; 3732 3733 edp_tx: edp-tx@1c500000 { 3734 compatible = "mediatek,mt8195-edp-tx"; 3735 reg = <0 0x1c500000 0 0x8000>; 3736 nvmem-cells = <&dp_calibration>; 3737 nvmem-cell-names = "dp_calibration_data"; 3738 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>; 3739 interrupts = <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH 0>; 3740 max-linkrate-mhz = <8100>; 3741 status = "disabled"; 3742 }; 3743 3744 dp_tx: dp-tx@1c600000 { 3745 compatible = "mediatek,mt8195-dp-tx"; 3746 reg = <0 0x1c600000 0 0x8000>; 3747 nvmem-cells = <&dp_calibration>; 3748 nvmem-cell-names = "dp_calibration_data"; 3749 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>; 3750 interrupts = <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH 0>; 3751 max-linkrate-mhz = <8100>; 3752 status = "disabled"; 3753 }; 3754 }; 3755 3756 thermal_zones: thermal-zones { 3757 cpu0-thermal { 3758 polling-delay = <1000>; 3759 polling-delay-passive = <250>; 3760 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; 3761 3762 trips { 3763 cpu0_alert: trip-alert { 3764 temperature = <85000>; 3765 hysteresis = <2000>; 3766 type = "passive"; 3767 }; 3768 3769 cpu0_crit: trip-crit { 3770 temperature = <100000>; 3771 hysteresis = <2000>; 3772 type = "critical"; 3773 }; 3774 }; 3775 3776 cooling-maps { 3777 map0 { 3778 trip = <&cpu0_alert>; 3779 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3780 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3781 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3782 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3783 }; 3784 }; 3785 }; 3786 3787 cpu1-thermal { 3788 polling-delay = <1000>; 3789 polling-delay-passive = <250>; 3790 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>; 3791 3792 trips { 3793 cpu1_alert: trip-alert { 3794 temperature = <85000>; 3795 hysteresis = <2000>; 3796 type = "passive"; 3797 }; 3798 3799 cpu1_crit: trip-crit { 3800 temperature = <100000>; 3801 hysteresis = <2000>; 3802 type = "critical"; 3803 }; 3804 }; 3805 3806 cooling-maps { 3807 map0 { 3808 trip = <&cpu1_alert>; 3809 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3810 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3811 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3812 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3813 }; 3814 }; 3815 }; 3816 3817 cpu2-thermal { 3818 polling-delay = <1000>; 3819 polling-delay-passive = <250>; 3820 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>; 3821 3822 trips { 3823 cpu2_alert: trip-alert { 3824 temperature = <85000>; 3825 hysteresis = <2000>; 3826 type = "passive"; 3827 }; 3828 3829 cpu2_crit: trip-crit { 3830 temperature = <100000>; 3831 hysteresis = <2000>; 3832 type = "critical"; 3833 }; 3834 }; 3835 3836 cooling-maps { 3837 map0 { 3838 trip = <&cpu2_alert>; 3839 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3840 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3841 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3842 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3843 }; 3844 }; 3845 }; 3846 3847 cpu3-thermal { 3848 polling-delay = <1000>; 3849 polling-delay-passive = <250>; 3850 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>; 3851 3852 trips { 3853 cpu3_alert: trip-alert { 3854 temperature = <85000>; 3855 hysteresis = <2000>; 3856 type = "passive"; 3857 }; 3858 3859 cpu3_crit: trip-crit { 3860 temperature = <100000>; 3861 hysteresis = <2000>; 3862 type = "critical"; 3863 }; 3864 }; 3865 3866 cooling-maps { 3867 map0 { 3868 trip = <&cpu3_alert>; 3869 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3870 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3871 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3872 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3873 }; 3874 }; 3875 }; 3876 3877 cpu4-thermal { 3878 polling-delay = <1000>; 3879 polling-delay-passive = <250>; 3880 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>; 3881 3882 trips { 3883 cpu4_alert: trip-alert { 3884 temperature = <85000>; 3885 hysteresis = <2000>; 3886 type = "passive"; 3887 }; 3888 3889 cpu4_crit: trip-crit { 3890 temperature = <100000>; 3891 hysteresis = <2000>; 3892 type = "critical"; 3893 }; 3894 }; 3895 3896 cooling-maps { 3897 map0 { 3898 trip = <&cpu4_alert>; 3899 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3900 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3901 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3902 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3903 }; 3904 }; 3905 }; 3906 3907 cpu5-thermal { 3908 polling-delay = <1000>; 3909 polling-delay-passive = <250>; 3910 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>; 3911 3912 trips { 3913 cpu5_alert: trip-alert { 3914 temperature = <85000>; 3915 hysteresis = <2000>; 3916 type = "passive"; 3917 }; 3918 3919 cpu5_crit: trip-crit { 3920 temperature = <100000>; 3921 hysteresis = <2000>; 3922 type = "critical"; 3923 }; 3924 }; 3925 3926 cooling-maps { 3927 map0 { 3928 trip = <&cpu5_alert>; 3929 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3930 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3931 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3932 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3933 }; 3934 }; 3935 }; 3936 3937 cpu6-thermal { 3938 polling-delay = <1000>; 3939 polling-delay-passive = <250>; 3940 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>; 3941 3942 trips { 3943 cpu6_alert: trip-alert { 3944 temperature = <85000>; 3945 hysteresis = <2000>; 3946 type = "passive"; 3947 }; 3948 3949 cpu6_crit: trip-crit { 3950 temperature = <100000>; 3951 hysteresis = <2000>; 3952 type = "critical"; 3953 }; 3954 }; 3955 3956 cooling-maps { 3957 map0 { 3958 trip = <&cpu6_alert>; 3959 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3960 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3961 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3962 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3963 }; 3964 }; 3965 }; 3966 3967 cpu7-thermal { 3968 polling-delay = <1000>; 3969 polling-delay-passive = <250>; 3970 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>; 3971 3972 trips { 3973 cpu7_alert: trip-alert { 3974 temperature = <85000>; 3975 hysteresis = <2000>; 3976 type = "passive"; 3977 }; 3978 3979 cpu7_crit: trip-crit { 3980 temperature = <100000>; 3981 hysteresis = <2000>; 3982 type = "critical"; 3983 }; 3984 }; 3985 3986 cooling-maps { 3987 map0 { 3988 trip = <&cpu7_alert>; 3989 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3990 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3991 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 3992 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 3993 }; 3994 }; 3995 }; 3996 3997 vpu0-thermal { 3998 polling-delay = <1000>; 3999 polling-delay-passive = <250>; 4000 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>; 4001 4002 trips { 4003 vpu0_alert: trip-alert { 4004 temperature = <85000>; 4005 hysteresis = <2000>; 4006 type = "passive"; 4007 }; 4008 4009 vpu0_crit: trip-crit { 4010 temperature = <100000>; 4011 hysteresis = <2000>; 4012 type = "critical"; 4013 }; 4014 }; 4015 }; 4016 4017 vpu1-thermal { 4018 polling-delay = <1000>; 4019 polling-delay-passive = <250>; 4020 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>; 4021 4022 trips { 4023 vpu1_alert: trip-alert { 4024 temperature = <85000>; 4025 hysteresis = <2000>; 4026 type = "passive"; 4027 }; 4028 4029 vpu1_crit: trip-crit { 4030 temperature = <100000>; 4031 hysteresis = <2000>; 4032 type = "critical"; 4033 }; 4034 }; 4035 }; 4036 4037 gpu-thermal { 4038 polling-delay = <1000>; 4039 polling-delay-passive = <250>; 4040 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; 4041 4042 trips { 4043 gpu0_alert: trip-alert { 4044 temperature = <85000>; 4045 hysteresis = <2000>; 4046 type = "passive"; 4047 }; 4048 4049 gpu0_crit: trip-crit { 4050 temperature = <100000>; 4051 hysteresis = <2000>; 4052 type = "critical"; 4053 }; 4054 }; 4055 }; 4056 4057 gpu1-thermal { 4058 polling-delay = <1000>; 4059 polling-delay-passive = <250>; 4060 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>; 4061 4062 trips { 4063 gpu1_alert: trip-alert { 4064 temperature = <85000>; 4065 hysteresis = <2000>; 4066 type = "passive"; 4067 }; 4068 4069 gpu1_crit: trip-crit { 4070 temperature = <100000>; 4071 hysteresis = <2000>; 4072 type = "critical"; 4073 }; 4074 }; 4075 }; 4076 4077 vdec-thermal { 4078 polling-delay = <1000>; 4079 polling-delay-passive = <250>; 4080 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>; 4081 4082 trips { 4083 vdec_alert: trip-alert { 4084 temperature = <85000>; 4085 hysteresis = <2000>; 4086 type = "passive"; 4087 }; 4088 4089 vdec_crit: trip-crit { 4090 temperature = <100000>; 4091 hysteresis = <2000>; 4092 type = "critical"; 4093 }; 4094 }; 4095 }; 4096 4097 img-thermal { 4098 polling-delay = <1000>; 4099 polling-delay-passive = <250>; 4100 thermal-sensors = <&lvts_ap MT8195_AP_IMG>; 4101 4102 trips { 4103 img_alert: trip-alert { 4104 temperature = <85000>; 4105 hysteresis = <2000>; 4106 type = "passive"; 4107 }; 4108 4109 img_crit: trip-crit { 4110 temperature = <100000>; 4111 hysteresis = <2000>; 4112 type = "critical"; 4113 }; 4114 }; 4115 }; 4116 4117 infra-thermal { 4118 polling-delay = <1000>; 4119 polling-delay-passive = <250>; 4120 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>; 4121 4122 trips { 4123 infra_alert: trip-alert { 4124 temperature = <85000>; 4125 hysteresis = <2000>; 4126 type = "passive"; 4127 }; 4128 4129 infra_crit: trip-crit { 4130 temperature = <100000>; 4131 hysteresis = <2000>; 4132 type = "critical"; 4133 }; 4134 }; 4135 }; 4136 4137 cam0-thermal { 4138 polling-delay = <1000>; 4139 polling-delay-passive = <250>; 4140 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>; 4141 4142 trips { 4143 cam0_alert: trip-alert { 4144 temperature = <85000>; 4145 hysteresis = <2000>; 4146 type = "passive"; 4147 }; 4148 4149 cam0_crit: trip-crit { 4150 temperature = <100000>; 4151 hysteresis = <2000>; 4152 type = "critical"; 4153 }; 4154 }; 4155 }; 4156 4157 cam1-thermal { 4158 polling-delay = <1000>; 4159 polling-delay-passive = <250>; 4160 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>; 4161 4162 trips { 4163 cam1_alert: trip-alert { 4164 temperature = <85000>; 4165 hysteresis = <2000>; 4166 type = "passive"; 4167 }; 4168 4169 cam1_crit: trip-crit { 4170 temperature = <100000>; 4171 hysteresis = <2000>; 4172 type = "critical"; 4173 }; 4174 }; 4175 }; 4176 }; 4177};
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