FILE
mt8188-geralt.dtsi

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linux-6.19.14/arch/arm64/boot/dts/mediatek/mt8188-geralt.dtsi DEVICETREE
   1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
   2/*
   3 * Copyright (C) 2022 MediaTek Inc.
   4 */
   5/dts-v1/;
   6#include <dt-bindings/gpio/gpio.h>
   7#include "mt8188.dtsi"
   8#include "mt6359.dtsi"
   9
  10/ {
  11	aliases {
  12		dsi0 = &disp_dsi0;
  13		i2c0 = &i2c0;
  14		i2c1 = &i2c1;
  15		i2c2 = &i2c2;
  16		i2c3 = &i2c3;
  17		i2c4 = &i2c4;
  18		i2c5 = &i2c5;
  19		i2c6 = &i2c6;
  20		mmc0 = &mmc0;
  21		serial0 = &uart0;
  22	};
  23
  24	backlight_lcd0: backlight-lcd0 {
  25		compatible = "pwm-backlight";
  26		brightness-levels = <0 1023>;
  27		default-brightness-level = <576>;
  28		enable-gpios = <&pio 1 GPIO_ACTIVE_HIGH>;
  29		num-interpolated-steps = <1023>;
  30		power-supply = <&ppvar_sys>;
  31		pwms = <&disp_pwm0 0 500000>;
  32	};
  33
  34	chosen {
  35		stdout-path = "serial0:115200n8";
  36	};
  37
  38	dmic-codec {
  39		compatible = "dmic-codec";
  40		num-channels = <2>;
  41		wakeup-delay-ms = <100>;
  42	};
  43
  44	memory@40000000 {
  45		device_type = "memory";
  46		/* The size will be filled in by the bootloader */
  47		reg = <0 0x40000000 0 0>;
  48	};
  49
  50	/* system wide LDO 1.8V power rail */
  51	pp1800_ldo_z1: regulator-pp1800-ldo-z1 {
  52		compatible = "regulator-fixed";
  53		regulator-name = "pp1800_ldo_z1";
  54		/* controlled by PP3300_Z1 */
  55		regulator-always-on;
  56		regulator-boot-on;
  57		regulator-min-microvolt = <1800000>;
  58		regulator-max-microvolt = <1800000>;
  59		vin-supply = <&pp3300_z1>;
  60	};
  61
  62	/* separately switched 3.3V power rail */
  63	pp3300_s3: regulator-pp3300-s3 {
  64		compatible = "regulator-fixed";
  65		regulator-name = "pp3300_s3";
  66		/* controlled by PMIC */
  67		regulator-always-on;
  68		regulator-boot-on;
  69		regulator-min-microvolt = <3300000>;
  70		regulator-max-microvolt = <3300000>;
  71		vin-supply = <&pp3300_z1>;
  72	};
  73
  74	/* system wide 3.3V power rail */
  75	pp3300_z1: regulator-pp3300-z1 {
  76		compatible = "regulator-fixed";
  77		regulator-name = "pp3300_z1";
  78		/* controlled by PP3300_LDO_Z5 & EN_PWR_Z1 */
  79		regulator-always-on;
  80		regulator-boot-on;
  81		regulator-min-microvolt = <3300000>;
  82		regulator-max-microvolt = <3300000>;
  83		vin-supply = <&ppvar_sys>;
  84	};
  85
  86	pp3300_wlan: regulator-pp3300-wlan {
  87		compatible = "regulator-fixed";
  88		regulator-name = "pp3300_wlan";
  89		regulator-always-on;
  90		regulator-min-microvolt = <3300000>;
  91		regulator-max-microvolt = <3300000>;
  92		enable-active-high;
  93		gpio = <&pio 12 GPIO_ACTIVE_HIGH>;
  94		pinctrl-0 = <&wlan_en>;
  95		pinctrl-names = "default";
  96		vin-supply = <&pp3300_z1>;
  97	};
  98
  99	/* system wide 4.2V power rail */
 100	pp4200_s5: regulator-pp4200-s5 {
 101		compatible = "regulator-fixed";
 102		regulator-name = "pp4200_s5";
 103		/* controlled by EC */
 104		regulator-always-on;
 105		regulator-boot-on;
 106		regulator-min-microvolt = <4200000>;
 107		regulator-max-microvolt = <4200000>;
 108		vin-supply = <&ppvar_sys>;
 109	};
 110
 111	/* system wide 5.0V power rail */
 112	pp5000_z1: regulator-pp5000-z1 {
 113		compatible = "regulator-fixed";
 114		regulator-name = "pp5000_z1";
 115		/* controlled by EC */
 116		regulator-always-on;
 117		regulator-boot-on;
 118		regulator-min-microvolt = <5000000>;
 119		regulator-max-microvolt = <5000000>;
 120		vin-supply = <&ppvar_sys>;
 121	};
 122
 123	pp5000_usb_vbus: regulator-pp5000-usb-vbus {
 124		compatible = "regulator-fixed";
 125		regulator-name = "pp5000_usb_vbus";
 126		regulator-min-microvolt = <5000000>;
 127		regulator-max-microvolt = <5000000>;
 128		enable-active-high;
 129		gpio = <&pio 150 GPIO_ACTIVE_HIGH>;
 130		vin-supply = <&pp5000_z1>;
 131	};
 132
 133	/* system wide semi-regulated power rail from battery or USB */
 134	ppvar_sys: regulator-ppvar-sys {
 135		compatible = "regulator-fixed";
 136		regulator-name = "ppvar_sys";
 137		regulator-always-on;
 138		regulator-boot-on;
 139	};
 140
 141	ppvar_mipi_disp_avdd: regulator-ppvar-mipi-disp-avdd {
 142		compatible = "regulator-fixed";
 143		regulator-name = "ppvar_mipi_disp_avdd";
 144		enable-active-high;
 145		gpio = <&pio 3 GPIO_ACTIVE_HIGH>;
 146		pinctrl-names = "default";
 147		pinctrl-0 = <&mipi_disp_avdd_en>;
 148		vin-supply = <&pp5000_z1>;
 149	};
 150
 151	ppvar_mipi_disp_avee: regulator-ppvar-mipi-disp-avee {
 152		compatible = "regulator-fixed";
 153		regulator-name = "ppvar_mipi_disp_avee";
 154		regulator-enable-ramp-delay = <10000>;
 155		enable-active-high;
 156		gpio = <&pio 4 GPIO_ACTIVE_HIGH>;
 157		pinctrl-names = "default";
 158		pinctrl-0 = <&mipi_disp_avee_en>;
 159		vin-supply = <&pp5000_z1>;
 160	};
 161
 162	reserved_memory: reserved-memory {
 163		#address-cells = <2>;
 164		#size-cells = <2>;
 165		ranges;
 166
 167		scp_mem_reserved: memory@50000000 {
 168			compatible = "shared-dma-pool";
 169			reg = <0 0x50000000 0 0x800000>;
 170			no-map;
 171		};
 172
 173		apu_mem: memory@55000000 {
 174			compatible = "shared-dma-pool";
 175			reg = <0 0x55000000 0 0x1400000>;
 176		};
 177
 178		adsp_mem: memory@60000000 {
 179			compatible = "shared-dma-pool";
 180			reg = <0 0x60000000 0 0xf00000>;
 181			no-map;
 182		};
 183
 184		afe_dma_mem: memory@60f00000 {
 185			compatible = "shared-dma-pool";
 186			reg = <0 0x60f00000 0 0x100000>;
 187			no-map;
 188		};
 189
 190		adsp_dma_mem: memory@61000000 {
 191			compatible = "shared-dma-pool";
 192			reg = <0 0x61000000 0 0x100000>;
 193			no-map;
 194		};
 195	};
 196};
 197
 198&adsp {
 199	memory-region = <&adsp_dma_mem>, <&adsp_mem>;
 200	pinctrl-names = "default";
 201	pinctrl-0 = <&adsp_uart_pins>;
 202	status = "okay";
 203};
 204
 205&afe {
 206	memory-region = <&afe_dma_mem>;
 207	mediatek,etdm-out1-cowork-source = <0>; /* in1 */
 208	mediatek,etdm-in2-cowork-source = <3>; /* out2 */
 209	status = "okay";
 210};
 211
 212&auxadc {
 213	status = "okay";
 214};
 215
 216&cam_vcore {
 217	domain-supply = <&mt6359_vproc1_buck_reg>;
 218};
 219
 220/*
 221 * Geralt is the reference design and doesn't have target TDP.
 222 * Ciri is (currently) the only device following Geralt, and its
 223 * TDP target is 90 degrees.
 224 **/
 225&cpu_little0_alert0 {
 226	temperature = <90000>;
 227	hysteresis = <2000>;
 228	type = "passive";
 229};
 230
 231&cpu_little1_alert0 {
 232	temperature = <90000>;
 233	hysteresis = <2000>;
 234	type = "passive";
 235};
 236
 237&cpu_little2_alert0 {
 238	temperature = <90000>;
 239	hysteresis = <2000>;
 240	type = "passive";
 241};
 242
 243&cpu_little3_alert0 {
 244	temperature = <90000>;
 245	hysteresis = <2000>;
 246	type = "passive";
 247};
 248
 249&cpu_big0_alert0 {
 250	temperature = <90000>;
 251	hysteresis = <2000>;
 252	type = "passive";
 253};
 254
 255&cpu_big1_alert0 {
 256	temperature = <90000>;
 257	hysteresis = <2000>;
 258	type = "passive";
 259};
 260
 261&disp_dsi0 {
 262	#address-cells = <1>;
 263	#size-cells = <0>;
 264	status = "okay";
 265
 266	dsi_panel: panel@0 {
 267		/* Compatible string for different panels can be found in each device dts */
 268		reg = <0>;
 269		enable-gpios = <&pio 25 GPIO_ACTIVE_HIGH>;
 270		pinctrl-names = "default";
 271		pinctrl-0 = <&mipi_dsi_pins>;
 272
 273		backlight = <&backlight_lcd0>;
 274		avdd-supply = <&ppvar_mipi_disp_avdd>;
 275		avee-supply = <&ppvar_mipi_disp_avee>;
 276		pp1800-supply = <&mt6359_vm18_ldo_reg>;
 277		rotation = <270>;
 278
 279		status = "okay";
 280
 281		port {
 282			dsi_panel_in: endpoint {
 283				remote-endpoint = <&dsi0_out>;
 284			};
 285		};
 286	};
 287
 288	ports {
 289		#address-cells = <1>;
 290		#size-cells = <0>;
 291
 292		port@0 {
 293			reg = <0>;
 294			dsi0_in: endpoint {
 295				remote-endpoint = <&dither0_out>;
 296			};
 297		};
 298
 299		port@1 {
 300			reg = <1>;
 301			dsi0_out: endpoint {
 302				remote-endpoint = <&dsi_panel_in>;
 303			};
 304		};
 305	};
 306};
 307
 308&disp_pwm0 {
 309	pinctrl-names = "default";
 310	pinctrl-0 = <&disp_pwm0_pins>;
 311	status = "okay";
 312};
 313
 314&disp_pwm1 {
 315	pinctrl-names = "default";
 316	pinctrl-0 = <&disp_pwm1_pins>;
 317};
 318
 319&dither0_in {
 320	remote-endpoint = <&postmask0_out>;
 321};
 322
 323&dither0_out {
 324	remote-endpoint = <&dsi0_in>;
 325};
 326
 327&ethdr0 {
 328	ports {
 329		#address-cells = <1>;
 330		#size-cells = <0>;
 331
 332		port@0 {
 333			#address-cells = <1>;
 334			#size-cells = <0>;
 335			reg = <0>;
 336
 337			ethdr0_in: endpoint@1 {
 338				reg = <1>;
 339				remote-endpoint = <&vdosys1_ep_ext>;
 340			};
 341		};
 342
 343		port@1 {
 344			#address-cells = <1>;
 345			#size-cells = <0>;
 346			reg = <1>;
 347
 348			ethdr0_out: endpoint@1 {
 349				reg = <1>;
 350				remote-endpoint = <&merge5_in>;
 351			};
 352		};
 353	};
 354};
 355
 356&gamma0_out {
 357	remote-endpoint = <&postmask0_in>;
 358};
 359
 360&dp_intf1 {
 361	status = "okay";
 362
 363	ports {
 364		#address-cells = <1>;
 365		#size-cells = <0>;
 366
 367		port@0 {
 368			#address-cells = <1>;
 369			#size-cells = <0>;
 370			reg = <0>;
 371
 372			dp_intf1_in: endpoint@1 {
 373				reg = <1>;
 374				remote-endpoint = <&merge5_out>;
 375			};
 376		};
 377
 378		port@1 {
 379			#address-cells = <1>;
 380			#size-cells = <0>;
 381			reg = <1>;
 382
 383			dp_intf1_out: endpoint@1 {
 384				reg = <1>;
 385				remote-endpoint = <&dptx_in>;
 386			};
 387		};
 388	};
 389};
 390
 391&dp_tx {
 392	pinctrl-names = "default";
 393	pinctrl-0 = <&dp_tx_hpd>;
 394	#sound-dai-cells = <0>;
 395	status = "okay";
 396
 397	ports {
 398		#address-cells = <1>;
 399		#size-cells = <0>;
 400
 401		port@0 {
 402			reg = <0>;
 403			dptx_in: endpoint {
 404				remote-endpoint = <&dp_intf1_out>;
 405			};
 406		};
 407
 408		port@1 {
 409			reg = <1>;
 410			dptx_out: endpoint {
 411				data-lanes = <0 1 2 3>;
 412			};
 413		};
 414	};
 415};
 416
 417&gpu {
 418	mali-supply = <&mt6359_vproc2_buck_reg>;
 419	status = "okay";
 420};
 421
 422&i2c0 {
 423	pinctrl-names = "default";
 424	pinctrl-0 = <&i2c0_pins>;
 425	clock-frequency = <400000>;
 426	status = "okay";
 427};
 428
 429&i2c1 {
 430	pinctrl-names = "default";
 431	pinctrl-0 = <&i2c1_pins>;
 432	clock-frequency = <400000>;
 433	status = "okay";
 434
 435	tpm@50 {
 436		compatible = "google,cr50";
 437		reg = <0x50>;
 438		interrupts-extended = <&pio 0 IRQ_TYPE_EDGE_RISING>;
 439		pinctrl-names = "default";
 440		pinctrl-0 = <&gsc_int>;
 441	};
 442};
 443
 444&i2c2 {
 445	pinctrl-names = "default";
 446	pinctrl-0 = <&i2c2_pins>;
 447	clock-frequency = <400000>;
 448	status = "okay";
 449};
 450
 451&i2c3 {
 452	pinctrl-names = "default";
 453	pinctrl-0 = <&i2c3_pins>;
 454	clock-frequency = <400000>;
 455	status = "okay";
 456};
 457
 458&i2c4 {
 459	pinctrl-names = "default";
 460	pinctrl-0 = <&i2c4_pins>;
 461	clock-frequency = <400000>;
 462	status = "okay";
 463};
 464
 465&i2c5 {
 466	pinctrl-names = "default";
 467	pinctrl-0 = <&i2c5_pins>;
 468	clock-frequency = <400000>;
 469	status = "okay";
 470};
 471
 472&i2c6 {
 473	pinctrl-names = "default";
 474	pinctrl-0 = <&i2c6_pins>;
 475	clock-frequency = <400000>;
 476	status = "okay";
 477};
 478
 479&merge5 {
 480	ports {
 481		#address-cells = <1>;
 482		#size-cells = <0>;
 483
 484		port@0 {
 485			#address-cells = <1>;
 486			#size-cells = <0>;
 487			reg = <0>;
 488
 489			merge5_in: endpoint@1 {
 490				reg = <1>;
 491				remote-endpoint = <&ethdr0_out>;
 492			};
 493		};
 494
 495		port@1 {
 496			#address-cells = <1>;
 497			#size-cells = <0>;
 498			reg = <1>;
 499
 500			merge5_out: endpoint@1 {
 501				reg = <1>;
 502				remote-endpoint = <&dp_intf1_in>;
 503			};
 504		};
 505	};
 506};
 507
 508&mfg0 {
 509	domain-supply = <&mt6359_vproc2_buck_reg>;
 510};
 511
 512&mfg1 {
 513	domain-supply = <&mt6359_vsram_others_ldo_reg>;
 514};
 515
 516&mipi_tx_config0 {
 517	status = "okay";
 518};
 519
 520&mmc0 {
 521	bus-width = <8>;
 522	cap-mmc-highspeed;
 523	cap-mmc-hw-reset;
 524	hs400-ds-delay = <0x1481b>;
 525	max-frequency = <200000000>;
 526	mmc-hs200-1_8v;
 527	mmc-hs400-1_8v;
 528	mmc-hs400-enhanced-strobe;
 529	no-sd;
 530	no-sdio;
 531	non-removable;
 532	pinctrl-names = "default", "state_uhs";
 533	pinctrl-0 = <&mmc0_pins_default>;
 534	pinctrl-1 = <&mmc0_pins_uhs>;
 535	supports-cqe;
 536	vmmc-supply = <&mt6359_vemc_1_ldo_reg>;
 537	vqmmc-supply = <&mt6359_vufs_ldo_reg>;
 538	status = "okay";
 539};
 540
 541&mt6359codec {
 542	mediatek,dmic-mode = <1>; /* one-wire */
 543	mediatek,mic-type-0 = <2>; /* DMIC */
 544	mediatek,mic-type-2 = <2>; /* DMIC */
 545};
 546
 547&mt6359_vcore_buck_reg {
 548	regulator-always-on;
 549};
 550
 551&mt6359_vgpu11_buck_reg {
 552	regulator-always-on;
 553};
 554
 555&mt6359_vgpu11_sshub_buck_reg {
 556	regulator-min-microvolt = <550000>;
 557	regulator-max-microvolt = <550000>;
 558	regulator-always-on;
 559};
 560
 561&mt6359_vio28_ldo_reg {
 562	/delete-property/ regulator-always-on;
 563};
 564
 565&mt6359_vm18_ldo_reg {
 566	/delete-property/ regulator-always-on;
 567};
 568
 569&mt6359_vmodem_buck_reg {
 570	regulator-min-microvolt = <775000>;
 571	regulator-max-microvolt = <775000>;
 572};
 573
 574&mt6359_vpa_buck_reg {
 575	regulator-max-microvolt = <3100000>;
 576};
 577
 578&mt6359_vproc2_buck_reg {
 579	/*
 580	 * Called "ppvar_dvdd_gpu" in the schematic. Renamed to
 581	 * "ppvar_dvdd_vgpu" here to match mtk-regulator-coupler requirements.
 582	 */
 583	regulator-name = "ppvar_dvdd_vgpu";
 584	regulator-min-microvolt = <550000>;
 585	regulator-max-microvolt = <800000>;
 586	regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>;
 587	regulator-coupled-max-spread = <6250>;
 588};
 589
 590&mt6359_vpu_buck_reg {
 591	regulator-always-on;
 592};
 593
 594&mt6359_vrf12_ldo_reg {
 595	regulator-always-on;
 596};
 597
 598&mt6359_vsram_md_ldo_reg {
 599	regulator-min-microvolt = <800000>;
 600	regulator-max-microvolt = <800000>;
 601};
 602
 603&mt6359_vsram_others_ldo_reg {
 604	regulator-name = "pp0850_dvdd_sram_gpu";
 605	regulator-min-microvolt = <750000>;
 606	regulator-max-microvolt = <800000>;
 607	regulator-coupled-with = <&mt6359_vproc2_buck_reg>;
 608	regulator-coupled-max-spread = <6250>;
 609};
 610
 611&mt6359_vufs_ldo_reg {
 612	regulator-always-on;
 613};
 614
 615&nor_flash {
 616	pinctrl-names = "default";
 617	pinctrl-0 = <&nor_pins>;
 618	status = "okay";
 619
 620	flash@0 {
 621		compatible = "jedec,spi-nor";
 622		reg = <0>;
 623		spi-max-frequency = <52000000>;
 624	};
 625};
 626
 627&ovl0_in {
 628	remote-endpoint = <&vdosys0_ep_main>;
 629};
 630
 631&pcie {
 632	pinctrl-names = "default";
 633	pinctrl-0 = <&pcie_pins>;
 634	status = "okay";
 635};
 636
 637&pciephy {
 638	status = "okay";
 639};
 640
 641&pio {
 642	gpio-line-names =
 643		"gsc_int",
 644		"AP_DISP_BKLTEN",
 645		"",
 646		"EN_PPVAR_MIPI_DISP",
 647		"EN_PPVAR_MIPI_DISP_150MA",
 648		"TCHSCR_RST_1V8_L",
 649		"TCHSRC_REPORT_DISABLE",
 650		"",
 651		"",
 652		"",
 653		"",
 654		"I2S_SPKR_DATAOUT",
 655		"EN_PP3300_WLAN_X",
 656		"WIFI_KILL_1V8_L",
 657		"BT_KILL_1V8_L",
 658		"AP_FLASH_WP_L", /* ... is crossystem ABI. Rev1 schematics call it AP_WP_ODL. */
 659		"",
 660		"EDP_HPD_1V8",
 661		"WCAM_PWDN_L",
 662		"WCAM_RST_L",
 663		"UCAM_PWDM_L",
 664		"UCAM_RST_L",
 665		"WCAM_24M_CLK",
 666		"UCAM_24M_CLK",
 667		"MT6319_INT",
 668		"DISP_RST_1V8_L",
 669		"DSIO_DSI_TE",
 670		"EN_PP3300_EDP_DISP_X",
 671		"TP",
 672		"MIPI_BL_PWM_1V8",
 673		"EDP_BL_PWM_1V8",
 674		"UART_AP_TX_GSC_RX",
 675		"UART_GSC_TX_AP_RX",
 676		"UART_SSPM_TX_DBGCON_RX",
 677		"UART_DBGCON_TX_SSPM_RX",
 678		"UART_ADSP_TX_DBGCON_RX",
 679		"UART_DBGCON_TX_ADSP_RX",
 680		"JTAG_AP_TMS",
 681		"JTAG_AP_TCK",
 682		"JTAG_AP_TDI",
 683		"JTAG_AP_TDO",
 684		"JTAG_AP_TRST",
 685		"AP_KPCOL0",
 686		"TP",
 687		"BEEP_ON_OD",
 688		"TP",
 689		"EC_AP_HPD_OD",
 690		"PCIE_WAKE_1V8_ODL",
 691		"PCIE_RST_1V8_L",
 692		"PCIE_CLKREQ_1V8_ODL",
 693		"",
 694		"",
 695		"",
 696		"",
 697		"",
 698		"AP_I2C_AUD_SCL_1V8",
 699		"AP_I2C_AUD_SDA_1V8",
 700		"AP_I2C_TPM_SCL_1V8",
 701		"AP_I2C_TPM_SDA_1V8",
 702		"AP_I2C_TCHSCR_SCL_1V8",
 703		"AP_I2C_TCHSCR_SDA_1V8",
 704		"AP_I2C_PMIC_SAR_SCL_1V8",
 705		"AP_I2C_PMIC_SAR_SDA_1V8",
 706		"AP_I2C_EC_HID_KB_SCL_1V8",
 707		"AP_I2C_EC_HID_KB_SDA_1V8",
 708		"AP_I2C_UCAM_SCL_1V8",
 709		"AP_I2C_UCAM_SDA_1V8",
 710		"AP_I2C_WCAM_SCL_1V8",
 711		"AP_I2C_WCAM_SDA_1V8",
 712		"SPI_AP_CS_EC_L",
 713		"SPI_AP_CLK_EC",
 714		"SPI_AP_DO_EC_DI",
 715		"SPI_AP_DI_EC_DO",
 716		"TP",
 717		"TP",
 718		"SPI_AP_CS_TCHSCR_L",
 719		"SPI_AP_CLK_TCHSCR",
 720		"SPI_AP_DO_TCHSCR_DI",
 721		"SPI_AP_DI_TCHSCR_DO",
 722		"TP",
 723		"TP",
 724		"TP",
 725		"TP",
 726		"",
 727		"",
 728		"",
 729		"TP",
 730		"",
 731		"SAR_INT_ODL",
 732		"",
 733		"",
 734		"",
 735		"PWRAP_SPI_CS_L",
 736		"PWRAP_SPI_CK",
 737		"PWRAP_SPI_MOSI",
 738		"PWRAP_SPI_MISO",
 739		"SRCLKENA0",
 740		"SRCLKENA1",
 741		"SCP_VREQ_VAO",
 742		"AP_RTC_CLK32K",
 743		"AP_PMIC_WDTRST_L",
 744		"AUD_CLK_MOSI",
 745		"AUD_SYNC_MOSI",
 746		"AUD_DAT_MOSI0",
 747		"AUD_DAT_MOSI1",
 748		"AUD_DAT_MISO0",
 749		"AUD_DAT_MISO1",
 750		"SD_CD_ODL",
 751		"HP_INT_ODL",
 752		"SPKR_INT_ODL",
 753		"I2S_HP_DATAIN",
 754		"EN_SPKR",
 755		"I2S_SPKR_MCLK",
 756		"I2S_SPKR_BCLK",
 757		"I2S_HP_MCLK",
 758		"I2S_HP_BCLK",
 759		"I2S_HP_LRCK",
 760		"I2S_HP_DATAOUT",
 761		"RST_SPKR_L",
 762		"I2S_SPKR_LRCK",
 763		"I2S_SPKR_DATAIN",
 764		"",
 765		"",
 766		"",
 767		"",
 768		"SPI_AP_CLK_ROM",
 769		"SPI_AP_CS_ROM_L",
 770		"SPI_AP_DO_ROM_DI",
 771		"SPI_AP_DI_ROM_DO",
 772		"TP",
 773		"TP",
 774		"",
 775		"",
 776		"",
 777		"",
 778		"",
 779		"",
 780		"",
 781		"",
 782		"EN_PP2800A_UCAM_X",
 783		"EN_PP1200_UCAM_X",
 784		"EN_PP2800A_WCAM_X",
 785		"EN_PP1100_WCAM_X",
 786		"TCHSCR_INT_1V8_L",
 787		"EN_PP3300_MIPI_TCHSCR_X",
 788		"MT7921_PMU_EN_1V8",
 789		"EN_PP3300_EDP_TCHSCR_X",
 790		"AP_EC_WARM_RST_REQ",
 791		"EC_AP_HID_INT_ODL",
 792		"EC_AP_INT_ODL",
 793		"AP_XHCI_INIT_DONE",
 794		"EMMC_DAT7",
 795		"EMMC_DAT6",
 796		"EMMC_DAT5",
 797		"EMMC_DAT4",
 798		"EMMC_RST_L",
 799		"EMMC_CMD",
 800		"EMMC_CLK",
 801		"EMMC_DAT3",
 802		"EMMC_DAT2",
 803		"EMMC_DAT1",
 804		"EMMC_DAT0",
 805		"EMMC_DSL",
 806		"SD_CMD",
 807		"SD_CLK",
 808		"SD_DAT0",
 809		"SD_DAT1",
 810		"SD_DAT2",
 811		"SD_DAT3",
 812		"",
 813		"",
 814		"USB3_HUB_RST_L",
 815		"EC_AP_RSVD0_ODL",
 816		"",
 817		"",
 818		"SPMI_SCL",
 819		"SPMI_SDA";
 820
 821	adsp_uart_pins: adsp-uart-pins {
 822		pins-bus {
 823			pinmux = <PINMUX_GPIO35__FUNC_O_ADSP_UTXD0>,
 824				 <PINMUX_GPIO36__FUNC_I1_ADSP_URXD0>;
 825		};
 826	};
 827
 828	aud_etdm_hp_on: aud-etdm-hp-on-pins {
 829		pins-bus {
 830			pinmux = <PINMUX_GPIO110__FUNC_I0_I2SIN_D0>,
 831				 <PINMUX_GPIO115__FUNC_B0_I2SO2_BCK>,
 832				 <PINMUX_GPIO116__FUNC_B0_I2SO2_WS>,
 833				 <PINMUX_GPIO117__FUNC_O_I2SO2_D0>;
 834		};
 835	};
 836
 837	aud_etdm_hp_off: aud-etdm-hp-off-pins {
 838		pins-bus {
 839			pinmux = <PINMUX_GPIO110__FUNC_B_GPIO110>,
 840				 <PINMUX_GPIO115__FUNC_B_GPIO115>,
 841				 <PINMUX_GPIO116__FUNC_B_GPIO116>,
 842				 <PINMUX_GPIO117__FUNC_B_GPIO117>;
 843			bias-pull-down;
 844			input-enable;
 845		};
 846	};
 847
 848	aud_etdm_spk_on: aud-etdm-spk-on-pins {
 849		pins-bus {
 850			pinmux = <PINMUX_GPIO11__FUNC_O_I2SO1_D0>,
 851				 <PINMUX_GPIO113__FUNC_B0_TDMIN_BCK>,
 852				 <PINMUX_GPIO119__FUNC_B0_TDMIN_LRCK>,
 853				 <PINMUX_GPIO120__FUNC_I0_TDMIN_DI>;
 854			drive-strength = <8>;
 855		};
 856	};
 857
 858	aud_etdm_spk_off: aud-etdm-spk-off-pins {
 859		pins-bus {
 860			pinmux = <PINMUX_GPIO11__FUNC_B_GPIO11>,
 861				 <PINMUX_GPIO113__FUNC_B_GPIO113>,
 862				 <PINMUX_GPIO119__FUNC_B_GPIO119>,
 863				 <PINMUX_GPIO120__FUNC_B_GPIO120>;
 864			bias-pull-down;
 865			input-enable;
 866		};
 867	};
 868
 869	aud_mtkaif_on: aud-mtkaif-on-pins {
 870		pins-bus {
 871			pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI>,
 872				 <PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI>,
 873				 <PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0>,
 874				 <PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1>,
 875				 <PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0>,
 876				 <PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>;
 877		};
 878	};
 879
 880	aud_mtkaif_off: aud-mtkaif-off-pins {
 881		pins-bus {
 882			pinmux = <PINMUX_GPIO101__FUNC_B_GPIO101>,
 883				 <PINMUX_GPIO102__FUNC_B_GPIO102>,
 884				 <PINMUX_GPIO103__FUNC_B_GPIO103>,
 885				 <PINMUX_GPIO104__FUNC_B_GPIO104>,
 886				 <PINMUX_GPIO105__FUNC_B_GPIO105>,
 887				 <PINMUX_GPIO106__FUNC_B_GPIO106>;
 888			bias-pull-down;
 889			input-enable;
 890		};
 891	};
 892
 893	cros_ec_int: cros-ec-int-pins {
 894		pins-ec-ap-int-odl {
 895			pinmux = <PINMUX_GPIO149__FUNC_B_GPIO149>;
 896			input-enable;
 897		};
 898	};
 899
 900	disp_pwm0_pins: disp-pwm0-pins {
 901		pins-disp-pwm0 {
 902			pinmux = <PINMUX_GPIO29__FUNC_O_DISP_PWM0>;
 903			output-high;
 904		};
 905	};
 906
 907	disp_pwm1_pins: disp-pwm1-pins {
 908		pins-disp-pwm1 {
 909			pinmux = <PINMUX_GPIO30__FUNC_O_DISP_PWM1>;
 910			output-high;
 911		};
 912	};
 913
 914	dp_tx_hpd: dp-tx-hpd-pins {
 915		pins-dp-tx-hpd {
 916			pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>;
 917		};
 918	};
 919
 920	gsc_int: gsc-int-pins {
 921		pins-gsc-ap-int-odl {
 922			pinmux = <PINMUX_GPIO0__FUNC_B_GPIO0>;
 923			input-enable;
 924		};
 925	};
 926
 927	i2c0_pins: i2c0-pins {
 928		pins-bus {
 929			pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>,
 930				 <PINMUX_GPIO55__FUNC_B1_SCL0>;
 931		};
 932	};
 933
 934	i2c1_pins: i2c1-pins {
 935		pins-bus {
 936			pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>,
 937				 <PINMUX_GPIO57__FUNC_B1_SCL1>;
 938		};
 939	};
 940
 941	i2c2_pins: i2c2-pins {
 942		pins-bus {
 943			pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>,
 944				 <PINMUX_GPIO59__FUNC_B1_SCL2>;
 945			bias-disable;
 946			drive-strength = <12>;
 947		};
 948	};
 949
 950	i2c3_pins: i2c3-pins {
 951		pins-bus {
 952			pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>,
 953				 <PINMUX_GPIO61__FUNC_B1_SCL3>;
 954		};
 955	};
 956
 957	i2c4_pins: i2c4-pins {
 958		pins-bus {
 959			pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>,
 960				 <PINMUX_GPIO63__FUNC_B1_SCL4>;
 961		};
 962	};
 963
 964	i2c5_pins: i2c5-pins {
 965		pins-bus {
 966			pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>,
 967				 <PINMUX_GPIO65__FUNC_B1_SCL5>;
 968		};
 969	};
 970
 971	i2c6_pins: i2c6-pins {
 972		pins-bus {
 973			pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>,
 974				 <PINMUX_GPIO67__FUNC_B1_SCL6>;
 975		};
 976	};
 977
 978	mipi_disp_avdd_en: mipi-disp-avdd-en-pins {
 979		pins-en-ppvar-mipi-disp {
 980			pinmux = <PINMUX_GPIO3__FUNC_B_GPIO3>;
 981			output-low;
 982		};
 983	};
 984
 985	mipi_disp_avee_en: mipi-disp-avee-en-pins {
 986		pins-en-ppvar-mipi-disp-150ma {
 987			pinmux = <PINMUX_GPIO4__FUNC_B_GPIO4>;
 988			output-low;
 989		};
 990	};
 991
 992	mipi_dsi_pins: mipi-dsi-pins {
 993		pins-bus {
 994			pinmux = <PINMUX_GPIO1__FUNC_B_GPIO1>,
 995				 <PINMUX_GPIO25__FUNC_B_GPIO25>;
 996			output-low;
 997		};
 998	};
 999
1000	mmc0_pins_default: mmc0-default-pins {
1001		pins-bus {
1002			pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
1003				 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
1004				 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
1005				 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
1006				 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
1007				 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
1008				 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
1009				 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
1010				 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
1011			input-enable;
1012			drive-strength = <6>;
1013			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1014		};
1015
1016		pins-clk {
1017			pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
1018			drive-strength = <6>;
1019			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1020		};
1021
1022		pins-rst {
1023			pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
1024			drive-strength = <6>;
1025			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1026		};
1027	};
1028
1029	mmc0_pins_uhs: mmc0-uhs-pins {
1030		pins-bus {
1031			pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>,
1032				 <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>,
1033				 <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>,
1034				 <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>,
1035				 <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>,
1036				 <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>,
1037				 <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>,
1038				 <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>,
1039				 <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>;
1040			input-enable;
1041			drive-strength = <8>;
1042			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1043		};
1044
1045		pins-clk {
1046			pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>;
1047			drive-strength = <8>;
1048			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1049		};
1050
1051		pins-ds {
1052			pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>;
1053			drive-strength = <8>;
1054			bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
1055		};
1056
1057		pins-rst {
1058			pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>;
1059			drive-strength = <8>;
1060			bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
1061		};
1062	};
1063
1064	nor_pins: nor-default-pins {
1065		pins-clk {
1066			pinmux = <PINMUX_GPIO127__FUNC_B0_SPINOR_IO0>,
1067				 <PINMUX_GPIO125__FUNC_O_SPINOR_CK>,
1068				 <PINMUX_GPIO128__FUNC_B0_SPINOR_IO1>;
1069			bias-pull-down;
1070		};
1071
1072		pins-cs {
1073			pinmux = <PINMUX_GPIO126__FUNC_O_SPINOR_CS>;
1074			bias-pull-up;
1075		};
1076	};
1077
1078	pcie_pins: pcie-default-pins {
1079		pins-bus {
1080			pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>,
1081				 <PINMUX_GPIO48__FUNC_O_PERSTN>,
1082				 <PINMUX_GPIO49__FUNC_B1_CLKREQN>;
1083		};
1084	};
1085
1086	scp_pins: scp-pins {
1087		pins-scp-vreq {
1088			pinmux = <PINMUX_GPIO98__FUNC_O_SCP_VREQ_VAO>;
1089			bias-disable;
1090		};
1091	};
1092
1093	spi0_pins: spi0-pins {
1094		pins-bus {
1095			pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>,
1096				 <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>,
1097				 <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>,
1098				 <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>;
1099			bias-disable;
1100		};
1101	};
1102
1103	spi1_pins_default: spi1-default-pins {
1104		pins-bus {
1105			pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>,
1106				 <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>,
1107				 <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>,
1108				 <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>;
1109			bias-disable;
1110		};
1111	};
1112
1113	spi1_pins_sleep: spi1-sleep-pins {
1114		pins-bus {
1115			pinmux = <PINMUX_GPIO75__FUNC_B_GPIO75>,
1116				 <PINMUX_GPIO76__FUNC_B_GPIO76>,
1117				 <PINMUX_GPIO77__FUNC_B_GPIO77>,
1118				 <PINMUX_GPIO78__FUNC_B_GPIO78>;
1119			bias-pull-down;
1120			input-enable;
1121		};
1122	};
1123
1124	spi2_pins: spi2-pins {
1125		pins-bus {
1126			pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>,
1127				 <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>,
1128				 <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>,
1129				 <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>;
1130			bias-disable;
1131		};
1132	};
1133
1134	uart0_pins: uart0-pins {
1135		pins-bus {
1136			pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>,
1137				 <PINMUX_GPIO32__FUNC_I1_URXD0>;
1138			bias-pull-up;
1139		};
1140	};
1141
1142	wlan_en: wlan-en-pins {
1143		pins-en-pp3300-wlan {
1144			pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>;
1145			output-low;
1146		};
1147	};
1148};
1149
1150&pmic {
1151	interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>;
1152};
1153
1154&postmask0_in {
1155	remote-endpoint = <&gamma0_out>;
1156};
1157
1158&postmask0_out {
1159	remote-endpoint = <&dither0_in>;
1160};
1161
1162&scp_cluster {
1163	status = "okay";
1164};
1165
1166&scp_c0 {
1167	pinctrl-names = "default";
1168	pinctrl-0 = <&scp_pins>;
1169	firmware-name = "mediatek/mt8188/scp.img";
1170	memory-region = <&scp_mem_reserved>;
1171	status = "okay";
1172};
1173
1174&sound {
1175	pinctrl-names = "aud_etdm_hp_on", "aud_etdm_hp_off",
1176			"aud_etdm_spk_on", "aud_etdm_spk_off",
1177			"aud_mtkaif_on", "aud_mtkaif_off";
1178	pinctrl-0 = <&aud_etdm_hp_on>;
1179	pinctrl-1 = <&aud_etdm_hp_off>;
1180	pinctrl-2 = <&aud_etdm_spk_on>;
1181	pinctrl-3 = <&aud_etdm_spk_off>;
1182	pinctrl-4 = <&aud_mtkaif_on>;
1183	pinctrl-5 = <&aud_mtkaif_off>;
1184	mediatek,adsp = <&adsp>;
1185	/* The audio-routing is defined in each board dts */
1186
1187	status = "okay";
1188};
1189
1190&spi0 {
1191	pinctrl-names = "default";
1192	pinctrl-0 = <&spi0_pins>;
1193	status = "okay";
1194
1195	cros_ec: ec@0 {
1196		compatible = "google,cros-ec-spi";
1197		reg = <0>;
1198		interrupts-extended = <&pio 149 IRQ_TYPE_LEVEL_LOW>;
1199		pinctrl-names = "default";
1200		pinctrl-0 = <&cros_ec_int>;
1201		spi-max-frequency = <3000000>;
1202
1203		i2c_tunnel: i2c-tunnel {
1204			compatible = "google,cros-ec-i2c-tunnel";
1205			google,remote-bus = <1>;
1206			#address-cells = <1>;
1207			#size-cells = <0>;
1208		};
1209
1210		cbas {
1211			compatible = "google,cros-cbas";
1212		};
1213	};
1214};
1215
1216&spi1 {
1217	pinctrl-names = "default", "sleep";
1218	pinctrl-0 = <&spi1_pins_default>;
1219	pinctrl-1 = <&spi1_pins_sleep>;
1220	status = "okay";
1221};
1222
1223&spi2 {
1224	pinctrl-names = "default";
1225	pinctrl-0 = <&spi2_pins>;
1226	status = "okay";
1227};
1228
1229&uart0 {
1230	pinctrl-names = "default";
1231	pinctrl-0 = <&uart0_pins>;
1232	status = "okay";
1233};
1234
1235&u3phy0 {
1236	status = "okay";
1237};
1238
1239&u3phy1 {
1240	status = "okay";
1241};
1242
1243&u3phy2 {
1244	status = "okay";
1245};
1246
1247/* USB detachable base */
1248&ssusb0 {
1249	dr_mode = "host";
1250	vusb33-supply = <&pp3300_s3>;
1251	status = "okay";
1252};
1253
1254&xhci0 {
1255	/* controlled by EC */
1256	vbus-supply = <&pp3300_z1>;
1257	status = "okay";
1258};
1259
1260/* USB3 hub */
1261&ssusb1 {
1262	dr_mode = "host";
1263	vusb33-supply = <&pp3300_s3>;
1264	status = "okay";
1265};
1266
1267&xhci1 {
1268	vusb33-supply = <&pp3300_s3>;
1269	vbus-supply = <&pp5000_usb_vbus>;
1270	status = "okay";
1271};
1272
1273/* USB BT */
1274&ssusb2 {
1275	dr_mode = "host";
1276	vusb33-supply = <&pp3300_s3>;
1277	status = "okay";
1278};
1279
1280&vdosys0 {
1281	port {
1282		#address-cells = <1>;
1283		#size-cells = <0>;
1284
1285		vdosys0_ep_main: endpoint@0 {
1286			reg = <0>;
1287			remote-endpoint = <&ovl0_in>;
1288		};
1289	};
1290};
1291
1292&vdosys1 {
1293	port {
1294		#address-cells = <1>;
1295		#size-cells = <0>;
1296
1297		vdosys1_ep_ext: endpoint@1 {
1298			reg = <1>;
1299			remote-endpoint = <&ethdr0_in>;
1300		};
1301	};
1302};
1303
1304&xhci2 {
1305	/* no power supply since MT7921's power is controlled by PCIe */
1306	/* MT7921's USB BT has issues with USB2 LPM */
1307	usb2-lpm-disable;
1308	status = "okay";
1309};
1310
1311#include <arm/cros-ec-keyboard.dtsi>
1312
1313&keyboard_controller {
1314	function-row-physmap = <
1315		MATRIX_KEY(0x00, 0x02, 0)	/* T1 */
1316		MATRIX_KEY(0x03, 0x02, 0)	/* T2 */
1317		MATRIX_KEY(0x02, 0x02, 0)	/* T3 */
1318		MATRIX_KEY(0x01, 0x02, 0)	/* T4 */
1319		MATRIX_KEY(0x03, 0x04, 0)	/* T5 */
1320		MATRIX_KEY(0x02, 0x04, 0)	/* T6 */
1321		MATRIX_KEY(0x01, 0x04, 0)	/* T7 */
1322		MATRIX_KEY(0x02, 0x09, 0)	/* T8 */
1323		MATRIX_KEY(0x01, 0x09, 0)	/* T9 */
1324		MATRIX_KEY(0x00, 0x04, 0)	/* T10 */
1325	>;
1326
1327	linux,keymap = <
1328		MATRIX_KEY(0x00, 0x02, KEY_BACK)
1329		MATRIX_KEY(0x03, 0x02, KEY_REFRESH)
1330		MATRIX_KEY(0x02, 0x02, KEY_ZOOM)
1331		MATRIX_KEY(0x01, 0x02, KEY_SCALE)
1332		MATRIX_KEY(0x03, 0x04, KEY_BRIGHTNESSDOWN)
1333		MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSUP)
1334		MATRIX_KEY(0x01, 0x04, KEY_MICMUTE)
1335		MATRIX_KEY(0x02, 0x09, KEY_MUTE)
1336		MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN)
1337		MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP)
1338		CROS_STD_MAIN_KEYMAP
1339	>;
1340};
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