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mt8183.dtsi
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linux-6.19.14/arch/arm64/boot/dts/mediatek/mt8183.dtsi
1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2018 MediaTek Inc. 4 * Author: Ben Ho <ben.ho@mediatek.com> 5 * Erin Lo <erin.lo@mediatek.com> 6 */ 7 8#include <dt-bindings/clock/mt8183-clk.h> 9#include <dt-bindings/gce/mt8183-gce.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/memory/mt8183-larb-port.h> 13#include <dt-bindings/power/mt8183-power.h> 14#include <dt-bindings/reset/mt8183-resets.h> 15#include <dt-bindings/phy/phy.h> 16#include <dt-bindings/thermal/thermal.h> 17#include <dt-bindings/pinctrl/mt8183-pinfunc.h> 18 19/ { 20 compatible = "mediatek,mt8183"; 21 interrupt-parent = <&sysirq>; 22 #address-cells = <2>; 23 #size-cells = <2>; 24 25 aliases { 26 i2c0 = &i2c0; 27 i2c1 = &i2c1; 28 i2c2 = &i2c2; 29 i2c3 = &i2c3; 30 i2c4 = &i2c4; 31 i2c5 = &i2c5; 32 i2c6 = &i2c6; 33 i2c7 = &i2c7; 34 i2c8 = &i2c8; 35 i2c9 = &i2c9; 36 i2c10 = &i2c10; 37 i2c11 = &i2c11; 38 ovl0 = &ovl0; 39 ovl-2l0 = &ovl_2l0; 40 ovl-2l1 = &ovl_2l1; 41 rdma0 = &rdma0; 42 rdma1 = &rdma1; 43 }; 44 45 cluster0_opp: opp-table-cluster0 { 46 compatible = "operating-points-v2"; 47 opp-shared; 48 opp0-793000000 { 49 opp-hz = /bits/ 64 <793000000>; 50 opp-microvolt = <650000>; 51 required-opps = <&opp2_00>; 52 }; 53 opp0-910000000 { 54 opp-hz = /bits/ 64 <910000000>; 55 opp-microvolt = <687500>; 56 required-opps = <&opp2_01>; 57 }; 58 opp0-1014000000 { 59 opp-hz = /bits/ 64 <1014000000>; 60 opp-microvolt = <718750>; 61 required-opps = <&opp2_02>; 62 }; 63 opp0-1131000000 { 64 opp-hz = /bits/ 64 <1131000000>; 65 opp-microvolt = <756250>; 66 required-opps = <&opp2_03>; 67 }; 68 opp0-1248000000 { 69 opp-hz = /bits/ 64 <1248000000>; 70 opp-microvolt = <800000>; 71 required-opps = <&opp2_04>; 72 }; 73 opp0-1326000000 { 74 opp-hz = /bits/ 64 <1326000000>; 75 opp-microvolt = <818750>; 76 required-opps = <&opp2_05>; 77 }; 78 opp0-1417000000 { 79 opp-hz = /bits/ 64 <1417000000>; 80 opp-microvolt = <850000>; 81 required-opps = <&opp2_06>; 82 }; 83 opp0-1508000000 { 84 opp-hz = /bits/ 64 <1508000000>; 85 opp-microvolt = <868750>; 86 required-opps = <&opp2_07>; 87 }; 88 opp0-1586000000 { 89 opp-hz = /bits/ 64 <1586000000>; 90 opp-microvolt = <893750>; 91 required-opps = <&opp2_08>; 92 }; 93 opp0-1625000000 { 94 opp-hz = /bits/ 64 <1625000000>; 95 opp-microvolt = <906250>; 96 required-opps = <&opp2_09>; 97 }; 98 opp0-1677000000 { 99 opp-hz = /bits/ 64 <1677000000>; 100 opp-microvolt = <931250>; 101 required-opps = <&opp2_10>; 102 }; 103 opp0-1716000000 { 104 opp-hz = /bits/ 64 <1716000000>; 105 opp-microvolt = <943750>; 106 required-opps = <&opp2_11>; 107 }; 108 opp0-1781000000 { 109 opp-hz = /bits/ 64 <1781000000>; 110 opp-microvolt = <975000>; 111 required-opps = <&opp2_12>; 112 }; 113 opp0-1846000000 { 114 opp-hz = /bits/ 64 <1846000000>; 115 opp-microvolt = <1000000>; 116 required-opps = <&opp2_13>; 117 }; 118 opp0-1924000000 { 119 opp-hz = /bits/ 64 <1924000000>; 120 opp-microvolt = <1025000>; 121 required-opps = <&opp2_14>; 122 }; 123 opp0-1989000000 { 124 opp-hz = /bits/ 64 <1989000000>; 125 opp-microvolt = <1050000>; 126 required-opps = <&opp2_15>; 127 }; }; 128 129 cluster1_opp: opp-table-cluster1 { 130 compatible = "operating-points-v2"; 131 opp-shared; 132 opp1-793000000 { 133 opp-hz = /bits/ 64 <793000000>; 134 opp-microvolt = <700000>; 135 required-opps = <&opp2_00>; 136 }; 137 opp1-910000000 { 138 opp-hz = /bits/ 64 <910000000>; 139 opp-microvolt = <725000>; 140 required-opps = <&opp2_01>; 141 }; 142 opp1-1014000000 { 143 opp-hz = /bits/ 64 <1014000000>; 144 opp-microvolt = <750000>; 145 required-opps = <&opp2_02>; 146 }; 147 opp1-1131000000 { 148 opp-hz = /bits/ 64 <1131000000>; 149 opp-microvolt = <775000>; 150 required-opps = <&opp2_03>; 151 }; 152 opp1-1248000000 { 153 opp-hz = /bits/ 64 <1248000000>; 154 opp-microvolt = <800000>; 155 required-opps = <&opp2_04>; 156 }; 157 opp1-1326000000 { 158 opp-hz = /bits/ 64 <1326000000>; 159 opp-microvolt = <825000>; 160 required-opps = <&opp2_05>; 161 }; 162 opp1-1417000000 { 163 opp-hz = /bits/ 64 <1417000000>; 164 opp-microvolt = <850000>; 165 required-opps = <&opp2_06>; 166 }; 167 opp1-1508000000 { 168 opp-hz = /bits/ 64 <1508000000>; 169 opp-microvolt = <875000>; 170 required-opps = <&opp2_07>; 171 }; 172 opp1-1586000000 { 173 opp-hz = /bits/ 64 <1586000000>; 174 opp-microvolt = <900000>; 175 required-opps = <&opp2_08>; 176 }; 177 opp1-1625000000 { 178 opp-hz = /bits/ 64 <1625000000>; 179 opp-microvolt = <912500>; 180 required-opps = <&opp2_09>; 181 }; 182 opp1-1677000000 { 183 opp-hz = /bits/ 64 <1677000000>; 184 opp-microvolt = <931250>; 185 required-opps = <&opp2_10>; 186 }; 187 opp1-1716000000 { 188 opp-hz = /bits/ 64 <1716000000>; 189 opp-microvolt = <950000>; 190 required-opps = <&opp2_11>; 191 }; 192 opp1-1781000000 { 193 opp-hz = /bits/ 64 <1781000000>; 194 opp-microvolt = <975000>; 195 required-opps = <&opp2_12>; 196 }; 197 opp1-1846000000 { 198 opp-hz = /bits/ 64 <1846000000>; 199 opp-microvolt = <1000000>; 200 required-opps = <&opp2_13>; 201 }; 202 opp1-1924000000 { 203 opp-hz = /bits/ 64 <1924000000>; 204 opp-microvolt = <1025000>; 205 required-opps = <&opp2_14>; 206 }; 207 opp1-1989000000 { 208 opp-hz = /bits/ 64 <1989000000>; 209 opp-microvolt = <1050000>; 210 required-opps = <&opp2_15>; 211 }; 212 }; 213 214 cci_opp: opp-table-cci { 215 compatible = "operating-points-v2"; 216 opp-shared; 217 opp2_00: opp-273000000 { 218 opp-hz = /bits/ 64 <273000000>; 219 opp-microvolt = <650000>; 220 }; 221 opp2_01: opp-338000000 { 222 opp-hz = /bits/ 64 <338000000>; 223 opp-microvolt = <687500>; 224 }; 225 opp2_02: opp-403000000 { 226 opp-hz = /bits/ 64 <403000000>; 227 opp-microvolt = <718750>; 228 }; 229 opp2_03: opp-463000000 { 230 opp-hz = /bits/ 64 <463000000>; 231 opp-microvolt = <756250>; 232 }; 233 opp2_04: opp-546000000 { 234 opp-hz = /bits/ 64 <546000000>; 235 opp-microvolt = <800000>; 236 }; 237 opp2_05: opp-624000000 { 238 opp-hz = /bits/ 64 <624000000>; 239 opp-microvolt = <818750>; 240 }; 241 opp2_06: opp-689000000 { 242 opp-hz = /bits/ 64 <689000000>; 243 opp-microvolt = <850000>; 244 }; 245 opp2_07: opp-767000000 { 246 opp-hz = /bits/ 64 <767000000>; 247 opp-microvolt = <868750>; 248 }; 249 opp2_08: opp-845000000 { 250 opp-hz = /bits/ 64 <845000000>; 251 opp-microvolt = <893750>; 252 }; 253 opp2_09: opp-871000000 { 254 opp-hz = /bits/ 64 <871000000>; 255 opp-microvolt = <906250>; 256 }; 257 opp2_10: opp-923000000 { 258 opp-hz = /bits/ 64 <923000000>; 259 opp-microvolt = <931250>; 260 }; 261 opp2_11: opp-962000000 { 262 opp-hz = /bits/ 64 <962000000>; 263 opp-microvolt = <943750>; 264 }; 265 opp2_12: opp-1027000000 { 266 opp-hz = /bits/ 64 <1027000000>; 267 opp-microvolt = <975000>; 268 }; 269 opp2_13: opp-1092000000 { 270 opp-hz = /bits/ 64 <1092000000>; 271 opp-microvolt = <1000000>; 272 }; 273 opp2_14: opp-1144000000 { 274 opp-hz = /bits/ 64 <1144000000>; 275 opp-microvolt = <1025000>; 276 }; 277 opp2_15: opp-1196000000 { 278 opp-hz = /bits/ 64 <1196000000>; 279 opp-microvolt = <1050000>; 280 }; 281 }; 282 283 cci: cci { 284 compatible = "mediatek,mt8183-cci"; 285 clocks = <&mcucfg CLK_MCU_BUS_SEL>, 286 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 287 clock-names = "cci", "intermediate"; 288 operating-points-v2 = <&cci_opp>; 289 }; 290 291 cpus { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 295 cpu-map { 296 cluster0 { 297 core0 { 298 cpu = <&cpu0>; 299 }; 300 core1 { 301 cpu = <&cpu1>; 302 }; 303 core2 { 304 cpu = <&cpu2>; 305 }; 306 core3 { 307 cpu = <&cpu3>; 308 }; 309 }; 310 311 cluster1 { 312 core0 { 313 cpu = <&cpu4>; 314 }; 315 core1 { 316 cpu = <&cpu5>; 317 }; 318 core2 { 319 cpu = <&cpu6>; 320 }; 321 core3 { 322 cpu = <&cpu7>; 323 }; 324 }; 325 }; 326 327 cpu0: cpu@0 { 328 device_type = "cpu"; 329 compatible = "arm,cortex-a53"; 330 reg = <0x000>; 331 enable-method = "psci"; 332 capacity-dmips-mhz = <741>; 333 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 334 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 335 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 336 clock-names = "cpu", "intermediate"; 337 operating-points-v2 = <&cluster0_opp>; 338 dynamic-power-coefficient = <84>; 339 i-cache-size = <32768>; 340 i-cache-line-size = <64>; 341 i-cache-sets = <256>; 342 d-cache-size = <32768>; 343 d-cache-line-size = <64>; 344 d-cache-sets = <128>; 345 next-level-cache = <&l2_0>; 346 #cooling-cells = <2>; 347 mediatek,cci = <&cci>; 348 }; 349 350 cpu1: cpu@1 { 351 device_type = "cpu"; 352 compatible = "arm,cortex-a53"; 353 reg = <0x001>; 354 enable-method = "psci"; 355 capacity-dmips-mhz = <741>; 356 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 357 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 358 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 359 clock-names = "cpu", "intermediate"; 360 operating-points-v2 = <&cluster0_opp>; 361 dynamic-power-coefficient = <84>; 362 i-cache-size = <32768>; 363 i-cache-line-size = <64>; 364 i-cache-sets = <256>; 365 d-cache-size = <32768>; 366 d-cache-line-size = <64>; 367 d-cache-sets = <128>; 368 next-level-cache = <&l2_0>; 369 #cooling-cells = <2>; 370 mediatek,cci = <&cci>; 371 }; 372 373 cpu2: cpu@2 { 374 device_type = "cpu"; 375 compatible = "arm,cortex-a53"; 376 reg = <0x002>; 377 enable-method = "psci"; 378 capacity-dmips-mhz = <741>; 379 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 380 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 381 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 382 clock-names = "cpu", "intermediate"; 383 operating-points-v2 = <&cluster0_opp>; 384 dynamic-power-coefficient = <84>; 385 i-cache-size = <32768>; 386 i-cache-line-size = <64>; 387 i-cache-sets = <256>; 388 d-cache-size = <32768>; 389 d-cache-line-size = <64>; 390 d-cache-sets = <128>; 391 next-level-cache = <&l2_0>; 392 #cooling-cells = <2>; 393 mediatek,cci = <&cci>; 394 }; 395 396 cpu3: cpu@3 { 397 device_type = "cpu"; 398 compatible = "arm,cortex-a53"; 399 reg = <0x003>; 400 enable-method = "psci"; 401 capacity-dmips-mhz = <741>; 402 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP0>; 403 clocks = <&mcucfg CLK_MCU_MP0_SEL>, 404 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 405 clock-names = "cpu", "intermediate"; 406 operating-points-v2 = <&cluster0_opp>; 407 dynamic-power-coefficient = <84>; 408 i-cache-size = <32768>; 409 i-cache-line-size = <64>; 410 i-cache-sets = <256>; 411 d-cache-size = <32768>; 412 d-cache-line-size = <64>; 413 d-cache-sets = <128>; 414 next-level-cache = <&l2_0>; 415 #cooling-cells = <2>; 416 mediatek,cci = <&cci>; 417 }; 418 419 cpu4: cpu@100 { 420 device_type = "cpu"; 421 compatible = "arm,cortex-a73"; 422 reg = <0x100>; 423 enable-method = "psci"; 424 capacity-dmips-mhz = <1024>; 425 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 426 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 427 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 428 clock-names = "cpu", "intermediate"; 429 operating-points-v2 = <&cluster1_opp>; 430 dynamic-power-coefficient = <211>; 431 i-cache-size = <65536>; 432 i-cache-line-size = <64>; 433 i-cache-sets = <256>; 434 d-cache-size = <65536>; 435 d-cache-line-size = <64>; 436 d-cache-sets = <256>; 437 next-level-cache = <&l2_1>; 438 #cooling-cells = <2>; 439 mediatek,cci = <&cci>; 440 }; 441 442 cpu5: cpu@101 { 443 device_type = "cpu"; 444 compatible = "arm,cortex-a73"; 445 reg = <0x101>; 446 enable-method = "psci"; 447 capacity-dmips-mhz = <1024>; 448 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 449 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 450 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 451 clock-names = "cpu", "intermediate"; 452 operating-points-v2 = <&cluster1_opp>; 453 dynamic-power-coefficient = <211>; 454 i-cache-size = <65536>; 455 i-cache-line-size = <64>; 456 i-cache-sets = <256>; 457 d-cache-size = <65536>; 458 d-cache-line-size = <64>; 459 d-cache-sets = <256>; 460 next-level-cache = <&l2_1>; 461 #cooling-cells = <2>; 462 mediatek,cci = <&cci>; 463 }; 464 465 cpu6: cpu@102 { 466 device_type = "cpu"; 467 compatible = "arm,cortex-a73"; 468 reg = <0x102>; 469 enable-method = "psci"; 470 capacity-dmips-mhz = <1024>; 471 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 472 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 473 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 474 clock-names = "cpu", "intermediate"; 475 operating-points-v2 = <&cluster1_opp>; 476 dynamic-power-coefficient = <211>; 477 i-cache-size = <65536>; 478 i-cache-line-size = <64>; 479 i-cache-sets = <256>; 480 d-cache-size = <65536>; 481 d-cache-line-size = <64>; 482 d-cache-sets = <256>; 483 next-level-cache = <&l2_1>; 484 #cooling-cells = <2>; 485 mediatek,cci = <&cci>; 486 }; 487 488 cpu7: cpu@103 { 489 device_type = "cpu"; 490 compatible = "arm,cortex-a73"; 491 reg = <0x103>; 492 enable-method = "psci"; 493 capacity-dmips-mhz = <1024>; 494 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP1>; 495 clocks = <&mcucfg CLK_MCU_MP2_SEL>, 496 <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>; 497 clock-names = "cpu", "intermediate"; 498 operating-points-v2 = <&cluster1_opp>; 499 dynamic-power-coefficient = <211>; 500 i-cache-size = <65536>; 501 i-cache-line-size = <64>; 502 i-cache-sets = <256>; 503 d-cache-size = <65536>; 504 d-cache-line-size = <64>; 505 d-cache-sets = <256>; 506 next-level-cache = <&l2_1>; 507 #cooling-cells = <2>; 508 mediatek,cci = <&cci>; 509 }; 510 511 idle-states { 512 entry-method = "psci"; 513 514 CPU_SLEEP: cpu-sleep { 515 compatible = "arm,idle-state"; 516 local-timer-stop; 517 arm,psci-suspend-param = <0x00010001>; 518 entry-latency-us = <200>; 519 exit-latency-us = <200>; 520 min-residency-us = <800>; 521 }; 522 523 CLUSTER_SLEEP0: cluster-sleep-0 { 524 compatible = "arm,idle-state"; 525 local-timer-stop; 526 arm,psci-suspend-param = <0x01010001>; 527 entry-latency-us = <250>; 528 exit-latency-us = <400>; 529 min-residency-us = <1000>; 530 }; 531 CLUSTER_SLEEP1: cluster-sleep-1 { 532 compatible = "arm,idle-state"; 533 local-timer-stop; 534 arm,psci-suspend-param = <0x01010001>; 535 entry-latency-us = <250>; 536 exit-latency-us = <400>; 537 min-residency-us = <1300>; 538 }; 539 }; 540 541 l2_0: l2-cache0 { 542 compatible = "cache"; 543 cache-level = <2>; 544 cache-size = <1048576>; 545 cache-line-size = <64>; 546 cache-sets = <1024>; 547 cache-unified; 548 }; 549 550 l2_1: l2-cache1 { 551 compatible = "cache"; 552 cache-level = <2>; 553 cache-size = <1048576>; 554 cache-line-size = <64>; 555 cache-sets = <1024>; 556 cache-unified; 557 }; 558 }; 559 560 gpu_opp_table: opp-table-0 { 561 compatible = "operating-points-v2"; 562 opp-shared; 563 564 opp-300000000 { 565 opp-hz = /bits/ 64 <300000000>; 566 opp-microvolt = <625000>; 567 }; 568 569 opp-320000000 { 570 opp-hz = /bits/ 64 <320000000>; 571 opp-microvolt = <631250>; 572 }; 573 574 opp-340000000 { 575 opp-hz = /bits/ 64 <340000000>; 576 opp-microvolt = <637500>; 577 }; 578 579 opp-360000000 { 580 opp-hz = /bits/ 64 <360000000>; 581 opp-microvolt = <643750>; 582 }; 583 584 opp-380000000 { 585 opp-hz = /bits/ 64 <380000000>; 586 opp-microvolt = <650000>; 587 }; 588 589 opp-400000000 { 590 opp-hz = /bits/ 64 <400000000>; 591 opp-microvolt = <656250>; 592 }; 593 594 opp-420000000 { 595 opp-hz = /bits/ 64 <420000000>; 596 opp-microvolt = <662500>; 597 }; 598 599 opp-460000000 { 600 opp-hz = /bits/ 64 <460000000>; 601 opp-microvolt = <675000>; 602 }; 603 604 opp-500000000 { 605 opp-hz = /bits/ 64 <500000000>; 606 opp-microvolt = <687500>; 607 }; 608 609 opp-540000000 { 610 opp-hz = /bits/ 64 <540000000>; 611 opp-microvolt = <700000>; 612 }; 613 614 opp-580000000 { 615 opp-hz = /bits/ 64 <580000000>; 616 opp-microvolt = <712500>; 617 }; 618 619 opp-620000000 { 620 opp-hz = /bits/ 64 <620000000>; 621 opp-microvolt = <725000>; 622 }; 623 624 opp-653000000 { 625 opp-hz = /bits/ 64 <653000000>; 626 opp-microvolt = <743750>; 627 }; 628 629 opp-698000000 { 630 opp-hz = /bits/ 64 <698000000>; 631 opp-microvolt = <768750>; 632 }; 633 634 opp-743000000 { 635 opp-hz = /bits/ 64 <743000000>; 636 opp-microvolt = <793750>; 637 }; 638 639 opp-800000000 { 640 opp-hz = /bits/ 64 <800000000>; 641 opp-microvolt = <825000>; 642 }; 643 }; 644 645 pmu-a53 { 646 compatible = "arm,cortex-a53-pmu"; 647 interrupt-parent = <&gic>; 648 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>; 649 }; 650 651 pmu-a73 { 652 compatible = "arm,cortex-a73-pmu"; 653 interrupt-parent = <&gic>; 654 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>; 655 }; 656 657 psci { 658 compatible = "arm,psci-1.0"; 659 method = "smc"; 660 }; 661 662 clk13m: fixed-factor-clock-13m { 663 compatible = "fixed-factor-clock"; 664 #clock-cells = <0>; 665 clocks = <&clk26m>; 666 clock-div = <2>; 667 clock-mult = <1>; 668 clock-output-names = "clk13m"; 669 }; 670 671 clk26m: oscillator { 672 compatible = "fixed-clock"; 673 #clock-cells = <0>; 674 clock-frequency = <26000000>; 675 clock-output-names = "clk26m"; 676 }; 677 678 timer { 679 compatible = "arm,armv8-timer"; 680 interrupt-parent = <&gic>; 681 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 682 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 683 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 684 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 685 }; 686 687 soc { 688 #address-cells = <2>; 689 #size-cells = <2>; 690 compatible = "simple-bus"; 691 ranges; 692 693 soc_data: efuse@8000000 { 694 compatible = "mediatek,mt8183-efuse", 695 "mediatek,efuse"; 696 reg = <0 0x08000000 0 0x0010>; 697 #address-cells = <1>; 698 #size-cells = <1>; 699 status = "disabled"; 700 }; 701 702 gic: interrupt-controller@c000000 { 703 compatible = "arm,gic-v3"; 704 #interrupt-cells = <4>; 705 interrupt-parent = <&gic>; 706 interrupt-controller; 707 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 708 <0 0x0c100000 0 0x200000>, /* GICR */ 709 <0 0x0c400000 0 0x2000>, /* GICC */ 710 <0 0x0c410000 0 0x1000>, /* GICH */ 711 <0 0x0c420000 0 0x2000>; /* GICV */ 712 713 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 714 ppi-partitions { 715 ppi_cluster0: interrupt-partition-0 { 716 affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; 717 }; 718 ppi_cluster1: interrupt-partition-1 { 719 affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; 720 }; 721 }; 722 }; 723 724 mcucfg: syscon@c530000 { 725 compatible = "mediatek,mt8183-mcucfg", "syscon"; 726 reg = <0 0x0c530000 0 0x1000>; 727 #clock-cells = <1>; 728 }; 729 730 sysirq: interrupt-controller@c530a80 { 731 compatible = "mediatek,mt8183-sysirq", 732 "mediatek,mt6577-sysirq"; 733 interrupt-controller; 734 #interrupt-cells = <3>; 735 interrupt-parent = <&gic>; 736 reg = <0 0x0c530a80 0 0x50>; 737 }; 738 739 cpu_debug0: cpu-debug@d410000 { 740 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 741 reg = <0x0 0xd410000 0x0 0x1000>; 742 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 743 clock-names = "apb_pclk"; 744 cpu = <&cpu0>; 745 }; 746 747 cpu_debug1: cpu-debug@d510000 { 748 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 749 reg = <0x0 0xd510000 0x0 0x1000>; 750 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 751 clock-names = "apb_pclk"; 752 cpu = <&cpu1>; 753 }; 754 755 cpu_debug2: cpu-debug@d610000 { 756 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 757 reg = <0x0 0xd610000 0x0 0x1000>; 758 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 759 clock-names = "apb_pclk"; 760 cpu = <&cpu2>; 761 }; 762 763 cpu_debug3: cpu-debug@d710000 { 764 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 765 reg = <0x0 0xd710000 0x0 0x1000>; 766 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 767 clock-names = "apb_pclk"; 768 cpu = <&cpu3>; 769 }; 770 771 cpu_debug4: cpu-debug@d810000 { 772 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 773 reg = <0x0 0xd810000 0x0 0x1000>; 774 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 775 clock-names = "apb_pclk"; 776 cpu = <&cpu4>; 777 }; 778 779 cpu_debug5: cpu-debug@d910000 { 780 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 781 reg = <0x0 0xd910000 0x0 0x1000>; 782 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 783 clock-names = "apb_pclk"; 784 cpu = <&cpu5>; 785 }; 786 787 cpu_debug6: cpu-debug@da10000 { 788 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 789 reg = <0x0 0xda10000 0x0 0x1000>; 790 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 791 clock-names = "apb_pclk"; 792 cpu = <&cpu6>; 793 }; 794 795 cpu_debug7: cpu-debug@db10000 { 796 compatible = "arm,coresight-cpu-debug", "arm,primecell"; 797 reg = <0x0 0xdb10000 0x0 0x1000>; 798 clocks = <&infracfg CLK_INFRA_DEBUGSYS>; 799 clock-names = "apb_pclk"; 800 cpu = <&cpu7>; 801 }; 802 803 topckgen: syscon@10000000 { 804 compatible = "mediatek,mt8183-topckgen", "syscon"; 805 reg = <0 0x10000000 0 0x1000>; 806 #clock-cells = <1>; 807 }; 808 809 infracfg: syscon@10001000 { 810 compatible = "mediatek,mt8183-infracfg", "syscon"; 811 reg = <0 0x10001000 0 0x1000>; 812 #clock-cells = <1>; 813 #reset-cells = <1>; 814 }; 815 816 pericfg: syscon@10003000 { 817 compatible = "mediatek,mt8183-pericfg", "syscon"; 818 reg = <0 0x10003000 0 0x1000>; 819 #clock-cells = <1>; 820 }; 821 822 pio: pinctrl@10005000 { 823 compatible = "mediatek,mt8183-pinctrl"; 824 reg = <0 0x10005000 0 0x1000>, 825 <0 0x11f20000 0 0x1000>, 826 <0 0x11e80000 0 0x1000>, 827 <0 0x11e70000 0 0x1000>, 828 <0 0x11e90000 0 0x1000>, 829 <0 0x11d30000 0 0x1000>, 830 <0 0x11d20000 0 0x1000>, 831 <0 0x11c50000 0 0x1000>, 832 <0 0x11f30000 0 0x1000>, 833 <0 0x1000b000 0 0x1000>; 834 reg-names = "iocfg0", "iocfg1", "iocfg2", 835 "iocfg3", "iocfg4", "iocfg5", 836 "iocfg6", "iocfg7", "iocfg8", 837 "eint"; 838 gpio-controller; 839 #gpio-cells = <2>; 840 gpio-ranges = <&pio 0 0 192>; 841 interrupt-controller; 842 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 843 #interrupt-cells = <2>; 844 }; 845 846 scpsys: syscon@10006000 { 847 compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd"; 848 reg = <0 0x10006000 0 0x1000>; 849 850 /* System Power Manager */ 851 spm: power-controller { 852 compatible = "mediatek,mt8183-power-controller"; 853 #address-cells = <1>; 854 #size-cells = <0>; 855 #power-domain-cells = <1>; 856 857 /* power domain of the SoC */ 858 power-domain@MT8183_POWER_DOMAIN_AUDIO { 859 reg = <MT8183_POWER_DOMAIN_AUDIO>; 860 clocks = <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 861 <&infracfg CLK_INFRA_AUDIO>, 862 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>; 863 clock-names = "audio", "audio1", "audio2"; 864 #power-domain-cells = <0>; 865 }; 866 867 power-domain@MT8183_POWER_DOMAIN_CONN { 868 reg = <MT8183_POWER_DOMAIN_CONN>; 869 mediatek,infracfg = <&infracfg>; 870 #power-domain-cells = <0>; 871 }; 872 873 mfg_async: power-domain@MT8183_POWER_DOMAIN_MFG_ASYNC { 874 reg = <MT8183_POWER_DOMAIN_MFG_ASYNC>; 875 #address-cells = <1>; 876 #size-cells = <0>; 877 #power-domain-cells = <1>; 878 879 mfg: power-domain@MT8183_POWER_DOMAIN_MFG { 880 reg = <MT8183_POWER_DOMAIN_MFG>; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 #power-domain-cells = <1>; 884 885 power-domain@MT8183_POWER_DOMAIN_MFG_CORE0 { 886 reg = <MT8183_POWER_DOMAIN_MFG_CORE0>; 887 #power-domain-cells = <0>; 888 }; 889 890 power-domain@MT8183_POWER_DOMAIN_MFG_CORE1 { 891 reg = <MT8183_POWER_DOMAIN_MFG_CORE1>; 892 #power-domain-cells = <0>; 893 }; 894 895 power-domain@MT8183_POWER_DOMAIN_MFG_2D { 896 reg = <MT8183_POWER_DOMAIN_MFG_2D>; 897 mediatek,infracfg = <&infracfg>; 898 #power-domain-cells = <0>; 899 }; 900 }; 901 }; 902 903 power-domain@MT8183_POWER_DOMAIN_DISP { 904 reg = <MT8183_POWER_DOMAIN_DISP>; 905 clocks = <&topckgen CLK_TOP_MUX_MM>, 906 <&mmsys CLK_MM_SMI_COMMON>, 907 <&mmsys CLK_MM_SMI_LARB0>, 908 <&mmsys CLK_MM_SMI_LARB1>, 909 <&mmsys CLK_MM_GALS_COMM0>, 910 <&mmsys CLK_MM_GALS_COMM1>, 911 <&mmsys CLK_MM_GALS_CCU2MM>, 912 <&mmsys CLK_MM_GALS_IPU12MM>, 913 <&mmsys CLK_MM_GALS_IMG2MM>, 914 <&mmsys CLK_MM_GALS_CAM2MM>, 915 <&mmsys CLK_MM_GALS_IPU2MM>; 916 clock-names = "mm", "mm-0", "mm-1", "mm-2", "mm-3", 917 "mm-4", "mm-5", "mm-6", "mm-7", 918 "mm-8", "mm-9"; 919 mediatek,infracfg = <&infracfg>; 920 mediatek,smi = <&smi_common>; 921 #address-cells = <1>; 922 #size-cells = <0>; 923 #power-domain-cells = <1>; 924 925 power-domain@MT8183_POWER_DOMAIN_CAM { 926 reg = <MT8183_POWER_DOMAIN_CAM>; 927 clocks = <&topckgen CLK_TOP_MUX_CAM>, 928 <&camsys CLK_CAM_LARB6>, 929 <&camsys CLK_CAM_LARB3>, 930 <&camsys CLK_CAM_SENINF>, 931 <&camsys CLK_CAM_CAMSV0>, 932 <&camsys CLK_CAM_CAMSV1>, 933 <&camsys CLK_CAM_CAMSV2>, 934 <&camsys CLK_CAM_CCU>; 935 clock-names = "cam", "cam-0", "cam-1", 936 "cam-2", "cam-3", "cam-4", 937 "cam-5", "cam-6"; 938 mediatek,infracfg = <&infracfg>; 939 mediatek,smi = <&smi_common>; 940 #power-domain-cells = <0>; 941 }; 942 943 power-domain@MT8183_POWER_DOMAIN_ISP { 944 reg = <MT8183_POWER_DOMAIN_ISP>; 945 clocks = <&topckgen CLK_TOP_MUX_IMG>, 946 <&imgsys CLK_IMG_LARB5>, 947 <&imgsys CLK_IMG_LARB2>; 948 clock-names = "isp", "isp-0", "isp-1"; 949 mediatek,infracfg = <&infracfg>; 950 mediatek,smi = <&smi_common>; 951 #power-domain-cells = <0>; 952 }; 953 954 power-domain@MT8183_POWER_DOMAIN_VDEC { 955 reg = <MT8183_POWER_DOMAIN_VDEC>; 956 mediatek,smi = <&smi_common>; 957 #power-domain-cells = <0>; 958 }; 959 960 power-domain@MT8183_POWER_DOMAIN_VENC { 961 reg = <MT8183_POWER_DOMAIN_VENC>; 962 mediatek,smi = <&smi_common>; 963 #power-domain-cells = <0>; 964 }; 965 966 power-domain@MT8183_POWER_DOMAIN_VPU_TOP { 967 reg = <MT8183_POWER_DOMAIN_VPU_TOP>; 968 clocks = <&topckgen CLK_TOP_MUX_IPU_IF>, 969 <&topckgen CLK_TOP_MUX_DSP>, 970 <&ipu_conn CLK_IPU_CONN_IPU>, 971 <&ipu_conn CLK_IPU_CONN_AHB>, 972 <&ipu_conn CLK_IPU_CONN_AXI>, 973 <&ipu_conn CLK_IPU_CONN_ISP>, 974 <&ipu_conn CLK_IPU_CONN_CAM_ADL>, 975 <&ipu_conn CLK_IPU_CONN_IMG_ADL>; 976 clock-names = "vpu", "vpu1", "vpu-0", "vpu-1", 977 "vpu-2", "vpu-3", "vpu-4", "vpu-5"; 978 mediatek,infracfg = <&infracfg>; 979 mediatek,smi = <&smi_common>; 980 #address-cells = <1>; 981 #size-cells = <0>; 982 #power-domain-cells = <1>; 983 984 power-domain@MT8183_POWER_DOMAIN_VPU_CORE0 { 985 reg = <MT8183_POWER_DOMAIN_VPU_CORE0>; 986 clocks = <&topckgen CLK_TOP_MUX_DSP1>; 987 clock-names = "vpu2"; 988 mediatek,infracfg = <&infracfg>; 989 #power-domain-cells = <0>; 990 }; 991 992 power-domain@MT8183_POWER_DOMAIN_VPU_CORE1 { 993 reg = <MT8183_POWER_DOMAIN_VPU_CORE1>; 994 clocks = <&topckgen CLK_TOP_MUX_DSP2>; 995 clock-names = "vpu3"; 996 mediatek,infracfg = <&infracfg>; 997 #power-domain-cells = <0>; 998 }; 999 }; 1000 }; 1001 }; 1002 }; 1003 1004 watchdog: watchdog@10007000 { 1005 compatible = "mediatek,mt8183-wdt"; 1006 reg = <0 0x10007000 0 0x100>; 1007 #reset-cells = <1>; 1008 }; 1009 1010 apmixedsys: syscon@1000c000 { 1011 compatible = "mediatek,mt8183-apmixedsys", "syscon"; 1012 reg = <0 0x1000c000 0 0x1000>; 1013 #clock-cells = <1>; 1014 }; 1015 1016 pwrap: pwrap@1000d000 { 1017 compatible = "mediatek,mt8183-pwrap"; 1018 reg = <0 0x1000d000 0 0x1000>; 1019 reg-names = "pwrap"; 1020 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1021 clocks = <&topckgen CLK_TOP_MUX_PMICSPI>, 1022 <&infracfg CLK_INFRA_PMIC_AP>; 1023 clock-names = "spi", "wrap"; 1024 }; 1025 1026 keyboard: keyboard@10010000 { 1027 compatible = "mediatek,mt8183-keypad", 1028 "mediatek,mt6779-keypad"; 1029 reg = <0 0x10010000 0 0x1000>; 1030 interrupts = <GIC_SPI 186 IRQ_TYPE_EDGE_FALLING>; 1031 clocks = <&clk26m>; 1032 clock-names = "kpd"; 1033 status = "disabled"; 1034 }; 1035 1036 scp: scp@10500000 { 1037 compatible = "mediatek,mt8183-scp"; 1038 reg = <0 0x10500000 0 0x80000>, 1039 <0 0x105c0000 0 0x19080>; 1040 reg-names = "sram", "cfg"; 1041 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1042 clocks = <&infracfg CLK_INFRA_SCPSYS>; 1043 clock-names = "main"; 1044 memory-region = <&scp_mem_reserved>; 1045 status = "disabled"; 1046 }; 1047 1048 systimer: timer@10017000 { 1049 compatible = "mediatek,mt8183-timer", 1050 "mediatek,mt6765-timer"; 1051 reg = <0 0x10017000 0 0x1000>; 1052 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>; 1053 clocks = <&clk13m>; 1054 }; 1055 1056 iommu: iommu@10205000 { 1057 compatible = "mediatek,mt8183-m4u"; 1058 reg = <0 0x10205000 0 0x1000>; 1059 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>; 1060 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, <&larb3>, 1061 <&larb4>, <&larb5>, <&larb6>; 1062 #iommu-cells = <1>; 1063 }; 1064 1065 gce: mailbox@10238000 { 1066 compatible = "mediatek,mt8183-gce"; 1067 reg = <0 0x10238000 0 0x4000>; 1068 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>; 1069 #mbox-cells = <2>; 1070 clocks = <&infracfg CLK_INFRA_GCE>; 1071 clock-names = "gce"; 1072 }; 1073 1074 auxadc: auxadc@11001000 { 1075 compatible = "mediatek,mt8183-auxadc", 1076 "mediatek,mt8173-auxadc"; 1077 reg = <0 0x11001000 0 0x1000>; 1078 clocks = <&infracfg CLK_INFRA_AUXADC>; 1079 clock-names = "main"; 1080 #io-channel-cells = <1>; 1081 status = "disabled"; 1082 }; 1083 1084 uart0: serial@11002000 { 1085 compatible = "mediatek,mt8183-uart", 1086 "mediatek,mt6577-uart"; 1087 reg = <0 0x11002000 0 0x1000>; 1088 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 1089 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART0>; 1090 clock-names = "baud", "bus"; 1091 status = "disabled"; 1092 }; 1093 1094 uart1: serial@11003000 { 1095 compatible = "mediatek,mt8183-uart", 1096 "mediatek,mt6577-uart"; 1097 reg = <0 0x11003000 0 0x1000>; 1098 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 1099 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART1>; 1100 clock-names = "baud", "bus"; 1101 status = "disabled"; 1102 }; 1103 1104 uart2: serial@11004000 { 1105 compatible = "mediatek,mt8183-uart", 1106 "mediatek,mt6577-uart"; 1107 reg = <0 0x11004000 0 0x1000>; 1108 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 1109 clocks = <&clk26m>, <&infracfg CLK_INFRA_UART2>; 1110 clock-names = "baud", "bus"; 1111 status = "disabled"; 1112 }; 1113 1114 i2c6: i2c@11005000 { 1115 compatible = "mediatek,mt8183-i2c"; 1116 reg = <0 0x11005000 0 0x1000>, 1117 <0 0x11000600 0 0x80>; 1118 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 1119 clocks = <&infracfg CLK_INFRA_I2C6>, 1120 <&infracfg CLK_INFRA_AP_DMA>; 1121 clock-names = "main", "dma"; 1122 clock-div = <1>; 1123 #address-cells = <1>; 1124 #size-cells = <0>; 1125 status = "disabled"; 1126 }; 1127 1128 i2c0: i2c@11007000 { 1129 compatible = "mediatek,mt8183-i2c"; 1130 reg = <0 0x11007000 0 0x1000>, 1131 <0 0x11000080 0 0x80>; 1132 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 1133 clocks = <&infracfg CLK_INFRA_I2C0>, 1134 <&infracfg CLK_INFRA_AP_DMA>; 1135 clock-names = "main", "dma"; 1136 clock-div = <1>; 1137 #address-cells = <1>; 1138 #size-cells = <0>; 1139 status = "disabled"; 1140 }; 1141 1142 i2c4: i2c@11008000 { 1143 compatible = "mediatek,mt8183-i2c"; 1144 reg = <0 0x11008000 0 0x1000>, 1145 <0 0x11000100 0 0x80>; 1146 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 1147 clocks = <&infracfg CLK_INFRA_I2C1>, 1148 <&infracfg CLK_INFRA_AP_DMA>, 1149 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1150 clock-names = "main", "dma","arb"; 1151 clock-div = <1>; 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 status = "disabled"; 1155 }; 1156 1157 i2c2: i2c@11009000 { 1158 compatible = "mediatek,mt8183-i2c"; 1159 reg = <0 0x11009000 0 0x1000>, 1160 <0 0x11000280 0 0x80>; 1161 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 1162 clocks = <&infracfg CLK_INFRA_I2C2>, 1163 <&infracfg CLK_INFRA_AP_DMA>, 1164 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1165 clock-names = "main", "dma", "arb"; 1166 clock-div = <1>; 1167 #address-cells = <1>; 1168 #size-cells = <0>; 1169 status = "disabled"; 1170 }; 1171 1172 spi0: spi@1100a000 { 1173 compatible = "mediatek,mt8183-spi"; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 reg = <0 0x1100a000 0 0x1000>; 1177 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_LOW>; 1178 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1179 <&topckgen CLK_TOP_MUX_SPI>, 1180 <&infracfg CLK_INFRA_SPI0>; 1181 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1182 status = "disabled"; 1183 }; 1184 1185 thermal: thermal-sensor@1100b000 { 1186 #thermal-sensor-cells = <1>; 1187 compatible = "mediatek,mt8183-thermal"; 1188 reg = <0 0x1100b000 0 0xc00>; 1189 clocks = <&infracfg CLK_INFRA_THERM>, 1190 <&infracfg CLK_INFRA_AUXADC>; 1191 clock-names = "therm", "auxadc"; 1192 resets = <&infracfg MT8183_INFRACFG_AO_THERM_SW_RST>; 1193 interrupts = <0 76 IRQ_TYPE_LEVEL_LOW>; 1194 mediatek,auxadc = <&auxadc>; 1195 mediatek,apmixedsys = <&apmixedsys>; 1196 nvmem-cells = <&thermal_calibration>; 1197 nvmem-cell-names = "calibration-data"; 1198 }; 1199 1200 svs: svs@1100bc00 { 1201 compatible = "mediatek,mt8183-svs"; 1202 reg = <0 0x1100bc00 0 0x400>; 1203 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 1204 clocks = <&infracfg CLK_INFRA_THERM>; 1205 clock-names = "main"; 1206 nvmem-cells = <&svs_calibration>, 1207 <&thermal_calibration>; 1208 nvmem-cell-names = "svs-calibration-data", 1209 "t-calibration-data"; 1210 }; 1211 1212 pwm0: pwm@1100e000 { 1213 compatible = "mediatek,mt8183-disp-pwm"; 1214 reg = <0 0x1100e000 0 0x1000>; 1215 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 1216 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1217 #pwm-cells = <2>; 1218 clocks = <&topckgen CLK_TOP_MUX_DISP_PWM>, 1219 <&infracfg CLK_INFRA_DISP_PWM>; 1220 clock-names = "main", "mm"; 1221 }; 1222 1223 pwm1: pwm@11006000 { 1224 compatible = "mediatek,mt8183-pwm"; 1225 reg = <0 0x11006000 0 0x1000>; 1226 #pwm-cells = <2>; 1227 clocks = <&infracfg CLK_INFRA_PWM>, 1228 <&infracfg CLK_INFRA_PWM_HCLK>, 1229 <&infracfg CLK_INFRA_PWM1>, 1230 <&infracfg CLK_INFRA_PWM2>, 1231 <&infracfg CLK_INFRA_PWM3>, 1232 <&infracfg CLK_INFRA_PWM4>; 1233 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 1234 "pwm4"; 1235 }; 1236 1237 i2c3: i2c@1100f000 { 1238 compatible = "mediatek,mt8183-i2c"; 1239 reg = <0 0x1100f000 0 0x1000>, 1240 <0 0x11000400 0 0x80>; 1241 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 1242 clocks = <&infracfg CLK_INFRA_I2C3>, 1243 <&infracfg CLK_INFRA_AP_DMA>; 1244 clock-names = "main", "dma"; 1245 clock-div = <1>; 1246 #address-cells = <1>; 1247 #size-cells = <0>; 1248 status = "disabled"; 1249 }; 1250 1251 spi1: spi@11010000 { 1252 compatible = "mediatek,mt8183-spi"; 1253 #address-cells = <1>; 1254 #size-cells = <0>; 1255 reg = <0 0x11010000 0 0x1000>; 1256 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_LOW>; 1257 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1258 <&topckgen CLK_TOP_MUX_SPI>, 1259 <&infracfg CLK_INFRA_SPI1>; 1260 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1261 status = "disabled"; 1262 }; 1263 1264 i2c1: i2c@11011000 { 1265 compatible = "mediatek,mt8183-i2c"; 1266 reg = <0 0x11011000 0 0x1000>, 1267 <0 0x11000480 0 0x80>; 1268 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 1269 clocks = <&infracfg CLK_INFRA_I2C4>, 1270 <&infracfg CLK_INFRA_AP_DMA>; 1271 clock-names = "main", "dma"; 1272 clock-div = <1>; 1273 #address-cells = <1>; 1274 #size-cells = <0>; 1275 status = "disabled"; 1276 }; 1277 1278 spi2: spi@11012000 { 1279 compatible = "mediatek,mt8183-spi"; 1280 #address-cells = <1>; 1281 #size-cells = <0>; 1282 reg = <0 0x11012000 0 0x1000>; 1283 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 1284 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1285 <&topckgen CLK_TOP_MUX_SPI>, 1286 <&infracfg CLK_INFRA_SPI2>; 1287 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1288 status = "disabled"; 1289 }; 1290 1291 spi3: spi@11013000 { 1292 compatible = "mediatek,mt8183-spi"; 1293 #address-cells = <1>; 1294 #size-cells = <0>; 1295 reg = <0 0x11013000 0 0x1000>; 1296 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_LOW>; 1297 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1298 <&topckgen CLK_TOP_MUX_SPI>, 1299 <&infracfg CLK_INFRA_SPI3>; 1300 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1301 status = "disabled"; 1302 }; 1303 1304 i2c9: i2c@11014000 { 1305 compatible = "mediatek,mt8183-i2c"; 1306 reg = <0 0x11014000 0 0x1000>, 1307 <0 0x11000180 0 0x80>; 1308 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_LOW>; 1309 clocks = <&infracfg CLK_INFRA_I2C1_IMM>, 1310 <&infracfg CLK_INFRA_AP_DMA>, 1311 <&infracfg CLK_INFRA_I2C1_ARBITER>; 1312 clock-names = "main", "dma", "arb"; 1313 clock-div = <1>; 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 status = "disabled"; 1317 }; 1318 1319 i2c10: i2c@11015000 { 1320 compatible = "mediatek,mt8183-i2c"; 1321 reg = <0 0x11015000 0 0x1000>, 1322 <0 0x11000300 0 0x80>; 1323 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; 1324 clocks = <&infracfg CLK_INFRA_I2C2_IMM>, 1325 <&infracfg CLK_INFRA_AP_DMA>, 1326 <&infracfg CLK_INFRA_I2C2_ARBITER>; 1327 clock-names = "main", "dma", "arb"; 1328 clock-div = <1>; 1329 #address-cells = <1>; 1330 #size-cells = <0>; 1331 status = "disabled"; 1332 }; 1333 1334 i2c5: i2c@11016000 { 1335 compatible = "mediatek,mt8183-i2c"; 1336 reg = <0 0x11016000 0 0x1000>, 1337 <0 0x11000500 0 0x80>; 1338 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 1339 clocks = <&infracfg CLK_INFRA_I2C5>, 1340 <&infracfg CLK_INFRA_AP_DMA>, 1341 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1342 clock-names = "main", "dma", "arb"; 1343 clock-div = <1>; 1344 #address-cells = <1>; 1345 #size-cells = <0>; 1346 status = "disabled"; 1347 }; 1348 1349 i2c11: i2c@11017000 { 1350 compatible = "mediatek,mt8183-i2c"; 1351 reg = <0 0x11017000 0 0x1000>, 1352 <0 0x11000580 0 0x80>; 1353 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_LOW>; 1354 clocks = <&infracfg CLK_INFRA_I2C5_IMM>, 1355 <&infracfg CLK_INFRA_AP_DMA>, 1356 <&infracfg CLK_INFRA_I2C5_ARBITER>; 1357 clock-names = "main", "dma", "arb"; 1358 clock-div = <1>; 1359 #address-cells = <1>; 1360 #size-cells = <0>; 1361 status = "disabled"; 1362 }; 1363 1364 spi4: spi@11018000 { 1365 compatible = "mediatek,mt8183-spi"; 1366 #address-cells = <1>; 1367 #size-cells = <0>; 1368 reg = <0 0x11018000 0 0x1000>; 1369 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_LOW>; 1370 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1371 <&topckgen CLK_TOP_MUX_SPI>, 1372 <&infracfg CLK_INFRA_SPI4>; 1373 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1374 status = "disabled"; 1375 }; 1376 1377 spi5: spi@11019000 { 1378 compatible = "mediatek,mt8183-spi"; 1379 #address-cells = <1>; 1380 #size-cells = <0>; 1381 reg = <0 0x11019000 0 0x1000>; 1382 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 1383 clocks = <&topckgen CLK_TOP_SYSPLL_D5_D2>, 1384 <&topckgen CLK_TOP_MUX_SPI>, 1385 <&infracfg CLK_INFRA_SPI5>; 1386 clock-names = "parent-clk", "sel-clk", "spi-clk"; 1387 status = "disabled"; 1388 }; 1389 1390 i2c7: i2c@1101a000 { 1391 compatible = "mediatek,mt8183-i2c"; 1392 reg = <0 0x1101a000 0 0x1000>, 1393 <0 0x11000680 0 0x80>; 1394 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 1395 clocks = <&infracfg CLK_INFRA_I2C7>, 1396 <&infracfg CLK_INFRA_AP_DMA>; 1397 clock-names = "main", "dma"; 1398 clock-div = <1>; 1399 #address-cells = <1>; 1400 #size-cells = <0>; 1401 status = "disabled"; 1402 }; 1403 1404 i2c8: i2c@1101b000 { 1405 compatible = "mediatek,mt8183-i2c"; 1406 reg = <0 0x1101b000 0 0x1000>, 1407 <0 0x11000700 0 0x80>; 1408 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 1409 clocks = <&infracfg CLK_INFRA_I2C8>, 1410 <&infracfg CLK_INFRA_AP_DMA>; 1411 clock-names = "main", "dma"; 1412 clock-div = <1>; 1413 #address-cells = <1>; 1414 #size-cells = <0>; 1415 status = "disabled"; 1416 }; 1417 1418 ssusb: usb@11201000 { 1419 compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3"; 1420 reg = <0 0x11201000 0 0x2e00>, 1421 <0 0x11203e00 0 0x0100>; 1422 reg-names = "mac", "ippc"; 1423 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 1424 phys = <&u2port0 PHY_TYPE_USB2>, 1425 <&u3port0 PHY_TYPE_USB3>; 1426 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1427 <&infracfg CLK_INFRA_USB>; 1428 clock-names = "sys_ck", "ref_ck"; 1429 mediatek,syscon-wakeup = <&pericfg 0x420 101>; 1430 #address-cells = <2>; 1431 #size-cells = <2>; 1432 ranges; 1433 status = "disabled"; 1434 1435 usb_host: usb@11200000 { 1436 compatible = "mediatek,mt8183-xhci", 1437 "mediatek,mtk-xhci"; 1438 reg = <0 0x11200000 0 0x1000>; 1439 reg-names = "mac"; 1440 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 1441 clocks = <&infracfg CLK_INFRA_UNIPRO_SCK>, 1442 <&infracfg CLK_INFRA_USB>; 1443 clock-names = "sys_ck", "ref_ck"; 1444 status = "disabled"; 1445 }; 1446 }; 1447 1448 audiosys: clock-controller@11220000 { 1449 compatible = "mediatek,mt8183-audiosys", "syscon"; 1450 reg = <0 0x11220000 0 0x1000>; 1451 #clock-cells = <1>; 1452 afe: audio-controller { 1453 compatible = "mediatek,mt8183-audio"; 1454 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; 1455 resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; 1456 reset-names = "audiosys"; 1457 power-domains = 1458 <&spm MT8183_POWER_DOMAIN_AUDIO>; 1459 clocks = <&audiosys CLK_AUDIO_AFE>, 1460 <&audiosys CLK_AUDIO_DAC>, 1461 <&audiosys CLK_AUDIO_DAC_PREDIS>, 1462 <&audiosys CLK_AUDIO_ADC>, 1463 <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, 1464 <&audiosys CLK_AUDIO_22M>, 1465 <&audiosys CLK_AUDIO_24M>, 1466 <&audiosys CLK_AUDIO_APLL_TUNER>, 1467 <&audiosys CLK_AUDIO_APLL2_TUNER>, 1468 <&audiosys CLK_AUDIO_I2S1>, 1469 <&audiosys CLK_AUDIO_I2S2>, 1470 <&audiosys CLK_AUDIO_I2S3>, 1471 <&audiosys CLK_AUDIO_I2S4>, 1472 <&audiosys CLK_AUDIO_TDM>, 1473 <&audiosys CLK_AUDIO_TML>, 1474 <&infracfg CLK_INFRA_AUDIO>, 1475 <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, 1476 <&topckgen CLK_TOP_MUX_AUDIO>, 1477 <&topckgen CLK_TOP_MUX_AUD_INTBUS>, 1478 <&topckgen CLK_TOP_SYSPLL_D2_D4>, 1479 <&topckgen CLK_TOP_MUX_AUD_1>, 1480 <&topckgen CLK_TOP_APLL1_CK>, 1481 <&topckgen CLK_TOP_MUX_AUD_2>, 1482 <&topckgen CLK_TOP_APLL2_CK>, 1483 <&topckgen CLK_TOP_MUX_AUD_ENG1>, 1484 <&topckgen CLK_TOP_APLL1_D8>, 1485 <&topckgen CLK_TOP_MUX_AUD_ENG2>, 1486 <&topckgen CLK_TOP_APLL2_D8>, 1487 <&topckgen CLK_TOP_MUX_APLL_I2S0>, 1488 <&topckgen CLK_TOP_MUX_APLL_I2S1>, 1489 <&topckgen CLK_TOP_MUX_APLL_I2S2>, 1490 <&topckgen CLK_TOP_MUX_APLL_I2S3>, 1491 <&topckgen CLK_TOP_MUX_APLL_I2S4>, 1492 <&topckgen CLK_TOP_MUX_APLL_I2S5>, 1493 <&topckgen CLK_TOP_APLL12_DIV0>, 1494 <&topckgen CLK_TOP_APLL12_DIV1>, 1495 <&topckgen CLK_TOP_APLL12_DIV2>, 1496 <&topckgen CLK_TOP_APLL12_DIV3>, 1497 <&topckgen CLK_TOP_APLL12_DIV4>, 1498 <&topckgen CLK_TOP_APLL12_DIVB>, 1499 /*<&topckgen CLK_TOP_APLL12_DIV5>,*/ 1500 <&clk26m>; 1501 clock-names = "aud_afe_clk", 1502 "aud_dac_clk", 1503 "aud_dac_predis_clk", 1504 "aud_adc_clk", 1505 "aud_adc_adda6_clk", 1506 "aud_apll22m_clk", 1507 "aud_apll24m_clk", 1508 "aud_apll1_tuner_clk", 1509 "aud_apll2_tuner_clk", 1510 "aud_i2s1_bclk_sw", 1511 "aud_i2s2_bclk_sw", 1512 "aud_i2s3_bclk_sw", 1513 "aud_i2s4_bclk_sw", 1514 "aud_tdm_clk", 1515 "aud_tml_clk", 1516 "aud_infra_clk", 1517 "mtkaif_26m_clk", 1518 "top_mux_audio", 1519 "top_mux_aud_intbus", 1520 "top_syspll_d2_d4", 1521 "top_mux_aud_1", 1522 "top_apll1_ck", 1523 "top_mux_aud_2", 1524 "top_apll2_ck", 1525 "top_mux_aud_eng1", 1526 "top_apll1_d8", 1527 "top_mux_aud_eng2", 1528 "top_apll2_d8", 1529 "top_i2s0_m_sel", 1530 "top_i2s1_m_sel", 1531 "top_i2s2_m_sel", 1532 "top_i2s3_m_sel", 1533 "top_i2s4_m_sel", 1534 "top_i2s5_m_sel", 1535 "top_apll12_div0", 1536 "top_apll12_div1", 1537 "top_apll12_div2", 1538 "top_apll12_div3", 1539 "top_apll12_div4", 1540 "top_apll12_divb", 1541 /*"top_apll12_div5",*/ 1542 "top_clk26m_clk"; 1543 }; 1544 }; 1545 1546 mmc0: mmc@11230000 { 1547 compatible = "mediatek,mt8183-mmc"; 1548 reg = <0 0x11230000 0 0x1000>, 1549 <0 0x11f50000 0 0x1000>; 1550 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 1551 clocks = <&topckgen CLK_TOP_MUX_MSDC50_0>, 1552 <&infracfg CLK_INFRA_MSDC0>, 1553 <&infracfg CLK_INFRA_MSDC0_SCK>; 1554 clock-names = "source", "hclk", "source_cg"; 1555 status = "disabled"; 1556 }; 1557 1558 mmc1: mmc@11240000 { 1559 compatible = "mediatek,mt8183-mmc"; 1560 reg = <0 0x11240000 0 0x1000>, 1561 <0 0x11e10000 0 0x1000>; 1562 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 1563 clocks = <&topckgen CLK_TOP_MUX_MSDC30_1>, 1564 <&infracfg CLK_INFRA_MSDC1>, 1565 <&infracfg CLK_INFRA_MSDC1_SCK>; 1566 clock-names = "source", "hclk", "source_cg"; 1567 status = "disabled"; 1568 }; 1569 1570 mipi_tx0: dsi-phy@11e50000 { 1571 compatible = "mediatek,mt8183-mipi-tx"; 1572 reg = <0 0x11e50000 0 0x1000>; 1573 clocks = <&apmixedsys CLK_APMIXED_MIPID0_26M>; 1574 #clock-cells = <0>; 1575 #phy-cells = <0>; 1576 clock-output-names = "mipi_tx0_pll"; 1577 nvmem-cells = <&mipi_tx_calibration>; 1578 nvmem-cell-names = "calibration-data"; 1579 }; 1580 1581 efuse: efuse@11f10000 { 1582 compatible = "mediatek,mt8183-efuse", 1583 "mediatek,efuse"; 1584 reg = <0 0x11f10000 0 0x1000>; 1585 #address-cells = <1>; 1586 #size-cells = <1>; 1587 1588 socinfo-data1@4c { 1589 reg = <0x04c 0x4>; 1590 }; 1591 1592 socinfo-data2@60 { 1593 reg = <0x060 0x4>; 1594 }; 1595 1596 thermal_calibration: calib@180 { 1597 reg = <0x180 0xc>; 1598 }; 1599 1600 mipi_tx_calibration: calib@190 { 1601 reg = <0x190 0xc>; 1602 }; 1603 1604 svs_calibration: calib@580 { 1605 reg = <0x580 0x64>; 1606 }; 1607 }; 1608 1609 u3phy: t-phy@11f40000 { 1610 compatible = "mediatek,mt8183-tphy", 1611 "mediatek,generic-tphy-v2"; 1612 #address-cells = <1>; 1613 #size-cells = <1>; 1614 ranges = <0 0 0x11f40000 0x1000>; 1615 status = "okay"; 1616 1617 u2port0: usb-phy@0 { 1618 reg = <0x0 0x700>; 1619 clocks = <&clk26m>; 1620 clock-names = "ref"; 1621 #phy-cells = <1>; 1622 mediatek,discth = <15>; 1623 status = "okay"; 1624 }; 1625 1626 u3port0: usb-phy@700 { 1627 reg = <0x0700 0x900>; 1628 clocks = <&clk26m>; 1629 clock-names = "ref"; 1630 #phy-cells = <1>; 1631 status = "okay"; 1632 }; 1633 }; 1634 1635 mfgcfg: syscon@13000000 { 1636 compatible = "mediatek,mt8183-mfgcfg", "syscon"; 1637 reg = <0 0x13000000 0 0x1000>; 1638 #clock-cells = <1>; 1639 power-domains = <&spm MT8183_POWER_DOMAIN_MFG_ASYNC>; 1640 }; 1641 1642 gpu: gpu@13040000 { 1643 compatible = "mediatek,mt8183b-mali", "arm,mali-bifrost"; 1644 reg = <0 0x13040000 0 0x4000>; 1645 interrupts = 1646 <GIC_SPI 280 IRQ_TYPE_LEVEL_LOW>, 1647 <GIC_SPI 279 IRQ_TYPE_LEVEL_LOW>, 1648 <GIC_SPI 278 IRQ_TYPE_LEVEL_LOW>; 1649 interrupt-names = "job", "mmu", "gpu"; 1650 1651 clocks = <&mfgcfg CLK_MFG_BG3D>; 1652 1653 power-domains = 1654 <&spm MT8183_POWER_DOMAIN_MFG_CORE0>, 1655 <&spm MT8183_POWER_DOMAIN_MFG_CORE1>, 1656 <&spm MT8183_POWER_DOMAIN_MFG_2D>; 1657 power-domain-names = "core0", "core1", "core2"; 1658 1659 operating-points-v2 = <&gpu_opp_table>; 1660 }; 1661 1662 mmsys: syscon@14000000 { 1663 compatible = "mediatek,mt8183-mmsys", "syscon"; 1664 reg = <0 0x14000000 0 0x1000>; 1665 #clock-cells = <1>; 1666 #reset-cells = <1>; 1667 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1668 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1669 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1670 1671 port { 1672 #address-cells = <1>; 1673 #size-cells = <0>; 1674 1675 mmsys_ep_main: endpoint@0 { 1676 reg = <0>; 1677 remote-endpoint = <&ovl0_in>; 1678 }; 1679 1680 mmsys_ep_ext: endpoint@1 { 1681 reg = <1>; 1682 remote-endpoint = <&ovl_2l1_in>; 1683 }; 1684 }; 1685 }; 1686 1687 dma-controller0@14001000 { 1688 compatible = "mediatek,mt8183-mdp3-rdma"; 1689 reg = <0 0x14001000 0 0x1000>; 1690 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; 1691 mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, 1692 <CMDQ_EVENT_MDP_RDMA0_EOF>; 1693 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1694 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1695 <&mmsys CLK_MM_MDP_RSZ1>; 1696 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1697 mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, 1698 <&gce 21 CMDQ_THR_PRIO_LOWEST 0>; 1699 #dma-cells = <1>; 1700 }; 1701 1702 mdp3-rsz0@14003000 { 1703 compatible = "mediatek,mt8183-mdp3-rsz"; 1704 reg = <0 0x14003000 0 0x1000>; 1705 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; 1706 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>, 1707 <CMDQ_EVENT_MDP_RSZ0_EOF>; 1708 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1709 }; 1710 1711 mdp3-rsz1@14004000 { 1712 compatible = "mediatek,mt8183-mdp3-rsz"; 1713 reg = <0 0x14004000 0 0x1000>; 1714 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; 1715 mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>, 1716 <CMDQ_EVENT_MDP_RSZ1_EOF>; 1717 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1718 }; 1719 1720 dma-controller@14005000 { 1721 compatible = "mediatek,mt8183-mdp3-wrot"; 1722 reg = <0 0x14005000 0 0x1000>; 1723 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; 1724 mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>, 1725 <CMDQ_EVENT_MDP_WROT0_EOF>; 1726 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1727 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1728 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1729 #dma-cells = <1>; 1730 }; 1731 1732 mdp3-wdma@14006000 { 1733 compatible = "mediatek,mt8183-mdp3-wdma"; 1734 reg = <0 0x14006000 0 0x1000>; 1735 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; 1736 mediatek,gce-events = <CMDQ_EVENT_MDP_WDMA0_SOF>, 1737 <CMDQ_EVENT_MDP_WDMA0_EOF>; 1738 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1739 clocks = <&mmsys CLK_MM_MDP_WDMA0>; 1740 iommus = <&iommu M4U_PORT_MDP_WDMA0>; 1741 }; 1742 1743 ovl0: ovl@14008000 { 1744 compatible = "mediatek,mt8183-disp-ovl"; 1745 reg = <0 0x14008000 0 0x1000>; 1746 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 1747 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1748 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1749 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1750 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>; 1751 1752 ports { 1753 #address-cells = <1>; 1754 #size-cells = <0>; 1755 1756 port@0 { 1757 reg = <0>; 1758 ovl0_in: endpoint { 1759 remote-endpoint = <&mmsys_ep_main>; 1760 }; 1761 }; 1762 1763 port@1 { 1764 reg = <1>; 1765 ovl0_out: endpoint { 1766 remote-endpoint = <&ovl_2l0_in>; 1767 }; 1768 }; 1769 }; 1770 }; 1771 1772 ovl_2l0: ovl@14009000 { 1773 compatible = "mediatek,mt8183-disp-ovl-2l"; 1774 reg = <0 0x14009000 0 0x1000>; 1775 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_LOW>; 1776 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1777 clocks = <&mmsys CLK_MM_DISP_OVL0_2L>; 1778 iommus = <&iommu M4U_PORT_DISP_2L_OVL0_LARB0>; 1779 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x9000 0x1000>; 1780 1781 ports { 1782 #address-cells = <1>; 1783 #size-cells = <0>; 1784 1785 port@0 { 1786 reg = <0>; 1787 ovl_2l0_in: endpoint { 1788 remote-endpoint = <&ovl0_out>; 1789 }; 1790 }; 1791 1792 port@1 { 1793 reg = <1>; 1794 ovl_2l0_out: endpoint { 1795 remote-endpoint = <&rdma0_in>; 1796 }; 1797 }; 1798 }; 1799 }; 1800 1801 ovl_2l1: ovl@1400a000 { 1802 compatible = "mediatek,mt8183-disp-ovl-2l"; 1803 reg = <0 0x1400a000 0 0x1000>; 1804 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_LOW>; 1805 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1806 clocks = <&mmsys CLK_MM_DISP_OVL1_2L>; 1807 iommus = <&iommu M4U_PORT_DISP_2L_OVL1_LARB0>; 1808 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xa000 0x1000>; 1809 1810 ports { 1811 #address-cells = <1>; 1812 #size-cells = <0>; 1813 1814 port@0 { 1815 #address-cells = <1>; 1816 #size-cells = <0>; 1817 reg = <0>; 1818 1819 ovl_2l1_in: endpoint@1 { 1820 reg = <1>; 1821 remote-endpoint = <&mmsys_ep_ext>; 1822 }; 1823 }; 1824 1825 port@1 { 1826 #address-cells = <1>; 1827 #size-cells = <0>; 1828 reg = <1>; 1829 1830 ovl_2l1_out: endpoint@1 { 1831 reg = <1>; 1832 remote-endpoint = <&rdma1_in>; 1833 }; 1834 }; 1835 }; 1836 }; 1837 1838 rdma0: rdma@1400b000 { 1839 compatible = "mediatek,mt8183-disp-rdma"; 1840 reg = <0 0x1400b000 0 0x1000>; 1841 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 1842 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1843 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1844 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1845 mediatek,rdma-fifo-size = <5120>; 1846 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>; 1847 1848 ports { 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 1852 port@0 { 1853 reg = <0>; 1854 rdma0_in: endpoint { 1855 remote-endpoint = <&ovl_2l0_out>; 1856 }; 1857 }; 1858 1859 port@1 { 1860 reg = <1>; 1861 rdma0_out: endpoint { 1862 remote-endpoint = <&color0_in>; 1863 }; 1864 }; 1865 }; 1866 }; 1867 1868 rdma1: rdma@1400c000 { 1869 compatible = "mediatek,mt8183-disp-rdma"; 1870 reg = <0 0x1400c000 0 0x1000>; 1871 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 1872 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1873 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1874 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1875 mediatek,rdma-fifo-size = <2048>; 1876 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1877 1878 ports { 1879 #address-cells = <1>; 1880 #size-cells = <0>; 1881 1882 port@0 { 1883 #address-cells = <1>; 1884 #size-cells = <0>; 1885 reg = <0>; 1886 1887 rdma1_in: endpoint@1 { 1888 reg = <1>; 1889 remote-endpoint = <&ovl_2l1_out>; 1890 }; 1891 }; 1892 1893 port@1 { 1894 #address-cells = <1>; 1895 #size-cells = <0>; 1896 reg = <1>; 1897 1898 rdma1_out: endpoint@1 { 1899 reg = <1>; 1900 remote-endpoint = <&dpi_in>; 1901 }; 1902 }; 1903 }; 1904 }; 1905 1906 color0: color@1400e000 { 1907 compatible = "mediatek,mt8183-disp-color", 1908 "mediatek,mt8173-disp-color"; 1909 reg = <0 0x1400e000 0 0x1000>; 1910 interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_LOW>; 1911 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1912 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1913 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1914 1915 ports { 1916 #address-cells = <1>; 1917 #size-cells = <0>; 1918 1919 port@0 { 1920 reg = <0>; 1921 color0_in: endpoint { 1922 remote-endpoint = <&rdma0_out>; 1923 }; 1924 }; 1925 1926 port@1 { 1927 reg = <1>; 1928 color0_out: endpoint { 1929 remote-endpoint = <&ccorr0_in>; 1930 }; 1931 }; 1932 }; 1933 }; 1934 1935 ccorr0: ccorr@1400f000 { 1936 compatible = "mediatek,mt8183-disp-ccorr"; 1937 reg = <0 0x1400f000 0 0x1000>; 1938 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 1939 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1940 clocks = <&mmsys CLK_MM_DISP_CCORR0>; 1941 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1942 1943 ports { 1944 #address-cells = <1>; 1945 #size-cells = <0>; 1946 1947 port@0 { 1948 reg = <0>; 1949 ccorr0_in: endpoint { 1950 remote-endpoint = <&color0_out>; 1951 }; 1952 }; 1953 1954 port@1 { 1955 reg = <1>; 1956 ccorr0_out: endpoint { 1957 remote-endpoint = <&aal0_in>; 1958 }; 1959 }; 1960 }; 1961 }; 1962 1963 aal0: aal@14010000 { 1964 compatible = "mediatek,mt8183-disp-aal"; 1965 reg = <0 0x14010000 0 0x1000>; 1966 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_LOW>; 1967 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1968 clocks = <&mmsys CLK_MM_DISP_AAL0>; 1969 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1970 1971 ports { 1972 #address-cells = <1>; 1973 #size-cells = <0>; 1974 1975 port@0 { 1976 reg = <0>; 1977 aal0_in: endpoint { 1978 remote-endpoint = <&ccorr0_out>; 1979 }; 1980 }; 1981 1982 port@1 { 1983 reg = <1>; 1984 aal0_out: endpoint { 1985 remote-endpoint = <&gamma0_in>; 1986 }; 1987 }; 1988 }; 1989 }; 1990 1991 gamma0: gamma@14011000 { 1992 compatible = "mediatek,mt8183-disp-gamma"; 1993 reg = <0 0x14011000 0 0x1000>; 1994 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_LOW>; 1995 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 1996 clocks = <&mmsys CLK_MM_DISP_GAMMA0>; 1997 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1998 1999 ports { 2000 #address-cells = <1>; 2001 #size-cells = <0>; 2002 2003 port@0 { 2004 reg = <0>; 2005 gamma0_in: endpoint { 2006 remote-endpoint = <&aal0_out>; 2007 }; 2008 }; 2009 2010 port@1 { 2011 reg = <1>; 2012 gamma0_out: endpoint { 2013 remote-endpoint = <&dither0_in>; 2014 }; 2015 }; 2016 }; 2017 }; 2018 2019 dither0: dither@14012000 { 2020 compatible = "mediatek,mt8183-disp-dither"; 2021 reg = <0 0x14012000 0 0x1000>; 2022 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_LOW>; 2023 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 2024 clocks = <&mmsys CLK_MM_DISP_DITHER0>; 2025 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 2026 2027 ports { 2028 #address-cells = <1>; 2029 #size-cells = <0>; 2030 2031 port@0 { 2032 reg = <0>; 2033 dither0_in: endpoint { 2034 remote-endpoint = <&gamma0_out>; 2035 }; 2036 }; 2037 2038 port@1 { 2039 reg = <1>; 2040 dither0_out: endpoint { 2041 remote-endpoint = <&dsi_in>; 2042 }; 2043 }; 2044 }; 2045 }; 2046 2047 dsi0: dsi@14014000 { 2048 compatible = "mediatek,mt8183-dsi"; 2049 reg = <0 0x14014000 0 0x1000>; 2050 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_LOW>; 2051 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 2052 clocks = <&mmsys CLK_MM_DSI0_MM>, 2053 <&mmsys CLK_MM_DSI0_IF>, 2054 <&mipi_tx0>; 2055 clock-names = "engine", "digital", "hs"; 2056 resets = <&mmsys MT8183_MMSYS_SW0_RST_B_DISP_DSI0>; 2057 phys = <&mipi_tx0>; 2058 phy-names = "dphy"; 2059 status = "disabled"; 2060 2061 ports { 2062 #address-cells = <1>; 2063 #size-cells = <0>; 2064 2065 port@0 { 2066 reg = <0>; 2067 dsi_in: endpoint { 2068 remote-endpoint = <&dither0_out>; 2069 }; 2070 }; 2071 2072 port@1 { 2073 reg = <1>; 2074 dsi_out: endpoint { }; 2075 }; 2076 }; 2077 }; 2078 2079 dpi0: dpi@14015000 { 2080 compatible = "mediatek,mt8183-dpi"; 2081 reg = <0 0x14015000 0 0x1000>; 2082 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; 2083 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 2084 clocks = <&mmsys CLK_MM_DPI_IF>, 2085 <&mmsys CLK_MM_DPI_MM>, 2086 <&apmixedsys CLK_APMIXED_TVDPLL>; 2087 clock-names = "pixel", "engine", "pll"; 2088 status = "disabled"; 2089 2090 ports { 2091 #address-cells = <1>; 2092 #size-cells = <0>; 2093 2094 port@0 { 2095 #address-cells = <1>; 2096 #size-cells = <0>; 2097 reg = <0>; 2098 2099 dpi_in: endpoint@1 { 2100 reg = <1>; 2101 remote-endpoint = <&rdma1_out>; 2102 }; 2103 }; 2104 2105 port@1 { 2106 #address-cells = <1>; 2107 #size-cells = <0>; 2108 reg = <1>; 2109 2110 dpi_out: endpoint@1 { 2111 reg = <1>; 2112 }; 2113 }; 2114 }; 2115 }; 2116 2117 mutex: mutex@14016000 { 2118 compatible = "mediatek,mt8183-disp-mutex"; 2119 reg = <0 0x14016000 0 0x1000>; 2120 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>; 2121 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 2122 mediatek,gce-events = <CMDQ_EVENT_MUTEX_STREAM_DONE0>, 2123 <CMDQ_EVENT_MUTEX_STREAM_DONE1>; 2124 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 2125 }; 2126 2127 larb0: larb@14017000 { 2128 compatible = "mediatek,mt8183-smi-larb"; 2129 reg = <0 0x14017000 0 0x1000>; 2130 mediatek,smi = <&smi_common>; 2131 clocks = <&mmsys CLK_MM_SMI_LARB0>, 2132 <&mmsys CLK_MM_SMI_LARB0>; 2133 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 2134 clock-names = "apb", "smi"; 2135 }; 2136 2137 smi_common: smi@14019000 { 2138 compatible = "mediatek,mt8183-smi-common"; 2139 reg = <0 0x14019000 0 0x1000>; 2140 clocks = <&mmsys CLK_MM_SMI_COMMON>, 2141 <&mmsys CLK_MM_SMI_COMMON>, 2142 <&mmsys CLK_MM_GALS_COMM0>, 2143 <&mmsys CLK_MM_GALS_COMM1>; 2144 clock-names = "apb", "smi", "gals0", "gals1"; 2145 power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; 2146 }; 2147 2148 mdp3-ccorr@1401c000 { 2149 compatible = "mediatek,mt8183-mdp3-ccorr"; 2150 reg = <0 0x1401c000 0 0x1000>; 2151 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; 2152 mediatek,gce-events = <CMDQ_EVENT_MDP_CCORR_SOF>, 2153 <CMDQ_EVENT_MDP_CCORR_EOF>; 2154 clocks = <&mmsys CLK_MM_MDP_CCORR>; 2155 }; 2156 2157 imgsys: syscon@15020000 { 2158 compatible = "mediatek,mt8183-imgsys", "syscon"; 2159 reg = <0 0x15020000 0 0x1000>; 2160 #clock-cells = <1>; 2161 }; 2162 2163 larb5: larb@15021000 { 2164 compatible = "mediatek,mt8183-smi-larb"; 2165 reg = <0 0x15021000 0 0x1000>; 2166 mediatek,smi = <&smi_common>; 2167 clocks = <&imgsys CLK_IMG_LARB5>, <&imgsys CLK_IMG_LARB5>, 2168 <&mmsys CLK_MM_GALS_IMG2MM>; 2169 clock-names = "apb", "smi", "gals"; 2170 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 2171 }; 2172 2173 larb2: larb@1502f000 { 2174 compatible = "mediatek,mt8183-smi-larb"; 2175 reg = <0 0x1502f000 0 0x1000>; 2176 mediatek,smi = <&smi_common>; 2177 clocks = <&imgsys CLK_IMG_LARB2>, <&imgsys CLK_IMG_LARB2>, 2178 <&mmsys CLK_MM_GALS_IPU2MM>; 2179 clock-names = "apb", "smi", "gals"; 2180 power-domains = <&spm MT8183_POWER_DOMAIN_ISP>; 2181 }; 2182 2183 vdecsys: syscon@16000000 { 2184 compatible = "mediatek,mt8183-vdecsys", "syscon"; 2185 reg = <0 0x16000000 0 0x1000>; 2186 #clock-cells = <1>; 2187 }; 2188 2189 vcodec_dec: video-codec@16020000 { 2190 compatible = "mediatek,mt8183-vcodec-dec"; 2191 reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 2192 <0 0x16021000 0 0x800>, /* VDEC_VLD */ 2193 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 2194 <0 0x16022000 0 0x1000>, /* VDEC_MC */ 2195 <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */ 2196 <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */ 2197 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 2198 <0 0x16026800 0 0x800>, /* VP8_VD */ 2199 <0 0x16027000 0 0x800>, /* VP6_VD */ 2200 <0 0x16027800 0 0x800>, /* VP8_VL */ 2201 <0 0x16028400 0 0x400>; /* VP9_VD */ 2202 reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp", 2203 "hwd", "hwq", "hwb", "hwg"; 2204 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_LOW>; 2205 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 2206 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 2207 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 2208 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 2209 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 2210 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 2211 <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>; 2212 mediatek,scp = <&scp>; 2213 mediatek,vdecsys = <&vdecsys>; 2214 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 2215 clocks = <&vdecsys CLK_VDEC_VDEC>; 2216 clock-names = "vdec"; 2217 }; 2218 2219 larb1: larb@16010000 { 2220 compatible = "mediatek,mt8183-smi-larb"; 2221 reg = <0 0x16010000 0 0x1000>; 2222 mediatek,smi = <&smi_common>; 2223 clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LARB1>; 2224 clock-names = "apb", "smi"; 2225 power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; 2226 }; 2227 2228 vencsys: syscon@17000000 { 2229 compatible = "mediatek,mt8183-vencsys", "syscon"; 2230 reg = <0 0x17000000 0 0x1000>; 2231 #clock-cells = <1>; 2232 }; 2233 2234 larb4: larb@17010000 { 2235 compatible = "mediatek,mt8183-smi-larb"; 2236 reg = <0 0x17010000 0 0x1000>; 2237 mediatek,smi = <&smi_common>; 2238 clocks = <&vencsys CLK_VENC_LARB>, 2239 <&vencsys CLK_VENC_LARB>; 2240 clock-names = "apb", "smi"; 2241 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 2242 }; 2243 2244 vcodec_enc: vcodec@17020000 { 2245 compatible = "mediatek,mt8183-vcodec-enc"; 2246 reg = <0 0x17020000 0 0x1000>; 2247 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_LOW>; 2248 iommus = <&iommu M4U_PORT_VENC_REC>, 2249 <&iommu M4U_PORT_VENC_BSDMA>, 2250 <&iommu M4U_PORT_VENC_RD_COMV>, 2251 <&iommu M4U_PORT_VENC_CUR_LUMA>, 2252 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 2253 <&iommu M4U_PORT_VENC_REF_LUMA>, 2254 <&iommu M4U_PORT_VENC_REF_CHROMA>; 2255 mediatek,scp = <&scp>; 2256 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 2257 clocks = <&vencsys CLK_VENC_VENC>; 2258 clock-names = "venc_sel"; 2259 }; 2260 2261 venc_jpg: jpeg-encoder@17030000 { 2262 compatible = "mediatek,mt8183-jpgenc", "mediatek,mtk-jpgenc"; 2263 reg = <0 0x17030000 0 0x1000>; 2264 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 2265 iommus = <&iommu M4U_PORT_JPGENC_RDMA>, 2266 <&iommu M4U_PORT_JPGENC_BSDMA>; 2267 power-domains = <&spm MT8183_POWER_DOMAIN_VENC>; 2268 clocks = <&vencsys CLK_VENC_JPGENC>; 2269 clock-names = "jpgenc"; 2270 }; 2271 2272 ipu_conn: syscon@19000000 { 2273 compatible = "mediatek,mt8183-ipu_conn", "syscon"; 2274 reg = <0 0x19000000 0 0x1000>; 2275 #clock-cells = <1>; 2276 }; 2277 2278 ipu_adl: syscon@19010000 { 2279 compatible = "mediatek,mt8183-ipu_adl", "syscon"; 2280 reg = <0 0x19010000 0 0x1000>; 2281 #clock-cells = <1>; 2282 }; 2283 2284 ipu_core0: syscon@19180000 { 2285 compatible = "mediatek,mt8183-ipu_core0", "syscon"; 2286 reg = <0 0x19180000 0 0x1000>; 2287 #clock-cells = <1>; 2288 }; 2289 2290 ipu_core1: syscon@19280000 { 2291 compatible = "mediatek,mt8183-ipu_core1", "syscon"; 2292 reg = <0 0x19280000 0 0x1000>; 2293 #clock-cells = <1>; 2294 }; 2295 2296 camsys: syscon@1a000000 { 2297 compatible = "mediatek,mt8183-camsys", "syscon"; 2298 reg = <0 0x1a000000 0 0x1000>; 2299 #clock-cells = <1>; 2300 }; 2301 2302 larb6: larb@1a001000 { 2303 compatible = "mediatek,mt8183-smi-larb"; 2304 reg = <0 0x1a001000 0 0x1000>; 2305 mediatek,smi = <&smi_common>; 2306 clocks = <&camsys CLK_CAM_LARB6>, <&camsys CLK_CAM_LARB6>, 2307 <&mmsys CLK_MM_GALS_CAM2MM>; 2308 clock-names = "apb", "smi", "gals"; 2309 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 2310 }; 2311 2312 larb3: larb@1a002000 { 2313 compatible = "mediatek,mt8183-smi-larb"; 2314 reg = <0 0x1a002000 0 0x1000>; 2315 mediatek,smi = <&smi_common>; 2316 clocks = <&camsys CLK_CAM_LARB3>, <&camsys CLK_CAM_LARB3>, 2317 <&mmsys CLK_MM_GALS_IPU12MM>; 2318 clock-names = "apb", "smi", "gals"; 2319 power-domains = <&spm MT8183_POWER_DOMAIN_CAM>; 2320 }; 2321 }; 2322 2323 thermal_zones: thermal-zones { 2324 cpu_thermal: cpu-thermal { 2325 polling-delay-passive = <100>; 2326 polling-delay = <500>; 2327 thermal-sensors = <&thermal 0>; 2328 sustainable-power = <5000>; 2329 2330 trips { 2331 threshold: trip-point0 { 2332 temperature = <68000>; 2333 hysteresis = <2000>; 2334 type = "passive"; 2335 }; 2336 2337 target: trip-point1 { 2338 temperature = <80000>; 2339 hysteresis = <2000>; 2340 type = "passive"; 2341 }; 2342 2343 cpu_crit: cpu-crit { 2344 temperature = <115000>; 2345 hysteresis = <2000>; 2346 type = "critical"; 2347 }; 2348 }; 2349 2350 cooling-maps { 2351 map0 { 2352 trip = <&target>; 2353 cooling-device = <&cpu0 2354 THERMAL_NO_LIMIT 2355 THERMAL_NO_LIMIT>, 2356 <&cpu1 2357 THERMAL_NO_LIMIT 2358 THERMAL_NO_LIMIT>, 2359 <&cpu2 2360 THERMAL_NO_LIMIT 2361 THERMAL_NO_LIMIT>, 2362 <&cpu3 2363 THERMAL_NO_LIMIT 2364 THERMAL_NO_LIMIT>; 2365 contribution = <3072>; 2366 }; 2367 map1 { 2368 trip = <&target>; 2369 cooling-device = <&cpu4 2370 THERMAL_NO_LIMIT 2371 THERMAL_NO_LIMIT>, 2372 <&cpu5 2373 THERMAL_NO_LIMIT 2374 THERMAL_NO_LIMIT>, 2375 <&cpu6 2376 THERMAL_NO_LIMIT 2377 THERMAL_NO_LIMIT>, 2378 <&cpu7 2379 THERMAL_NO_LIMIT 2380 THERMAL_NO_LIMIT>; 2381 contribution = <1024>; 2382 }; 2383 }; 2384 }; 2385 2386 tzts1: soc-thermal { 2387 polling-delay = <1000>; 2388 polling-delay-passive = <250>; 2389 thermal-sensors = <&thermal 1>; 2390 sustainable-power = <5000>; 2391 trips { 2392 soc_alert: trip-alert { 2393 temperature = <85000>; 2394 hysteresis = <2000>; 2395 type = "passive"; 2396 }; 2397 2398 soc_crit: trip-crit { 2399 temperature = <100000>; 2400 hysteresis = <2000>; 2401 type = "critical"; 2402 }; 2403 }; 2404 }; 2405 2406 tzts2: gpu-thermal { 2407 polling-delay = <1000>; 2408 polling-delay-passive = <250>; 2409 thermal-sensors = <&thermal 2>; 2410 sustainable-power = <5000>; 2411 2412 trips { 2413 gpu_alert: trip-alert { 2414 temperature = <85000>; 2415 hysteresis = <2000>; 2416 type = "passive"; 2417 }; 2418 2419 gpu_crit: trip-crit { 2420 temperature = <100000>; 2421 hysteresis = <2000>; 2422 type = "critical"; 2423 }; 2424 }; 2425 }; 2426 2427 tzts3: md1-thermal { 2428 polling-delay = <1000>; 2429 polling-delay-passive = <250>; 2430 thermal-sensors = <&thermal 3>; 2431 sustainable-power = <5000>; 2432 2433 trips { 2434 md1_alert: trip-alert { 2435 temperature = <85000>; 2436 hysteresis = <2000>; 2437 type = "passive"; 2438 }; 2439 2440 md1_crit: trip-crit { 2441 temperature = <100000>; 2442 hysteresis = <2000>; 2443 type = "critical"; 2444 }; 2445 }; 2446 }; 2447 2448 tzts4: cpu-little-thermal { 2449 polling-delay = <1000>; 2450 polling-delay-passive = <250>; 2451 thermal-sensors = <&thermal 4>; 2452 sustainable-power = <5000>; 2453 2454 trips { 2455 cpul_alert: trip-alert { 2456 temperature = <85000>; 2457 hysteresis = <2000>; 2458 type = "passive"; 2459 }; 2460 2461 cpul_crit: trip-crit { 2462 temperature = <100000>; 2463 hysteresis = <2000>; 2464 type = "critical"; 2465 }; 2466 }; 2467 }; 2468 2469 tzts5: cpu-big-thermal { 2470 polling-delay = <1000>; 2471 polling-delay-passive = <250>; 2472 thermal-sensors = <&thermal 5>; 2473 sustainable-power = <5000>; 2474 2475 trips { 2476 cpub_alert: trip-alert { 2477 temperature = <85000>; 2478 hysteresis = <2000>; 2479 type = "passive"; 2480 }; 2481 2482 cpub_crit: trip-crit { 2483 temperature = <100000>; 2484 hysteresis = <2000>; 2485 type = "critical"; 2486 }; 2487 }; 2488 }; 2489 2490 tztsABB: tsabb-thermal { 2491 polling-delay = <1000>; 2492 polling-delay-passive = <250>; 2493 thermal-sensors = <&thermal 6>; 2494 sustainable-power = <5000>; 2495 2496 trips { 2497 tsabb_alert: trip-alert { 2498 temperature = <85000>; 2499 hysteresis = <2000>; 2500 type = "passive"; 2501 }; 2502 2503 tsabb_crit: trip-crit { 2504 temperature = <100000>; 2505 hysteresis = <2000>; 2506 type = "critical"; 2507 }; 2508 }; 2509 }; 2510 }; 2511};
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