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mt8173.dtsi
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linux-6.19.14/arch/arm64/boot/dts/mediatek/mt8173.dtsi
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014 MediaTek Inc. 4 * Author: Eddie Huang <eddie.huang@mediatek.com> 5 */ 6 7#include <dt-bindings/clock/mt8173-clk.h> 8#include <dt-bindings/interrupt-controller/irq.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/memory/mt8173-larb-port.h> 11#include <dt-bindings/phy/phy.h> 12#include <dt-bindings/power/mt8173-power.h> 13#include <dt-bindings/reset/mt8173-resets.h> 14#include <dt-bindings/gce/mt8173-gce.h> 15#include <dt-bindings/thermal/thermal.h> 16#include "mt8173-pinfunc.h" 17 18/ { 19 compatible = "mediatek,mt8173"; 20 interrupt-parent = <&sysirq>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ovl0 = &ovl0; 26 ovl1 = &ovl1; 27 rdma0 = &rdma0; 28 rdma1 = &rdma1; 29 rdma2 = &rdma2; 30 wdma0 = &wdma0; 31 wdma1 = &wdma1; 32 color0 = &color0; 33 color1 = &color1; 34 split0 = &split0; 35 split1 = &split1; 36 dpi0 = &dpi0; 37 dsi0 = &dsi0; 38 dsi1 = &dsi1; 39 mdp-rdma0 = &mdp_rdma0; 40 mdp-rdma1 = &mdp_rdma1; 41 mdp-rsz0 = &mdp_rsz0; 42 mdp-rsz1 = &mdp_rsz1; 43 mdp-rsz2 = &mdp_rsz2; 44 mdp-wdma0 = &mdp_wdma0; 45 mdp-wrot0 = &mdp_wrot0; 46 mdp-wrot1 = &mdp_wrot1; 47 serial0 = &uart0; 48 serial1 = &uart1; 49 serial2 = &uart2; 50 serial3 = &uart3; 51 }; 52 53 cluster0_opp: opp-table-0 { 54 compatible = "operating-points-v2"; 55 opp-shared; 56 opp-507000000 { 57 opp-hz = /bits/ 64 <507000000>; 58 opp-microvolt = <859000>; 59 }; 60 opp-702000000 { 61 opp-hz = /bits/ 64 <702000000>; 62 opp-microvolt = <908000>; 63 }; 64 opp-1001000000 { 65 opp-hz = /bits/ 64 <1001000000>; 66 opp-microvolt = <983000>; 67 }; 68 opp-1105000000 { 69 opp-hz = /bits/ 64 <1105000000>; 70 opp-microvolt = <1009000>; 71 }; 72 opp-1209000000 { 73 opp-hz = /bits/ 64 <1209000000>; 74 opp-microvolt = <1034000>; 75 }; 76 opp-1300000000 { 77 opp-hz = /bits/ 64 <1300000000>; 78 opp-microvolt = <1057000>; 79 }; 80 opp-1508000000 { 81 opp-hz = /bits/ 64 <1508000000>; 82 opp-microvolt = <1109000>; 83 }; 84 opp-1703000000 { 85 opp-hz = /bits/ 64 <1703000000>; 86 opp-microvolt = <1125000>; 87 }; 88 }; 89 90 cluster1_opp: opp-table-1 { 91 compatible = "operating-points-v2"; 92 opp-shared; 93 opp-507000000 { 94 opp-hz = /bits/ 64 <507000000>; 95 opp-microvolt = <828000>; 96 }; 97 opp-702000000 { 98 opp-hz = /bits/ 64 <702000000>; 99 opp-microvolt = <867000>; 100 }; 101 opp-1001000000 { 102 opp-hz = /bits/ 64 <1001000000>; 103 opp-microvolt = <927000>; 104 }; 105 opp-1209000000 { 106 opp-hz = /bits/ 64 <1209000000>; 107 opp-microvolt = <968000>; 108 }; 109 opp-1404000000 { 110 opp-hz = /bits/ 64 <1404000000>; 111 opp-microvolt = <1007000>; 112 }; 113 opp-1612000000 { 114 opp-hz = /bits/ 64 <1612000000>; 115 opp-microvolt = <1049000>; 116 }; 117 opp-1807000000 { 118 opp-hz = /bits/ 64 <1807000000>; 119 opp-microvolt = <1089000>; 120 }; 121 opp-2106000000 { 122 opp-hz = /bits/ 64 <2106000000>; 123 opp-microvolt = <1125000>; 124 }; 125 }; 126 127 cpus { 128 #address-cells = <1>; 129 #size-cells = <0>; 130 131 cpu-map { 132 cluster0 { 133 core0 { 134 cpu = <&cpu0>; 135 }; 136 core1 { 137 cpu = <&cpu1>; 138 }; 139 }; 140 141 cluster1 { 142 core0 { 143 cpu = <&cpu2>; 144 }; 145 core1 { 146 cpu = <&cpu3>; 147 }; 148 }; 149 }; 150 151 cpu0: cpu@0 { 152 device_type = "cpu"; 153 compatible = "arm,cortex-a53"; 154 reg = <0x000>; 155 enable-method = "psci"; 156 cpu-idle-states = <&CPU_SLEEP_0>; 157 #cooling-cells = <2>; 158 dynamic-power-coefficient = <263>; 159 clocks = <&infracfg CLK_INFRA_CA53SEL>, 160 <&apmixedsys CLK_APMIXED_MAINPLL>; 161 clock-names = "cpu", "intermediate"; 162 operating-points-v2 = <&cluster0_opp>; 163 capacity-dmips-mhz = <740>; 164 }; 165 166 cpu1: cpu@1 { 167 device_type = "cpu"; 168 compatible = "arm,cortex-a53"; 169 reg = <0x001>; 170 enable-method = "psci"; 171 cpu-idle-states = <&CPU_SLEEP_0>; 172 #cooling-cells = <2>; 173 dynamic-power-coefficient = <263>; 174 clocks = <&infracfg CLK_INFRA_CA53SEL>, 175 <&apmixedsys CLK_APMIXED_MAINPLL>; 176 clock-names = "cpu", "intermediate"; 177 operating-points-v2 = <&cluster0_opp>; 178 capacity-dmips-mhz = <740>; 179 }; 180 181 cpu2: cpu@100 { 182 device_type = "cpu"; 183 compatible = "arm,cortex-a72"; 184 reg = <0x100>; 185 enable-method = "psci"; 186 cpu-idle-states = <&CPU_SLEEP_0>; 187 #cooling-cells = <2>; 188 dynamic-power-coefficient = <530>; 189 clocks = <&infracfg CLK_INFRA_CA72SEL>, 190 <&apmixedsys CLK_APMIXED_MAINPLL>; 191 clock-names = "cpu", "intermediate"; 192 operating-points-v2 = <&cluster1_opp>; 193 capacity-dmips-mhz = <1024>; 194 }; 195 196 cpu3: cpu@101 { 197 device_type = "cpu"; 198 compatible = "arm,cortex-a72"; 199 reg = <0x101>; 200 enable-method = "psci"; 201 cpu-idle-states = <&CPU_SLEEP_0>; 202 #cooling-cells = <2>; 203 dynamic-power-coefficient = <530>; 204 clocks = <&infracfg CLK_INFRA_CA72SEL>, 205 <&apmixedsys CLK_APMIXED_MAINPLL>; 206 clock-names = "cpu", "intermediate"; 207 operating-points-v2 = <&cluster1_opp>; 208 capacity-dmips-mhz = <1024>; 209 }; 210 211 idle-states { 212 entry-method = "psci"; 213 214 CPU_SLEEP_0: cpu-sleep-0 { 215 compatible = "arm,idle-state"; 216 local-timer-stop; 217 entry-latency-us = <639>; 218 exit-latency-us = <680>; 219 min-residency-us = <1088>; 220 arm,psci-suspend-param = <0x0010000>; 221 }; 222 }; 223 }; 224 225 pmu-a53 { 226 compatible = "arm,cortex-a53-pmu"; 227 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 228 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 229 interrupt-affinity = <&cpu0>, <&cpu1>; 230 }; 231 232 pmu-a72 { 233 compatible = "arm,cortex-a72-pmu"; 234 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_LOW>, 235 <GIC_SPI 13 IRQ_TYPE_LEVEL_LOW>; 236 interrupt-affinity = <&cpu2>, <&cpu3>; 237 }; 238 239 psci { 240 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci"; 241 method = "smc"; 242 cpu_suspend = <0x84000001>; 243 cpu_off = <0x84000002>; 244 cpu_on = <0x84000003>; 245 }; 246 247 clk26m: oscillator0 { 248 compatible = "fixed-clock"; 249 #clock-cells = <0>; 250 clock-frequency = <26000000>; 251 clock-output-names = "clk26m"; 252 }; 253 254 clk32k: oscillator1 { 255 compatible = "fixed-clock"; 256 #clock-cells = <0>; 257 clock-frequency = <32000>; 258 clock-output-names = "clk32k"; 259 }; 260 261 cpum_ck: oscillator2 { 262 compatible = "fixed-clock"; 263 #clock-cells = <0>; 264 clock-frequency = <0>; 265 clock-output-names = "cpum_ck"; 266 }; 267 268 thermal-zones { 269 cpu_thermal: cpu-thermal { 270 polling-delay-passive = <1000>; /* milliseconds */ 271 polling-delay = <1000>; /* milliseconds */ 272 273 thermal-sensors = <&thermal>; 274 sustainable-power = <1500>; /* milliwatts */ 275 276 trips { 277 threshold: trip-point0 { 278 temperature = <68000>; 279 hysteresis = <2000>; 280 type = "passive"; 281 }; 282 283 target: trip-point1 { 284 temperature = <85000>; 285 hysteresis = <2000>; 286 type = "passive"; 287 }; 288 289 cpu_crit: cpu-crit0 { 290 temperature = <115000>; 291 hysteresis = <2000>; 292 type = "critical"; 293 }; 294 }; 295 296 cooling-maps { 297 map0 { 298 trip = <&target>; 299 cooling-device = <&cpu0 THERMAL_NO_LIMIT 300 THERMAL_NO_LIMIT>, 301 <&cpu1 THERMAL_NO_LIMIT 302 THERMAL_NO_LIMIT>; 303 contribution = <3072>; 304 }; 305 map1 { 306 trip = <&target>; 307 cooling-device = <&cpu2 THERMAL_NO_LIMIT 308 THERMAL_NO_LIMIT>, 309 <&cpu3 THERMAL_NO_LIMIT 310 THERMAL_NO_LIMIT>; 311 contribution = <1024>; 312 }; 313 }; 314 }; 315 }; 316 317 reserved-memory { 318 #address-cells = <2>; 319 #size-cells = <2>; 320 ranges; 321 322 afe_dma_mem: audio-dma-pool { 323 compatible = "shared-dma-pool"; 324 size = <0 0x100000>; 325 alignment = <0 0x10>; 326 no-map; 327 }; 328 329 vpu_dma_reserved: vpu-dma-mem@b7000000 { 330 compatible = "shared-dma-pool"; 331 reg = <0 0xb7000000 0 0x500000>; 332 alignment = <0x1000>; 333 no-map; 334 }; 335 }; 336 337 timer { 338 compatible = "arm,armv8-timer"; 339 interrupt-parent = <&gic>; 340 interrupts = <GIC_PPI 13 341 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 342 <GIC_PPI 14 343 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 344 <GIC_PPI 11 345 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 346 <GIC_PPI 10 347 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 348 arm,no-tick-in-suspend; 349 }; 350 351 soc { 352 #address-cells = <2>; 353 #size-cells = <2>; 354 compatible = "simple-bus"; 355 ranges; 356 357 topckgen: clock-controller@10000000 { 358 compatible = "mediatek,mt8173-topckgen"; 359 reg = <0 0x10000000 0 0x1000>; 360 #clock-cells = <1>; 361 }; 362 363 infracfg: clock-controller@10001000 { 364 compatible = "mediatek,mt8173-infracfg", "syscon"; 365 reg = <0 0x10001000 0 0x1000>; 366 #clock-cells = <1>; 367 #reset-cells = <1>; 368 }; 369 370 pericfg: clock-controller@10003000 { 371 compatible = "mediatek,mt8173-pericfg", "syscon"; 372 reg = <0 0x10003000 0 0x1000>; 373 #clock-cells = <1>; 374 #reset-cells = <1>; 375 }; 376 377 syscfg_pctl_a: syscon@10005000 { 378 compatible = "mediatek,mt8173-pctl-a-syscfg", "syscon"; 379 reg = <0 0x10005000 0 0x1000>; 380 }; 381 382 pio: pinctrl@1000b000 { 383 compatible = "mediatek,mt8173-pinctrl"; 384 reg = <0 0x1000b000 0 0x1000>; 385 mediatek,pctl-regmap = <&syscfg_pctl_a>; 386 gpio-controller; 387 #gpio-cells = <2>; 388 interrupt-controller; 389 #interrupt-cells = <2>; 390 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 391 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 392 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 393 394 hdmi_pin: xxx { 395 396 /*hdmi htplg pin*/ 397 pins1 { 398 pinmux = <MT8173_PIN_21_HTPLG__FUNC_HTPLG>; 399 input-enable; 400 bias-pull-down; 401 }; 402 }; 403 404 i2c0_pins_a: i2c0 { 405 pins1 { 406 pinmux = <MT8173_PIN_45_SDA0__FUNC_SDA0>, 407 <MT8173_PIN_46_SCL0__FUNC_SCL0>; 408 bias-disable; 409 }; 410 }; 411 412 i2c1_pins_a: i2c1 { 413 pins1 { 414 pinmux = <MT8173_PIN_125_SDA1__FUNC_SDA1>, 415 <MT8173_PIN_126_SCL1__FUNC_SCL1>; 416 bias-disable; 417 }; 418 }; 419 420 i2c2_pins_a: i2c2 { 421 pins1 { 422 pinmux = <MT8173_PIN_43_SDA2__FUNC_SDA2>, 423 <MT8173_PIN_44_SCL2__FUNC_SCL2>; 424 bias-disable; 425 }; 426 }; 427 428 i2c3_pins_a: i2c3 { 429 pins1 { 430 pinmux = <MT8173_PIN_106_SDA3__FUNC_SDA3>, 431 <MT8173_PIN_107_SCL3__FUNC_SCL3>; 432 bias-disable; 433 }; 434 }; 435 436 i2c4_pins_a: i2c4 { 437 pins1 { 438 pinmux = <MT8173_PIN_133_SDA4__FUNC_SDA4>, 439 <MT8173_PIN_134_SCL4__FUNC_SCL4>; 440 bias-disable; 441 }; 442 }; 443 444 i2c6_pins_a: i2c6 { 445 pins1 { 446 pinmux = <MT8173_PIN_100_MSDC2_DAT0__FUNC_SDA5>, 447 <MT8173_PIN_101_MSDC2_DAT1__FUNC_SCL5>; 448 bias-disable; 449 }; 450 }; 451 }; 452 453 scpsys: syscon@10006000 { 454 compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd"; 455 reg = <0 0x10006000 0 0x1000>; 456 457 /* System Power Manager */ 458 spm: power-controller { 459 compatible = "mediatek,mt8173-power-controller"; 460 #address-cells = <1>; 461 #size-cells = <0>; 462 #power-domain-cells = <1>; 463 464 /* power domains of the SoC */ 465 power-domain@MT8173_POWER_DOMAIN_VDEC { 466 reg = <MT8173_POWER_DOMAIN_VDEC>; 467 clocks = <&topckgen CLK_TOP_MM_SEL>; 468 clock-names = "mm"; 469 #power-domain-cells = <0>; 470 }; 471 power-domain@MT8173_POWER_DOMAIN_VENC { 472 reg = <MT8173_POWER_DOMAIN_VENC>; 473 clocks = <&topckgen CLK_TOP_MM_SEL>, 474 <&topckgen CLK_TOP_VENC_SEL>; 475 clock-names = "mm", "venc"; 476 #power-domain-cells = <0>; 477 }; 478 power-domain@MT8173_POWER_DOMAIN_ISP { 479 reg = <MT8173_POWER_DOMAIN_ISP>; 480 clocks = <&topckgen CLK_TOP_MM_SEL>; 481 clock-names = "mm"; 482 #power-domain-cells = <0>; 483 }; 484 power-domain@MT8173_POWER_DOMAIN_MM { 485 reg = <MT8173_POWER_DOMAIN_MM>; 486 clocks = <&topckgen CLK_TOP_MM_SEL>; 487 clock-names = "mm"; 488 #power-domain-cells = <0>; 489 mediatek,infracfg = <&infracfg>; 490 }; 491 power-domain@MT8173_POWER_DOMAIN_VENC_LT { 492 reg = <MT8173_POWER_DOMAIN_VENC_LT>; 493 clocks = <&topckgen CLK_TOP_MM_SEL>, 494 <&topckgen CLK_TOP_VENC_LT_SEL>; 495 clock-names = "mm", "venclt"; 496 #power-domain-cells = <0>; 497 }; 498 power-domain@MT8173_POWER_DOMAIN_AUDIO { 499 reg = <MT8173_POWER_DOMAIN_AUDIO>; 500 #power-domain-cells = <0>; 501 }; 502 power-domain@MT8173_POWER_DOMAIN_USB { 503 reg = <MT8173_POWER_DOMAIN_USB>; 504 #power-domain-cells = <0>; 505 }; 506 mfg_async: power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC { 507 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>; 508 clocks = <&clk26m>; 509 clock-names = "mfg"; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 #power-domain-cells = <1>; 513 514 power-domain@MT8173_POWER_DOMAIN_MFG_2D { 515 reg = <MT8173_POWER_DOMAIN_MFG_2D>; 516 #address-cells = <1>; 517 #size-cells = <0>; 518 #power-domain-cells = <1>; 519 520 power-domain@MT8173_POWER_DOMAIN_MFG { 521 reg = <MT8173_POWER_DOMAIN_MFG>; 522 #power-domain-cells = <0>; 523 mediatek,infracfg = <&infracfg>; 524 }; 525 }; 526 }; 527 }; 528 }; 529 530 watchdog: watchdog@10007000 { 531 compatible = "mediatek,mt8173-wdt", 532 "mediatek,mt6589-wdt"; 533 reg = <0 0x10007000 0 0x100>; 534 }; 535 536 timer: timer@10008000 { 537 compatible = "mediatek,mt8173-timer", 538 "mediatek,mt6577-timer"; 539 reg = <0 0x10008000 0 0x1000>; 540 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>; 541 clocks = <&infracfg CLK_INFRA_CLK_13M>, 542 <&topckgen CLK_TOP_RTC_SEL>; 543 }; 544 545 pwrap: pwrap@1000d000 { 546 compatible = "mediatek,mt8173-pwrap"; 547 reg = <0 0x1000d000 0 0x1000>; 548 reg-names = "pwrap"; 549 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 550 resets = <&infracfg MT8173_INFRA_PMIC_WRAP_RST>; 551 reset-names = "pwrap"; 552 clocks = <&infracfg CLK_INFRA_PMICSPI>, <&infracfg CLK_INFRA_PMICWRAP>; 553 clock-names = "spi", "wrap"; 554 }; 555 556 cec: cec@10013000 { 557 compatible = "mediatek,mt8173-cec"; 558 reg = <0 0x10013000 0 0xbc>; 559 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>; 560 clocks = <&infracfg CLK_INFRA_CEC>; 561 status = "disabled"; 562 }; 563 564 vpu: vpu@10020000 { 565 compatible = "mediatek,mt8173-vpu"; 566 reg = <0 0x10020000 0 0x30000>, 567 <0 0x10050000 0 0x100>; 568 reg-names = "tcm", "cfg_reg"; 569 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 570 clocks = <&topckgen CLK_TOP_SCP_SEL>; 571 clock-names = "main"; 572 memory-region = <&vpu_dma_reserved>; 573 }; 574 575 sysirq: interrupt-controller@10200620 { 576 compatible = "mediatek,mt8173-sysirq", 577 "mediatek,mt6577-sysirq"; 578 interrupt-controller; 579 #interrupt-cells = <3>; 580 interrupt-parent = <&gic>; 581 reg = <0 0x10200620 0 0x20>; 582 }; 583 584 iommu: iommu@10205000 { 585 compatible = "mediatek,mt8173-m4u"; 586 reg = <0 0x10205000 0 0x1000>; 587 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_LOW>; 588 clocks = <&infracfg CLK_INFRA_M4U>; 589 clock-names = "bclk"; 590 mediatek,infracfg = <&infracfg>; 591 mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 592 <&larb3>, <&larb4>, <&larb5>; 593 #iommu-cells = <1>; 594 }; 595 596 efuse: efuse@10206000 { 597 compatible = "mediatek,mt8173-efuse"; 598 reg = <0 0x10206000 0 0x1000>; 599 #address-cells = <1>; 600 #size-cells = <1>; 601 602 socinfo-data1@40 { 603 reg = <0x040 0x4>; 604 }; 605 606 socinfo-data2@44 { 607 reg = <0x044 0x4>; 608 }; 609 610 thermal_calibration: calib@528 { 611 reg = <0x528 0xc>; 612 }; 613 }; 614 615 apmixedsys: clock-controller@10209000 { 616 compatible = "mediatek,mt8173-apmixedsys"; 617 reg = <0 0x10209000 0 0x1000>; 618 #clock-cells = <1>; 619 }; 620 621 hdmi_phy: hdmi-phy@10209100 { 622 compatible = "mediatek,mt8173-hdmi-phy"; 623 reg = <0 0x10209100 0 0x24>; 624 clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>; 625 clock-names = "pll_ref"; 626 clock-output-names = "hdmitx_dig_cts"; 627 mediatek,ibias = <0xa>; 628 mediatek,ibias_up = <0x1c>; 629 #clock-cells = <0>; 630 #phy-cells = <0>; 631 status = "disabled"; 632 }; 633 634 gce: mailbox@10212000 { 635 compatible = "mediatek,mt8173-gce"; 636 reg = <0 0x10212000 0 0x1000>; 637 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_LOW>; 638 clocks = <&infracfg CLK_INFRA_GCE>; 639 clock-names = "gce"; 640 #mbox-cells = <2>; 641 }; 642 643 mipi_tx0: dsi-phy@10215000 { 644 compatible = "mediatek,mt8173-mipi-tx"; 645 reg = <0 0x10215000 0 0x1000>; 646 clocks = <&clk26m>; 647 clock-output-names = "mipi_tx0_pll"; 648 #clock-cells = <0>; 649 #phy-cells = <0>; 650 status = "disabled"; 651 }; 652 653 mipi_tx1: dsi-phy@10216000 { 654 compatible = "mediatek,mt8173-mipi-tx"; 655 reg = <0 0x10216000 0 0x1000>; 656 clocks = <&clk26m>; 657 clock-output-names = "mipi_tx1_pll"; 658 #clock-cells = <0>; 659 #phy-cells = <0>; 660 status = "disabled"; 661 }; 662 663 gic: interrupt-controller@10221000 { 664 compatible = "arm,gic-400"; 665 #interrupt-cells = <3>; 666 interrupt-parent = <&gic>; 667 interrupt-controller; 668 reg = <0 0x10221000 0 0x1000>, 669 <0 0x10222000 0 0x2000>, 670 <0 0x10224000 0 0x2000>, 671 <0 0x10226000 0 0x2000>; 672 interrupts = <GIC_PPI 9 673 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 674 }; 675 676 auxadc: auxadc@11001000 { 677 compatible = "mediatek,mt8173-auxadc"; 678 reg = <0 0x11001000 0 0x1000>; 679 clocks = <&pericfg CLK_PERI_AUXADC>; 680 clock-names = "main"; 681 #io-channel-cells = <1>; 682 }; 683 684 uart0: serial@11002000 { 685 compatible = "mediatek,mt8173-uart", 686 "mediatek,mt6577-uart"; 687 reg = <0 0x11002000 0 0x400>; 688 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 689 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 690 clock-names = "baud", "bus"; 691 status = "disabled"; 692 }; 693 694 uart1: serial@11003000 { 695 compatible = "mediatek,mt8173-uart", 696 "mediatek,mt6577-uart"; 697 reg = <0 0x11003000 0 0x400>; 698 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 699 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 700 clock-names = "baud", "bus"; 701 status = "disabled"; 702 }; 703 704 uart2: serial@11004000 { 705 compatible = "mediatek,mt8173-uart", 706 "mediatek,mt6577-uart"; 707 reg = <0 0x11004000 0 0x400>; 708 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 709 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 710 clock-names = "baud", "bus"; 711 status = "disabled"; 712 }; 713 714 uart3: serial@11005000 { 715 compatible = "mediatek,mt8173-uart", 716 "mediatek,mt6577-uart"; 717 reg = <0 0x11005000 0 0x400>; 718 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 719 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 720 clock-names = "baud", "bus"; 721 status = "disabled"; 722 }; 723 724 i2c0: i2c@11007000 { 725 compatible = "mediatek,mt8173-i2c"; 726 reg = <0 0x11007000 0 0x70>, 727 <0 0x11000100 0 0x80>; 728 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>; 729 clock-div = <16>; 730 clocks = <&pericfg CLK_PERI_I2C0>, 731 <&pericfg CLK_PERI_AP_DMA>; 732 clock-names = "main", "dma"; 733 pinctrl-names = "default"; 734 pinctrl-0 = <&i2c0_pins_a>; 735 #address-cells = <1>; 736 #size-cells = <0>; 737 status = "disabled"; 738 }; 739 740 i2c1: i2c@11008000 { 741 compatible = "mediatek,mt8173-i2c"; 742 reg = <0 0x11008000 0 0x70>, 743 <0 0x11000180 0 0x80>; 744 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 745 clock-div = <16>; 746 clocks = <&pericfg CLK_PERI_I2C1>, 747 <&pericfg CLK_PERI_AP_DMA>; 748 clock-names = "main", "dma"; 749 pinctrl-names = "default"; 750 pinctrl-0 = <&i2c1_pins_a>; 751 #address-cells = <1>; 752 #size-cells = <0>; 753 status = "disabled"; 754 }; 755 756 i2c2: i2c@11009000 { 757 compatible = "mediatek,mt8173-i2c"; 758 reg = <0 0x11009000 0 0x70>, 759 <0 0x11000200 0 0x80>; 760 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>; 761 clock-div = <16>; 762 clocks = <&pericfg CLK_PERI_I2C2>, 763 <&pericfg CLK_PERI_AP_DMA>; 764 clock-names = "main", "dma"; 765 pinctrl-names = "default"; 766 pinctrl-0 = <&i2c2_pins_a>; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 status = "disabled"; 770 }; 771 772 spi: spi@1100a000 { 773 compatible = "mediatek,mt8173-spi"; 774 #address-cells = <1>; 775 #size-cells = <0>; 776 reg = <0 0x1100a000 0 0x1000>; 777 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 778 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 779 <&topckgen CLK_TOP_SPI_SEL>, 780 <&pericfg CLK_PERI_SPI0>; 781 clock-names = "parent-clk", "sel-clk", "spi-clk"; 782 status = "disabled"; 783 }; 784 785 thermal: thermal@1100b000 { 786 #thermal-sensor-cells = <0>; 787 compatible = "mediatek,mt8173-thermal"; 788 reg = <0 0x1100b000 0 0x1000>; 789 interrupts = <0 70 IRQ_TYPE_LEVEL_LOW>; 790 clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>; 791 clock-names = "therm", "auxadc"; 792 resets = <&pericfg MT8173_PERI_THERM_SW_RST>; 793 mediatek,auxadc = <&auxadc>; 794 mediatek,apmixedsys = <&apmixedsys>; 795 nvmem-cells = <&thermal_calibration>; 796 nvmem-cell-names = "calibration-data"; 797 }; 798 799 nor_flash: spi@1100d000 { 800 compatible = "mediatek,mt8173-nor"; 801 reg = <0 0x1100d000 0 0xe0>; 802 assigned-clocks = <&topckgen CLK_TOP_SPI_SEL>; 803 assigned-clock-parents = <&clk26m>; 804 clocks = <&pericfg CLK_PERI_SPI>, 805 <&topckgen CLK_TOP_SPINFI_IFR_SEL>, 806 <&pericfg CLK_PERI_NFI>; 807 clock-names = "spi", "sf", "axi"; 808 #address-cells = <1>; 809 #size-cells = <0>; 810 status = "disabled"; 811 }; 812 813 i2c3: i2c@11010000 { 814 compatible = "mediatek,mt8173-i2c"; 815 reg = <0 0x11010000 0 0x70>, 816 <0 0x11000280 0 0x80>; 817 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 818 clock-div = <16>; 819 clocks = <&pericfg CLK_PERI_I2C3>, 820 <&pericfg CLK_PERI_AP_DMA>; 821 clock-names = "main", "dma"; 822 pinctrl-names = "default"; 823 pinctrl-0 = <&i2c3_pins_a>; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 status = "disabled"; 827 }; 828 829 i2c4: i2c@11011000 { 830 compatible = "mediatek,mt8173-i2c"; 831 reg = <0 0x11011000 0 0x70>, 832 <0 0x11000300 0 0x80>; 833 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 834 clock-div = <16>; 835 clocks = <&pericfg CLK_PERI_I2C4>, 836 <&pericfg CLK_PERI_AP_DMA>; 837 clock-names = "main", "dma"; 838 pinctrl-names = "default"; 839 pinctrl-0 = <&i2c4_pins_a>; 840 #address-cells = <1>; 841 #size-cells = <0>; 842 status = "disabled"; 843 }; 844 845 hdmiddc0: i2c@11012000 { 846 compatible = "mediatek,mt8173-hdmi-ddc"; 847 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 848 reg = <0 0x11012000 0 0x1C>; 849 clocks = <&pericfg CLK_PERI_I2C5>; 850 clock-names = "ddc-i2c"; 851 }; 852 853 i2c6: i2c@11013000 { 854 compatible = "mediatek,mt8173-i2c"; 855 reg = <0 0x11013000 0 0x70>, 856 <0 0x11000080 0 0x80>; 857 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 858 clock-div = <16>; 859 clocks = <&pericfg CLK_PERI_I2C6>, 860 <&pericfg CLK_PERI_AP_DMA>; 861 clock-names = "main", "dma"; 862 pinctrl-names = "default"; 863 pinctrl-0 = <&i2c6_pins_a>; 864 #address-cells = <1>; 865 #size-cells = <0>; 866 status = "disabled"; 867 }; 868 869 afe: audio-controller@11220000 { 870 compatible = "mediatek,mt8173-afe-pcm"; 871 reg = <0 0x11220000 0 0x1000>; 872 interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_FALLING>; 873 power-domains = <&spm MT8173_POWER_DOMAIN_AUDIO>; 874 clocks = <&infracfg CLK_INFRA_AUDIO>, 875 <&topckgen CLK_TOP_AUDIO_SEL>, 876 <&topckgen CLK_TOP_AUD_INTBUS_SEL>, 877 <&topckgen CLK_TOP_APLL1_DIV0>, 878 <&topckgen CLK_TOP_APLL2_DIV0>, 879 <&topckgen CLK_TOP_I2S0_M_SEL>, 880 <&topckgen CLK_TOP_I2S1_M_SEL>, 881 <&topckgen CLK_TOP_I2S2_M_SEL>, 882 <&topckgen CLK_TOP_I2S3_M_SEL>, 883 <&topckgen CLK_TOP_I2S3_B_SEL>; 884 clock-names = "infra_sys_audio_clk", 885 "top_pdn_audio", 886 "top_pdn_aud_intbus", 887 "bck0", 888 "bck1", 889 "i2s0_m", 890 "i2s1_m", 891 "i2s2_m", 892 "i2s3_m", 893 "i2s3_b"; 894 assigned-clocks = <&topckgen CLK_TOP_AUD_1_SEL>, 895 <&topckgen CLK_TOP_AUD_2_SEL>; 896 assigned-clock-parents = <&topckgen CLK_TOP_APLL1>, 897 <&topckgen CLK_TOP_APLL2>; 898 memory-region = <&afe_dma_mem>; 899 }; 900 901 mmc0: mmc@11230000 { 902 compatible = "mediatek,mt8173-mmc"; 903 reg = <0 0x11230000 0 0x1000>; 904 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_LOW>; 905 clocks = <&pericfg CLK_PERI_MSDC30_0>, 906 <&topckgen CLK_TOP_MSDC50_0_H_SEL>; 907 clock-names = "source", "hclk"; 908 status = "disabled"; 909 }; 910 911 mmc1: mmc@11240000 { 912 compatible = "mediatek,mt8173-mmc"; 913 reg = <0 0x11240000 0 0x1000>; 914 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_LOW>; 915 clocks = <&pericfg CLK_PERI_MSDC30_1>, 916 <&topckgen CLK_TOP_AXI_SEL>; 917 clock-names = "source", "hclk"; 918 status = "disabled"; 919 }; 920 921 mmc2: mmc@11250000 { 922 compatible = "mediatek,mt8173-mmc"; 923 reg = <0 0x11250000 0 0x1000>; 924 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_LOW>; 925 clocks = <&pericfg CLK_PERI_MSDC30_2>, 926 <&topckgen CLK_TOP_AXI_SEL>; 927 clock-names = "source", "hclk"; 928 status = "disabled"; 929 }; 930 931 mmc3: mmc@11260000 { 932 compatible = "mediatek,mt8173-mmc"; 933 reg = <0 0x11260000 0 0x1000>; 934 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_LOW>; 935 clocks = <&pericfg CLK_PERI_MSDC30_3>, 936 <&topckgen CLK_TOP_MSDC50_2_H_SEL>; 937 clock-names = "source", "hclk"; 938 status = "disabled"; 939 }; 940 941 ssusb: usb@11271000 { 942 compatible = "mediatek,mt8173-mtu3", "mediatek,mtu3"; 943 reg = <0 0x11271000 0 0x3000>, 944 <0 0x11280700 0 0x0100>; 945 reg-names = "mac", "ippc"; 946 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_LOW>; 947 phys = <&u2port0 PHY_TYPE_USB2>, 948 <&u3port0 PHY_TYPE_USB3>, 949 <&u2port1 PHY_TYPE_USB2>; 950 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 951 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 952 clock-names = "sys_ck", "ref_ck"; 953 mediatek,syscon-wakeup = <&pericfg 0x400 1>; 954 #address-cells = <2>; 955 #size-cells = <2>; 956 ranges; 957 status = "disabled"; 958 959 usb_host: usb@11270000 { 960 compatible = "mediatek,mt8173-xhci", 961 "mediatek,mtk-xhci"; 962 reg = <0 0x11270000 0 0x1000>; 963 reg-names = "mac"; 964 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 965 power-domains = <&spm MT8173_POWER_DOMAIN_USB>; 966 clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 967 clock-names = "sys_ck", "ref_ck"; 968 status = "disabled"; 969 }; 970 }; 971 972 u3phy: t-phy@11290000 { 973 compatible = "mediatek,mt8173-u3phy"; 974 reg = <0 0x11290000 0 0x800>; 975 #address-cells = <2>; 976 #size-cells = <2>; 977 ranges; 978 status = "okay"; 979 980 u2port0: usb-phy@11290800 { 981 reg = <0 0x11290800 0 0x100>; 982 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 983 clock-names = "ref"; 984 #phy-cells = <1>; 985 status = "okay"; 986 }; 987 988 u3port0: usb-phy@11290900 { 989 reg = <0 0x11290900 0 0x700>; 990 clocks = <&clk26m>; 991 clock-names = "ref"; 992 #phy-cells = <1>; 993 status = "okay"; 994 }; 995 996 u2port1: usb-phy@11291000 { 997 reg = <0 0x11291000 0 0x100>; 998 clocks = <&apmixedsys CLK_APMIXED_REF2USB_TX>; 999 clock-names = "ref"; 1000 #phy-cells = <1>; 1001 status = "okay"; 1002 }; 1003 }; 1004 1005 mmsys: syscon@14000000 { 1006 compatible = "mediatek,mt8173-mmsys", "syscon"; 1007 reg = <0 0x14000000 0 0x1000>; 1008 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1009 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 1010 assigned-clock-rates = <400000000>; 1011 #clock-cells = <1>; 1012 #reset-cells = <1>; 1013 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 1014 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 1015 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 1016 }; 1017 1018 mdp_rdma0: rdma@14001000 { 1019 compatible = "mediatek,mt8173-mdp-rdma", 1020 "mediatek,mt8173-mdp"; 1021 reg = <0 0x14001000 0 0x1000>; 1022 clocks = <&mmsys CLK_MM_MDP_RDMA0>, 1023 <&mmsys CLK_MM_MUTEX_32K>; 1024 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1025 iommus = <&iommu M4U_PORT_MDP_RDMA0>; 1026 mediatek,vpu = <&vpu>; 1027 }; 1028 1029 mdp_rdma1: rdma@14002000 { 1030 compatible = "mediatek,mt8173-mdp-rdma"; 1031 reg = <0 0x14002000 0 0x1000>; 1032 clocks = <&mmsys CLK_MM_MDP_RDMA1>, 1033 <&mmsys CLK_MM_MUTEX_32K>; 1034 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1035 iommus = <&iommu M4U_PORT_MDP_RDMA1>; 1036 }; 1037 1038 mdp_rsz0: rsz@14003000 { 1039 compatible = "mediatek,mt8173-mdp-rsz"; 1040 reg = <0 0x14003000 0 0x1000>; 1041 clocks = <&mmsys CLK_MM_MDP_RSZ0>; 1042 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1043 }; 1044 1045 mdp_rsz1: rsz@14004000 { 1046 compatible = "mediatek,mt8173-mdp-rsz"; 1047 reg = <0 0x14004000 0 0x1000>; 1048 clocks = <&mmsys CLK_MM_MDP_RSZ1>; 1049 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1050 }; 1051 1052 mdp_rsz2: rsz@14005000 { 1053 compatible = "mediatek,mt8173-mdp-rsz"; 1054 reg = <0 0x14005000 0 0x1000>; 1055 clocks = <&mmsys CLK_MM_MDP_RSZ2>; 1056 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1057 }; 1058 1059 mdp_wdma0: wdma@14006000 { 1060 compatible = "mediatek,mt8173-mdp-wdma"; 1061 reg = <0 0x14006000 0 0x1000>; 1062 clocks = <&mmsys CLK_MM_MDP_WDMA>; 1063 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1064 iommus = <&iommu M4U_PORT_MDP_WDMA>; 1065 }; 1066 1067 mdp_wrot0: wrot@14007000 { 1068 compatible = "mediatek,mt8173-mdp-wrot"; 1069 reg = <0 0x14007000 0 0x1000>; 1070 clocks = <&mmsys CLK_MM_MDP_WROT0>; 1071 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1072 iommus = <&iommu M4U_PORT_MDP_WROT0>; 1073 }; 1074 1075 mdp_wrot1: wrot@14008000 { 1076 compatible = "mediatek,mt8173-mdp-wrot"; 1077 reg = <0 0x14008000 0 0x1000>; 1078 clocks = <&mmsys CLK_MM_MDP_WROT1>; 1079 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1080 iommus = <&iommu M4U_PORT_MDP_WROT1>; 1081 }; 1082 1083 ovl0: ovl@1400c000 { 1084 compatible = "mediatek,mt8173-disp-ovl"; 1085 reg = <0 0x1400c000 0 0x1000>; 1086 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>; 1087 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1088 clocks = <&mmsys CLK_MM_DISP_OVL0>; 1089 iommus = <&iommu M4U_PORT_DISP_OVL0>; 1090 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 1091 }; 1092 1093 ovl1: ovl@1400d000 { 1094 compatible = "mediatek,mt8173-disp-ovl"; 1095 reg = <0 0x1400d000 0 0x1000>; 1096 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>; 1097 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1098 clocks = <&mmsys CLK_MM_DISP_OVL1>; 1099 iommus = <&iommu M4U_PORT_DISP_OVL1>; 1100 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 1101 }; 1102 1103 rdma0: rdma@1400e000 { 1104 compatible = "mediatek,mt8173-disp-rdma"; 1105 reg = <0 0x1400e000 0 0x1000>; 1106 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>; 1107 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1108 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 1109 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 1110 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 1111 }; 1112 1113 rdma1: rdma@1400f000 { 1114 compatible = "mediatek,mt8173-disp-rdma"; 1115 reg = <0 0x1400f000 0 0x1000>; 1116 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>; 1117 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1118 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 1119 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 1120 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 1121 }; 1122 1123 rdma2: rdma@14010000 { 1124 compatible = "mediatek,mt8173-disp-rdma"; 1125 reg = <0 0x14010000 0 0x1000>; 1126 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>; 1127 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1128 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 1129 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 1130 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 1131 }; 1132 1133 wdma0: wdma@14011000 { 1134 compatible = "mediatek,mt8173-disp-wdma"; 1135 reg = <0 0x14011000 0 0x1000>; 1136 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>; 1137 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1138 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 1139 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 1140 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 1141 }; 1142 1143 wdma1: wdma@14012000 { 1144 compatible = "mediatek,mt8173-disp-wdma"; 1145 reg = <0 0x14012000 0 0x1000>; 1146 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>; 1147 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1148 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 1149 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 1150 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 1151 }; 1152 1153 color0: color@14013000 { 1154 compatible = "mediatek,mt8173-disp-color"; 1155 reg = <0 0x14013000 0 0x1000>; 1156 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>; 1157 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1158 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 1159 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 1160 }; 1161 1162 color1: color@14014000 { 1163 compatible = "mediatek,mt8173-disp-color"; 1164 reg = <0 0x14014000 0 0x1000>; 1165 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 1166 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1167 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 1168 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 1169 }; 1170 1171 aal@14015000 { 1172 compatible = "mediatek,mt8173-disp-aal"; 1173 reg = <0 0x14015000 0 0x1000>; 1174 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 1175 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1176 clocks = <&mmsys CLK_MM_DISP_AAL>; 1177 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 1178 }; 1179 1180 gamma@14016000 { 1181 compatible = "mediatek,mt8173-disp-gamma"; 1182 reg = <0 0x14016000 0 0x1000>; 1183 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 1184 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1185 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 1186 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 1187 }; 1188 1189 merge@14017000 { 1190 compatible = "mediatek,mt8173-disp-merge"; 1191 reg = <0 0x14017000 0 0x1000>; 1192 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1193 clocks = <&mmsys CLK_MM_DISP_MERGE>; 1194 }; 1195 1196 split0: split@14018000 { 1197 compatible = "mediatek,mt8173-disp-split"; 1198 reg = <0 0x14018000 0 0x1000>; 1199 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1200 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 1201 }; 1202 1203 split1: split@14019000 { 1204 compatible = "mediatek,mt8173-disp-split"; 1205 reg = <0 0x14019000 0 0x1000>; 1206 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1207 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 1208 }; 1209 1210 ufoe@1401a000 { 1211 compatible = "mediatek,mt8173-disp-ufoe"; 1212 reg = <0 0x1401a000 0 0x1000>; 1213 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 1214 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1215 clocks = <&mmsys CLK_MM_DISP_UFOE>; 1216 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; 1217 }; 1218 1219 dsi0: dsi@1401b000 { 1220 compatible = "mediatek,mt8173-dsi"; 1221 reg = <0 0x1401b000 0 0x1000>; 1222 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 1223 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1224 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 1225 <&mmsys CLK_MM_DSI0_DIGITAL>, 1226 <&mipi_tx0>; 1227 clock-names = "engine", "digital", "hs"; 1228 resets = <&mmsys MT8173_MMSYS_SW0_RST_B_DISP_DSI0>; 1229 phys = <&mipi_tx0>; 1230 phy-names = "dphy"; 1231 status = "disabled"; 1232 }; 1233 1234 dsi1: dsi@1401c000 { 1235 compatible = "mediatek,mt8173-dsi"; 1236 reg = <0 0x1401c000 0 0x1000>; 1237 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 1238 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1239 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 1240 <&mmsys CLK_MM_DSI1_DIGITAL>, 1241 <&mipi_tx1>; 1242 clock-names = "engine", "digital", "hs"; 1243 phys = <&mipi_tx1>; 1244 phy-names = "dphy"; 1245 status = "disabled"; 1246 }; 1247 1248 dpi0: dpi@1401d000 { 1249 compatible = "mediatek,mt8173-dpi"; 1250 reg = <0 0x1401d000 0 0x1000>; 1251 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 1252 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1253 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 1254 <&mmsys CLK_MM_DPI_ENGINE>, 1255 <&apmixedsys CLK_APMIXED_TVDPLL>; 1256 clock-names = "pixel", "engine", "pll"; 1257 status = "disabled"; 1258 1259 port { 1260 dpi0_out: endpoint { 1261 remote-endpoint = <&hdmi0_in>; 1262 }; 1263 }; 1264 }; 1265 1266 pwm0: pwm@1401e000 { 1267 compatible = "mediatek,mt8173-disp-pwm"; 1268 reg = <0 0x1401e000 0 0x1000>; 1269 #pwm-cells = <2>; 1270 clocks = <&mmsys CLK_MM_DISP_PWM026M>, 1271 <&mmsys CLK_MM_DISP_PWM0MM>; 1272 clock-names = "main", "mm"; 1273 status = "disabled"; 1274 }; 1275 1276 pwm1: pwm@1401f000 { 1277 compatible = "mediatek,mt8173-disp-pwm"; 1278 reg = <0 0x1401f000 0 0x1000>; 1279 #pwm-cells = <2>; 1280 clocks = <&mmsys CLK_MM_DISP_PWM126M>, 1281 <&mmsys CLK_MM_DISP_PWM1MM>; 1282 clock-names = "main", "mm"; 1283 status = "disabled"; 1284 }; 1285 1286 mutex: mutex@14020000 { 1287 compatible = "mediatek,mt8173-disp-mutex"; 1288 reg = <0 0x14020000 0 0x1000>; 1289 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>; 1290 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1291 clocks = <&mmsys CLK_MM_MUTEX_32K>; 1292 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; 1293 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 1294 <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 1295 }; 1296 1297 larb0: larb@14021000 { 1298 compatible = "mediatek,mt8173-smi-larb"; 1299 reg = <0 0x14021000 0 0x1000>; 1300 mediatek,smi = <&smi_common>; 1301 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1302 clocks = <&mmsys CLK_MM_SMI_LARB0>, 1303 <&mmsys CLK_MM_SMI_LARB0>; 1304 clock-names = "apb", "smi"; 1305 }; 1306 1307 smi_common: smi@14022000 { 1308 compatible = "mediatek,mt8173-smi-common"; 1309 reg = <0 0x14022000 0 0x1000>; 1310 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1311 clocks = <&mmsys CLK_MM_SMI_COMMON>, 1312 <&mmsys CLK_MM_SMI_COMMON>; 1313 clock-names = "apb", "smi"; 1314 }; 1315 1316 od@14023000 { 1317 compatible = "mediatek,mt8173-disp-od"; 1318 reg = <0 0x14023000 0 0x1000>; 1319 clocks = <&mmsys CLK_MM_DISP_OD>; 1320 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; 1321 }; 1322 1323 hdmi0: hdmi@14025000 { 1324 compatible = "mediatek,mt8173-hdmi"; 1325 reg = <0 0x14025000 0 0x400>; 1326 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>; 1327 clocks = <&mmsys CLK_MM_HDMI_PIXEL>, 1328 <&mmsys CLK_MM_HDMI_PLLCK>, 1329 <&mmsys CLK_MM_HDMI_AUDIO>, 1330 <&mmsys CLK_MM_HDMI_SPDIF>; 1331 clock-names = "pixel", "pll", "bclk", "spdif"; 1332 pinctrl-names = "default"; 1333 pinctrl-0 = <&hdmi_pin>; 1334 phys = <&hdmi_phy>; 1335 phy-names = "hdmi"; 1336 mediatek,syscon-hdmi = <&mmsys 0x900>; 1337 assigned-clocks = <&topckgen CLK_TOP_HDMI_SEL>; 1338 assigned-clock-parents = <&hdmi_phy>; 1339 status = "disabled"; 1340 1341 ports { 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 1345 port@0 { 1346 reg = <0>; 1347 1348 hdmi0_in: endpoint { 1349 remote-endpoint = <&dpi0_out>; 1350 }; 1351 }; 1352 }; 1353 }; 1354 1355 larb4: larb@14027000 { 1356 compatible = "mediatek,mt8173-smi-larb"; 1357 reg = <0 0x14027000 0 0x1000>; 1358 mediatek,smi = <&smi_common>; 1359 power-domains = <&spm MT8173_POWER_DOMAIN_MM>; 1360 clocks = <&mmsys CLK_MM_SMI_LARB4>, 1361 <&mmsys CLK_MM_SMI_LARB4>; 1362 clock-names = "apb", "smi"; 1363 }; 1364 1365 imgsys: clock-controller@15000000 { 1366 compatible = "mediatek,mt8173-imgsys", "syscon"; 1367 reg = <0 0x15000000 0 0x1000>; 1368 #clock-cells = <1>; 1369 }; 1370 1371 larb2: larb@15001000 { 1372 compatible = "mediatek,mt8173-smi-larb"; 1373 reg = <0 0x15001000 0 0x1000>; 1374 mediatek,smi = <&smi_common>; 1375 power-domains = <&spm MT8173_POWER_DOMAIN_ISP>; 1376 clocks = <&imgsys CLK_IMG_LARB2_SMI>, 1377 <&imgsys CLK_IMG_LARB2_SMI>; 1378 clock-names = "apb", "smi"; 1379 }; 1380 1381 vdecsys: clock-controller@16000000 { 1382 compatible = "mediatek,mt8173-vdecsys", "syscon"; 1383 reg = <0 0x16000000 0 0x1000>; 1384 #clock-cells = <1>; 1385 }; 1386 1387 vcodec_dec: vcodec@16020000 { 1388 compatible = "mediatek,mt8173-vcodec-dec"; 1389 reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */ 1390 <0 0x16021000 0 0x800>, /* VDEC_LD */ 1391 <0 0x16021800 0 0x800>, /* VDEC_TOP */ 1392 <0 0x16022000 0 0x1000>, /* VDEC_CM */ 1393 <0 0x16023000 0 0x1000>, /* VDEC_AD */ 1394 <0 0x16024000 0 0x1000>, /* VDEC_AV */ 1395 <0 0x16025000 0 0x1000>, /* VDEC_PP */ 1396 <0 0x16026800 0 0x800>, /* VDEC_HWD */ 1397 <0 0x16027000 0 0x800>, /* VDEC_HWQ */ 1398 <0 0x16027800 0 0x800>, /* VDEC_HWB */ 1399 <0 0x16028400 0 0x400>; /* VDEC_HWG */ 1400 reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp", 1401 "hwd", "hwq", "hwb", "hwg"; 1402 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>; 1403 iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, 1404 <&iommu M4U_PORT_HW_VDEC_PP_EXT>, 1405 <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, 1406 <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, 1407 <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, 1408 <&iommu M4U_PORT_HW_VDEC_UFO_EXT>, 1409 <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, 1410 <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; 1411 mediatek,vpu = <&vpu>; 1412 mediatek,vdecsys = <&vdecsys>; 1413 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1414 clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, 1415 <&topckgen CLK_TOP_UNIVPLL_D2>, 1416 <&topckgen CLK_TOP_CCI400_SEL>, 1417 <&topckgen CLK_TOP_VDEC_SEL>, 1418 <&topckgen CLK_TOP_VCODECPLL>, 1419 <&apmixedsys CLK_APMIXED_VENCPLL>, 1420 <&topckgen CLK_TOP_VENC_LT_SEL>, 1421 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1422 clock-names = "vcodecpll", 1423 "univpll_d2", 1424 "clk_cci400_sel", 1425 "vdec_sel", 1426 "vdecpll", 1427 "vencpll", 1428 "venc_lt_sel", 1429 "vdec_bus_clk_src"; 1430 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, 1431 <&topckgen CLK_TOP_CCI400_SEL>, 1432 <&topckgen CLK_TOP_VDEC_SEL>, 1433 <&apmixedsys CLK_APMIXED_VCODECPLL>, 1434 <&apmixedsys CLK_APMIXED_VENCPLL>; 1435 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, 1436 <&topckgen CLK_TOP_UNIVPLL_D2>, 1437 <&topckgen CLK_TOP_VCODECPLL>; 1438 assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; 1439 }; 1440 1441 larb1: larb@16010000 { 1442 compatible = "mediatek,mt8173-smi-larb"; 1443 reg = <0 0x16010000 0 0x1000>; 1444 mediatek,smi = <&smi_common>; 1445 power-domains = <&spm MT8173_POWER_DOMAIN_VDEC>; 1446 clocks = <&vdecsys CLK_VDEC_CKEN>, 1447 <&vdecsys CLK_VDEC_LARB_CKEN>; 1448 clock-names = "apb", "smi"; 1449 }; 1450 1451 vencsys: clock-controller@18000000 { 1452 compatible = "mediatek,mt8173-vencsys", "syscon"; 1453 reg = <0 0x18000000 0 0x1000>; 1454 #clock-cells = <1>; 1455 }; 1456 1457 larb3: larb@18001000 { 1458 compatible = "mediatek,mt8173-smi-larb"; 1459 reg = <0 0x18001000 0 0x1000>; 1460 mediatek,smi = <&smi_common>; 1461 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1462 clocks = <&vencsys CLK_VENC_CKE1>, 1463 <&vencsys CLK_VENC_CKE0>; 1464 clock-names = "apb", "smi"; 1465 }; 1466 1467 vcodec_enc_avc: vcodec@18002000 { 1468 compatible = "mediatek,mt8173-vcodec-enc"; 1469 reg = <0 0x18002000 0 0x1000>; /* VENC_SYS */ 1470 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 1471 iommus = <&iommu M4U_PORT_VENC_RCPU>, 1472 <&iommu M4U_PORT_VENC_REC>, 1473 <&iommu M4U_PORT_VENC_BSDMA>, 1474 <&iommu M4U_PORT_VENC_SV_COMV>, 1475 <&iommu M4U_PORT_VENC_RD_COMV>, 1476 <&iommu M4U_PORT_VENC_CUR_LUMA>, 1477 <&iommu M4U_PORT_VENC_CUR_CHROMA>, 1478 <&iommu M4U_PORT_VENC_REF_LUMA>, 1479 <&iommu M4U_PORT_VENC_REF_CHROMA>, 1480 <&iommu M4U_PORT_VENC_NBM_RDMA>, 1481 <&iommu M4U_PORT_VENC_NBM_WDMA>; 1482 mediatek,vpu = <&vpu>; 1483 clocks = <&topckgen CLK_TOP_VENC_SEL>; 1484 clock-names = "venc_sel"; 1485 assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; 1486 assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; 1487 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1488 }; 1489 1490 jpegdec: jpegdec@18004000 { 1491 compatible = "mediatek,mt8173-jpgdec"; 1492 reg = <0 0x18004000 0 0x1000>; 1493 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_LOW>; 1494 clocks = <&vencsys CLK_VENC_CKE0>, 1495 <&vencsys CLK_VENC_CKE3>; 1496 clock-names = "jpgdec-smi", 1497 "jpgdec"; 1498 power-domains = <&spm MT8173_POWER_DOMAIN_VENC>; 1499 iommus = <&iommu M4U_PORT_JPGDEC_WDMA>, 1500 <&iommu M4U_PORT_JPGDEC_BSDMA>; 1501 }; 1502 1503 vencltsys: clock-controller@19000000 { 1504 compatible = "mediatek,mt8173-vencltsys", "syscon"; 1505 reg = <0 0x19000000 0 0x1000>; 1506 #clock-cells = <1>; 1507 }; 1508 1509 larb5: larb@19001000 { 1510 compatible = "mediatek,mt8173-smi-larb"; 1511 reg = <0 0x19001000 0 0x1000>; 1512 mediatek,smi = <&smi_common>; 1513 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; 1514 clocks = <&vencltsys CLK_VENCLT_CKE1>, 1515 <&vencltsys CLK_VENCLT_CKE0>; 1516 clock-names = "apb", "smi"; 1517 }; 1518 1519 vcodec_enc_vp8: vcodec@19002000 { 1520 compatible = "mediatek,mt8173-vcodec-enc-vp8"; 1521 reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ 1522 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 1523 iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, 1524 <&iommu M4U_PORT_VENC_REC_FRM_SET2>, 1525 <&iommu M4U_PORT_VENC_BSDMA_SET2>, 1526 <&iommu M4U_PORT_VENC_SV_COMA_SET2>, 1527 <&iommu M4U_PORT_VENC_RD_COMA_SET2>, 1528 <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, 1529 <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, 1530 <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, 1531 <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; 1532 mediatek,vpu = <&vpu>; 1533 clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1534 clock-names = "venc_lt_sel"; 1535 assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; 1536 assigned-clock-parents = 1537 <&topckgen CLK_TOP_VCODECPLL_370P5>; 1538 power-domains = <&spm MT8173_POWER_DOMAIN_VENC_LT>; 1539 }; 1540 }; 1541};
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