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mt7988a.dtsi
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linux-6.19.14/arch/arm64/boot/dts/mediatek/mt7988a.dtsi
1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2 3#include <dt-bindings/clock/mediatek,mt7988-clk.h> 4#include <dt-bindings/interrupt-controller/arm-gic.h> 5#include <dt-bindings/phy/phy.h> 6#include <dt-bindings/pinctrl/mt65xx.h> 7#include <dt-bindings/reset/mediatek,mt7988-resets.h> 8 9/ { 10 compatible = "mediatek,mt7988a"; 11 interrupt-parent = <&gic>; 12 #address-cells = <2>; 13 #size-cells = <2>; 14 15 cci: cci { 16 compatible = "mediatek,mt7988-cci", "mediatek,mt8183-cci"; 17 clocks = <&mcusys CLK_MCU_BUS_DIV_SEL>, 18 <&topckgen CLK_TOP_XTAL>; 19 clock-names = "cci", "intermediate"; 20 operating-points-v2 = <&cci_opp>; 21 }; 22 23 cci_opp: opp-table-cci { 24 compatible = "operating-points-v2"; 25 opp-shared; 26 opp-480000000 { 27 opp-hz = /bits/ 64 <480000000>; 28 opp-microvolt = <850000>; 29 }; 30 opp-660000000 { 31 opp-hz = /bits/ 64 <660000000>; 32 opp-microvolt = <850000>; 33 }; 34 opp-900000000 { 35 opp-hz = /bits/ 64 <900000000>; 36 opp-microvolt = <850000>; 37 }; 38 opp-1080000000 { 39 opp-hz = /bits/ 64 <1080000000>; 40 opp-microvolt = <900000>; 41 }; 42 }; 43 44 cpus { 45 #address-cells = <1>; 46 #size-cells = <0>; 47 48 cpu0: cpu@0 { 49 compatible = "arm,cortex-a73"; 50 reg = <0x0>; 51 device_type = "cpu"; 52 enable-method = "psci"; 53 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 54 <&topckgen CLK_TOP_XTAL>; 55 clock-names = "cpu", "intermediate"; 56 operating-points-v2 = <&cluster0_opp>; 57 mediatek,cci = <&cci>; 58 }; 59 60 cpu1: cpu@1 { 61 compatible = "arm,cortex-a73"; 62 reg = <0x1>; 63 device_type = "cpu"; 64 enable-method = "psci"; 65 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 66 <&topckgen CLK_TOP_XTAL>; 67 clock-names = "cpu", "intermediate"; 68 operating-points-v2 = <&cluster0_opp>; 69 mediatek,cci = <&cci>; 70 }; 71 72 cpu2: cpu@2 { 73 compatible = "arm,cortex-a73"; 74 reg = <0x2>; 75 device_type = "cpu"; 76 enable-method = "psci"; 77 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 78 <&topckgen CLK_TOP_XTAL>; 79 clock-names = "cpu", "intermediate"; 80 operating-points-v2 = <&cluster0_opp>; 81 mediatek,cci = <&cci>; 82 }; 83 84 cpu3: cpu@3 { 85 compatible = "arm,cortex-a73"; 86 reg = <0x3>; 87 device_type = "cpu"; 88 enable-method = "psci"; 89 clocks = <&mcusys CLK_MCU_ARM_DIV_SEL>, 90 <&topckgen CLK_TOP_XTAL>; 91 clock-names = "cpu", "intermediate"; 92 operating-points-v2 = <&cluster0_opp>; 93 mediatek,cci = <&cci>; 94 }; 95 96 cluster0_opp: opp-table-0 { 97 compatible = "operating-points-v2"; 98 opp-shared; 99 100 opp-800000000 { 101 opp-hz = /bits/ 64 <800000000>; 102 opp-microvolt = <850000>; 103 }; 104 opp-1100000000 { 105 opp-hz = /bits/ 64 <1100000000>; 106 opp-microvolt = <850000>; 107 }; 108 opp-1500000000 { 109 opp-hz = /bits/ 64 <1500000000>; 110 opp-microvolt = <850000>; 111 }; 112 opp-1800000000 { 113 opp-hz = /bits/ 64 <1800000000>; 114 opp-microvolt = <900000>; 115 }; 116 }; 117 }; 118 119 oscillator-40m { 120 compatible = "fixed-clock"; 121 clock-frequency = <40000000>; 122 #clock-cells = <0>; 123 clock-output-names = "clkxtal"; 124 }; 125 126 pmu { 127 compatible = "arm,cortex-a73-pmu"; 128 interrupt-parent = <&gic>; 129 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 130 }; 131 132 psci { 133 compatible = "arm,psci-0.2"; 134 method = "smc"; 135 }; 136 137 reserved-memory { 138 #address-cells = <2>; 139 #size-cells = <2>; 140 ranges; 141 142 /* 320 KiB reserved for ARM Trusted Firmware (BL31 and BL32) */ 143 secmon@43000000 { 144 reg = <0 0x43000000 0 0x50000>; 145 no-map; 146 }; 147 }; 148 149 soc { 150 compatible = "simple-bus"; 151 ranges; 152 #address-cells = <2>; 153 #size-cells = <2>; 154 155 gic: interrupt-controller@c000000 { 156 compatible = "arm,gic-v3"; 157 reg = <0 0x0c000000 0 0x40000>, /* GICD */ 158 <0 0x0c080000 0 0x200000>, /* GICR */ 159 <0 0x0c400000 0 0x2000>, /* GICC */ 160 <0 0x0c410000 0 0x1000>, /* GICH */ 161 <0 0x0c420000 0 0x2000>; /* GICV */ 162 interrupt-parent = <&gic>; 163 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 164 interrupt-controller; 165 #interrupt-cells = <3>; 166 }; 167 168 infracfg: clock-controller@10001000 { 169 compatible = "mediatek,mt7988-infracfg", "syscon"; 170 reg = <0 0x10001000 0 0x1000>; 171 #clock-cells = <1>; 172 #reset-cells = <1>; 173 }; 174 175 topckgen: clock-controller@1001b000 { 176 compatible = "mediatek,mt7988-topckgen", "syscon"; 177 reg = <0 0x1001b000 0 0x1000>; 178 #clock-cells = <1>; 179 }; 180 181 watchdog: watchdog@1001c000 { 182 compatible = "mediatek,mt7988-wdt"; 183 reg = <0 0x1001c000 0 0x1000>; 184 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 185 #reset-cells = <1>; 186 }; 187 188 apmixedsys: clock-controller@1001e000 { 189 compatible = "mediatek,mt7988-apmixedsys"; 190 reg = <0 0x1001e000 0 0x1000>; 191 #clock-cells = <1>; 192 }; 193 194 pio: pinctrl@1001f000 { 195 compatible = "mediatek,mt7988-pinctrl"; 196 reg = <0 0x1001f000 0 0x1000>, 197 <0 0x11c10000 0 0x1000>, 198 <0 0x11d00000 0 0x1000>, 199 <0 0x11d20000 0 0x1000>, 200 <0 0x11e00000 0 0x1000>, 201 <0 0x11f00000 0 0x1000>, 202 <0 0x1000b000 0 0x1000>; 203 reg-names = "gpio", "iocfg_tr", 204 "iocfg_br", "iocfg_rb", 205 "iocfg_lb", "iocfg_tl", "eint"; 206 gpio-controller; 207 #gpio-cells = <2>; 208 gpio-ranges = <&pio 0 0 84>; 209 interrupt-controller; 210 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 211 interrupt-parent = <&gic>; 212 #interrupt-cells = <2>; 213 214 pcie0_pins: pcie0-pins { 215 mux { 216 function = "pcie"; 217 groups = "pcie_2l_0_pereset", "pcie_clk_req_n0_0", 218 "pcie_wake_n0_0"; 219 }; 220 }; 221 222 pcie1_pins: pcie1-pins { 223 mux { 224 function = "pcie"; 225 groups = "pcie_2l_1_pereset", "pcie_clk_req_n1", 226 "pcie_wake_n1_0"; 227 }; 228 }; 229 230 pcie2_pins: pcie2-pins { 231 mux { 232 function = "pcie"; 233 groups = "pcie_1l_0_pereset", "pcie_clk_req_n2_0", 234 "pcie_wake_n2_0"; 235 }; 236 }; 237 238 pcie3_pins: pcie3-pins { 239 mux { 240 function = "pcie"; 241 groups = "pcie_1l_1_pereset", "pcie_clk_req_n3", 242 "pcie_wake_n3_0"; 243 }; 244 }; 245 246 spi1_pins: spi1-pins { 247 mux { 248 function = "spi"; 249 groups = "spi1"; 250 }; 251 }; 252 253 uart0_pins: uart0-pins { 254 mux { 255 function = "uart"; 256 groups = "uart0"; 257 }; 258 }; 259 }; 260 261 pwm: pwm@10048000 { 262 compatible = "mediatek,mt7988-pwm"; 263 reg = <0 0x10048000 0 0x1000>; 264 clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, 265 <&infracfg CLK_INFRA_66M_PWM_HCK>, 266 <&infracfg CLK_INFRA_66M_PWM_CK1>, 267 <&infracfg CLK_INFRA_66M_PWM_CK2>, 268 <&infracfg CLK_INFRA_66M_PWM_CK3>, 269 <&infracfg CLK_INFRA_66M_PWM_CK4>, 270 <&infracfg CLK_INFRA_66M_PWM_CK5>, 271 <&infracfg CLK_INFRA_66M_PWM_CK6>, 272 <&infracfg CLK_INFRA_66M_PWM_CK7>, 273 <&infracfg CLK_INFRA_66M_PWM_CK8>; 274 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 275 "pwm4", "pwm5", "pwm6", "pwm7", "pwm8"; 276 #pwm-cells = <2>; 277 status = "disabled"; 278 }; 279 280 mcusys: mcusys@100e0000 { 281 compatible = "mediatek,mt7988-mcusys", "syscon"; 282 reg = <0 0x100e0000 0 0x1000>; 283 #clock-cells = <1>; 284 }; 285 286 serial0: serial@11000000 { 287 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 288 reg = <0 0x11000000 0 0x100>; 289 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 290 interrupt-names = "uart", "wakeup"; 291 clocks = <&topckgen CLK_TOP_UART_SEL>, 292 <&infracfg CLK_INFRA_52M_UART0_CK>; 293 clock-names = "baud", "bus"; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&uart0_pins>; 296 status = "disabled"; 297 }; 298 299 serial@11000100 { 300 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 301 reg = <0 0x11000100 0 0x100>; 302 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; 303 interrupt-names = "uart", "wakeup"; 304 clocks = <&topckgen CLK_TOP_UART_SEL>, 305 <&infracfg CLK_INFRA_52M_UART1_CK>; 306 clock-names = "baud", "bus"; 307 status = "disabled"; 308 }; 309 310 serial@11000200 { 311 compatible = "mediatek,mt7988-uart", "mediatek,mt6577-uart"; 312 reg = <0 0x11000200 0 0x100>; 313 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 314 interrupt-names = "uart", "wakeup"; 315 clocks = <&topckgen CLK_TOP_UART_SEL>, 316 <&infracfg CLK_INFRA_52M_UART2_CK>; 317 clock-names = "baud", "bus"; 318 status = "disabled"; 319 }; 320 321 i2c0: i2c@11003000 { 322 compatible = "mediatek,mt7981-i2c"; 323 reg = <0 0x11003000 0 0x1000>, 324 <0 0x10217080 0 0x80>; 325 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 326 clock-div = <1>; 327 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 328 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 329 clock-names = "main", "dma"; 330 #address-cells = <1>; 331 #size-cells = <0>; 332 status = "disabled"; 333 }; 334 335 i2c1: i2c@11004000 { 336 compatible = "mediatek,mt7981-i2c"; 337 reg = <0 0x11004000 0 0x1000>, 338 <0 0x10217100 0 0x80>; 339 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 340 clock-div = <1>; 341 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 342 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 343 clock-names = "main", "dma"; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 status = "disabled"; 347 }; 348 349 i2c2: i2c@11005000 { 350 compatible = "mediatek,mt7981-i2c"; 351 reg = <0 0x11005000 0 0x1000>, 352 <0 0x10217180 0 0x80>; 353 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 354 clock-div = <1>; 355 clocks = <&infracfg CLK_INFRA_I2C_BCK>, 356 <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; 357 clock-names = "main", "dma"; 358 #address-cells = <1>; 359 #size-cells = <0>; 360 status = "disabled"; 361 }; 362 363 spi0: spi@11007000 { 364 compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; 365 reg = <0 0x11007000 0 0x100>; 366 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&topckgen CLK_TOP_MPLL_D2>, 368 <&topckgen CLK_TOP_SPI_SEL>, 369 <&infracfg CLK_INFRA_104M_SPI0>, 370 <&infracfg CLK_INFRA_66M_SPI0_HCK>; 371 clock-names = "parent-clk", "sel-clk", "spi-clk", 372 "hclk"; 373 #address-cells = <1>; 374 #size-cells = <0>; 375 status = "disabled"; 376 }; 377 378 spi1: spi@11008000 { 379 compatible = "mediatek,mt7988-spi-single", "mediatek,spi-ipm"; 380 reg = <0 0x11008000 0 0x100>; 381 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 382 clocks = <&topckgen CLK_TOP_MPLL_D2>, 383 <&topckgen CLK_TOP_SPIM_MST_SEL>, 384 <&infracfg CLK_INFRA_104M_SPI1>, 385 <&infracfg CLK_INFRA_66M_SPI1_HCK>; 386 clock-names = "parent-clk", "sel-clk", "spi-clk", 387 "hclk"; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 pinctrl-names = "default"; 391 pinctrl-0 = <&spi1_pins>; 392 status = "disabled"; 393 }; 394 395 spi2: spi@11009000 { 396 compatible = "mediatek,mt7988-spi-quad", "mediatek,spi-ipm"; 397 reg = <0 0x11009000 0 0x100>; 398 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&topckgen CLK_TOP_MPLL_D2>, 400 <&topckgen CLK_TOP_SPI_SEL>, 401 <&infracfg CLK_INFRA_104M_SPI2_BCK>, 402 <&infracfg CLK_INFRA_66M_SPI2_HCK>; 403 clock-names = "parent-clk", "sel-clk", "spi-clk", 404 "hclk"; 405 #address-cells = <1>; 406 #size-cells = <0>; 407 status = "disabled"; 408 }; 409 410 lvts: lvts@1100a000 { 411 compatible = "mediatek,mt7988-lvts-ap"; 412 #thermal-sensor-cells = <1>; 413 reg = <0 0x1100a000 0 0x1000>; 414 clocks = <&infracfg CLK_INFRA_26M_THERM_SYSTEM>; 415 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 416 resets = <&infracfg MT7988_INFRA_RST1_THERM_CTRL_SWRST>; 417 nvmem-cells = <&lvts_calibration>; 418 nvmem-cell-names = "lvts-calib-data-1"; 419 }; 420 421 ssusb0: usb@11190000 { 422 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; 423 reg = <0 0x11190000 0 0x2e00>, 424 <0 0x11193e00 0 0x0100>; 425 reg-names = "mac", "ippc"; 426 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 427 clocks = <&infracfg CLK_INFRA_USB_SYS>, 428 <&infracfg CLK_INFRA_USB_REF>, 429 <&infracfg CLK_INFRA_66M_USB_HCK>, 430 <&infracfg CLK_INFRA_133M_USB_HCK>, 431 <&infracfg CLK_INFRA_USB_XHCI>; 432 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 433 phys = <&xphyu2port0 PHY_TYPE_USB2>, 434 <&xphyu3port0 PHY_TYPE_USB3>; 435 status = "disabled"; 436 }; 437 438 ssusb1: usb@11200000 { 439 compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; 440 reg = <0 0x11200000 0 0x2e00>, 441 <0 0x11203e00 0 0x0100>; 442 reg-names = "mac", "ippc"; 443 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 444 clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, 445 <&infracfg CLK_INFRA_USB_CK_P1>, 446 <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, 447 <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, 448 <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; 449 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; 450 phys = <&tphyu2port0 PHY_TYPE_USB2>, 451 <&tphyu3port0 PHY_TYPE_USB3>; 452 status = "disabled"; 453 }; 454 455 mmc0: mmc@11230000 { 456 compatible = "mediatek,mt7988-mmc"; 457 reg = <0 0x11230000 0 0x1000>, 458 <0 0x11D60000 0 0x1000>; 459 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&infracfg CLK_INFRA_MSDC400>, 461 <&infracfg CLK_INFRA_MSDC2_HCK>, 462 <&infracfg CLK_INFRA_66M_MSDC_0_HCK>, 463 <&infracfg CLK_INFRA_133M_MSDC_0_HCK>; 464 assigned-clocks = <&topckgen CLK_TOP_EMMC_250M_SEL>, 465 <&topckgen CLK_TOP_EMMC_400M_SEL>; 466 assigned-clock-parents = <&topckgen CLK_TOP_NET1PLL_D5_D2>, 467 <&apmixedsys CLK_APMIXED_MSDCPLL>; 468 clock-names = "source", "hclk", "axi_cg", "ahb_cg"; 469 #address-cells = <1>; 470 #size-cells = <0>; 471 status = "disabled"; 472 }; 473 474 pcie2: pcie@11280000 { 475 compatible = "mediatek,mt7986-pcie", 476 "mediatek,mt8192-pcie"; 477 device_type = "pci"; 478 #address-cells = <3>; 479 #size-cells = <2>; 480 reg = <0 0x11280000 0 0x2000>; 481 reg-names = "pcie-mac"; 482 linux,pci-domain = <3>; 483 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 484 bus-range = <0x00 0xff>; 485 ranges = <0x81000000 0x00 0x20000000 0x00 486 0x20000000 0x00 0x00200000>, 487 <0x82000000 0x00 0x20200000 0x00 488 0x20200000 0x00 0x07e00000>; 489 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P2>, 490 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P2>, 491 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P2>, 492 <&infracfg CLK_INFRA_133M_PCIE_CK_P2>; 493 clock-names = "pl_250m", "tl_26m", "peri_26m", 494 "top_133m"; 495 pinctrl-names = "default"; 496 pinctrl-0 = <&pcie2_pins>; 497 status = "disabled"; 498 499 phys = <&xphyu3port0 PHY_TYPE_PCIE>; 500 phy-names = "pcie-phy"; 501 502 #interrupt-cells = <1>; 503 interrupt-map-mask = <0 0 0 0x7>; 504 interrupt-map = <0 0 0 1 &pcie_intc2 0>, 505 <0 0 0 2 &pcie_intc2 1>, 506 <0 0 0 3 &pcie_intc2 2>, 507 <0 0 0 4 &pcie_intc2 3>; 508 pcie_intc2: interrupt-controller { 509 #address-cells = <0>; 510 #interrupt-cells = <1>; 511 interrupt-controller; 512 }; 513 }; 514 515 pcie3: pcie@11290000 { 516 compatible = "mediatek,mt7986-pcie", 517 "mediatek,mt8192-pcie"; 518 device_type = "pci"; 519 #address-cells = <3>; 520 #size-cells = <2>; 521 reg = <0 0x11290000 0 0x2000>; 522 reg-names = "pcie-mac"; 523 linux,pci-domain = <2>; 524 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 525 bus-range = <0x00 0xff>; 526 ranges = <0x81000000 0x00 0x28000000 0x00 527 0x28000000 0x00 0x00200000>, 528 <0x82000000 0x00 0x28200000 0x00 529 0x28200000 0x00 0x07e00000>; 530 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P3>, 531 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P3>, 532 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P3>, 533 <&infracfg CLK_INFRA_133M_PCIE_CK_P3>; 534 clock-names = "pl_250m", "tl_26m", "peri_26m", 535 "top_133m"; 536 pinctrl-names = "default"; 537 pinctrl-0 = <&pcie3_pins>; 538 status = "disabled"; 539 540 #interrupt-cells = <1>; 541 interrupt-map-mask = <0 0 0 0x7>; 542 interrupt-map = <0 0 0 1 &pcie_intc3 0>, 543 <0 0 0 2 &pcie_intc3 1>, 544 <0 0 0 3 &pcie_intc3 2>, 545 <0 0 0 4 &pcie_intc3 3>; 546 pcie_intc3: interrupt-controller { 547 #address-cells = <0>; 548 #interrupt-cells = <1>; 549 interrupt-controller; 550 }; 551 }; 552 553 pcie0: pcie@11300000 { 554 compatible = "mediatek,mt7986-pcie", 555 "mediatek,mt8192-pcie"; 556 device_type = "pci"; 557 #address-cells = <3>; 558 #size-cells = <2>; 559 reg = <0 0x11300000 0 0x2000>; 560 reg-names = "pcie-mac"; 561 linux,pci-domain = <0>; 562 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; 563 bus-range = <0x00 0xff>; 564 ranges = <0x81000000 0x00 0x30000000 0x00 565 0x30000000 0x00 0x00200000>, 566 <0x82000000 0x00 0x30200000 0x00 567 0x30200000 0x00 0x07e00000>; 568 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P0>, 569 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P0>, 570 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P0>, 571 <&infracfg CLK_INFRA_133M_PCIE_CK_P0>; 572 clock-names = "pl_250m", "tl_26m", "peri_26m", 573 "top_133m"; 574 pinctrl-names = "default"; 575 pinctrl-0 = <&pcie0_pins>; 576 status = "disabled"; 577 578 #interrupt-cells = <1>; 579 interrupt-map-mask = <0 0 0 0x7>; 580 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 581 <0 0 0 2 &pcie_intc0 1>, 582 <0 0 0 3 &pcie_intc0 2>, 583 <0 0 0 4 &pcie_intc0 3>; 584 pcie_intc0: interrupt-controller { 585 #address-cells = <0>; 586 #interrupt-cells = <1>; 587 interrupt-controller; 588 }; 589 }; 590 591 pcie1: pcie@11310000 { 592 compatible = "mediatek,mt7986-pcie", 593 "mediatek,mt8192-pcie"; 594 device_type = "pci"; 595 #address-cells = <3>; 596 #size-cells = <2>; 597 reg = <0 0x11310000 0 0x2000>; 598 reg-names = "pcie-mac"; 599 linux,pci-domain = <1>; 600 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 601 bus-range = <0x00 0xff>; 602 ranges = <0x81000000 0x00 0x38000000 0x00 603 0x38000000 0x00 0x00200000>, 604 <0x82000000 0x00 0x38200000 0x00 605 0x38200000 0x00 0x07e00000>; 606 clocks = <&infracfg CLK_INFRA_PCIE_PIPE_P1>, 607 <&infracfg CLK_INFRA_PCIE_GFMUX_TL_P1>, 608 <&infracfg CLK_INFRA_PCIE_PERI_26M_CK_P1>, 609 <&infracfg CLK_INFRA_133M_PCIE_CK_P1>; 610 clock-names = "pl_250m", "tl_26m", "peri_26m", 611 "top_133m"; 612 pinctrl-names = "default"; 613 pinctrl-0 = <&pcie1_pins>; 614 status = "disabled"; 615 616 #interrupt-cells = <1>; 617 interrupt-map-mask = <0 0 0 0x7>; 618 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 619 <0 0 0 2 &pcie_intc1 1>, 620 <0 0 0 3 &pcie_intc1 2>, 621 <0 0 0 4 &pcie_intc1 3>; 622 pcie_intc1: interrupt-controller { 623 #address-cells = <0>; 624 #interrupt-cells = <1>; 625 interrupt-controller; 626 }; 627 }; 628 629 tphy: t-phy@11c50000 { 630 compatible = "mediatek,mt7986-tphy", 631 "mediatek,generic-tphy-v2"; 632 #address-cells = <2>; 633 #size-cells = <2>; 634 ranges; 635 status = "disabled"; 636 637 tphyu2port0: usb-phy@11c50000 { 638 reg = <0 0x11c50000 0 0x700>; 639 clocks = <&infracfg CLK_INFRA_USB_UTMI_CK_P1>; 640 clock-names = "ref"; 641 #phy-cells = <1>; 642 }; 643 644 tphyu3port0: usb-phy@11c50700 { 645 reg = <0 0x11c50700 0 0x900>; 646 clocks = <&infracfg CLK_INFRA_USB_PIPE_CK_P1>; 647 clock-names = "ref"; 648 #phy-cells = <1>; 649 }; 650 }; 651 652 653 topmisc: system-controller@11d10084 { 654 compatible = "mediatek,mt7988-topmisc", 655 "syscon"; 656 reg = <0 0x11d10084 0 0xff80>; 657 }; 658 659 xsphy: xs-phy@11e10000 { 660 compatible = "mediatek,mt7988-xsphy", 661 "mediatek,xsphy"; 662 #address-cells = <2>; 663 #size-cells = <2>; 664 ranges; 665 status = "disabled"; 666 667 xphyu2port0: usb-phy@11e10000 { 668 reg = <0 0x11e10000 0 0x400>; 669 clocks = <&infracfg CLK_INFRA_USB_UTMI>; 670 clock-names = "ref"; 671 #phy-cells = <1>; 672 }; 673 674 xphyu3port0: usb-phy@11e13000 { 675 reg = <0 0x11e13400 0 0x500>; 676 clocks = <&infracfg CLK_INFRA_USB_PIPE>; 677 clock-names = "ref"; 678 #phy-cells = <1>; 679 mediatek,syscon-type = <&topmisc 0x194 0>; 680 }; 681 }; 682 683 xfi_tphy0: phy@11f20000 { 684 compatible = "mediatek,mt7988-xfi-tphy"; 685 reg = <0 0x11f20000 0 0x10000>; 686 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, 687 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>; 688 clock-names = "xfipll", "topxtal"; 689 resets = <&watchdog 14>; 690 mediatek,usxgmii-performance-errata; 691 #phy-cells = <0>; 692 }; 693 694 xfi_tphy1: phy@11f30000 { 695 compatible = "mediatek,mt7988-xfi-tphy"; 696 reg = <0 0x11f30000 0 0x10000>; 697 clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>, 698 <&topckgen CLK_TOP_XFI_PHY_1_XTAL_SEL>; 699 clock-names = "xfipll", "topxtal"; 700 resets = <&watchdog 15>; 701 #phy-cells = <0>; 702 }; 703 704 xfi_pll: clock-controller@11f40000 { 705 compatible = "mediatek,mt7988-xfi-pll"; 706 reg = <0 0x11f40000 0 0x1000>; 707 resets = <&watchdog 16>; 708 #clock-cells = <1>; 709 }; 710 711 efuse@11f50000 { 712 compatible = "mediatek,mt7988-efuse", "mediatek,efuse"; 713 reg = <0 0x11f50000 0 0x1000>; 714 #address-cells = <1>; 715 #size-cells = <1>; 716 717 soc-uuid@140 { 718 reg = <0x140 0x10>; 719 }; 720 721 lvts_calibration: calib@918 { 722 reg = <0x918 0x28>; 723 }; 724 725 phy_calibration_p0: calib@940 { 726 reg = <0x940 0x10>; 727 }; 728 729 phy_calibration_p1: calib@954 { 730 reg = <0x954 0x10>; 731 }; 732 733 phy_calibration_p2: calib@968 { 734 reg = <0x968 0x10>; 735 }; 736 737 phy_calibration_p3: calib@97c { 738 reg = <0x97c 0x10>; 739 }; 740 }; 741 742 ethsys: clock-controller@15000000 { 743 compatible = "mediatek,mt7988-ethsys", "syscon"; 744 reg = <0 0x15000000 0 0x1000>; 745 #clock-cells = <1>; 746 #reset-cells = <1>; 747 }; 748 749 switch: switch@15020000 { 750 compatible = "mediatek,mt7988-switch"; 751 reg = <0 0x15020000 0 0x8000>; 752 interrupt-controller; 753 #interrupt-cells = <1>; 754 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; 755 resets = <ðwarp MT7988_ETHWARP_RST_SWITCH>; 756 757 ports { 758 #address-cells = <1>; 759 #size-cells = <0>; 760 761 gsw_port0: port@0 { 762 reg = <0>; 763 phy-handle = <&gsw_phy0>; 764 phy-mode = "internal"; 765 }; 766 767 gsw_port1: port@1 { 768 reg = <1>; 769 phy-handle = <&gsw_phy1>; 770 phy-mode = "internal"; 771 }; 772 773 gsw_port2: port@2 { 774 reg = <2>; 775 phy-handle = <&gsw_phy2>; 776 phy-mode = "internal"; 777 }; 778 779 gsw_port3: port@3 { 780 reg = <3>; 781 phy-handle = <&gsw_phy3>; 782 phy-mode = "internal"; 783 }; 784 785 port@6 { 786 reg = <6>; 787 ethernet = <&gmac0>; 788 phy-mode = "internal"; 789 790 fixed-link { 791 speed = <10000>; 792 full-duplex; 793 pause; 794 }; 795 }; 796 }; 797 798 mdio { 799 #address-cells = <1>; 800 #size-cells = <0>; 801 mediatek,pio = <&pio>; 802 803 gsw_phy0: ethernet-phy@0 { 804 compatible = "ethernet-phy-ieee802.3-c22"; 805 reg = <0>; 806 interrupts = <0>; 807 nvmem-cells = <&phy_calibration_p0>; 808 nvmem-cell-names = "phy-cal-data"; 809 810 leds { 811 #address-cells = <1>; 812 #size-cells = <0>; 813 814 gsw_phy0_led0: led@0 { 815 reg = <0>; 816 status = "disabled"; 817 }; 818 819 gsw_phy0_led1: led@1 { 820 reg = <1>; 821 status = "disabled"; 822 }; 823 }; 824 }; 825 826 gsw_phy1: ethernet-phy@1 { 827 compatible = "ethernet-phy-ieee802.3-c22"; 828 reg = <1>; 829 interrupts = <1>; 830 nvmem-cells = <&phy_calibration_p1>; 831 nvmem-cell-names = "phy-cal-data"; 832 833 leds { 834 #address-cells = <1>; 835 #size-cells = <0>; 836 837 gsw_phy1_led0: led@0 { 838 reg = <0>; 839 status = "disabled"; 840 }; 841 842 gsw_phy1_led1: led@1 { 843 reg = <1>; 844 status = "disabled"; 845 }; 846 }; 847 }; 848 849 gsw_phy2: ethernet-phy@2 { 850 compatible = "ethernet-phy-ieee802.3-c22"; 851 reg = <2>; 852 interrupts = <2>; 853 nvmem-cells = <&phy_calibration_p2>; 854 nvmem-cell-names = "phy-cal-data"; 855 856 leds { 857 #address-cells = <1>; 858 #size-cells = <0>; 859 860 gsw_phy2_led0: led@0 { 861 reg = <0>; 862 status = "disabled"; 863 }; 864 865 gsw_phy2_led1: led@1 { 866 reg = <1>; 867 status = "disabled"; 868 }; 869 }; 870 }; 871 872 gsw_phy3: ethernet-phy@3 { 873 compatible = "ethernet-phy-ieee802.3-c22"; 874 reg = <3>; 875 interrupts = <3>; 876 nvmem-cells = <&phy_calibration_p3>; 877 nvmem-cell-names = "phy-cal-data"; 878 879 leds { 880 #address-cells = <1>; 881 #size-cells = <0>; 882 883 gsw_phy3_led0: led@0 { 884 reg = <0>; 885 status = "disabled"; 886 }; 887 888 gsw_phy3_led1: led@1 { 889 reg = <1>; 890 status = "disabled"; 891 }; 892 }; 893 }; 894 }; 895 }; 896 897 ethwarp: clock-controller@15031000 { 898 compatible = "mediatek,mt7988-ethwarp"; 899 reg = <0 0x15031000 0 0x1000>; 900 #clock-cells = <1>; 901 #reset-cells = <1>; 902 }; 903 904 eth: ethernet@15100000 { 905 compatible = "mediatek,mt7988-eth"; 906 reg = <0 0x15100000 0 0x40000>; 907 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 913 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 914 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 915 interrupt-names = "fe0", "fe1", "fe2", "fe3", "pdma0", 916 "pdma1", "pdma2", "pdma3"; 917 clocks = <ðsys CLK_ETHDMA_CRYPT0_EN>, 918 <ðsys CLK_ETHDMA_FE_EN>, 919 <ðsys CLK_ETHDMA_GP2_EN>, 920 <ðsys CLK_ETHDMA_GP1_EN>, 921 <ðsys CLK_ETHDMA_GP3_EN>, 922 <ðwarp CLK_ETHWARP_WOCPU2_EN>, 923 <ðwarp CLK_ETHWARP_WOCPU1_EN>, 924 <ðwarp CLK_ETHWARP_WOCPU0_EN>, 925 <ðsys CLK_ETHDMA_ESW_EN>, 926 <&topckgen CLK_TOP_ETH_GMII_SEL>, 927 <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, 928 <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, 929 <&topckgen CLK_TOP_ETH_SYS_SEL>, 930 <&topckgen CLK_TOP_ETH_XGMII_SEL>, 931 <&topckgen CLK_TOP_ETH_MII_SEL>, 932 <&topckgen CLK_TOP_NETSYS_SEL>, 933 <&topckgen CLK_TOP_NETSYS_500M_SEL>, 934 <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, 935 <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, 936 <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, 937 <&topckgen CLK_TOP_NETSYS_WARP_SEL>, 938 <ðsys CLK_ETHDMA_XGP1_EN>, 939 <ðsys CLK_ETHDMA_XGP2_EN>, 940 <ðsys CLK_ETHDMA_XGP3_EN>; 941 clock-names = "crypto", "fe", "gp2", "gp1", "gp3", 942 "ethwarp_wocpu2", "ethwarp_wocpu1", 943 "ethwarp_wocpu0", "esw", "top_eth_gmii_sel", 944 "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", 945 "top_eth_sys_sel", "top_eth_xgmii_sel", 946 "top_eth_mii_sel", "top_netsys_sel", 947 "top_netsys_500m_sel", "top_netsys_pao_2x_sel", 948 "top_netsys_sync_250m_sel", 949 "top_netsys_ppefb_250m_sel", 950 "top_netsys_warp_sel","xgp1", "xgp2", "xgp3"; 951 assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, 952 <&topckgen CLK_TOP_NETSYS_GSW_SEL>, 953 <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, 954 <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, 955 <&topckgen CLK_TOP_SGM_0_SEL>, 956 <&topckgen CLK_TOP_SGM_1_SEL>; 957 assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, 958 <&topckgen CLK_TOP_NET1PLL_D4>, 959 <&topckgen CLK_TOP_NET1PLL_D8_D4>, 960 <&topckgen CLK_TOP_NET1PLL_D8_D4>, 961 <&apmixedsys CLK_APMIXED_SGMPLL>, 962 <&apmixedsys CLK_APMIXED_SGMPLL>; 963 sram = <ð_sram>; 964 #address-cells = <1>; 965 #size-cells = <0>; 966 mediatek,ethsys = <ðsys>; 967 mediatek,infracfg = <&topmisc>; 968 969 gmac0: mac@0 { 970 compatible = "mediatek,eth-mac"; 971 reg = <0>; 972 phy-mode = "internal"; 973 974 /* Connected to internal switch */ 975 fixed-link { 976 speed = <10000>; 977 full-duplex; 978 pause; 979 }; 980 }; 981 982 gmac1: mac@1 { 983 compatible = "mediatek,eth-mac"; 984 reg = <1>; 985 status = "disabled"; 986 }; 987 988 gmac2: mac@2 { 989 compatible = "mediatek,eth-mac"; 990 reg = <2>; 991 status = "disabled"; 992 }; 993 994 mdio_bus: mdio-bus { 995 #address-cells = <1>; 996 #size-cells = <0>; 997 998 /* internal 2.5G PHY */ 999 int_2p5g_phy: ethernet-phy@15 { 1000 compatible = "ethernet-phy-ieee802.3-c45"; 1001 reg = <15>; 1002 status = "disabled"; 1003 }; 1004 }; 1005 }; 1006 1007 eth_sram: sram@15400000 { 1008 compatible = "mmio-sram"; 1009 reg = <0 0x15400000 0 0x200000>; 1010 #address-cells = <1>; 1011 #size-cells = <1>; 1012 ranges = <0 0x15400000 0 0x200000>; 1013 }; 1014 }; 1015 1016 thermal-zones { 1017 cpu_thermal: cpu-thermal { 1018 polling-delay-passive = <1000>; 1019 polling-delay = <1000>; 1020 thermal-sensors = <&lvts 0>; 1021 trips { 1022 cpu_trip_crit: crit { 1023 temperature = <125000>; 1024 hysteresis = <2000>; 1025 type = "critical"; 1026 }; 1027 }; 1028 }; 1029 }; 1030 1031 timer { 1032 compatible = "arm,armv8-timer"; 1033 interrupt-parent = <&gic>; 1034 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1035 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1036 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1037 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1038 }; 1039};
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