mt7981b.dtsi

  1// SPDX-License-Identifier: GPL-2.0-only OR MIT
  2
  3#include <dt-bindings/clock/mediatek,mt7981-clk.h>
  4#include <dt-bindings/interrupt-controller/arm-gic.h>
  5#include <dt-bindings/reset/mt7986-resets.h>
  6
  7/ {
  8	compatible = "mediatek,mt7981b";
  9	interrupt-parent = <&gic>;
 10	#address-cells = <2>;
 11	#size-cells = <2>;
 12
 13	cpus {
 14		#address-cells = <1>;
 15		#size-cells = <0>;
 16
 17		cpu@0 {
 18			compatible = "arm,cortex-a53";
 19			reg = <0x0>;
 20			device_type = "cpu";
 21			enable-method = "psci";
 22		};
 23
 24		cpu@1 {
 25			compatible = "arm,cortex-a53";
 26			reg = <0x1>;
 27			device_type = "cpu";
 28			enable-method = "psci";
 29		};
 30	};
 31
 32	oscillator-40m {
 33		compatible = "fixed-clock";
 34		clock-frequency = <40000000>;
 35		clock-output-names = "clkxtal";
 36		#clock-cells = <0>;
 37	};
 38
 39	psci {
 40		compatible = "arm,psci-1.0";
 41		method = "smc";
 42	};
 43
 44	reserved-memory {
 45		#address-cells = <2>;
 46		#size-cells = <2>;
 47		ranges;
 48
 49		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
 50		secmon_reserved: secmon@43000000 {
 51			reg = <0 0x43000000 0 0x30000>;
 52			no-map;
 53		};
 54	};
 55
 56	soc {
 57		compatible = "simple-bus";
 58		ranges;
 59		#address-cells = <2>;
 60		#size-cells = <2>;
 61
 62		gic: interrupt-controller@c000000 {
 63			compatible = "arm,gic-v3";
 64			reg = <0 0x0c000000 0 0x40000>,  /* GICD */
 65			      <0 0x0c080000 0 0x200000>; /* GICR */
 66			interrupt-parent = <&gic>;
 67			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
 68			interrupt-controller;
 69			#interrupt-cells = <3>;
 70		};
 71
 72		infracfg: clock-controller@10001000 {
 73			compatible = "mediatek,mt7981-infracfg", "syscon";
 74			reg = <0 0x10001000 0 0x1000>;
 75			#clock-cells = <1>;
 76		};
 77
 78		topckgen: clock-controller@1001b000 {
 79			compatible = "mediatek,mt7981-topckgen", "syscon";
 80			reg = <0 0x1001b000 0 0x1000>;
 81			#clock-cells = <1>;
 82		};
 83
 84		watchdog: watchdog@1001c000 {
 85			compatible = "mediatek,mt7986-wdt";
 86			reg = <0 0x1001c000 0 0x1000>;
 87			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
 88			#reset-cells = <1>;
 89		};
 90
 91		apmixedsys: clock-controller@1001e000 {
 92			compatible = "mediatek,mt7981-apmixedsys";
 93			reg = <0 0x1001e000 0 0x1000>;
 94			#clock-cells = <1>;
 95		};
 96
 97		pwm: pwm@10048000 {
 98			compatible = "mediatek,mt7981-pwm";
 99			reg = <0 0x10048000 0 0x1000>;
100			clocks = <&infracfg CLK_INFRA_PWM_STA>,
101				 <&infracfg CLK_INFRA_PWM_HCK>,
102				 <&infracfg CLK_INFRA_PWM1_CK>,
103				 <&infracfg CLK_INFRA_PWM2_CK>,
104				 <&infracfg CLK_INFRA_PWM3_CK>;
105			clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
106			#pwm-cells = <2>;
107		};
108
109		uart0: serial@11002000 {
110			compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
111			reg = <0 0x11002000 0 0x100>;
112			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
113			interrupt-names = "uart", "wakeup";
114			clocks = <&infracfg CLK_INFRA_UART0_SEL>,
115				 <&infracfg CLK_INFRA_UART0_CK>;
116			clock-names = "baud", "bus";
117			pinctrl-names = "default";
118			pinctrl-0 = <&uart0_pins>;
119			status = "disabled";
120		};
121
122		uart1: serial@11003000 {
123			compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
124			reg = <0 0x11003000 0 0x100>;
125			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
126			interrupt-names = "uart", "wakeup";
127			clocks = <&infracfg CLK_INFRA_UART1_SEL>,
128				 <&infracfg CLK_INFRA_UART1_CK>;
129			clock-names = "baud", "bus";
130			status = "disabled";
131		};
132
133		uart2: serial@11004000 {
134			compatible = "mediatek,mt7981-uart", "mediatek,mt6577-uart";
135			reg = <0 0x11004000 0 0x100>;
136			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
137			interrupt-names = "uart", "wakeup";
138			clocks = <&infracfg CLK_INFRA_UART2_SEL>,
139				 <&infracfg CLK_INFRA_UART2_CK>;
140			clock-names = "baud", "bus";
141			status = "disabled";
142		};
143
144		i2c@11007000 {
145			compatible = "mediatek,mt7981-i2c";
146			reg = <0 0x11007000 0 0x1000>,
147			      <0 0x10217080 0 0x80>;
148			interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
149			clocks = <&infracfg CLK_INFRA_I2C0_CK>,
150				 <&infracfg CLK_INFRA_AP_DMA_CK>,
151				 <&infracfg CLK_INFRA_I2C_MCK_CK>,
152				 <&infracfg CLK_INFRA_I2C_PCK_CK>;
153			clock-names = "main", "dma", "arb", "pmic";
154			#address-cells = <1>;
155			#size-cells = <0>;
156			status = "disabled";
157		};
158
159		spi2: spi@11009000 {
160			compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
161			reg = <0 0x11009000 0 0x1000>;
162			interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
163			clocks = <&topckgen CLK_TOP_CB_M_D2>,
164				 <&topckgen CLK_TOP_SPI_SEL>,
165				 <&infracfg CLK_INFRA_SPI2_CK>,
166				 <&infracfg CLK_INFRA_SPI2_HCK_CK>;
167			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
168			#address-cells = <1>;
169			#size-cells = <0>;
170			status = "disabled";
171		};
172
173		spi@1100a000 {
174			compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
175			reg = <0 0x1100a000 0 0x1000>;
176			interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
177			clocks = <&topckgen CLK_TOP_CB_M_D2>,
178				 <&topckgen CLK_TOP_SPI_SEL>,
179				 <&infracfg CLK_INFRA_SPI0_CK>,
180				 <&infracfg CLK_INFRA_SPI0_HCK_CK>;
181			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
182			#address-cells = <1>;
183			#size-cells = <0>;
184			status = "disabled";
185		};
186
187		spi@1100b000 {
188			compatible = "mediatek,mt7981-spi-ipm", "mediatek,spi-ipm";
189			reg = <0 0x1100b000 0 0x1000>;
190			interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
191			clocks = <&topckgen CLK_TOP_CB_M_D2>,
192				 <&topckgen CLK_TOP_SPI_SEL>,
193				 <&infracfg CLK_INFRA_SPI1_CK>,
194				 <&infracfg CLK_INFRA_SPI1_HCK_CK>;
195			clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
196			#address-cells = <1>;
197			#size-cells = <0>;
198			status = "disabled";
199		};
200
201		thermal@1100c800 {
202			compatible = "mediatek,mt7981-thermal",
203				     "mediatek,mt7986-thermal";
204			reg = <0 0x1100c800 0 0x800>;
205			interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
206			clocks = <&infracfg CLK_INFRA_THERM_CK>,
207				 <&infracfg CLK_INFRA_ADC_26M_CK>;
208			clock-names = "therm", "auxadc";
209			nvmem-cells = <&thermal_calibration>;
210			nvmem-cell-names = "calibration-data";
211			#thermal-sensor-cells = <1>;
212			mediatek,auxadc = <&auxadc>;
213			mediatek,apmixedsys = <&apmixedsys>;
214		};
215
216		auxadc: adc@1100d000 {
217			compatible = "mediatek,mt7981-auxadc",
218				     "mediatek,mt7986-auxadc";
219			reg = <0 0x1100d000 0 0x1000>;
220			clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
221			clock-names = "main";
222			#io-channel-cells = <1>;
223			status = "disabled";
224		};
225
226		pio: pinctrl@11d00000 {
227			compatible = "mediatek,mt7981-pinctrl";
228			reg = <0 0x11d00000 0 0x1000>,
229			      <0 0x11c00000 0 0x1000>,
230			      <0 0x11c10000 0 0x1000>,
231			      <0 0x11d20000 0 0x1000>,
232			      <0 0x11e00000 0 0x1000>,
233			      <0 0x11e20000 0 0x1000>,
234			      <0 0x11f00000 0 0x1000>,
235			      <0 0x11f10000 0 0x1000>,
236			      <0 0x1000b000 0 0x1000>;
237			reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb",
238				    "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint";
239			interrupt-controller;
240			interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
241			interrupt-parent = <&gic>;
242			gpio-ranges = <&pio 0 0 56>;
243			gpio-controller;
244			#gpio-cells = <2>;
245			#interrupt-cells = <2>;
246
247			uart0_pins: uart0-pins {
248				mux {
249					function = "uart";
250					groups = "uart0";
251				};
252			};
253		};
254
255		efuse@11f20000 {
256			compatible = "mediatek,mt7981-efuse", "mediatek,efuse";
257			reg = <0 0x11f20000 0 0x1000>;
258			#address-cells = <1>;
259			#size-cells = <1>;
260
261			soc-uuid@140 {
262				reg = <0x140 0x10>;
263			};
264
265			thermal_calibration: thermal-calib@274 {
266				reg = <0x274 0xc>;
267			};
268		};
269
270		clock-controller@15000000 {
271			compatible = "mediatek,mt7981-ethsys", "syscon";
272			reg = <0 0x15000000 0 0x1000>;
273			#clock-cells = <1>;
274			#reset-cells = <1>;
275		};
276
277		wifi@18000000 {
278			compatible = "mediatek,mt7981-wmac";
279			reg = <0 0x18000000 0 0x1000000>,
280			      <0 0x10003000 0 0x1000>,
281			      <0 0x11d10000 0 0x1000>;
282			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
283				     <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
284				     <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
285				     <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
286			clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>,
287				 <&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
288			clock-names = "mcu", "ap2conn";
289			resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
290			reset-names = "consys";
291		};
292	};
293
294	timer {
295		compatible = "arm,armv8-timer";
296		interrupt-parent = <&gic>;
297		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
298			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
299			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
300			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
301	};
302};