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mt7622.dtsi
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linux-6.19.14/arch/arm64/boot/dts/mediatek/mt7622.dtsi
1/* 2 * Copyright (c) 2017 MediaTek Inc. 3 * Author: Ming Huang <ming.huang@mediatek.com> 4 * Sean Wang <sean.wang@mediatek.com> 5 * 6 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 7 */ 8 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/clock/mt7622-clk.h> 12#include <dt-bindings/phy/phy.h> 13#include <dt-bindings/power/mt7622-power.h> 14#include <dt-bindings/reset/mt7622-reset.h> 15#include <dt-bindings/thermal/thermal.h> 16 17/ { 18 compatible = "mediatek,mt7622"; 19 interrupt-parent = <&sysirq>; 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 cpu_opp_table: opp-table { 24 compatible = "operating-points-v2"; 25 opp-shared; 26 opp-300000000 { 27 opp-hz = /bits/ 64 <30000000>; 28 opp-microvolt = <950000>; 29 }; 30 31 opp-437500000 { 32 opp-hz = /bits/ 64 <437500000>; 33 opp-microvolt = <1000000>; 34 }; 35 36 opp-600000000 { 37 opp-hz = /bits/ 64 <600000000>; 38 opp-microvolt = <1050000>; 39 }; 40 41 opp-812500000 { 42 opp-hz = /bits/ 64 <812500000>; 43 opp-microvolt = <1100000>; 44 }; 45 46 opp-1025000000 { 47 opp-hz = /bits/ 64 <1025000000>; 48 opp-microvolt = <1150000>; 49 }; 50 51 opp-1137500000 { 52 opp-hz = /bits/ 64 <1137500000>; 53 opp-microvolt = <1200000>; 54 }; 55 56 opp-1262500000 { 57 opp-hz = /bits/ 64 <1262500000>; 58 opp-microvolt = <1250000>; 59 }; 60 61 opp-1350000000 { 62 opp-hz = /bits/ 64 <1350000000>; 63 opp-microvolt = <1310000>; 64 }; 65 }; 66 67 cpus { 68 #address-cells = <2>; 69 #size-cells = <0>; 70 71 cpu0: cpu@0 { 72 device_type = "cpu"; 73 compatible = "arm,cortex-a53"; 74 reg = <0x0 0x0>; 75 clocks = <&infracfg CLK_INFRA_MUX1_SEL>, 76 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; 77 clock-names = "cpu", "intermediate"; 78 operating-points-v2 = <&cpu_opp_table>; 79 #cooling-cells = <2>; 80 enable-method = "psci"; 81 clock-frequency = <1300000000>; 82 cci-control-port = <&cci_control2>; 83 next-level-cache = <&L2>; 84 }; 85 86 cpu1: cpu@1 { 87 device_type = "cpu"; 88 compatible = "arm,cortex-a53"; 89 reg = <0x0 0x1>; 90 clocks = <&infracfg CLK_INFRA_MUX1_SEL>, 91 <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>; 92 clock-names = "cpu", "intermediate"; 93 operating-points-v2 = <&cpu_opp_table>; 94 #cooling-cells = <2>; 95 enable-method = "psci"; 96 clock-frequency = <1300000000>; 97 cci-control-port = <&cci_control2>; 98 next-level-cache = <&L2>; 99 }; 100 101 L2: l2-cache { 102 compatible = "cache"; 103 cache-level = <2>; 104 cache-unified; 105 }; 106 }; 107 108 pwrap_clk: dummy40m { 109 compatible = "fixed-clock"; 110 clock-frequency = <40000000>; 111 #clock-cells = <0>; 112 }; 113 114 clk25m: oscillator { 115 compatible = "fixed-clock"; 116 #clock-cells = <0>; 117 clock-frequency = <25000000>; 118 clock-output-names = "clkxtal"; 119 }; 120 121 psci { 122 compatible = "arm,psci-0.2"; 123 method = "smc"; 124 }; 125 126 pmu { 127 compatible = "arm,cortex-a53-pmu"; 128 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 129 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>; 130 interrupt-affinity = <&cpu0>, <&cpu1>; 131 }; 132 133 reserved-memory { 134 #address-cells = <2>; 135 #size-cells = <2>; 136 ranges; 137 138 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ 139 secmon_reserved: secmon@43000000 { 140 reg = <0 0x43000000 0 0x30000>; 141 no-map; 142 }; 143 }; 144 145 thermal-zones { 146 cpu_thermal: cpu-thermal { 147 polling-delay-passive = <1000>; 148 polling-delay = <1000>; 149 150 thermal-sensors = <&thermal 0>; 151 152 trips { 153 cpu_passive: cpu-passive { 154 temperature = <47000>; 155 hysteresis = <2000>; 156 type = "passive"; 157 }; 158 159 cpu_active: cpu-active { 160 temperature = <67000>; 161 hysteresis = <2000>; 162 type = "active"; 163 }; 164 165 cpu_hot: cpu-hot { 166 temperature = <87000>; 167 hysteresis = <2000>; 168 type = "hot"; 169 }; 170 171 cpu-crit { 172 temperature = <107000>; 173 hysteresis = <2000>; 174 type = "critical"; 175 }; 176 }; 177 178 cooling-maps { 179 map0 { 180 trip = <&cpu_passive>; 181 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 182 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 183 }; 184 185 map1 { 186 trip = <&cpu_active>; 187 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 188 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 189 }; 190 191 map2 { 192 trip = <&cpu_hot>; 193 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 194 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 195 }; 196 }; 197 }; 198 }; 199 200 timer { 201 compatible = "arm,armv8-timer"; 202 interrupt-parent = <&gic>; 203 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | 204 IRQ_TYPE_LEVEL_HIGH)>, 205 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | 206 IRQ_TYPE_LEVEL_HIGH)>, 207 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | 208 IRQ_TYPE_LEVEL_HIGH)>, 209 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | 210 IRQ_TYPE_LEVEL_HIGH)>; 211 }; 212 213 infracfg: infracfg@10000000 { 214 compatible = "mediatek,mt7622-infracfg", 215 "syscon"; 216 reg = <0 0x10000000 0 0x1000>; 217 #clock-cells = <1>; 218 #reset-cells = <1>; 219 }; 220 221 pwrap: pwrap@10001000 { 222 compatible = "mediatek,mt7622-pwrap"; 223 reg = <0 0x10001000 0 0x250>; 224 reg-names = "pwrap"; 225 clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>; 226 clock-names = "spi", "wrap"; 227 resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>; 228 reset-names = "pwrap"; 229 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 230 status = "disabled"; 231 }; 232 233 pericfg: pericfg@10002000 { 234 compatible = "mediatek,mt7622-pericfg", 235 "syscon"; 236 reg = <0 0x10002000 0 0x1000>; 237 #clock-cells = <1>; 238 #reset-cells = <1>; 239 }; 240 241 scpsys: power-controller@10006000 { 242 compatible = "mediatek,mt7622-scpsys", 243 "syscon"; 244 #power-domain-cells = <1>; 245 reg = <0 0x10006000 0 0x1000>; 246 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>, 247 <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>, 248 <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>, 249 <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>; 250 infracfg = <&infracfg>; 251 clocks = <&topckgen CLK_TOP_HIF_SEL>; 252 clock-names = "hif_sel"; 253 }; 254 255 cir: ir-receiver@10009000 { 256 compatible = "mediatek,mt7622-cir"; 257 reg = <0 0x10009000 0 0x1000>; 258 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>; 259 clocks = <&infracfg CLK_INFRA_IRRX_PD>, 260 <&topckgen CLK_TOP_AXI_SEL>; 261 clock-names = "clk", "bus"; 262 status = "disabled"; 263 }; 264 265 sysirq: interrupt-controller@10200620 { 266 compatible = "mediatek,mt7622-sysirq", 267 "mediatek,mt6577-sysirq"; 268 interrupt-controller; 269 #interrupt-cells = <3>; 270 interrupt-parent = <&gic>; 271 reg = <0 0x10200620 0 0x20>; 272 }; 273 274 efuse: efuse@10206000 { 275 compatible = "mediatek,mt7622-efuse", 276 "mediatek,efuse"; 277 reg = <0 0x10206000 0 0x1000>; 278 #address-cells = <1>; 279 #size-cells = <1>; 280 281 soc-uuid@140 { 282 reg = <0x140 0x8>; 283 }; 284 285 thermal_calibration: calib@198 { 286 reg = <0x198 0xc>; 287 }; 288 }; 289 290 apmixedsys: clock-controller@10209000 { 291 compatible = "mediatek,mt7622-apmixedsys"; 292 reg = <0 0x10209000 0 0x1000>; 293 #clock-cells = <1>; 294 }; 295 296 topckgen: clock-controller@10210000 { 297 compatible = "mediatek,mt7622-topckgen"; 298 reg = <0 0x10210000 0 0x1000>; 299 #clock-cells = <1>; 300 }; 301 302 rng: rng@1020f000 { 303 compatible = "mediatek,mt7622-rng", 304 "mediatek,mt7623-rng"; 305 reg = <0 0x1020f000 0 0x1000>; 306 clocks = <&infracfg CLK_INFRA_TRNG>; 307 clock-names = "rng"; 308 }; 309 310 pio: pinctrl@10211000 { 311 compatible = "mediatek,mt7622-pinctrl"; 312 reg = <0 0x10211000 0 0x1000>, 313 <0 0x10005000 0 0x1000>; 314 reg-names = "base", "eint"; 315 gpio-controller; 316 #gpio-cells = <2>; 317 gpio-ranges = <&pio 0 0 103>; 318 interrupt-controller; 319 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 320 interrupt-parent = <&gic>; 321 #interrupt-cells = <2>; 322 }; 323 324 watchdog: watchdog@10212000 { 325 compatible = "mediatek,mt7622-wdt", 326 "mediatek,mt6589-wdt"; 327 reg = <0 0x10212000 0 0x800>; 328 }; 329 330 rtc: rtc@10212800 { 331 compatible = "mediatek,mt7622-rtc", 332 "mediatek,soc-rtc"; 333 reg = <0 0x10212800 0 0x200>; 334 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; 335 clocks = <&topckgen CLK_TOP_RTC>; 336 clock-names = "rtc"; 337 }; 338 339 gic: interrupt-controller@10300000 { 340 compatible = "arm,gic-400"; 341 interrupt-controller; 342 #interrupt-cells = <3>; 343 interrupt-parent = <&gic>; 344 reg = <0 0x10310000 0 0x1000>, 345 <0 0x10320000 0 0x1000>, 346 <0 0x10340000 0 0x2000>, 347 <0 0x10360000 0 0x2000>; 348 }; 349 350 cci: cci@10390000 { 351 compatible = "arm,cci-400"; 352 #address-cells = <1>; 353 #size-cells = <1>; 354 reg = <0 0x10390000 0 0x1000>; 355 ranges = <0 0 0x10390000 0x10000>; 356 357 cci_control0: slave-if@1000 { 358 compatible = "arm,cci-400-ctrl-if"; 359 interface-type = "ace-lite"; 360 reg = <0x1000 0x1000>; 361 }; 362 363 cci_control1: slave-if@4000 { 364 compatible = "arm,cci-400-ctrl-if"; 365 interface-type = "ace"; 366 reg = <0x4000 0x1000>; 367 }; 368 369 cci_control2: slave-if@5000 { 370 compatible = "arm,cci-400-ctrl-if", "syscon"; 371 interface-type = "ace"; 372 reg = <0x5000 0x1000>; 373 }; 374 375 pmu@9000 { 376 compatible = "arm,cci-400-pmu,r1"; 377 reg = <0x9000 0x5000>; 378 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 379 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 380 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 381 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 382 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 383 }; 384 }; 385 386 auxadc: adc@11001000 { 387 compatible = "mediatek,mt7622-auxadc"; 388 reg = <0 0x11001000 0 0x1000>; 389 clocks = <&pericfg CLK_PERI_AUXADC_PD>; 390 clock-names = "main"; 391 #io-channel-cells = <1>; 392 }; 393 394 uart0: serial@11002000 { 395 compatible = "mediatek,mt7622-uart", 396 "mediatek,mt6577-uart"; 397 reg = <0 0x11002000 0 0x400>; 398 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 399 clocks = <&topckgen CLK_TOP_UART_SEL>, 400 <&pericfg CLK_PERI_UART0_PD>; 401 clock-names = "baud", "bus"; 402 status = "disabled"; 403 }; 404 405 uart1: serial@11003000 { 406 compatible = "mediatek,mt7622-uart", 407 "mediatek,mt6577-uart"; 408 reg = <0 0x11003000 0 0x400>; 409 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 410 clocks = <&topckgen CLK_TOP_UART_SEL>, 411 <&pericfg CLK_PERI_UART1_PD>; 412 clock-names = "baud", "bus"; 413 status = "disabled"; 414 }; 415 416 uart2: serial@11004000 { 417 compatible = "mediatek,mt7622-uart", 418 "mediatek,mt6577-uart"; 419 reg = <0 0x11004000 0 0x400>; 420 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 421 clocks = <&topckgen CLK_TOP_UART_SEL>, 422 <&pericfg CLK_PERI_UART2_PD>; 423 clock-names = "baud", "bus"; 424 status = "disabled"; 425 }; 426 427 uart3: serial@11005000 { 428 compatible = "mediatek,mt7622-uart", 429 "mediatek,mt6577-uart"; 430 reg = <0 0x11005000 0 0x400>; 431 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 432 clocks = <&topckgen CLK_TOP_UART_SEL>, 433 <&pericfg CLK_PERI_UART3_PD>; 434 clock-names = "baud", "bus"; 435 status = "disabled"; 436 }; 437 438 pwm: pwm@11006000 { 439 compatible = "mediatek,mt7622-pwm"; 440 reg = <0 0x11006000 0 0x1000>; 441 #pwm-cells = <2>; 442 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 443 clocks = <&topckgen CLK_TOP_PWM_SEL>, 444 <&pericfg CLK_PERI_PWM_PD>, 445 <&pericfg CLK_PERI_PWM1_PD>, 446 <&pericfg CLK_PERI_PWM2_PD>, 447 <&pericfg CLK_PERI_PWM3_PD>, 448 <&pericfg CLK_PERI_PWM4_PD>, 449 <&pericfg CLK_PERI_PWM5_PD>, 450 <&pericfg CLK_PERI_PWM6_PD>; 451 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", 452 "pwm5", "pwm6"; 453 status = "disabled"; 454 }; 455 456 i2c0: i2c@11007000 { 457 compatible = "mediatek,mt7622-i2c"; 458 reg = <0 0x11007000 0 0x90>, 459 <0 0x11000100 0 0x80>; 460 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 461 clock-div = <16>; 462 clocks = <&pericfg CLK_PERI_I2C0_PD>, 463 <&pericfg CLK_PERI_AP_DMA_PD>; 464 clock-names = "main", "dma"; 465 #address-cells = <1>; 466 #size-cells = <0>; 467 status = "disabled"; 468 }; 469 470 i2c1: i2c@11008000 { 471 compatible = "mediatek,mt7622-i2c"; 472 reg = <0 0x11008000 0 0x90>, 473 <0 0x11000180 0 0x80>; 474 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 475 clock-div = <16>; 476 clocks = <&pericfg CLK_PERI_I2C1_PD>, 477 <&pericfg CLK_PERI_AP_DMA_PD>; 478 clock-names = "main", "dma"; 479 #address-cells = <1>; 480 #size-cells = <0>; 481 status = "disabled"; 482 }; 483 484 i2c2: i2c@11009000 { 485 compatible = "mediatek,mt7622-i2c"; 486 reg = <0 0x11009000 0 0x90>, 487 <0 0x11000200 0 0x80>; 488 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 489 clock-div = <16>; 490 clocks = <&pericfg CLK_PERI_I2C2_PD>, 491 <&pericfg CLK_PERI_AP_DMA_PD>; 492 clock-names = "main", "dma"; 493 #address-cells = <1>; 494 #size-cells = <0>; 495 status = "disabled"; 496 }; 497 498 spi0: spi@1100a000 { 499 compatible = "mediatek,mt7622-spi"; 500 reg = <0 0x1100a000 0 0x100>; 501 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>; 502 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 503 <&topckgen CLK_TOP_SPI0_SEL>, 504 <&pericfg CLK_PERI_SPI0_PD>; 505 clock-names = "parent-clk", "sel-clk", "spi-clk"; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 status = "disabled"; 509 }; 510 511 thermal: thermal@1100b000 { 512 #thermal-sensor-cells = <1>; 513 compatible = "mediatek,mt7622-thermal"; 514 reg = <0 0x1100b000 0 0x1000>; 515 interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>; 516 clocks = <&pericfg CLK_PERI_THERM_PD>, 517 <&pericfg CLK_PERI_AUXADC_PD>; 518 clock-names = "therm", "auxadc"; 519 resets = <&pericfg MT7622_PERI_THERM_SW_RST>; 520 mediatek,auxadc = <&auxadc>; 521 mediatek,apmixedsys = <&apmixedsys>; 522 nvmem-cells = <&thermal_calibration>; 523 nvmem-cell-names = "calibration-data"; 524 }; 525 526 btif: serial@1100c000 { 527 compatible = "mediatek,mt7622-btif", 528 "mediatek,mtk-btif"; 529 reg = <0 0x1100c000 0 0x1000>; 530 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; 531 clocks = <&pericfg CLK_PERI_BTIF_PD>; 532 reg-shift = <2>; 533 reg-io-width = <4>; 534 status = "disabled"; 535 536 bluetooth { 537 compatible = "mediatek,mt7622-bluetooth"; 538 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; 539 clocks = <&clk25m>; 540 clock-names = "ref"; 541 }; 542 }; 543 544 nandc: nand-controller@1100d000 { 545 compatible = "mediatek,mt7622-nfc"; 546 reg = <0 0x1100D000 0 0x1000>; 547 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 548 clocks = <&pericfg CLK_PERI_NFI_PD>, 549 <&pericfg CLK_PERI_SNFI_PD>; 550 clock-names = "nfi_clk", "pad_clk"; 551 ecc-engine = <&bch>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 status = "disabled"; 555 }; 556 557 snfi: spi@1100d000 { 558 compatible = "mediatek,mt7622-snand"; 559 reg = <0 0x1100d000 0 0x1000>; 560 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 561 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; 562 clock-names = "nfi_clk", "pad_clk"; 563 nand-ecc-engine = <&bch>; 564 #address-cells = <1>; 565 #size-cells = <0>; 566 status = "disabled"; 567 }; 568 569 bch: ecc@1100e000 { 570 compatible = "mediatek,mt7622-ecc"; 571 reg = <0 0x1100e000 0 0x1000>; 572 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; 573 clocks = <&pericfg CLK_PERI_NFIECC_PD>; 574 clock-names = "nfiecc_clk"; 575 status = "disabled"; 576 }; 577 578 nor_flash: spi@11014000 { 579 compatible = "mediatek,mt7622-nor", 580 "mediatek,mt8173-nor"; 581 reg = <0 0x11014000 0 0xe0>; 582 clocks = <&pericfg CLK_PERI_FLASH_PD>, 583 <&topckgen CLK_TOP_FLASH_SEL>; 584 clock-names = "spi", "sf"; 585 #address-cells = <1>; 586 #size-cells = <0>; 587 status = "disabled"; 588 }; 589 590 spi1: spi@11016000 { 591 compatible = "mediatek,mt7622-spi"; 592 reg = <0 0x11016000 0 0x100>; 593 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; 594 clocks = <&topckgen CLK_TOP_SYSPLL3_D2>, 595 <&topckgen CLK_TOP_SPI1_SEL>, 596 <&pericfg CLK_PERI_SPI1_PD>; 597 clock-names = "parent-clk", "sel-clk", "spi-clk"; 598 #address-cells = <1>; 599 #size-cells = <0>; 600 status = "disabled"; 601 }; 602 603 uart4: serial@11019000 { 604 compatible = "mediatek,mt7622-uart", 605 "mediatek,mt6577-uart"; 606 reg = <0 0x11019000 0 0x400>; 607 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 608 clocks = <&topckgen CLK_TOP_UART_SEL>, 609 <&pericfg CLK_PERI_UART4_PD>; 610 clock-names = "baud", "bus"; 611 status = "disabled"; 612 }; 613 614 audsys: clock-controller@11220000 { 615 compatible = "mediatek,mt7622-audsys", "syscon"; 616 reg = <0 0x11220000 0 0x2000>; 617 #clock-cells = <1>; 618 619 afe: audio-controller { 620 compatible = "mediatek,mt7622-audio"; 621 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>, 622 <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 623 interrupt-names = "afe", "asys"; 624 625 clocks = <&infracfg CLK_INFRA_AUDIO_PD>, 626 <&topckgen CLK_TOP_AUD1_SEL>, 627 <&topckgen CLK_TOP_AUD2_SEL>, 628 <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>, 629 <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>, 630 <&topckgen CLK_TOP_I2S0_MCK_SEL>, 631 <&topckgen CLK_TOP_I2S1_MCK_SEL>, 632 <&topckgen CLK_TOP_I2S2_MCK_SEL>, 633 <&topckgen CLK_TOP_I2S3_MCK_SEL>, 634 <&topckgen CLK_TOP_I2S0_MCK_DIV>, 635 <&topckgen CLK_TOP_I2S1_MCK_DIV>, 636 <&topckgen CLK_TOP_I2S2_MCK_DIV>, 637 <&topckgen CLK_TOP_I2S3_MCK_DIV>, 638 <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>, 639 <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>, 640 <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>, 641 <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>, 642 <&audsys CLK_AUDIO_I2SO1>, 643 <&audsys CLK_AUDIO_I2SO2>, 644 <&audsys CLK_AUDIO_I2SO3>, 645 <&audsys CLK_AUDIO_I2SO4>, 646 <&audsys CLK_AUDIO_I2SIN1>, 647 <&audsys CLK_AUDIO_I2SIN2>, 648 <&audsys CLK_AUDIO_I2SIN3>, 649 <&audsys CLK_AUDIO_I2SIN4>, 650 <&audsys CLK_AUDIO_ASRCO1>, 651 <&audsys CLK_AUDIO_ASRCO2>, 652 <&audsys CLK_AUDIO_ASRCO3>, 653 <&audsys CLK_AUDIO_ASRCO4>, 654 <&audsys CLK_AUDIO_AFE>, 655 <&audsys CLK_AUDIO_AFE_CONN>, 656 <&audsys CLK_AUDIO_A1SYS>, 657 <&audsys CLK_AUDIO_A2SYS>; 658 659 clock-names = "infra_sys_audio_clk", 660 "top_audio_mux1_sel", 661 "top_audio_mux2_sel", 662 "top_audio_a1sys_hp", 663 "top_audio_a2sys_hp", 664 "i2s0_src_sel", 665 "i2s1_src_sel", 666 "i2s2_src_sel", 667 "i2s3_src_sel", 668 "i2s0_src_div", 669 "i2s1_src_div", 670 "i2s2_src_div", 671 "i2s3_src_div", 672 "i2s0_mclk_en", 673 "i2s1_mclk_en", 674 "i2s2_mclk_en", 675 "i2s3_mclk_en", 676 "i2so0_hop_ck", 677 "i2so1_hop_ck", 678 "i2so2_hop_ck", 679 "i2so3_hop_ck", 680 "i2si0_hop_ck", 681 "i2si1_hop_ck", 682 "i2si2_hop_ck", 683 "i2si3_hop_ck", 684 "asrc0_out_ck", 685 "asrc1_out_ck", 686 "asrc2_out_ck", 687 "asrc3_out_ck", 688 "audio_afe_pd", 689 "audio_afe_conn_pd", 690 "audio_a1sys_pd", 691 "audio_a2sys_pd"; 692 693 assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>, 694 <&topckgen CLK_TOP_A2SYS_HP_SEL>, 695 <&topckgen CLK_TOP_A1SYS_HP_DIV>, 696 <&topckgen CLK_TOP_A2SYS_HP_DIV>; 697 assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>, 698 <&topckgen CLK_TOP_AUD2PLL>; 699 assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; 700 }; 701 }; 702 703 mmc0: mmc@11230000 { 704 compatible = "mediatek,mt7622-mmc"; 705 reg = <0 0x11230000 0 0x1000>; 706 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 707 clocks = <&pericfg CLK_PERI_MSDC30_0_PD>, 708 <&topckgen CLK_TOP_MSDC50_0_SEL>; 709 clock-names = "source", "hclk"; 710 resets = <&pericfg MT7622_PERI_MSDC0_SW_RST>; 711 reset-names = "hrst"; 712 status = "disabled"; 713 }; 714 715 mmc1: mmc@11240000 { 716 compatible = "mediatek,mt7622-mmc"; 717 reg = <0 0x11240000 0 0x1000>; 718 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 719 clocks = <&pericfg CLK_PERI_MSDC30_1_PD>, 720 <&topckgen CLK_TOP_AXI_SEL>; 721 clock-names = "source", "hclk"; 722 resets = <&pericfg MT7622_PERI_MSDC1_SW_RST>; 723 reset-names = "hrst"; 724 status = "disabled"; 725 }; 726 727 wmac: wmac@18000000 { 728 compatible = "mediatek,mt7622-wmac"; 729 reg = <0 0x18000000 0 0x100000>; 730 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>; 731 732 mediatek,infracfg = <&infracfg>; 733 status = "disabled"; 734 735 power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>; 736 }; 737 738 ssusbsys: clock-controller@1a000000 { 739 compatible = "mediatek,mt7622-ssusbsys"; 740 reg = <0 0x1a000000 0 0x1000>; 741 #clock-cells = <1>; 742 #reset-cells = <1>; 743 }; 744 745 ssusb: usb@1a0c0000 { 746 compatible = "mediatek,mt7622-xhci", 747 "mediatek,mtk-xhci"; 748 reg = <0 0x1a0c0000 0 0x01000>, 749 <0 0x1a0c4700 0 0x0100>; 750 reg-names = "mac", "ippc"; 751 interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>; 752 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>; 753 clocks = <&ssusbsys CLK_SSUSB_SYS_EN>, 754 <&ssusbsys CLK_SSUSB_REF_EN>, 755 <&ssusbsys CLK_SSUSB_MCU_EN>, 756 <&ssusbsys CLK_SSUSB_DMA_EN>; 757 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck"; 758 phys = <&u2port0 PHY_TYPE_USB2>, 759 <&u3port0 PHY_TYPE_USB3>, 760 <&u2port1 PHY_TYPE_USB2>; 761 762 status = "disabled"; 763 }; 764 765 u3phy: t-phy@1a0c4000 { 766 compatible = "mediatek,mt7622-tphy", 767 "mediatek,generic-tphy-v1"; 768 reg = <0 0x1a0c4000 0 0x700>; 769 #address-cells = <2>; 770 #size-cells = <2>; 771 ranges; 772 status = "disabled"; 773 774 u2port0: usb-phy@1a0c4800 { 775 reg = <0 0x1a0c4800 0 0x0100>; 776 #phy-cells = <1>; 777 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>; 778 clock-names = "ref"; 779 }; 780 781 u3port0: usb-phy@1a0c4900 { 782 reg = <0 0x1a0c4900 0 0x0700>; 783 #phy-cells = <1>; 784 clocks = <&clk25m>; 785 clock-names = "ref"; 786 }; 787 788 u2port1: usb-phy@1a0c5000 { 789 reg = <0 0x1a0c5000 0 0x0100>; 790 #phy-cells = <1>; 791 clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>; 792 clock-names = "ref"; 793 }; 794 }; 795 796 pciesys: clock-controller@1a100800 { 797 compatible = "mediatek,mt7622-pciesys"; 798 reg = <0 0x1a100800 0 0x1000>; 799 #clock-cells = <1>; 800 #reset-cells = <1>; 801 }; 802 803 pciecfg: pciecfg@1a140000 { 804 compatible = "mediatek,generic-pciecfg", "syscon"; 805 reg = <0 0x1a140000 0 0x1000>; 806 }; 807 808 pcie0: pcie@1a143000 { 809 compatible = "mediatek,mt7622-pcie"; 810 device_type = "pci"; 811 reg = <0 0x1a143000 0 0x1000>; 812 reg-names = "port0"; 813 linux,pci-domain = <0>; 814 #address-cells = <3>; 815 #size-cells = <2>; 816 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>; 817 interrupt-names = "pcie_irq"; 818 clocks = <&pciesys CLK_PCIE_P0_MAC_EN>, 819 <&pciesys CLK_PCIE_P0_AHB_EN>, 820 <&pciesys CLK_PCIE_P0_AUX_EN>, 821 <&pciesys CLK_PCIE_P0_AXI_EN>, 822 <&pciesys CLK_PCIE_P0_OBFF_EN>, 823 <&pciesys CLK_PCIE_P0_PIPE_EN>; 824 clock-names = "sys_ck0", "ahb_ck0", "aux_ck0", 825 "axi_ck0", "obff_ck0", "pipe_ck0"; 826 827 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 828 bus-range = <0x00 0xff>; 829 ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>; 830 status = "disabled"; 831 832 #interrupt-cells = <1>; 833 interrupt-map-mask = <0 0 0 7>; 834 interrupt-map = <0 0 0 1 &pcie_intc0 0>, 835 <0 0 0 2 &pcie_intc0 1>, 836 <0 0 0 3 &pcie_intc0 2>, 837 <0 0 0 4 &pcie_intc0 3>; 838 pcie_intc0: interrupt-controller { 839 interrupt-controller; 840 #address-cells = <0>; 841 #interrupt-cells = <1>; 842 }; 843 }; 844 845 pcie1: pcie@1a145000 { 846 compatible = "mediatek,mt7622-pcie"; 847 device_type = "pci"; 848 reg = <0 0x1a145000 0 0x1000>; 849 reg-names = "port1"; 850 linux,pci-domain = <1>; 851 #address-cells = <3>; 852 #size-cells = <2>; 853 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>; 854 interrupt-names = "pcie_irq"; 855 clocks = <&pciesys CLK_PCIE_P1_MAC_EN>, 856 /* designer has connect RC1 with p0_ahb clock */ 857 <&pciesys CLK_PCIE_P0_AHB_EN>, 858 <&pciesys CLK_PCIE_P1_AUX_EN>, 859 <&pciesys CLK_PCIE_P1_AXI_EN>, 860 <&pciesys CLK_PCIE_P1_OBFF_EN>, 861 <&pciesys CLK_PCIE_P1_PIPE_EN>; 862 clock-names = "sys_ck1", "ahb_ck1", "aux_ck1", 863 "axi_ck1", "obff_ck1", "pipe_ck1"; 864 865 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 866 bus-range = <0x00 0xff>; 867 ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>; 868 status = "disabled"; 869 870 #interrupt-cells = <1>; 871 interrupt-map-mask = <0 0 0 7>; 872 interrupt-map = <0 0 0 1 &pcie_intc1 0>, 873 <0 0 0 2 &pcie_intc1 1>, 874 <0 0 0 3 &pcie_intc1 2>, 875 <0 0 0 4 &pcie_intc1 3>; 876 pcie_intc1: interrupt-controller { 877 interrupt-controller; 878 #address-cells = <0>; 879 #interrupt-cells = <1>; 880 }; 881 }; 882 883 sata: sata@1a200000 { 884 compatible = "mediatek,mt7622-ahci", 885 "mediatek,mtk-ahci"; 886 reg = <0 0x1a200000 0 0x1100>; 887 interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; 888 interrupt-names = "hostc"; 889 clocks = <&pciesys CLK_SATA_AHB_EN>, 890 <&pciesys CLK_SATA_AXI_EN>, 891 <&pciesys CLK_SATA_ASIC_EN>, 892 <&pciesys CLK_SATA_RBC_EN>, 893 <&pciesys CLK_SATA_PM_EN>; 894 clock-names = "ahb", "axi", "asic", "rbc", "pm"; 895 phys = <&sata_port PHY_TYPE_SATA>; 896 phy-names = "sata-phy"; 897 ports-implemented = <0x1>; 898 power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>; 899 resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, 900 <&pciesys MT7622_SATA_PHY_SW_RST>, 901 <&pciesys MT7622_SATA_PHY_REG_RST>; 902 reset-names = "axi", "sw", "reg"; 903 mediatek,phy-mode = <&pciesys>; 904 status = "disabled"; 905 }; 906 907 sata_phy: t-phy { 908 compatible = "mediatek,mt7622-tphy", 909 "mediatek,generic-tphy-v1"; 910 #address-cells = <2>; 911 #size-cells = <2>; 912 ranges; 913 status = "disabled"; 914 915 sata_port: sata-phy@1a243000 { 916 reg = <0 0x1a243000 0 0x0100>; 917 clocks = <&topckgen CLK_TOP_ETH_500M>; 918 clock-names = "ref"; 919 #phy-cells = <1>; 920 }; 921 }; 922 923 hifsys: clock-controller@1af00000 { 924 compatible = "mediatek,mt7622-hifsys"; 925 reg = <0 0x1af00000 0 0x70>; 926 #clock-cells = <1>; 927 }; 928 929 ethsys: clock-controller@1b000000 { 930 compatible = "mediatek,mt7622-ethsys", 931 "syscon"; 932 reg = <0 0x1b000000 0 0x1000>; 933 #clock-cells = <1>; 934 #reset-cells = <1>; 935 }; 936 937 hsdma: dma-controller@1b007000 { 938 compatible = "mediatek,mt7622-hsdma"; 939 reg = <0 0x1b007000 0 0x1000>; 940 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>; 941 clocks = <ðsys CLK_ETH_HSDMA_EN>; 942 clock-names = "hsdma"; 943 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; 944 #dma-cells = <1>; 945 dma-requests = <3>; 946 }; 947 948 pcie_mirror: pcie-mirror@10000400 { 949 compatible = "mediatek,mt7622-pcie-mirror", 950 "syscon"; 951 reg = <0 0x10000400 0 0x10>; 952 }; 953 954 wed0: wed@1020a000 { 955 compatible = "mediatek,mt7622-wed", 956 "syscon"; 957 reg = <0 0x1020a000 0 0x1000>; 958 interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_LOW>; 959 }; 960 961 wed1: wed@1020b000 { 962 compatible = "mediatek,mt7622-wed", 963 "syscon"; 964 reg = <0 0x1020b000 0 0x1000>; 965 interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_LOW>; 966 }; 967 968 eth: ethernet@1b100000 { 969 compatible = "mediatek,mt7622-eth"; 970 reg = <0 0x1b100000 0 0x20000>; 971 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>, 972 <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>, 973 <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>; 974 clocks = <&topckgen CLK_TOP_ETH_SEL>, 975 <ðsys CLK_ETH_ESW_EN>, 976 <ðsys CLK_ETH_GP0_EN>, 977 <ðsys CLK_ETH_GP1_EN>, 978 <ðsys CLK_ETH_GP2_EN>, 979 <&sgmiisys CLK_SGMII_TX250M_EN>, 980 <&sgmiisys CLK_SGMII_RX250M_EN>, 981 <&sgmiisys CLK_SGMII_CDR_REF>, 982 <&sgmiisys CLK_SGMII_CDR_FB>, 983 <&topckgen CLK_TOP_SGMIIPLL>, 984 <&apmixedsys CLK_APMIXED_ETH2PLL>; 985 clock-names = "ethif", "esw", "gp0", "gp1", "gp2", 986 "sgmii_tx250m", "sgmii_rx250m", 987 "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", 988 "eth2pll"; 989 power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>; 990 mediatek,ethsys = <ðsys>; 991 mediatek,sgmiisys = <&sgmiisys>; 992 cci-control-port = <&cci_control2>; 993 mediatek,wed = <&wed0>, <&wed1>; 994 mediatek,pcie-mirror = <&pcie_mirror>; 995 mediatek,hifsys = <&hifsys>; 996 dma-coherent; 997 #address-cells = <1>; 998 #size-cells = <0>; 999 status = "disabled"; 1000 }; 1001 1002 sgmiisys: sgmiisys@1b128000 { 1003 compatible = "mediatek,mt7622-sgmiisys", 1004 "syscon"; 1005 reg = <0 0x1b128000 0 0x3000>; 1006 #clock-cells = <1>; 1007 }; 1008};
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