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mt6795.dtsi
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linux-6.19.14/arch/arm64/boot/dts/mediatek/mt6795.dtsi
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Copyright (C) 2023 Collabora Ltd. 5 * Authors: Mars.C <mars.cheng@mediatek.com> 6 * AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 7 */ 8 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/clock/mediatek,mt6795-clk.h> 12#include <dt-bindings/gce/mediatek,mt6795-gce.h> 13#include <dt-bindings/memory/mt6795-larb-port.h> 14#include <dt-bindings/pinctrl/mt6795-pinfunc.h> 15#include <dt-bindings/power/mt6795-power.h> 16#include <dt-bindings/reset/mediatek,mt6795-resets.h> 17 18/ { 19 compatible = "mediatek,mt6795"; 20 interrupt-parent = <&sysirq>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ovl0 = &ovl0; 26 ovl1 = &ovl1; 27 rdma0 = &rdma0; 28 rdma1 = &rdma1; 29 rdma2 = &rdma2; 30 wdma0 = &wdma0; 31 wdma1 = &wdma1; 32 color0 = &color0; 33 color1 = &color1; 34 split0 = &split0; 35 split1 = &split1; 36 dpi0 = &dpi0; 37 dsi0 = &dsi0; 38 dsi1 = &dsi1; 39 }; 40 41 psci { 42 compatible = "arm,psci-0.2"; 43 method = "smc"; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 device_type = "cpu"; 52 compatible = "arm,cortex-a53"; 53 enable-method = "psci"; 54 reg = <0x000>; 55 cci-control-port = <&cci_control2>; 56 next-level-cache = <&l2_0>; 57 }; 58 59 cpu1: cpu@1 { 60 device_type = "cpu"; 61 compatible = "arm,cortex-a53"; 62 enable-method = "psci"; 63 reg = <0x001>; 64 cci-control-port = <&cci_control2>; 65 i-cache-size = <32768>; 66 i-cache-line-size = <64>; 67 i-cache-sets = <256>; 68 d-cache-size = <32768>; 69 d-cache-line-size = <64>; 70 d-cache-sets = <128>; 71 next-level-cache = <&l2_0>; 72 }; 73 74 cpu2: cpu@2 { 75 device_type = "cpu"; 76 compatible = "arm,cortex-a53"; 77 enable-method = "psci"; 78 reg = <0x002>; 79 cci-control-port = <&cci_control2>; 80 i-cache-size = <32768>; 81 i-cache-line-size = <64>; 82 i-cache-sets = <256>; 83 d-cache-size = <32768>; 84 d-cache-line-size = <64>; 85 d-cache-sets = <128>; 86 next-level-cache = <&l2_0>; 87 }; 88 89 cpu3: cpu@3 { 90 device_type = "cpu"; 91 compatible = "arm,cortex-a53"; 92 enable-method = "psci"; 93 reg = <0x003>; 94 cci-control-port = <&cci_control2>; 95 i-cache-size = <32768>; 96 i-cache-line-size = <64>; 97 i-cache-sets = <256>; 98 d-cache-size = <32768>; 99 d-cache-line-size = <64>; 100 d-cache-sets = <128>; 101 next-level-cache = <&l2_0>; 102 }; 103 104 cpu4: cpu@100 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a53"; 107 enable-method = "psci"; 108 reg = <0x100>; 109 cci-control-port = <&cci_control1>; 110 i-cache-size = <32768>; 111 i-cache-line-size = <64>; 112 i-cache-sets = <256>; 113 d-cache-size = <32768>; 114 d-cache-line-size = <64>; 115 d-cache-sets = <128>; 116 next-level-cache = <&l2_1>; 117 }; 118 119 cpu5: cpu@101 { 120 device_type = "cpu"; 121 compatible = "arm,cortex-a53"; 122 enable-method = "psci"; 123 reg = <0x101>; 124 cci-control-port = <&cci_control1>; 125 i-cache-size = <32768>; 126 i-cache-line-size = <64>; 127 i-cache-sets = <256>; 128 d-cache-size = <32768>; 129 d-cache-line-size = <64>; 130 d-cache-sets = <128>; 131 next-level-cache = <&l2_1>; 132 }; 133 134 cpu6: cpu@102 { 135 device_type = "cpu"; 136 compatible = "arm,cortex-a53"; 137 enable-method = "psci"; 138 reg = <0x102>; 139 cci-control-port = <&cci_control1>; 140 i-cache-size = <32768>; 141 i-cache-line-size = <64>; 142 i-cache-sets = <256>; 143 d-cache-size = <32768>; 144 d-cache-line-size = <64>; 145 d-cache-sets = <128>; 146 next-level-cache = <&l2_1>; 147 }; 148 149 cpu7: cpu@103 { 150 device_type = "cpu"; 151 compatible = "arm,cortex-a53"; 152 enable-method = "psci"; 153 reg = <0x103>; 154 cci-control-port = <&cci_control1>; 155 i-cache-size = <32768>; 156 i-cache-line-size = <64>; 157 i-cache-sets = <256>; 158 d-cache-size = <32768>; 159 d-cache-line-size = <64>; 160 d-cache-sets = <128>; 161 next-level-cache = <&l2_1>; 162 }; 163 164 cpu-map { 165 cluster0 { 166 core0 { 167 cpu = <&cpu0>; 168 }; 169 170 core1 { 171 cpu = <&cpu1>; 172 }; 173 174 core2 { 175 cpu = <&cpu2>; 176 }; 177 178 core3 { 179 cpu = <&cpu3>; 180 }; 181 }; 182 183 cluster1 { 184 core0 { 185 cpu = <&cpu4>; 186 }; 187 188 core1 { 189 cpu = <&cpu5>; 190 }; 191 192 core2 { 193 cpu = <&cpu6>; 194 }; 195 196 core3 { 197 cpu = <&cpu7>; 198 }; 199 }; 200 }; 201 202 l2_0: l2-cache0 { 203 compatible = "cache"; 204 cache-level = <2>; 205 cache-size = <1048576>; 206 cache-line-size = <64>; 207 cache-sets = <1024>; 208 cache-unified; 209 }; 210 211 l2_1: l2-cache1 { 212 compatible = "cache"; 213 cache-level = <2>; 214 cache-size = <1048576>; 215 cache-line-size = <64>; 216 cache-sets = <1024>; 217 cache-unified; 218 }; 219 }; 220 221 clk26m: oscillator-26m { 222 compatible = "fixed-clock"; 223 #clock-cells = <0>; 224 clock-frequency = <26000000>; 225 clock-output-names = "clk26m"; 226 }; 227 228 clk32k: oscillator-32k { 229 compatible = "fixed-clock"; 230 #clock-cells = <0>; 231 clock-frequency = <32000>; 232 clock-output-names = "clk32k"; 233 }; 234 235 system_clk: dummy13m { 236 compatible = "fixed-clock"; 237 clock-frequency = <13000000>; 238 #clock-cells = <0>; 239 }; 240 241 pmu { 242 compatible = "arm,cortex-a53-pmu"; 243 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_LOW>, 244 <GIC_SPI 9 IRQ_TYPE_LEVEL_LOW>, 245 <GIC_SPI 10 IRQ_TYPE_LEVEL_LOW>, 246 <GIC_SPI 11 IRQ_TYPE_LEVEL_LOW>; 247 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 248 }; 249 250 timer { 251 compatible = "arm,armv8-timer"; 252 interrupt-parent = <&gic>; 253 interrupts = <GIC_PPI 13 254 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 255 <GIC_PPI 14 256 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 257 <GIC_PPI 11 258 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 259 <GIC_PPI 10 260 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 261 }; 262 263 soc { 264 #address-cells = <2>; 265 #size-cells = <2>; 266 compatible = "simple-bus"; 267 ranges; 268 269 topckgen: syscon@10000000 { 270 compatible = "mediatek,mt6795-topckgen", "syscon"; 271 reg = <0 0x10000000 0 0x1000>; 272 #clock-cells = <1>; 273 }; 274 275 infracfg: syscon@10001000 { 276 compatible = "mediatek,mt6795-infracfg", "syscon"; 277 reg = <0 0x10001000 0 0x1000>; 278 #clock-cells = <1>; 279 #reset-cells = <1>; 280 }; 281 282 pericfg: syscon@10003000 { 283 compatible = "mediatek,mt6795-pericfg", "syscon"; 284 reg = <0 0x10003000 0 0x1000>; 285 #clock-cells = <1>; 286 #reset-cells = <1>; 287 }; 288 289 scpsys: syscon@10006000 { 290 compatible = "syscon", "simple-mfd"; 291 reg = <0 0x10006000 0 0x1000>; 292 #power-domain-cells = <1>; 293 294 /* System Power Manager */ 295 spm: power-controller { 296 compatible = "mediatek,mt6795-power-controller"; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 #power-domain-cells = <1>; 300 301 /* power domains of the SoC */ 302 power-domain@MT6795_POWER_DOMAIN_VDEC { 303 reg = <MT6795_POWER_DOMAIN_VDEC>; 304 clocks = <&topckgen CLK_TOP_MM_SEL>; 305 clock-names = "mm"; 306 #power-domain-cells = <0>; 307 }; 308 power-domain@MT6795_POWER_DOMAIN_VENC { 309 reg = <MT6795_POWER_DOMAIN_VENC>; 310 clocks = <&topckgen CLK_TOP_MM_SEL>, 311 <&topckgen CLK_TOP_VENC_SEL>; 312 clock-names = "mm", "venc"; 313 #power-domain-cells = <0>; 314 }; 315 power-domain@MT6795_POWER_DOMAIN_ISP { 316 reg = <MT6795_POWER_DOMAIN_ISP>; 317 clocks = <&topckgen CLK_TOP_MM_SEL>; 318 clock-names = "mm"; 319 #power-domain-cells = <0>; 320 }; 321 322 power-domain@MT6795_POWER_DOMAIN_MM { 323 reg = <MT6795_POWER_DOMAIN_MM>; 324 clocks = <&topckgen CLK_TOP_MM_SEL>; 325 clock-names = "mm"; 326 #power-domain-cells = <0>; 327 mediatek,infracfg = <&infracfg>; 328 }; 329 330 power-domain@MT6795_POWER_DOMAIN_MJC { 331 reg = <MT6795_POWER_DOMAIN_MJC>; 332 clocks = <&topckgen CLK_TOP_MM_SEL>, 333 <&topckgen CLK_TOP_MJC_SEL>; 334 clock-names = "mm", "mjc"; 335 #power-domain-cells = <0>; 336 }; 337 338 power-domain@MT6795_POWER_DOMAIN_AUDIO { 339 reg = <MT6795_POWER_DOMAIN_AUDIO>; 340 #power-domain-cells = <0>; 341 }; 342 343 mfg_async: power-domain@MT6795_POWER_DOMAIN_MFG_ASYNC { 344 reg = <MT6795_POWER_DOMAIN_MFG_ASYNC>; 345 clocks = <&clk26m>; 346 clock-names = "mfg"; 347 #address-cells = <1>; 348 #size-cells = <0>; 349 #power-domain-cells = <1>; 350 351 power-domain@MT6795_POWER_DOMAIN_MFG_2D { 352 reg = <MT6795_POWER_DOMAIN_MFG_2D>; 353 #address-cells = <1>; 354 #size-cells = <0>; 355 #power-domain-cells = <1>; 356 357 power-domain@MT6795_POWER_DOMAIN_MFG { 358 reg = <MT6795_POWER_DOMAIN_MFG>; 359 #power-domain-cells = <0>; 360 mediatek,infracfg = <&infracfg>; 361 }; 362 }; 363 }; 364 }; 365 }; 366 367 pio: pinctrl@10005000 { 368 compatible = "mediatek,mt6795-pinctrl"; 369 reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>; 370 reg-names = "base", "eint"; 371 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 372 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 373 gpio-controller; 374 #gpio-cells = <2>; 375 gpio-ranges = <&pio 0 0 196>; 376 interrupt-controller; 377 #interrupt-cells = <2>; 378 }; 379 380 watchdog: watchdog@10007000 { 381 compatible = "mediatek,mt6795-wdt"; 382 reg = <0 0x10007000 0 0x100>; 383 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; 384 #reset-cells = <1>; 385 timeout-sec = <20>; 386 }; 387 388 timer: timer@10008000 { 389 compatible = "mediatek,mt6795-timer", 390 "mediatek,mt6577-timer"; 391 reg = <0 0x10008000 0 0x1000>; 392 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>; 393 clocks = <&system_clk>, <&clk32k>; 394 }; 395 396 pwrap: pwrap@1000d000 { 397 compatible = "mediatek,mt6795-pwrap"; 398 reg = <0 0x1000d000 0 0x1000>; 399 reg-names = "pwrap"; 400 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>; 401 resets = <&infracfg MT6795_INFRA_RST0_PMIC_WRAP_RST>; 402 reset-names = "pwrap"; 403 clocks = <&topckgen CLK_TOP_PMICSPI_SEL>, <&clk26m>; 404 clock-names = "spi", "wrap"; 405 }; 406 407 sysirq: interrupt-controller@10200620 { 408 compatible = "mediatek,mt6795-sysirq", 409 "mediatek,mt6577-sysirq"; 410 interrupt-controller; 411 #interrupt-cells = <3>; 412 interrupt-parent = <&gic>; 413 reg = <0 0x10200620 0 0x20>; 414 }; 415 416 systimer: timer@10200670 { 417 compatible = "mediatek,mt6795-systimer"; 418 reg = <0 0x10200670 0 0x10>; 419 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 420 clocks = <&system_clk>; 421 clock-names = "clk13m"; 422 }; 423 424 iommu: iommu@10205000 { 425 compatible = "mediatek,mt6795-m4u"; 426 reg = <0 0x10205000 0 0x1000>; 427 clocks = <&infracfg CLK_INFRA_M4U>; 428 clock-names = "bclk"; 429 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_LOW>; 430 mediatek,infracfg = <&infracfg>; 431 mediatek,larbs = <&larb0 &larb1 &larb2 &larb3>; 432 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 433 #iommu-cells = <1>; 434 }; 435 436 apmixedsys: syscon@10209000 { 437 compatible = "mediatek,mt6795-apmixedsys", "syscon"; 438 reg = <0 0x10209000 0 0x1000>; 439 #clock-cells = <1>; 440 }; 441 442 fhctl: clock-controller@10209f00 { 443 compatible = "mediatek,mt6795-fhctl"; 444 reg = <0 0x10209f00 0 0x100>; 445 status = "disabled"; 446 }; 447 448 gce: mailbox@10212000 { 449 compatible = "mediatek,mt6795-gce", "mediatek,mt8173-gce"; 450 reg = <0 0x10212000 0 0x1000>; 451 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>; 452 clocks = <&infracfg CLK_INFRA_GCE>; 453 clock-names = "gce"; 454 #mbox-cells = <2>; 455 }; 456 457 mipi_tx0: dsi-phy@10215000 { 458 compatible = "mediatek,mt8173-mipi-tx"; 459 reg = <0 0x10215000 0 0x1000>; 460 clocks = <&clk26m>; 461 clock-output-names = "mipi_tx0_pll"; 462 #clock-cells = <0>; 463 #phy-cells = <0>; 464 status = "disabled"; 465 }; 466 467 mipi_tx1: dsi-phy@10216000 { 468 compatible = "mediatek,mt8173-mipi-tx"; 469 reg = <0 0x10216000 0 0x1000>; 470 clocks = <&clk26m>; 471 clock-output-names = "mipi_tx1_pll"; 472 #clock-cells = <0>; 473 #phy-cells = <0>; 474 status = "disabled"; 475 }; 476 477 gic: interrupt-controller@10221000 { 478 compatible = "arm,gic-400"; 479 #interrupt-cells = <3>; 480 interrupt-parent = <&gic>; 481 interrupt-controller; 482 reg = <0 0x10221000 0 0x1000>, 483 <0 0x10222000 0 0x2000>, 484 <0 0x10224000 0 0x2000>, 485 <0 0x10226000 0 0x2000>; 486 interrupts = <GIC_PPI 9 487 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 488 }; 489 490 cci: cci@10390000 { 491 compatible = "arm,cci-400"; 492 #address-cells = <1>; 493 #size-cells = <1>; 494 reg = <0 0x10390000 0 0x1000>; 495 ranges = <0 0 0x10390000 0x10000>; 496 497 cci_control0: slave-if@1000 { 498 compatible = "arm,cci-400-ctrl-if"; 499 interface-type = "ace-lite"; 500 reg = <0x1000 0x1000>; 501 }; 502 503 cci_control1: slave-if@4000 { 504 compatible = "arm,cci-400-ctrl-if"; 505 interface-type = "ace"; 506 reg = <0x4000 0x1000>; 507 }; 508 509 cci_control2: slave-if@5000 { 510 compatible = "arm,cci-400-ctrl-if"; 511 interface-type = "ace"; 512 reg = <0x5000 0x1000>; 513 }; 514 515 pmu@9000 { 516 compatible = "arm,cci-400-pmu,r1"; 517 reg = <0x9000 0x5000>; 518 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 519 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 520 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 521 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, 522 <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 523 }; 524 }; 525 526 uart0: serial@11002000 { 527 compatible = "mediatek,mt6795-uart", 528 "mediatek,mt6577-uart"; 529 reg = <0 0x11002000 0 0x400>; 530 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 531 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>; 532 clock-names = "baud", "bus"; 533 dmas = <&apdma 0>, <&apdma 1>; 534 dma-names = "tx", "rx"; 535 status = "disabled"; 536 }; 537 538 uart1: serial@11003000 { 539 compatible = "mediatek,mt6795-uart", 540 "mediatek,mt6577-uart"; 541 reg = <0 0x11003000 0 0x400>; 542 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 543 clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>; 544 clock-names = "baud", "bus"; 545 dmas = <&apdma 2>, <&apdma 3>; 546 dma-names = "tx", "rx"; 547 status = "disabled"; 548 }; 549 550 apdma: dma-controller@11000380 { 551 compatible = "mediatek,mt6795-uart-dma", 552 "mediatek,mt6577-uart-dma"; 553 reg = <0 0x11000380 0 0x60>, 554 <0 0x11000400 0 0x60>, 555 <0 0x11000480 0 0x60>, 556 <0 0x11000500 0 0x60>, 557 <0 0x11000580 0 0x60>, 558 <0 0x11000600 0 0x60>, 559 <0 0x11000680 0 0x60>, 560 <0 0x11000700 0 0x60>; 561 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, 562 <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 563 <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, 564 <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, 565 <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, 566 <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, 567 <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, 568 <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>; 569 dma-requests = <8>; 570 clocks = <&pericfg CLK_PERI_AP_DMA>; 571 clock-names = "apdma"; 572 mediatek,dma-33bits; 573 #dma-cells = <1>; 574 }; 575 576 uart2: serial@11004000 { 577 compatible = "mediatek,mt6795-uart", 578 "mediatek,mt6577-uart"; 579 reg = <0 0x11004000 0 0x400>; 580 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 581 clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>; 582 clock-names = "baud", "bus"; 583 dmas = <&apdma 4>, <&apdma 5>; 584 dma-names = "tx", "rx"; 585 status = "disabled"; 586 }; 587 588 uart3: serial@11005000 { 589 compatible = "mediatek,mt6795-uart", 590 "mediatek,mt6577-uart"; 591 reg = <0 0x11005000 0 0x400>; 592 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 593 clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>; 594 clock-names = "baud", "bus"; 595 dmas = <&apdma 6>, <&apdma 7>; 596 dma-names = "tx", "rx"; 597 status = "disabled"; 598 }; 599 600 pwm2: pwm@11006000 { 601 compatible = "mediatek,mt6795-pwm"; 602 reg = <0 0x11006000 0 0x1000>; 603 #pwm-cells = <2>; 604 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 605 clocks = <&topckgen CLK_TOP_PWM_SEL>, 606 <&pericfg CLK_PERI_PWM>, 607 <&pericfg CLK_PERI_PWM1>, 608 <&pericfg CLK_PERI_PWM2>, 609 <&pericfg CLK_PERI_PWM3>, 610 <&pericfg CLK_PERI_PWM4>, 611 <&pericfg CLK_PERI_PWM5>, 612 <&pericfg CLK_PERI_PWM6>, 613 <&pericfg CLK_PERI_PWM7>; 614 clock-names = "top", "main", "pwm1", "pwm2", "pwm3", 615 "pwm4", "pwm5", "pwm6", "pwm7"; 616 status = "disabled"; 617 }; 618 619 i2c0: i2c@11007000 { 620 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 621 reg = <0 0x11007000 0 0x70>, <0 0x11000100 0 0x80>; 622 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 623 clock-div = <16>; 624 clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>; 625 clock-names = "main", "dma"; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 i2c1: i2c@11008000 { 632 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 633 reg = <0 0x11008000 0 0x70>, <0 0x11000180 0 0x80>; 634 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 635 clock-div = <16>; 636 clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>; 637 clock-names = "main", "dma"; 638 #address-cells = <1>; 639 #size-cells = <0>; 640 status = "disabled"; 641 }; 642 643 i2c2: i2c@11009000 { 644 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 645 reg = <0 0x11009000 0 0x70>, <0 0x11000200 0 0x80>; 646 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 647 clock-div = <16>; 648 clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>; 649 clock-names = "main", "dma"; 650 #address-cells = <1>; 651 #size-cells = <0>; 652 status = "disabled"; 653 }; 654 655 i2c3: i2c@11010000 { 656 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 657 reg = <0 0x11010000 0 0x70>, <0 0x11000280 0 0x80>; 658 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 659 clock-div = <16>; 660 clocks = <&pericfg CLK_PERI_I2C3>, <&pericfg CLK_PERI_AP_DMA>; 661 clock-names = "main", "dma"; 662 #address-cells = <1>; 663 #size-cells = <0>; 664 status = "disabled"; 665 }; 666 667 i2c4: i2c@11011000 { 668 compatible = "mediatek,mt6795-i2c", "mediatek,mt8173-i2c"; 669 reg = <0 0x11011000 0 0x70>, <0 0x11000300 0 0x80>; 670 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 671 clock-div = <16>; 672 clocks = <&pericfg CLK_PERI_I2C4>, <&pericfg CLK_PERI_AP_DMA>; 673 clock-names = "main", "dma"; 674 #address-cells = <1>; 675 #size-cells = <0>; 676 status = "disabled"; 677 }; 678 679 mmc0: mmc@11230000 { 680 compatible = "mediatek,mt6795-mmc"; 681 reg = <0 0x11230000 0 0x1000>; 682 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 683 clocks = <&pericfg CLK_PERI_MSDC30_0>, 684 <&topckgen CLK_TOP_MSDC50_0_H_SEL>, 685 <&topckgen CLK_TOP_MSDC50_0_SEL>; 686 clock-names = "source", "hclk", "source_cg"; 687 status = "disabled"; 688 }; 689 690 mmc1: mmc@11240000 { 691 compatible = "mediatek,mt6795-mmc"; 692 reg = <0 0x11240000 0 0x1000>; 693 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 694 clocks = <&pericfg CLK_PERI_MSDC30_1>, 695 <&topckgen CLK_TOP_AXI_SEL>; 696 clock-names = "source", "hclk"; 697 status = "disabled"; 698 }; 699 700 mmc2: mmc@11250000 { 701 compatible = "mediatek,mt6795-mmc"; 702 reg = <0 0x11250000 0 0x1000>; 703 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 704 clocks = <&pericfg CLK_PERI_MSDC30_2>, 705 <&topckgen CLK_TOP_AXI_SEL>; 706 clock-names = "source", "hclk"; 707 status = "disabled"; 708 }; 709 710 mmc3: mmc@11260000 { 711 compatible = "mediatek,mt6795-mmc"; 712 reg = <0 0x11260000 0 0x1000>; 713 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_LOW>; 714 clocks = <&pericfg CLK_PERI_MSDC30_3>, 715 <&topckgen CLK_TOP_AXI_SEL>; 716 clock-names = "source", "hclk"; 717 status = "disabled"; 718 }; 719 720 mmsys: syscon@14000000 { 721 compatible = "mediatek,mt6795-mmsys", "syscon"; 722 reg = <0 0x14000000 0 0x1000>; 723 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 724 assigned-clocks = <&topckgen CLK_TOP_MM_SEL>; 725 assigned-clock-rates = <400000000>; 726 #clock-cells = <1>; 727 #reset-cells = <1>; 728 mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, 729 <&gce 1 CMDQ_THR_PRIO_HIGHEST>; 730 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; 731 }; 732 733 ovl0: ovl@1400c000 { 734 compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl"; 735 reg = <0 0x1400c000 0 0x1000>; 736 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>; 737 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 738 clocks = <&mmsys CLK_MM_DISP_OVL0>; 739 iommus = <&iommu M4U_PORT_DISP_OVL0>; 740 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>; 741 }; 742 743 ovl1: ovl@1400d000 { 744 compatible = "mediatek,mt6795-disp-ovl", "mediatek,mt8173-disp-ovl"; 745 reg = <0 0x1400d000 0 0x1000>; 746 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>; 747 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 748 clocks = <&mmsys CLK_MM_DISP_OVL1>; 749 iommus = <&iommu M4U_PORT_DISP_OVL1>; 750 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>; 751 }; 752 753 rdma0: rdma@1400e000 { 754 compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; 755 reg = <0 0x1400e000 0 0x1000>; 756 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>; 757 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 758 clocks = <&mmsys CLK_MM_DISP_RDMA0>; 759 iommus = <&iommu M4U_PORT_DISP_RDMA0>; 760 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>; 761 }; 762 763 rdma1: rdma@1400f000 { 764 compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; 765 reg = <0 0x1400f000 0 0x1000>; 766 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; 767 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 768 clocks = <&mmsys CLK_MM_DISP_RDMA1>; 769 iommus = <&iommu M4U_PORT_DISP_RDMA1>; 770 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>; 771 }; 772 773 rdma2: rdma@14010000 { 774 compatible = "mediatek,mt6795-disp-rdma", "mediatek,mt8173-disp-rdma"; 775 reg = <0 0x14010000 0 0x1000>; 776 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_LOW>; 777 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 778 clocks = <&mmsys CLK_MM_DISP_RDMA2>; 779 iommus = <&iommu M4U_PORT_DISP_RDMA2>; 780 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>; 781 }; 782 783 wdma0: wdma@14011000 { 784 compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma"; 785 reg = <0 0x14011000 0 0x1000>; 786 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>; 787 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 788 clocks = <&mmsys CLK_MM_DISP_WDMA0>; 789 iommus = <&iommu M4U_PORT_DISP_WDMA0>; 790 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>; 791 }; 792 793 wdma1: wdma@14012000 { 794 compatible = "mediatek,mt6795-disp-wdma", "mediatek,mt8173-disp-wdma"; 795 reg = <0 0x14012000 0 0x1000>; 796 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>; 797 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 798 clocks = <&mmsys CLK_MM_DISP_WDMA1>; 799 iommus = <&iommu M4U_PORT_DISP_WDMA1>; 800 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>; 801 }; 802 803 color0: color@14013000 { 804 compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color"; 805 reg = <0 0x14013000 0 0x1000>; 806 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>; 807 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 808 clocks = <&mmsys CLK_MM_DISP_COLOR0>; 809 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>; 810 }; 811 812 color1: color@14014000 { 813 compatible = "mediatek,mt6795-disp-color", "mediatek,mt8173-disp-color"; 814 reg = <0 0x14014000 0 0x1000>; 815 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>; 816 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 817 clocks = <&mmsys CLK_MM_DISP_COLOR1>; 818 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>; 819 }; 820 821 aal@14015000 { 822 compatible = "mediatek,mt6795-disp-aal", "mediatek,mt8173-disp-aal"; 823 reg = <0 0x14015000 0 0x1000>; 824 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>; 825 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 826 clocks = <&mmsys CLK_MM_DISP_AAL>; 827 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>; 828 }; 829 830 gamma@14016000 { 831 compatible = "mediatek,mt6795-disp-gamma", "mediatek,mt8173-disp-gamma"; 832 reg = <0 0x14016000 0 0x1000>; 833 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>; 834 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 835 clocks = <&mmsys CLK_MM_DISP_GAMMA>; 836 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>; 837 }; 838 839 merge@14017000 { 840 compatible = "mediatek,mt6795-disp-merge", "mediatek,mt8173-disp-merge"; 841 reg = <0 0x14017000 0 0x1000>; 842 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 843 clocks = <&mmsys CLK_MM_DISP_MERGE>; 844 }; 845 846 split0: split@14018000 { 847 compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split"; 848 reg = <0 0x14018000 0 0x1000>; 849 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 850 clocks = <&mmsys CLK_MM_DISP_SPLIT0>; 851 }; 852 853 split1: split@14019000 { 854 compatible = "mediatek,mt6795-disp-split", "mediatek,mt8173-disp-split"; 855 reg = <0 0x14019000 0 0x1000>; 856 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 857 clocks = <&mmsys CLK_MM_DISP_SPLIT1>; 858 }; 859 860 ufoe@1401a000 { 861 compatible = "mediatek,mt6795-disp-ufoe", "mediatek,mt8173-disp-ufoe"; 862 reg = <0 0x1401a000 0 0x1000>; 863 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>; 864 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 865 clocks = <&mmsys CLK_MM_DISP_UFOE>; 866 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; 867 }; 868 869 dsi0: dsi@1401b000 { 870 compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi"; 871 reg = <0 0x1401b000 0 0x1000>; 872 interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>; 873 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 874 clocks = <&mmsys CLK_MM_DSI0_ENGINE>, 875 <&mmsys CLK_MM_DSI0_DIGITAL>, 876 <&mipi_tx0>; 877 clock-names = "engine", "digital", "hs"; 878 phys = <&mipi_tx0>; 879 phy-names = "dphy"; 880 status = "disabled"; 881 }; 882 883 dsi1: dsi@1401c000 { 884 compatible = "mediatek,mt6795-dsi", "mediatek,mt8173-dsi"; 885 reg = <0 0x1401c000 0 0x1000>; 886 interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_LOW>; 887 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 888 clocks = <&mmsys CLK_MM_DSI1_ENGINE>, 889 <&mmsys CLK_MM_DSI1_DIGITAL>, 890 <&mipi_tx1>; 891 clock-names = "engine", "digital", "hs"; 892 phys = <&mipi_tx1>; 893 phy-names = "dphy"; 894 status = "disabled"; 895 }; 896 897 dpi0: dpi@1401d000 { 898 compatible = "mediatek,mt6795-dpi", "mediatek,mt8183-dpi"; 899 reg = <0 0x1401d000 0 0x1000>; 900 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>; 901 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 902 clocks = <&mmsys CLK_MM_DPI_PIXEL>, 903 <&mmsys CLK_MM_DPI_ENGINE>, 904 <&apmixedsys CLK_APMIXED_TVDPLL>; 905 clock-names = "pixel", "engine", "pll"; 906 status = "disabled"; 907 }; 908 909 pwm0: pwm@1401e000 { 910 compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm"; 911 reg = <0 0x1401e000 0 0x1000>; 912 #pwm-cells = <2>; 913 clocks = <&mmsys CLK_MM_DISP_PWM026M>, <&mmsys CLK_MM_DISP_PWM0MM>; 914 clock-names = "main", "mm"; 915 status = "disabled"; 916 }; 917 918 pwm1: pwm@1401f000 { 919 compatible = "mediatek,mt6795-disp-pwm", "mediatek,mt8173-disp-pwm"; 920 reg = <0 0x1401f000 0 0x1000>; 921 #pwm-cells = <2>; 922 clocks = <&mmsys CLK_MM_DISP_PWM126M>, <&mmsys CLK_MM_DISP_PWM1MM>; 923 clock-names = "main", "mm"; 924 status = "disabled"; 925 }; 926 927 mutex: mutex@14020000 { 928 compatible = "mediatek,mt8173-disp-mutex"; 929 reg = <0 0x14020000 0 0x1000>; 930 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_LOW>; 931 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 932 clocks = <&mmsys CLK_MM_MUTEX_32K>; 933 mediatek,gce-events = <CMDQ_EVENT_MUTEX0_STREAM_EOF>, 934 <CMDQ_EVENT_MUTEX1_STREAM_EOF>; 935 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0 0x1000>; 936 }; 937 938 larb0: larb@14021000 { 939 compatible = "mediatek,mt6795-smi-larb"; 940 reg = <0 0x14021000 0 0x1000>; 941 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&mmsys CLK_MM_SMI_LARB0>; 942 clock-names = "apb", "smi"; 943 mediatek,smi = <&smi_common>; 944 mediatek,larb-id = <0>; 945 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 946 }; 947 948 smi_common: smi@14022000 { 949 compatible = "mediatek,mt6795-smi-common"; 950 reg = <0 0x14022000 0 0x1000>; 951 power-domains = <&spm MT6795_POWER_DOMAIN_MM>; 952 clocks = <&infracfg CLK_INFRA_SMI>, <&mmsys CLK_MM_SMI_COMMON>; 953 clock-names = "apb", "smi"; 954 }; 955 956 od@14023000 { 957 compatible = "mediatek,mt6795-disp-od", "mediatek,mt8173-disp-od"; 958 reg = <0 0x14023000 0 0x1000>; 959 clocks = <&mmsys CLK_MM_DISP_OD>; 960 mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; 961 }; 962 963 larb2: larb@15001000 { 964 compatible = "mediatek,mt6795-smi-larb"; 965 reg = <0 0x15001000 0 0x1000>; 966 clocks = <&mmsys CLK_MM_SMI_COMMON>, <&infracfg CLK_INFRA_SMI>; 967 clock-names = "apb", "smi"; 968 mediatek,smi = <&smi_common>; 969 mediatek,larb-id = <2>; 970 power-domains = <&spm MT6795_POWER_DOMAIN_ISP>; 971 }; 972 973 vdecsys: clock-controller@16000000 { 974 compatible = "mediatek,mt6795-vdecsys"; 975 reg = <0 0x16000000 0 0x1000>; 976 #clock-cells = <1>; 977 }; 978 979 larb1: larb@16010000 { 980 compatible = "mediatek,mt6795-smi-larb"; 981 reg = <0 0x16010000 0 0x1000>; 982 mediatek,smi = <&smi_common>; 983 mediatek,larb-id = <1>; 984 clocks = <&vdecsys CLK_VDEC_CKEN>, <&vdecsys CLK_VDEC_LARB_CKEN>; 985 clock-names = "apb", "smi"; 986 power-domains = <&spm MT6795_POWER_DOMAIN_VDEC>; 987 }; 988 989 vencsys: clock-controller@18000000 { 990 compatible = "mediatek,mt6795-vencsys"; 991 reg = <0 0x18000000 0 0x1000>; 992 #clock-cells = <1>; 993 }; 994 995 larb3: larb@18001000 { 996 compatible = "mediatek,mt6795-smi-larb"; 997 reg = <0 0x18001000 0 0x1000>; 998 clocks = <&vencsys CLK_VENC_VENC>, <&vencsys CLK_VENC_LARB>; 999 clock-names = "apb", "smi"; 1000 mediatek,smi = <&smi_common>; 1001 mediatek,larb-id = <3>; 1002 power-domains = <&spm MT6795_POWER_DOMAIN_VENC>; 1003 }; 1004 }; 1005};
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