cn9132-db.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (C) 2020 Marvell International Ltd.
  4 *
  5 * Device tree for the CN9132-DB board.
  6 */
  7
  8#include "cn9131-db.dtsi"
  9
 10/ {
 11	compatible = "marvell,cn9132", "marvell,cn9131", "marvell,cn9130",
 12		     "marvell,armada-ap807-quad", "marvell,armada-ap807";
 13
 14	aliases {
 15		gpio5 = &cp2_gpio1;
 16		gpio6 = &cp2_gpio2;
 17		ethernet5 = &cp2_eth0;
 18	};
 19
 20	cp2_reg_usb3_vbus0: regulator-7 {
 21		compatible = "regulator-fixed";
 22		regulator-name = "cp2-xhci0-vbus";
 23		regulator-min-microvolt = <5000000>;
 24		regulator-max-microvolt = <5000000>;
 25		enable-active-high;
 26		gpio = <&cp2_gpio1 2 GPIO_ACTIVE_HIGH>;
 27	};
 28
 29	cp2_usb3_0_phy0: usb-phy-4 {
 30		compatible = "usb-nop-xceiv";
 31		vcc-supply = <&cp2_reg_usb3_vbus0>;
 32	};
 33
 34	cp2_reg_usb3_vbus1: regulator-8 {
 35		compatible = "regulator-fixed";
 36		regulator-name = "cp2-xhci1-vbus";
 37		regulator-min-microvolt = <5000000>;
 38		regulator-max-microvolt = <5000000>;
 39		enable-active-high;
 40		gpio = <&cp2_gpio1 3 GPIO_ACTIVE_HIGH>;
 41	};
 42
 43	cp2_usb3_0_phy1: usb-phy-5 {
 44		compatible = "usb-nop-xceiv";
 45		vcc-supply = <&cp2_reg_usb3_vbus1>;
 46	};
 47
 48	cp2_reg_sd_vccq: regulator-9 {
 49		compatible = "regulator-gpio";
 50		regulator-name = "cp2_sd_vcc";
 51		regulator-min-microvolt = <1800000>;
 52		regulator-max-microvolt = <3300000>;
 53		gpios = <&cp2_gpio2 17 GPIO_ACTIVE_HIGH>;
 54		states = <1800000 0x1 3300000 0x0>;
 55	};
 56
 57	cp2_sfp_eth0: sfp-eth-3 {
 58		compatible = "sff,sfp";
 59		i2c-bus = <&cp2_sfpp0_i2c>;
 60		los-gpios = <&cp2_module_expander1 11 GPIO_ACTIVE_HIGH>;
 61		mod-def0-gpios = <&cp2_module_expander1 10 GPIO_ACTIVE_LOW>;
 62		tx-disable-gpios = <&cp2_module_expander1 9 GPIO_ACTIVE_HIGH>;
 63		tx-fault-gpios = <&cp2_module_expander1 8 GPIO_ACTIVE_HIGH>;
 64		/*
 65		 * SFP cages are unconnected on early PCBs because of an the I2C
 66		 * lanes not being connected. Prevent the port for being
 67		 * unusable by disabling the SFP node.
 68		 */
 69		status = "disabled";
 70	};
 71};
 72
 73/*
 74 * Instantiate the second slave CP115
 75 */
 76
 77#define CP11X_NAME		cp2
 78#define CP11X_BASE		f6000000
 79#define CP11X_PCIEx_MEM_BASE(iface) (0xe5000000 + (iface * 0x1000000))
 80#define CP11X_PCIEx_MEM_SIZE(iface) 0xf00000
 81#define CP11X_PCIE0_BASE	f6600000
 82#define CP11X_PCIE1_BASE	f6620000
 83#define CP11X_PCIE2_BASE	f6640000
 84
 85#include "armada-cp115.dtsi"
 86
 87#undef CP11X_NAME
 88#undef CP11X_BASE
 89#undef CP11X_PCIEx_MEM_BASE
 90#undef CP11X_PCIEx_MEM_SIZE
 91#undef CP11X_PCIE0_BASE
 92#undef CP11X_PCIE1_BASE
 93#undef CP11X_PCIE2_BASE
 94
 95&cp2_crypto {
 96	status = "disabled";
 97};
 98
 99&cp2_ethernet {
100	status = "okay";
101};
102
103/* SLM-1521-V2, CON9 */
104&cp2_eth0 {
105	status = "disabled";
106	phy-mode = "10gbase-r";
107	/* Generic PHY, providing serdes lanes */
108	phys = <&cp2_comphy4 0>;
109	managed = "in-band-status";
110	sfp = <&cp2_sfp_eth0>;
111};
112
113&cp2_gpio1 {
114	status = "okay";
115};
116
117&cp2_gpio2 {
118	status = "okay";
119};
120
121&cp2_i2c0 {
122	clock-frequency = <100000>;
123
124	/* SLM-1521-V2 - U3 */
125	i2c-mux@72 {
126		compatible = "nxp,pca9544";
127		#address-cells = <1>;
128		#size-cells = <0>;
129		reg = <0x72>;
130		cp2_sfpp0_i2c: i2c@0 {
131			#address-cells = <1>;
132			#size-cells = <0>;
133			reg = <0>;
134		};
135
136		i2c@1 {
137			#address-cells = <1>;
138			#size-cells = <0>;
139			reg = <1>;
140			/* U12 */
141			cp2_module_expander1: pca9555@21 {
142				compatible = "nxp,pca9555";
143				pinctrl-names = "default";
144				gpio-controller;
145				#gpio-cells = <2>;
146				reg = <0x21>;
147			};
148		};
149	};
150};
151
152/* SLM-1521-V2, CON6 */
153&cp2_pcie0 {
154	status = "okay";
155	num-lanes = <2>;
156	num-viewport = <8>;
157	/* Generic PHY, providing serdes lanes */
158	phys = <&cp2_comphy0 0
159		&cp2_comphy1 0>;
160};
161
162/* SLM-1521-V2, CON8 */
163&cp2_pcie2 {
164	status = "okay";
165	num-lanes = <1>;
166	num-viewport = <8>;
167	/* Generic PHY, providing serdes lanes */
168	phys = <&cp2_comphy5 2>;
169};
170
171&cp2_sata0 {
172	status = "okay";
173
174	/* SLM-1521-V2, CON4 */
175	sata-port@0 {
176		/* Generic PHY, providing serdes lanes */
177		phys = <&cp2_comphy2 0>;
178		status = "okay";
179	};
180};
181
182/* CON 2 on SLM-1683 - microSD */
183&cp2_sdhci0 {
184	status = "okay";
185	pinctrl-names = "default";
186	pinctrl-0 = <&cp2_sdhci_pins>;
187	bus-width = <4>;
188	cd-gpios = <&cp2_gpio2 23 GPIO_ACTIVE_LOW>;
189	vqmmc-supply = <&cp2_reg_sd_vccq>;
190};
191
192&cp2_syscon0 {
193	cp2_pinctrl: pinctrl {
194		compatible = "marvell,cp115-standalone-pinctrl";
195
196		cp2_i2c0_pins: cp2-i2c-pins-0 {
197			marvell,pins = "mpp37", "mpp38";
198			marvell,function = "i2c0";
199		};
200		cp2_sdhci_pins: cp2-sdhi-pins-0 {
201			marvell,pins = "mpp56", "mpp57", "mpp58",
202				       "mpp59", "mpp60", "mpp61";
203			marvell,function = "sdio";
204		};
205	};
206};
207
208&cp2_utmi {
209	status = "okay";
210};
211
212&cp2_usb3_0 {
213	status = "okay";
214	usb-phy = <&cp2_usb3_0_phy0>;
215	phys = <&cp2_utmi0>;
216	phy-names = "usb";
217	dr_mode = "host";
218};
219
220/* SLM-1521-V2, CON11 */
221&cp2_usb3_1 {
222	status = "okay";
223	usb-phy = <&cp2_usb3_0_phy1>;
224	/* Generic PHY, providing serdes lanes */
225	phys = <&cp2_comphy3 1>, <&cp2_utmi1>;
226	phy-names = "usb", "utmi";
227	dr_mode = "host";
228};