cn9130-sr-som.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (C) 2024 Josua Mayer <josua@solid-run.com>
  4 *
  5 */
  6
  7#include <dt-bindings/gpio/gpio.h>
  8
  9/ {
 10	aliases {
 11		ethernet0 = &cp0_eth0;
 12		ethernet1 = &cp0_eth1;
 13		ethernet2 = &cp0_eth2;
 14		i2c0 = &cp0_i2c0;
 15		mmc0 = &ap_sdhci0;
 16		rtc0 = &cp0_rtc;
 17	};
 18
 19	chosen {
 20		stdout-path = "serial0:115200n8";
 21	};
 22
 23	v_1_8: regulator-1-8 {
 24		compatible = "regulator-fixed";
 25		regulator-name = "1v8";
 26		regulator-min-microvolt = <1800000>;
 27		regulator-max-microvolt = <1800000>;
 28	};
 29
 30	/* requires assembly of R9307 */
 31	vhv: regulator-vhv-1-8 {
 32		compatible = "regulator-fixed";
 33		regulator-name = "vhv-1v8";
 34		regulator-min-microvolt = <1800000>;
 35		regulator-max-microvolt = <1800000>;
 36		pinctrl-0 = <&cp0_reg_vhv_pins>;
 37		pinctrl-names = "default";
 38		gpios = <&cp0_gpio2 9 GPIO_ACTIVE_HIGH>;
 39		enable-active-high;
 40	};
 41};
 42
 43&ap_pinctrl {
 44	ap_mmc0_pins: ap-mmc0-pins {
 45		marvell,pins = "mpp0", "mpp1", "mpp2", "mpp3", "mpp4", "mpp5",
 46					   "mpp6", "mpp7", "mpp8", "mpp9", "mpp10", "mpp12";
 47		marvell,function = "sdio";
 48		/*
 49		 * mpp12 is emmc reset, function should be sdio (hw_rst),
 50		 * but pinctrl-mvebu does not support this.
 51		 *
 52		 * From pinctrl-mvebu.h:
 53		 * "The name will be used to switch to this setting in DT description, e.g.
 54		 * marvell,function = "uart2". subname is only for debugging purposes."
 55		 */
 56	};
 57};
 58
 59&ap_sdhci0 {
 60	bus-width = <8>;
 61	pinctrl-0 = <&ap_mmc0_pins>;
 62	pinctrl-names = "default";
 63	vqmmc-supply = <&v_1_8>;
 64	no-sdio;
 65	non-removable;
 66	status = "okay";
 67};
 68
 69&cp0_ethernet {
 70	status = "okay";
 71};
 72
 73/* for assembly with phy */
 74&cp0_eth2 {
 75	pinctrl-names = "default";
 76	pinctrl-0 = <&cp0_eth2_pins>;
 77	phy-mode = "rgmii-id";
 78	phy = <&cp0_eth2_phy>;
 79	status = "okay";
 80};
 81
 82&cp0_i2c0 {
 83	pinctrl-names = "default";
 84	pinctrl-0 = <&cp0_i2c0_pins>;
 85	clock-frequency = <100000>;
 86	status = "okay";
 87
 88	som_eeprom: eeprom@53 {
 89		compatible = "atmel,24c02";
 90		reg = <0x53>;
 91		pagesize = <8>;
 92	};
 93};
 94
 95&cp0_mdio {
 96	pinctrl-0 = <&cp0_mdio_pins>;
 97	status = "okay";
 98
 99	/* assembly option */
100	cp0_eth2_phy: ethernet-phy@0 {
101		reg = <0>;
102	};
103};
104
105&cp0_spi1 {
106	status = "okay";
107	pinctrl-names = "default";
108	pinctrl-0 = <&cp0_spi1_pins>;
109	/* max speed limited by a mux */
110	spi-max-frequency = <1800000000>;
111
112	flash@0 {
113		compatible = "jedec,spi-nor";
114		reg = <0>;
115		/* read command supports max. 50MHz */
116		spi-max-frequency = <50000000>;
117	};
118};
119
120&cp0_syscon0 {
121	cp0_pinctrl: pinctrl {
122		compatible = "marvell,cp115-standalone-pinctrl";
123
124		cp0_eth2_pins: cp0-ge2-rgmii-pins {
125			marvell,pins = "mpp44", "mpp45", "mpp46", "mpp47",
126				       "mpp48", "mpp49", "mpp50", "mpp51",
127				       "mpp52", "mpp53", "mpp54", "mpp55";
128			/* docs call it "ge2", but cp110-pinctrl "ge1" */
129			marvell,function = "ge1";
130		};
131
132		cp0_i2c0_pins: cp0-i2c0-pins {
133			marvell,pins = "mpp37", "mpp38";
134			marvell,function = "i2c0";
135		};
136
137		cp0_mdio_pins: cp0-mdio-pins {
138			marvell,pins = "mpp0", "mpp1";
139			marvell,function = "ge";
140		};
141
142		cp0_spi1_pins: cp0-spi1-pins {
143			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
144			marvell,function = "spi1";
145		};
146
147		cp0_reg_vhv_pins: cp0-reg-vhv-pins {
148			marvell,pins = "mpp41";
149			marvell,function = "gpio";
150		};
151	};
152};
153
154/* AP default console */
155&uart0 {
156	pinctrl-0 = <&uart0_pins>;
157	pinctrl-names = "default";
158	status = "okay";
159};