cn9130-db.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (C) 2019 Marvell International Ltd.
  4 *
  5 * Device tree for the CN9130-DB board.
  6 */
  7
  8#include "cn9130.dtsi"
  9
 10#include <dt-bindings/gpio/gpio.h>
 11
 12/ {
 13	chosen {
 14		stdout-path = "serial0:115200n8";
 15	};
 16
 17	aliases {
 18		gpio1 = &cp0_gpio1;
 19		gpio2 = &cp0_gpio2;
 20		i2c0 = &cp0_i2c0;
 21		ethernet0 = &cp0_eth0;
 22		ethernet1 = &cp0_eth1;
 23		ethernet2 = &cp0_eth2;
 24		spi1 = &cp0_spi0;
 25		spi2 = &cp0_spi1;
 26	};
 27
 28	memory@0 {
 29		device_type = "memory";
 30		reg = <0x0 0x0 0x0 0x80000000>;
 31	};
 32
 33	ap0_reg_sd_vccq: regulator-1 {
 34		compatible = "regulator-gpio";
 35		regulator-name = "ap0_sd_vccq";
 36		regulator-min-microvolt = <1800000>;
 37		regulator-max-microvolt = <3300000>;
 38		gpios = <&expander0 8 GPIO_ACTIVE_HIGH>;
 39		states = <1800000 0x1 3300000 0x0>;
 40	};
 41
 42	cp0_reg_usb3_vbus0: regulator-2 {
 43		compatible = "regulator-fixed";
 44		regulator-name = "cp0-xhci0-vbus";
 45		regulator-min-microvolt = <5000000>;
 46		regulator-max-microvolt = <5000000>;
 47		enable-active-high;
 48		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
 49	};
 50
 51	cp0_usb3_0_phy0: usb-phy-1 {
 52		compatible = "usb-nop-xceiv";
 53		vcc-supply = <&cp0_reg_usb3_vbus0>;
 54	};
 55
 56	cp0_reg_usb3_vbus1: regulator-3 {
 57		compatible = "regulator-fixed";
 58		regulator-name = "cp0-xhci1-vbus";
 59		regulator-min-microvolt = <5000000>;
 60		regulator-max-microvolt = <5000000>;
 61		enable-active-high;
 62		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
 63	};
 64
 65	cp0_usb3_0_phy1: usb-phy-2 {
 66		compatible = "usb-nop-xceiv";
 67		vcc-supply = <&cp0_reg_usb3_vbus1>;
 68	};
 69
 70	cp0_reg_sd_vccq: regulator-4 {
 71		compatible = "regulator-gpio";
 72		regulator-name = "cp0_sd_vccq";
 73		regulator-min-microvolt = <1800000>;
 74		regulator-max-microvolt = <3300000>;
 75		gpios = <&expander0 15 GPIO_ACTIVE_HIGH>;
 76		states = <1800000 0x1
 77			  3300000 0x0>;
 78	};
 79
 80	cp0_reg_sd_vcc: regulator-5 {
 81		compatible = "regulator-fixed";
 82		regulator-name = "cp0_sd_vcc";
 83		regulator-min-microvolt = <3300000>;
 84		regulator-max-microvolt = <3300000>;
 85		gpio = <&expander0 14 GPIO_ACTIVE_HIGH>;
 86		enable-active-high;
 87		regulator-always-on;
 88	};
 89
 90	cp0_sfp_eth0: sfp-eth-1 {
 91		compatible = "sff,sfp";
 92		i2c-bus = <&cp0_sfpp0_i2c>;
 93		los-gpios = <&cp0_module_expander1 11 GPIO_ACTIVE_HIGH>;
 94		mod-def0-gpios = <&cp0_module_expander1 10 GPIO_ACTIVE_LOW>;
 95		tx-disable-gpios = <&cp0_module_expander1 9 GPIO_ACTIVE_HIGH>;
 96		tx-fault-gpios = <&cp0_module_expander1 8 GPIO_ACTIVE_HIGH>;
 97		/*
 98		 * SFP cages are unconnected on early PCBs because of an the I2C
 99		 * lanes not being connected. Prevent the port for being
100		 * unusable by disabling the SFP node.
101		 */
102		status = "disabled";
103	};
104};
105
106&uart0 {
107	status = "okay";
108};
109
110/* on-board eMMC - U9 */
111&ap_sdhci0 {
112	pinctrl-names = "default";
113	bus-width = <8>;
114	vqmmc-supply = <&ap0_reg_sd_vccq>;
115	status = "okay";
116};
117
118&cp0_crypto {
119	status = "disabled";
120};
121
122&cp0_ethernet {
123	status = "okay";
124};
125
126/* SLM-1521-V2, CON9 */
127&cp0_eth0 {
128	status = "okay";
129	phy-mode = "10gbase-r";
130	/* Generic PHY, providing serdes lanes */
131	phys = <&cp0_comphy4 0>;
132	managed = "in-band-status";
133	sfp = <&cp0_sfp_eth0>;
134};
135
136/* CON56 */
137&cp0_eth1 {
138	status = "okay";
139	phy = <&phy0>;
140	phy-mode = "rgmii-id";
141};
142
143/* CON57 */
144&cp0_eth2 {
145	status = "okay";
146	phy = <&phy1>;
147	phy-mode = "rgmii-id";
148};
149
150&cp0_gpio1 {
151	status = "okay";
152};
153
154&cp0_gpio2 {
155	status = "okay";
156};
157
158&cp0_i2c0 {
159	status = "okay";
160	pinctrl-names = "default";
161	pinctrl-0 = <&cp0_i2c0_pins>;
162	clock-frequency = <100000>;
163
164	/* U36 */
165	expander0: pca953x@21 {
166		compatible = "nxp,pca9555";
167		pinctrl-names = "default";
168		gpio-controller;
169		#gpio-cells = <2>;
170		reg = <0x21>;
171		status = "okay";
172	};
173
174	/* U42 */
175	eeprom0: eeprom@50 {
176		compatible = "atmel,24c64";
177		reg = <0x50>;
178		pagesize = <0x20>;
179	};
180
181	/* U38 */
182	eeprom1: eeprom@57 {
183		compatible = "atmel,24c64";
184		reg = <0x57>;
185		pagesize = <0x20>;
186	};
187};
188
189&cp0_i2c1 {
190	status = "okay";
191	clock-frequency = <100000>;
192
193	/* SLM-1521-V2 - U3 */
194	i2c-mux@72 { /* verify address - depends on dpr */
195		compatible = "nxp,pca9544";
196		#address-cells = <1>;
197		#size-cells = <0>;
198		reg = <0x72>;
199		cp0_sfpp0_i2c: i2c@0 {
200			#address-cells = <1>;
201			#size-cells = <0>;
202			reg = <0>;
203		};
204
205		i2c@1 {
206			#address-cells = <1>;
207			#size-cells = <0>;
208			reg = <1>;
209			/* U12 */
210			cp0_module_expander1: pca9555@21 {
211				compatible = "nxp,pca9555";
212				gpio-controller;
213				#gpio-cells = <2>;
214				reg = <0x21>;
215			};
216
217		};
218	};
219};
220
221&cp0_mdio {
222	status = "okay";
223
224	phy0: ethernet-phy@0 {
225		reg = <0>;
226	};
227
228	phy1: ethernet-phy@1 {
229		reg = <1>;
230	};
231};
232
233/* U54 */
234&cp0_nand_controller {
235	status = "disabled";
236	pinctrl-names = "default";
237	pinctrl-0 = <&nand_pins &nand_rb>;
238
239	nand@0 {
240		reg = <0>;
241		label = "main-storage";
242		nand-rb = <0>;
243		nand-ecc-mode = "hw";
244		nand-on-flash-bbt;
245		nand-ecc-strength = <8>;
246		nand-ecc-step-size = <512>;
247
248		partitions {
249			compatible = "fixed-partitions";
250			#address-cells = <1>;
251			#size-cells = <1>;
252
253			partition@0 {
254				label = "U-Boot";
255				reg = <0 0x200000>;
256			};
257			partition@200000 {
258				label = "Linux";
259				reg = <0x200000 0xe00000>;
260			};
261			partition@1000000 {
262				label = "Filesystem";
263				reg = <0x1000000 0x3f000000>;
264			};
265		};
266	};
267};
268
269/* SLM-1521-V2, CON6 */
270&cp0_pcie0 {
271	status = "okay";
272	num-lanes = <4>;
273	num-viewport = <8>;
274	/* Generic PHY, providing serdes lanes */
275	phys = <&cp0_comphy0 0
276		&cp0_comphy1 0
277		&cp0_comphy2 0
278		&cp0_comphy3 0>;
279};
280
281&cp0_sata0 {
282	status = "okay";
283
284	/* SLM-1521-V2, CON2 */
285	sata-port@1 {
286		status = "okay";
287		/* Generic PHY, providing serdes lanes */
288		phys = <&cp0_comphy5 1>;
289	};
290};
291
292/* CON 28 */
293&cp0_sdhci0 {
294	status = "okay";
295	pinctrl-names = "default";
296	pinctrl-0 = <&cp0_sdhci_pins
297		     &cp0_sdhci_cd_pins>;
298	bus-width = <4>;
299	cd-gpios = <&cp0_gpio2 11 GPIO_ACTIVE_LOW>;
300	no-1-8-v;
301	vqmmc-supply = <&cp0_reg_sd_vccq>;
302	vmmc-supply = <&cp0_reg_sd_vcc>;
303};
304
305/* U55 */
306&cp0_spi1 {
307	status = "disabled";
308	pinctrl-names = "default";
309	pinctrl-0 = <&cp0_spi1_pins>;
310	reg = <0x700680 0x50>;
311
312	flash@0 {
313		compatible = "jedec,spi-nor";
314		reg = <0x0>;
315		/* On-board MUX does not allow higher frequencies */
316		spi-max-frequency = <40000000>;
317
318		partitions {
319			compatible = "fixed-partitions";
320			#address-cells = <1>;
321			#size-cells = <1>;
322
323			partition@0 {
324				label = "U-Boot-0";
325				reg = <0x0 0x200000>;
326			};
327
328			partition@400000 {
329				label = "Filesystem-0";
330				reg = <0x200000 0xe00000>;
331			};
332		};
333	};
334};
335
336&cp0_syscon0 {
337	cp0_pinctrl: pinctrl {
338		compatible = "marvell,cp115-standalone-pinctrl";
339
340		cp0_i2c0_pins: cp0-i2c-pins-0 {
341			marvell,pins = "mpp37", "mpp38";
342			marvell,function = "i2c0";
343		};
344		cp0_i2c1_pins: cp0-i2c-pins-1 {
345			marvell,pins = "mpp35", "mpp36";
346			marvell,function = "i2c1";
347		};
348		cp0_ge1_rgmii_pins: cp0-ge-rgmii-pins-0 {
349			marvell,pins = "mpp0", "mpp1", "mpp2",
350				       "mpp3", "mpp4", "mpp5",
351				       "mpp6", "mpp7", "mpp8",
352				       "mpp9", "mpp10", "mpp11";
353			marvell,function = "ge0";
354		};
355		cp0_ge2_rgmii_pins: cp0-ge-rgmii-pins-1 {
356			marvell,pins = "mpp44", "mpp45", "mpp46",
357				       "mpp47", "mpp48", "mpp49",
358				       "mpp50", "mpp51", "mpp52",
359				       "mpp53", "mpp54", "mpp55";
360			marvell,function = "ge1";
361		};
362		cp0_sdhci_cd_pins: cp0-sdhci-cd-pins-0 {
363			marvell,pins = "mpp43";
364			marvell,function = "gpio";
365		};
366		cp0_sdhci_pins: cp0-sdhi-pins-0 {
367			marvell,pins = "mpp56", "mpp57", "mpp58",
368				       "mpp59", "mpp60", "mpp61";
369			marvell,function = "sdio";
370		};
371		cp0_spi1_pins: cp0-spi-pins-1 {
372			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
373			marvell,function = "spi1";
374		};
375		nand_pins: nand-pins {
376			marvell,pins = "mpp15", "mpp16", "mpp17", "mpp18",
377				       "mpp19", "mpp20", "mpp21", "mpp22",
378				       "mpp23", "mpp24", "mpp25", "mpp26",
379				       "mpp27";
380			marvell,function = "dev";
381		};
382		nand_rb: nand-rb-pins {
383			marvell,pins = "mpp13";
384			marvell,function = "nf";
385		};
386	};
387};
388
389&cp0_utmi {
390	status = "okay";
391};
392
393&cp0_usb3_0 {
394	status = "okay";
395	usb-phy = <&cp0_usb3_0_phy0>;
396	phys = <&cp0_utmi0>;
397	phy-names = "utmi";
398	dr_mode = "host";
399};
400
401&cp0_usb3_1 {
402	status = "okay";
403	usb-phy = <&cp0_usb3_0_phy1>;
404	phys = <&cp0_utmi1>;
405	phy-names = "utmi";
406	dr_mode = "host";
407};