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mba8xx.dtsi

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linux-6.19.14/arch/arm64/boot/dts/freescale/mba8xx.dtsi DEVICETREE 
  1// SPDX-License-Identifier: (GPL-2.0-or-later OR X11)
  2/*
  3 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>,
  4 * D-82229 Seefeld, Germany.
  5 * Author: Alexander Stein
  6 */
  7
  8#include <dt-bindings/input/input.h>
  9#include <dt-bindings/leds/common.h>
 10#include <dt-bindings/net/ti-dp83867.h>
 11
 12/ {
 13	adc {
 14		compatible = "iio-hwmon";
 15		io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>;
 16	};
 17
 18	aliases {
 19		rtc0 = &pcf85063;
 20		rtc1 = &rtc;
 21	};
 22
 23	backlight_lvds: backlight-lvds {
 24		compatible = "pwm-backlight";
 25		pinctrl-names = "default";
 26		pinctrl-0 = <&pinctrl_bl_lvds>;
 27		pwms = <&adma_pwm 0 5000000 0>;
 28		brightness-levels = <0 4 8 16 32 64 128 255>;
 29		default-brightness-level = <7>;
 30		power-supply = <&reg_12v0>;
 31		enable-gpios = <&lsio_gpio1 30 GPIO_ACTIVE_HIGH>;
 32		status = "disabled";
 33	};
 34
 35	chosen {
 36		stdout-path = &lpuart1;
 37	};
 38
 39	/* Non-controllable PCIe reference clock generator */
 40	pcie_refclk: clock-pcie-ref {
 41		compatible = "fixed-clock";
 42		#clock-cells = <0>;
 43		clock-frequency = <100000000>;
 44	};
 45
 46	gpio-keys {
 47		compatible = "gpio-keys";
 48		pinctrl-names = "default";
 49		pinctrl-0 = <&pinctrl_gpiobuttons>;
 50		autorepeat;
 51
 52		switch-a {
 53			label = "switcha";
 54			linux,code = <BTN_0>;
 55			gpios = <&lsio_gpio1 13 GPIO_ACTIVE_LOW>;
 56		};
 57
 58		switch-b {
 59			label = "switchb";
 60			linux,code = <BTN_1>;
 61			gpios = <&lsio_gpio1 14 GPIO_ACTIVE_LOW>;
 62		};
 63	};
 64
 65	gpio-leds {
 66		compatible = "gpio-leds";
 67
 68		led1 {
 69			color = <LED_COLOR_ID_GREEN>;
 70			function = LED_FUNCTION_STATUS;
 71			gpios = <&expander 1 GPIO_ACTIVE_HIGH>;
 72			linux,default-trigger = "default-on";
 73		};
 74
 75		led2 {
 76			color = <LED_COLOR_ID_GREEN>;
 77			function = LED_FUNCTION_HEARTBEAT;
 78			gpios = <&expander 2 GPIO_ACTIVE_HIGH>;
 79			linux,default-trigger = "heartbeat";
 80		};
 81	};
 82
 83	/* TODO LVDS panels */
 84
 85	reg_12v0: regulator-12v0 {
 86		compatible = "regulator-fixed";
 87		regulator-name = "V_12V";
 88		regulator-min-microvolt = <12000000>;
 89		regulator-max-microvolt = <12000000>;
 90		gpio = <&expander 6 GPIO_ACTIVE_HIGH>;
 91		enable-active-high;
 92	};
 93
 94	reg_pcie_1v5: regulator-pcie-1v5 {
 95		compatible = "regulator-fixed";
 96		regulator-name = "MBA8XX_PCIE_1V5";
 97		pinctrl-names = "default";
 98		pinctrl-0 = <&pinctrl_reg_pcie_1v5>;
 99		regulator-min-microvolt = <1500000>;
100		regulator-max-microvolt = <1500000>;
101		gpio = <&lsio_gpio0 30 GPIO_ACTIVE_HIGH>;
102		startup-delay-us = <1000>;
103		enable-active-high;
104	};
105
106	reg_pcie_3v3: regulator-pcie-3v3 {
107		compatible = "regulator-fixed";
108		regulator-name = "MBA8XX_PCIE_3V3";
109		pinctrl-names = "default";
110		pinctrl-0 = <&pinctrl_reg_pcie_3v3>;
111		regulator-min-microvolt = <3300000>;
112		regulator-max-microvolt = <3300000>;
113		gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
114		startup-delay-us = <1000>;
115		enable-active-high;
116		regulator-always-on;
117	};
118
119	reg_3v3_mb: regulator-usdhc2-vmmc {
120		compatible = "regulator-fixed";
121		regulator-name = "V_3V3_MB";
122		regulator-min-microvolt = <3300000>;
123		regulator-max-microvolt = <3300000>;
124	};
125
126	sound {
127		compatible = "fsl,imx-audio-tlv320aic32x4";
128		model = "tqm-tlv320aic32";
129		audio-codec = <&tlv320aic3x04>;
130		ssi-controller = <&sai1>;
131		audio-routing =
132			"IN3_L", "Mic Jack",
133			"Mic Jack", "Mic Bias",
134			"IN1_L", "Line In Jack",
135			"IN1_R", "Line In Jack",
136			"Line Out Jack", "LOL",
137			"Line Out Jack", "LOR";
138	};
139};
140
141&adc0 {
142	pinctrl-names = "default";
143	pinctrl-0 = <&pinctrl_adc0>;
144	vref-supply = <&reg_1v8>;
145	#io-channel-cells = <1>;
146	status = "okay";
147};
148
149&adma_pwm {
150	pinctrl-names = "default";
151	pinctrl-0 = <&pinctrl_admapwm>;
152};
153
154&fec1 {
155	pinctrl-names = "default";
156	pinctrl-0 = <&pinctrl_fec1>;
157	phy-mode = "rgmii-id";
158	phy-handle = <&ethphy0>;
159	status = "okay";
160
161	mdio {
162		#address-cells = <1>;
163		#size-cells = <0>;
164
165		ethphy0: ethernet-phy@0 {
166			compatible = "ethernet-phy-ieee802.3-c22";
167			reg = <0>;
168			pinctrl-names = "default";
169			pinctrl-0 = <&pinctrl_ethphy0>;
170			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
171			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
172			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
173			ti,dp83867-rxctrl-strap-quirk;
174			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
175			reset-gpios = <&lsio_gpio3 2 GPIO_ACTIVE_LOW>;
176			reset-assert-us = <500000>;
177			reset-deassert-us = <50000>;
178			enet-phy-lane-no-swap;
179			interrupt-parent = <&lsio_gpio3>;
180			interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
181		};
182
183		ethphy3: ethernet-phy@3 {
184			compatible = "ethernet-phy-ieee802.3-c22";
185			reg = <3>;
186			pinctrl-names = "default";
187			pinctrl-0 = <&pinctrl_ethphy3>;
188			ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
189			ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
190			ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
191			ti,dp83867-rxctrl-strap-quirk;
192			ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
193			reset-gpios = <&lsio_gpio3 3 GPIO_ACTIVE_LOW>;
194			reset-assert-us = <500000>;
195			reset-deassert-us = <50000>;
196			enet-phy-lane-no-swap;
197			interrupt-parent = <&lsio_gpio3>;
198			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
199		};
200	};
201};
202
203&fec2 {
204	pinctrl-names = "default";
205	pinctrl-0 = <&pinctrl_fec2>;
206	phy-mode = "rgmii-id";
207	phy-handle = <&ethphy3>;
208	status = "okay";
209};
210
211&flexcan1 {
212	pinctrl-names = "default";
213	pinctrl-0 = <&pinctrl_can0>;
214	xceiver-supply = <&reg_3v3>;
215	status = "okay";
216};
217
218&flexcan2 {
219	pinctrl-names = "default";
220	pinctrl-0 = <&pinctrl_can1>;
221	xceiver-supply = <&reg_3v3>;
222	status = "okay";
223};
224
225&hsio_phy {
226	fsl,hsio-cfg = "pciea-x2-pcieb";
227	fsl,refclk-pad-mode = "input";
228	status = "okay";
229};
230
231&i2c1 {
232	tlv320aic3x04: audio-codec@18 {
233		compatible = "ti,tlv320aic32x4";
234		reg = <0x18>;
235		clocks = <&mclkout0_lpcg 0>;
236		clock-names = "mclk";
237		iov-supply = <&reg_1v8>;
238		ldoin-supply = <&reg_3v3>;
239	};
240
241	se97b_1c: temperature-sensor@1c {
242		compatible = "nxp,se97b", "jedec,jc-42.4-temp";
243		reg = <0x1c>;
244	};
245
246	at24c02_54: eeprom@54 {
247		compatible = "nxp,se97b", "atmel,24c02";
248		reg = <0x54>;
249		pagesize = <16>;
250		vcc-supply = <&reg_3v3>;
251	};
252
253	expander: gpio@70 {
254		compatible = "nxp,pca9538";
255		reg = <0x70>;
256		pinctrl-names = "default";
257		pinctrl-0 = <&pinctrl_pca9538>;
258		gpio-controller;
259		#gpio-cells = <2>;
260		interrupt-parent = <&lsio_gpio4>;
261		interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
262		interrupt-controller;
263		#interrupt-cells = <2>;
264		vcc-supply = <&reg_1v8>;
265
266		gpio-line-names = "", "LED_A",
267				  "LED_B", "",
268				  "DSI_EN", "USB_RESET#",
269				  "V_12V_EN", "PCIE_DIS#";
270	};
271};
272
273&i2c2 {
274	clock-frequency = <100000>;
275	pinctrl-names = "default", "gpio";
276	pinctrl-0 = <&pinctrl_lpi2c2>;
277	pinctrl-1 = <&pinctrl_lpi2c2gpio>;
278	scl-gpios = <&lsio_gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
279	sda-gpios = <&lsio_gpio2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
280	status = "okay";
281};
282
283/* TODO LDB */
284
285&lpspi1 {
286	pinctrl-names = "default";
287	pinctrl-0 = <&pinctrl_spi1>;
288	cs-gpios = <&lsio_gpio0 27 GPIO_ACTIVE_LOW>, <&lsio_gpio0 29 GPIO_ACTIVE_LOW>;
289	status = "okay";
290};
291
292&lpspi2 {
293	pinctrl-names = "default";
294	pinctrl-0 = <&pinctrl_spi2>;
295	cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
296	status = "okay";
297};
298
299&lpspi3 {
300	pinctrl-names = "default";
301	pinctrl-0 = <&pinctrl_spi3>;
302	num-cs = <2>;
303	cs-gpios = <&lsio_gpio0 16 GPIO_ACTIVE_LOW>;
304	status = "okay";
305};
306
307&lpuart1 {
308	pinctrl-names = "default";
309	pinctrl-0 = <&pinctrl_lpuart1>;
310	status = "okay";
311};
312
313&lpuart3 {
314	pinctrl-names = "default";
315	pinctrl-0 = <&pinctrl_lpuart3>;
316	status = "okay";
317};
318
319&lsio_gpio3 {
320	pinctrl-names = "default";
321	pinctrl-0 = <&pinctrl_lsgpio3>;
322	gpio-line-names = "", "", "", "",
323			  "", "", "", "",
324			  "", "", "", "",
325			  "", "", "", "X4_15",
326			  "", "", "", "",
327			  "", "", "", "",
328			  "", "", "", "",
329			  "", "", "", "";
330};
331
332&pcieb {
333	phys = <&hsio_phy 0 PHY_TYPE_PCIE 0>;
334	phy-names = "pcie-phy";
335	pinctrl-0 = <&pinctrl_pcieb>;
336	pinctrl-names = "default";
337	reset-gpios = <&lsio_gpio4 0 GPIO_ACTIVE_LOW>;
338	vpcie-supply = <&reg_pcie_1v5>;
339	status = "okay";
340};
341
342&sai1 {
343	assigned-clocks = <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_PLL>,
344			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_SLV_BUS>,
345			  <&clk IMX_SC_R_AUDIO_PLL_0 IMX_SC_PM_CLK_MST_BUS>,
346			  <&sai1_lpcg 0>;
347	assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
348	pinctrl-names = "default";
349	pinctrl-0 = <&pinctrl_sai1>;
350	status = "okay";
351};
352
353&usbotg1 {
354	pinctrl-names = "default";
355	pinctrl-0 = <&pinctrl_usbotg1>;
356	srp-disable;
357	hnp-disable;
358	adp-disable;
359	power-active-high;
360	over-current-active-low;
361	dr_mode = "otg";
362	status = "okay";
363};
364
365&usbotg3 {
366	status = "okay";
367};
368
369&usbotg3_cdns3 {
370	dr_mode = "host";
371	status = "okay";
372};
373
374&usbphy1 {
375	status = "okay";
376};
377
378&usb3_phy {
379	status = "okay";
380};
381
382&usdhc2 {
383	pinctrl-names = "default", "state_100mhz", "state_200mhz";
384	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
385	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
386	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
387	bus-width = <4>;
388	cd-gpios = <&lsio_gpio4 22 GPIO_ACTIVE_LOW>;
389	wp-gpios = <&lsio_gpio4 21 GPIO_ACTIVE_HIGH>;
390	vmmc-supply = <&reg_3v3_mb>;
391	no-1-8-v;
392	no-sdio;
393	no-mmc;
394	status = "okay";
395};
396
397&iomuxc {
398	pinctrl_adc0: adc0grp {
399		fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0	0x02000060>,
400			   <IMX8QXP_ADC_IN1_ADMA_ADC_IN1	0x02000060>,
401			   <IMX8QXP_ADC_IN2_ADMA_ADC_IN2	0x02000060>,
402			   <IMX8QXP_ADC_IN3_ADMA_ADC_IN3	0x02000060>;
403	};
404
405	pinctrl_admapwm: admapwmgrp {
406		fsl,pins = <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT	0x00000021>;
407	};
408
409	pinctrl_bl_lvds: bllvdsgrp {
410		fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SDA_LSIO_GPIO1_IO30	0x00000021>;
411	};
412
413	pinctrl_can0: can0grp {
414		fsl,pins = <IMX8QXP_UART0_RX_ADMA_FLEXCAN0_RX		0x00000021>,
415			   <IMX8QXP_UART0_TX_ADMA_FLEXCAN0_TX		0x00000021>;
416	};
417
418	pinctrl_can1: can1grp {
419		fsl,pins = <IMX8QXP_UART2_RX_ADMA_FLEXCAN1_RX		0x00000021>,
420			   <IMX8QXP_UART2_TX_ADMA_FLEXCAN1_TX		0x00000021>;
421	};
422
423	pinctrl_ethphy0: ethphy0grp {
424		fsl,pins = <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02		0x00000040>,
425			   <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00		0x00000040>;
426	};
427
428	pinctrl_ethphy3: ethphy3grp {
429		fsl,pins = <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03		0x00000040>,
430			   <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01		0x00000040>;
431	};
432
433	pinctrl_fec1: fec1grp {
434		fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC			0x06000041>,
435			   <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO			0x06000041>,
436			   <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x00000040>,
437			   <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x00000040>,
438			   <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x00000040>,
439			   <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x00000040>,
440			   <IMX8QXP_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x00000040>,
441			   <IMX8QXP_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x00000040>,
442			   <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x00000040>,
443			   <IMX8QXP_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x00000040>,
444			   <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x00000040>,
445			   <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x00000040>,
446			   <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x00000040>,
447			   <IMX8QXP_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x00000040>;
448	};
449
450	pinctrl_fec2: fec2grp {
451		fsl,pins = <IMX8QXP_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x00000040>,
452			   <IMX8QXP_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x00000040>,
453			   <IMX8QXP_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0		0x00000040>,
454			   <IMX8QXP_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1		0x00000040>,
455			   <IMX8QXP_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x00000040>,
456			   <IMX8QXP_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x00000040>,
457			   <IMX8QXP_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x00000040>,
458			   <IMX8QXP_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x00000040>,
459			   <IMX8QXP_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x00000040>,
460			   <IMX8QXP_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1		0x00000040>,
461			   <IMX8QXP_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2		0x00000040>,
462			   <IMX8QXP_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x00000040>;
463	};
464
465	pinctrl_gpiobuttons: gpiobuttonsgrp {
466		fsl,pins = <IMX8QXP_ADC_IN5_LSIO_GPIO1_IO13	0x00000020>,
467			   <IMX8QXP_ADC_IN4_LSIO_GPIO1_IO14	0x00000020>;
468	};
469
470	pinctrl_lpi2c2: lpi2c2grp {
471		fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_ADMA_I2C2_SCL	0x06000021>,
472			   <IMX8QXP_MIPI_DSI1_GPIO0_01_ADMA_I2C2_SDA	0x06000021>;
473	};
474
475	pinctrl_lpi2c2gpio: lpi2c2gpiogrp {
476		fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31	0x06000021>,
477			   <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00	0x06000021>;
478	};
479
480	pinctrl_lpuart1: lpuart1grp {
481		fsl,pins = <IMX8QXP_UART1_RX_ADMA_UART1_RX	0x06000020>,
482			   <IMX8QXP_UART1_TX_ADMA_UART1_TX	0x06000020>;
483	};
484
485	pinctrl_lpuart3: lpuart3grp {
486		fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX	0x06000020>,
487			   <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX	0x06000020>;
488	};
489
490	pinctrl_lsgpio3: lsgpio3grp {
491		fsl,pins = <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15	0x00000021>;
492	};
493
494	pinctrl_pca9538: pca9538grp {
495		fsl,pins = <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x00000020>;
496	};
497
498	pinctrl_pcieb: pciebgrp {
499		fsl,pins = <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00		0x06000041>,
500			   <IMX8QXP_PCIE_CTRL0_CLKREQ_B_HSIO_PCIE0_CLKREQ_B	0x06000041>,
501			   <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02		0x04000041>;
502	};
503
504	pinctrl_reg_pcie_1v5: regpcie1v5grp {
505		fsl,pins = <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30	0x00000021>;
506	};
507
508	pinctrl_reg_pcie_3v3: regpcie3v3grp {
509		fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31	0x00000021>;
510	};
511
512	pinctrl_sai1: sai1grp {
513		fsl,pins = <IMX8QXP_MCLK_OUT0_ADMA_ACM_MCLK_OUT0	0x06000041>,
514			   <IMX8QXP_FLEXCAN0_RX_ADMA_SAI1_TXC		0x06000041>,
515			   <IMX8QXP_FLEXCAN0_TX_ADMA_SAI1_TXFS		0x06000041>,
516			   <IMX8QXP_FLEXCAN1_RX_ADMA_SAI1_TXD		0x06000041>,
517			   <IMX8QXP_FLEXCAN1_TX_ADMA_SAI1_RXD		0x06000041>;
518	};
519
520	pinctrl_spi1: spi1grp {
521		fsl,pins = <IMX8QXP_SAI0_TXC_ADMA_SPI1_SDI	0x00000041>,
522			   <IMX8QXP_SAI0_TXD_ADMA_SPI1_SDO	0x00000041>,
523			   <IMX8QXP_SAI0_TXFS_ADMA_SPI1_SCK	0x00000041>,
524			   <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27	0x00000021>,
525			   <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29	0x00000021>;
526	};
527
528	pinctrl_spi2: spi2grp {
529		fsl,pins = <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK	0x00000041>,
530			   <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI	0x00000041>,
531			   <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO	0x00000041>,
532			   <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00	0x00000021>;
533	};
534
535	pinctrl_spi3: spi3grp {
536		fsl,pins = <IMX8QXP_SPI3_SCK_ADMA_SPI3_SCK	0x00000041>,
537			   <IMX8QXP_SPI3_SDI_ADMA_SPI3_SDI	0x00000041>,
538			   <IMX8QXP_SPI3_SDO_ADMA_SPI3_SDO	0x00000041>,
539			   <IMX8QXP_SPI3_CS0_LSIO_GPIO0_IO16	0x00000021>,
540			   <IMX8QXP_SPI3_CS1_ADMA_SPI3_CS1	0x00000021>;
541	};
542
543	pinctrl_usbotg1: usbotg1grp {
544		fsl,pins = <IMX8QXP_USB_SS3_TC0_CONN_USB_OTG1_PWR	0x00000021>,
545			   <IMX8QXP_USB_SS3_TC2_CONN_USB_OTG1_OC	0x00000021>;
546	};
547
548	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
549		fsl,pins = <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21		0x00000021>,
550			   <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22		0x00000021>;
551	};
552
553	pinctrl_usdhc2: usdhc2grp {
554		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041>,
555			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000021>,
556			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000021>,
557			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000021>,
558			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000021>,
559			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000021>,
560			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000021>;
561	};
562
563	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
564		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040>,
565			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020>,
566			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020>,
567			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020>,
568			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020>,
569			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020>,
570			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020>;
571	};
572
573	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
574		fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040>,
575			   <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD		0x00000020>,
576			   <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0	0x00000020>,
577			   <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1	0x00000020>,
578			   <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2	0x00000020>,
579			   <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3	0x00000020>,
580			   <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x00000020>;
581	};
582};
~/ Read-only file preview.