FILE
imx95.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/imx95.dtsi
1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2024 NXP 4 */ 5 6#include <dt-bindings/clock/nxp,imx95-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/thermal/thermal.h> 12 13#include "imx95-clock.h" 14#include "imx95-pinfunc.h" 15#include "imx95-power.h" 16 17/ { 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <1>; 24 #size-cells = <0>; 25 26 idle-states { 27 entry-method = "psci"; 28 29 cpu_pd_wait: cpu-pd-wait { 30 compatible = "arm,idle-state"; 31 arm,psci-suspend-param = <0x0010033>; 32 local-timer-stop; 33 entry-latency-us = <10000>; 34 exit-latency-us = <7000>; 35 min-residency-us = <27000>; 36 wakeup-latency-us = <15000>; 37 }; 38 }; 39 40 A55_0: cpu@0 { 41 device_type = "cpu"; 42 compatible = "arm,cortex-a55"; 43 reg = <0x0>; 44 enable-method = "psci"; 45 #cooling-cells = <2>; 46 cpu-idle-states = <&cpu_pd_wait>; 47 power-domains = <&scmi_perf IMX95_PERF_A55>; 48 power-domain-names = "perf"; 49 i-cache-size = <32768>; 50 i-cache-line-size = <64>; 51 i-cache-sets = <128>; 52 d-cache-size = <32768>; 53 d-cache-line-size = <64>; 54 d-cache-sets = <128>; 55 next-level-cache = <&l2_cache_l0>; 56 }; 57 58 A55_1: cpu@100 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a55"; 61 reg = <0x100>; 62 enable-method = "psci"; 63 #cooling-cells = <2>; 64 cpu-idle-states = <&cpu_pd_wait>; 65 power-domains = <&scmi_perf IMX95_PERF_A55>; 66 power-domain-names = "perf"; 67 i-cache-size = <32768>; 68 i-cache-line-size = <64>; 69 i-cache-sets = <128>; 70 d-cache-size = <32768>; 71 d-cache-line-size = <64>; 72 d-cache-sets = <128>; 73 next-level-cache = <&l2_cache_l1>; 74 }; 75 76 A55_2: cpu@200 { 77 device_type = "cpu"; 78 compatible = "arm,cortex-a55"; 79 reg = <0x200>; 80 enable-method = "psci"; 81 #cooling-cells = <2>; 82 cpu-idle-states = <&cpu_pd_wait>; 83 power-domains = <&scmi_perf IMX95_PERF_A55>; 84 power-domain-names = "perf"; 85 i-cache-size = <32768>; 86 i-cache-line-size = <64>; 87 i-cache-sets = <128>; 88 d-cache-size = <32768>; 89 d-cache-line-size = <64>; 90 d-cache-sets = <128>; 91 next-level-cache = <&l2_cache_l2>; 92 }; 93 94 A55_3: cpu@300 { 95 device_type = "cpu"; 96 compatible = "arm,cortex-a55"; 97 reg = <0x300>; 98 enable-method = "psci"; 99 #cooling-cells = <2>; 100 cpu-idle-states = <&cpu_pd_wait>; 101 power-domains = <&scmi_perf IMX95_PERF_A55>; 102 power-domain-names = "perf"; 103 i-cache-size = <32768>; 104 i-cache-line-size = <64>; 105 i-cache-sets = <128>; 106 d-cache-size = <32768>; 107 d-cache-line-size = <64>; 108 d-cache-sets = <128>; 109 next-level-cache = <&l2_cache_l3>; 110 }; 111 112 A55_4: cpu@400 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a55"; 115 reg = <0x400>; 116 power-domains = <&scmi_perf IMX95_PERF_A55>; 117 power-domain-names = "perf"; 118 enable-method = "psci"; 119 #cooling-cells = <2>; 120 cpu-idle-states = <&cpu_pd_wait>; 121 i-cache-size = <32768>; 122 i-cache-line-size = <64>; 123 i-cache-sets = <128>; 124 d-cache-size = <32768>; 125 d-cache-line-size = <64>; 126 d-cache-sets = <128>; 127 next-level-cache = <&l2_cache_l4>; 128 }; 129 130 A55_5: cpu@500 { 131 device_type = "cpu"; 132 compatible = "arm,cortex-a55"; 133 reg = <0x500>; 134 power-domains = <&scmi_perf IMX95_PERF_A55>; 135 power-domain-names = "perf"; 136 enable-method = "psci"; 137 #cooling-cells = <2>; 138 cpu-idle-states = <&cpu_pd_wait>; 139 i-cache-size = <32768>; 140 i-cache-line-size = <64>; 141 i-cache-sets = <128>; 142 d-cache-size = <32768>; 143 d-cache-line-size = <64>; 144 d-cache-sets = <128>; 145 next-level-cache = <&l2_cache_l5>; 146 }; 147 148 l2_cache_l0: l2-cache-l0 { 149 compatible = "cache"; 150 cache-size = <65536>; 151 cache-line-size = <64>; 152 cache-sets = <256>; 153 cache-level = <2>; 154 cache-unified; 155 next-level-cache = <&l3_cache>; 156 }; 157 158 l2_cache_l1: l2-cache-l1 { 159 compatible = "cache"; 160 cache-size = <65536>; 161 cache-line-size = <64>; 162 cache-sets = <256>; 163 cache-level = <2>; 164 cache-unified; 165 next-level-cache = <&l3_cache>; 166 }; 167 168 l2_cache_l2: l2-cache-l2 { 169 compatible = "cache"; 170 cache-size = <65536>; 171 cache-line-size = <64>; 172 cache-sets = <256>; 173 cache-level = <2>; 174 cache-unified; 175 next-level-cache = <&l3_cache>; 176 }; 177 178 l2_cache_l3: l2-cache-l3 { 179 compatible = "cache"; 180 cache-size = <65536>; 181 cache-line-size = <64>; 182 cache-sets = <256>; 183 cache-level = <2>; 184 cache-unified; 185 next-level-cache = <&l3_cache>; 186 }; 187 188 l2_cache_l4: l2-cache-l4 { 189 compatible = "cache"; 190 cache-size = <65536>; 191 cache-line-size = <64>; 192 cache-sets = <256>; 193 cache-level = <2>; 194 cache-unified; 195 next-level-cache = <&l3_cache>; 196 }; 197 198 l2_cache_l5: l2-cache-l5 { 199 compatible = "cache"; 200 cache-size = <65536>; 201 cache-line-size = <64>; 202 cache-sets = <256>; 203 cache-level = <2>; 204 cache-unified; 205 next-level-cache = <&l3_cache>; 206 }; 207 208 l3_cache: l3-cache { 209 compatible = "cache"; 210 cache-size = <524288>; 211 cache-line-size = <64>; 212 cache-sets = <512>; 213 cache-level = <3>; 214 cache-unified; 215 }; 216 217 cpu-map { 218 cluster0 { 219 core0 { 220 cpu = <&A55_0>; 221 }; 222 223 core1 { 224 cpu = <&A55_1>; 225 }; 226 227 core2 { 228 cpu = <&A55_2>; 229 }; 230 231 core3 { 232 cpu = <&A55_3>; 233 }; 234 235 core4 { 236 cpu = <&A55_4>; 237 }; 238 239 core5 { 240 cpu = <&A55_5>; 241 }; 242 }; 243 }; 244 }; 245 246 dummy: clock-dummy { 247 compatible = "fixed-clock"; 248 #clock-cells = <0>; 249 clock-frequency = <0>; 250 clock-output-names = "dummy"; 251 }; 252 253 gpu_opp_table: opp-table { 254 compatible = "operating-points-v2"; 255 256 opp-500000000 { 257 opp-hz = /bits/ 64 <500000000>; 258 opp-hz-real = /bits/ 64 <500000000>; 259 opp-microvolt = <920000>; 260 }; 261 262 opp-800000000 { 263 opp-hz = /bits/ 64 <800000000>; 264 opp-hz-real = /bits/ 64 <800000000>; 265 opp-microvolt = <920000>; 266 }; 267 268 opp-1000000000 { 269 opp-hz = /bits/ 64 <1000000000>; 270 opp-hz-real = /bits/ 64 <1000000000>; 271 opp-microvolt = <920000>; 272 }; 273 }; 274 275 clk_ext1: clock-ext1 { 276 compatible = "fixed-clock"; 277 #clock-cells = <0>; 278 clock-frequency = <133000000>; 279 clock-output-names = "clk_ext1"; 280 }; 281 282 sai1_mclk: clock-sai-mclk1 { 283 compatible = "fixed-clock"; 284 #clock-cells = <0>; 285 clock-frequency = <0>; 286 clock-output-names = "sai1_mclk"; 287 }; 288 289 sai2_mclk: clock-sai-mclk2 { 290 compatible = "fixed-clock"; 291 #clock-cells = <0>; 292 clock-frequency = <0>; 293 clock-output-names = "sai2_mclk"; 294 }; 295 296 sai3_mclk: clock-sai-mclk3 { 297 compatible = "fixed-clock"; 298 #clock-cells = <0>; 299 clock-frequency = <0>; 300 clock-output-names = "sai3_mclk"; 301 }; 302 303 sai4_mclk: clock-sai-mclk4 { 304 compatible = "fixed-clock"; 305 #clock-cells = <0>; 306 clock-frequency = <0>; 307 clock-output-names = "sai4_mclk"; 308 }; 309 310 sai5_mclk: clock-sai-mclk5 { 311 compatible = "fixed-clock"; 312 #clock-cells = <0>; 313 clock-frequency = <0>; 314 clock-output-names = "sai5_mclk"; 315 }; 316 317 clk_sys100m: clock-sys100m { 318 compatible = "fixed-clock"; 319 #clock-cells = <0>; 320 clock-frequency = <100000000>; 321 clock-output-names = "clk_sys100m"; 322 }; 323 324 osc_24m: clock-24m { 325 compatible = "fixed-clock"; 326 #clock-cells = <0>; 327 clock-frequency = <24000000>; 328 clock-output-names = "osc_24m"; 329 }; 330 331 sram1: sram@204c0000 { 332 compatible = "mmio-sram"; 333 reg = <0x0 0x204c0000 0x0 0x18000>; 334 ranges = <0x0 0x0 0x204c0000 0x18000>; 335 #address-cells = <1>; 336 #size-cells = <1>; 337 }; 338 339 firmware { 340 scmi { 341 compatible = "arm,scmi"; 342 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 343 shmem = <&scmi_buf0>, <&scmi_buf1>; 344 #address-cells = <1>; 345 #size-cells = <0>; 346 arm,max-rx-timeout-ms = <5000>; 347 348 scmi_devpd: protocol@11 { 349 reg = <0x11>; 350 #power-domain-cells = <1>; 351 }; 352 353 scmi_sys_power: protocol@12 { 354 reg = <0x12>; 355 }; 356 357 scmi_perf: protocol@13 { 358 reg = <0x13>; 359 #power-domain-cells = <1>; 360 }; 361 362 scmi_clk: protocol@14 { 363 reg = <0x14>; 364 #clock-cells = <1>; 365 }; 366 367 scmi_sensor: protocol@15 { 368 reg = <0x15>; 369 #thermal-sensor-cells = <1>; 370 }; 371 372 scmi_iomuxc: protocol@19 { 373 reg = <0x19>; 374 }; 375 376 scmi_lmm: protocol@80 { 377 reg = <0x80>; 378 }; 379 380 scmi_bbm: protocol@81 { 381 reg = <0x81>; 382 }; 383 384 scmi_cpu: protocol@82 { 385 reg = <0x82>; 386 }; 387 388 scmi_misc: protocol@84 { 389 reg = <0x84>; 390 }; 391 }; 392 }; 393 394 pmu { 395 compatible = "arm,cortex-a55-pmu"; 396 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 397 }; 398 399 thermal_zones: thermal-zones { 400 a55-thermal { 401 polling-delay-passive = <250>; 402 polling-delay = <2000>; 403 thermal-sensors = <&scmi_sensor 1>; 404 405 trips { 406 cpu_alert0: trip0 { 407 temperature = <105000>; 408 hysteresis = <2000>; 409 type = "passive"; 410 }; 411 412 cpu_crit0: trip1 { 413 temperature = <125000>; 414 hysteresis = <2000>; 415 type = "critical"; 416 }; 417 }; 418 419 cooling-maps { 420 map0 { 421 trip = <&cpu_alert0>; 422 cooling-device = 423 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 424 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 425 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 426 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 427 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 428 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 429 }; 430 }; 431 }; 432 433 ana-thermal { 434 polling-delay-passive = <250>; 435 polling-delay = <2000>; 436 thermal-sensors = <&scmi_sensor 0>; 437 trips { 438 ana_alert: trip0 { 439 temperature = <105000>; 440 hysteresis = <2000>; 441 type = "passive"; 442 }; 443 444 ana_crit0: trip1 { 445 temperature = <125000>; 446 hysteresis = <2000>; 447 type = "critical"; 448 }; 449 }; 450 451 cooling-maps { 452 map0 { 453 trip = <&ana_alert>; 454 cooling-device = 455 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 456 <&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 457 <&A55_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 458 <&A55_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 459 <&A55_4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 460 <&A55_5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 461 }; 462 }; 463 }; 464 }; 465 466 psci { 467 compatible = "arm,psci-1.0"; 468 method = "smc"; 469 }; 470 471 timer { 472 compatible = "arm,armv8-timer"; 473 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 474 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 475 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 476 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 477 clock-frequency = <24000000>; 478 arm,no-tick-in-suspend; 479 interrupt-parent = <&gic>; 480 }; 481 482 gic: interrupt-controller@48000000 { 483 compatible = "arm,gic-v3"; 484 reg = <0 0x48000000 0 0x10000>, 485 <0 0x48060000 0 0xc0000>; 486 #address-cells = <2>; 487 #size-cells = <2>; 488 #interrupt-cells = <3>; 489 interrupt-controller; 490 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 491 interrupt-parent = <&gic>; 492 dma-noncoherent; 493 ranges; 494 495 its: msi-controller@48040000 { 496 compatible = "arm,gic-v3-its"; 497 reg = <0 0x48040000 0 0x20000>; 498 msi-controller; 499 #msi-cells = <1>; 500 dma-noncoherent; 501 }; 502 }; 503 504 usbphynop: usbphynop { 505 compatible = "usb-nop-xceiv"; 506 clocks = <&scmi_clk IMX95_CLK_HSIO>; 507 clock-names = "main_clk"; 508 #phy-cells = <0>; 509 }; 510 511 soc { 512 compatible = "simple-bus"; 513 #address-cells = <2>; 514 #size-cells = <2>; 515 ranges; 516 517 etm0: etm@40840000 { 518 compatible = "arm,coresight-etm4x", "arm,primecell"; 519 reg = <0x0 0x40840000 0x0 0x10000>; 520 arm,primecell-periphid = <0xbb95d>; 521 cpu = <&A55_0>; 522 clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; 523 clock-names = "apb_pclk"; 524 status = "disabled"; 525 526 out-ports { 527 port { 528 etm0_out_port: endpoint { 529 remote-endpoint = <&ca_funnel_in_port0>; 530 }; 531 }; 532 }; 533 }; 534 535 funnel0: funnel { 536 /* 537 * non-configurable funnel don't show up on the AMBA 538 * bus. As such no need to add "arm,primecell". 539 */ 540 compatible = "arm,coresight-static-funnel"; 541 status = "disabled"; 542 543 in-ports { 544 port { 545 ca_funnel_in_port0: endpoint { 546 remote-endpoint = <&etm0_out_port>; 547 }; 548 }; 549 }; 550 551 out-ports { 552 port { 553 ca_funnel_out_port0: endpoint { 554 remote-endpoint = <&hugo_funnel_in_port0>; 555 }; 556 }; 557 }; 558 }; 559 560 funnel1: funnel-sys { 561 compatible = "arm,coresight-static-funnel"; 562 status = "disabled"; 563 564 in-ports { 565 port { 566 hugo_funnel_in_port0: endpoint { 567 remote-endpoint = <&ca_funnel_out_port0>; 568 }; 569 }; 570 }; 571 572 out-ports { 573 port { 574 hugo_funnel_out_port0: endpoint { 575 remote-endpoint = <&etf_in_port>; 576 }; 577 }; 578 }; 579 }; 580 581 etf: etf@41030000 { 582 compatible = "arm,coresight-tmc", "arm,primecell"; 583 reg = <0x0 0x41030000 0x0 0x1000>; 584 clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; 585 clock-names = "apb_pclk"; 586 status = "disabled"; 587 588 in-ports { 589 port { 590 etf_in_port: endpoint { 591 remote-endpoint = <&hugo_funnel_out_port0>; 592 }; 593 }; 594 }; 595 596 out-ports { 597 port { 598 etf_out_port: endpoint { 599 remote-endpoint = <&etr_in_port>; 600 }; 601 }; 602 }; 603 }; 604 605 etr: etr@41040000 { 606 compatible = "arm,coresight-tmc", "arm,primecell"; 607 reg = <0x0 0x41040000 0x0 0x1000>; 608 clocks = <&scmi_clk IMX95_CLK_A55PERIPH>; 609 clock-names = "apb_pclk"; 610 status = "disabled"; 611 612 in-ports { 613 port { 614 etr_in_port: endpoint { 615 remote-endpoint = <&etf_out_port>; 616 }; 617 }; 618 }; 619 }; 620 621 aips2: bus@42000000 { 622 compatible = "fsl,aips-bus", "simple-bus"; 623 reg = <0x0 0x42000000 0x0 0x800000>; 624 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 625 <0x28000000 0x0 0x28000000 0x10000000>; 626 #address-cells = <1>; 627 #size-cells = <1>; 628 629 edma2: dma-controller@42000000 { 630 compatible = "fsl,imx95-edma5"; 631 reg = <0x42000000 0x210000>; 632 #dma-cells = <3>; 633 dma-channels = <64>; 634 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 635 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 660 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 661 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 662 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 663 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 664 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 665 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 666 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 667 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 668 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 669 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 670 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 671 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 672 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 673 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 674 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 675 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 676 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 677 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 678 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 679 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 680 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; 698 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 699 clock-names = "dma"; 700 }; 701 702 edma3: dma-controller@42210000 { 703 compatible = "fsl,imx95-edma5"; 704 reg = <0x42210000 0x210000>; 705 #dma-cells = <3>; 706 dma-channels = <64>; 707 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 708 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 709 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; 771 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 772 clock-names = "dma"; 773 }; 774 775 mu7: mailbox@42430000 { 776 compatible = "fsl,imx95-mu"; 777 reg = <0x42430000 0x10000>; 778 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 779 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 780 #mbox-cells = <2>; 781 status = "disabled"; 782 }; 783 784 wdog3: watchdog@42490000 { 785 compatible = "fsl,imx93-wdt"; 786 reg = <0x42490000 0x10000>; 787 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 788 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 789 timeout-sec = <40>; 790 status = "disabled"; 791 }; 792 793 tpm3: pwm@424e0000 { 794 compatible = "fsl,imx7ulp-pwm"; 795 reg = <0x424e0000 0x1000>; 796 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 797 #pwm-cells = <3>; 798 status = "disabled"; 799 }; 800 801 tpm4: pwm@424f0000 { 802 compatible = "fsl,imx7ulp-pwm"; 803 reg = <0x424f0000 0x1000>; 804 clocks = <&scmi_clk IMX95_CLK_TPM4>; 805 #pwm-cells = <3>; 806 status = "disabled"; 807 }; 808 809 tpm5: pwm@42500000 { 810 compatible = "fsl,imx7ulp-pwm"; 811 reg = <0x42500000 0x1000>; 812 clocks = <&scmi_clk IMX95_CLK_TPM5>; 813 #pwm-cells = <3>; 814 status = "disabled"; 815 }; 816 817 tpm6: pwm@42510000 { 818 compatible = "fsl,imx7ulp-pwm"; 819 reg = <0x42510000 0x1000>; 820 clocks = <&scmi_clk IMX95_CLK_TPM6>; 821 #pwm-cells = <3>; 822 status = "disabled"; 823 }; 824 825 i3c2: i3c@42520000 { 826 compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1"; 827 reg = <0x42520000 0x10000>; 828 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 829 #address-cells = <3>; 830 #size-cells = <0>; 831 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 832 <&scmi_clk IMX95_CLK_I3C2SLOW>; 833 clock-names = "pclk", "fast_clk"; 834 status = "disabled"; 835 }; 836 837 lpi2c3: i2c@42530000 { 838 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 839 reg = <0x42530000 0x10000>; 840 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&scmi_clk IMX95_CLK_LPI2C3>, 842 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 843 clock-names = "per", "ipg"; 844 #address-cells = <1>; 845 #size-cells = <0>; 846 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 847 dma-names = "tx", "rx"; 848 status = "disabled"; 849 }; 850 851 lpi2c4: i2c@42540000 { 852 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 853 reg = <0x42540000 0x10000>; 854 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&scmi_clk IMX95_CLK_LPI2C4>, 856 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 857 clock-names = "per", "ipg"; 858 #address-cells = <1>; 859 #size-cells = <0>; 860 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 861 dma-names = "tx", "rx"; 862 status = "disabled"; 863 }; 864 865 lpspi3: spi@42550000 { 866 #address-cells = <1>; 867 #size-cells = <0>; 868 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 869 reg = <0x42550000 0x10000>; 870 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&scmi_clk IMX95_CLK_LPSPI3>, 872 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 873 clock-names = "per", "ipg"; 874 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 875 dma-names = "tx", "rx"; 876 status = "disabled"; 877 }; 878 879 lpspi4: spi@42560000 { 880 #address-cells = <1>; 881 #size-cells = <0>; 882 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 883 reg = <0x42560000 0x10000>; 884 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 885 clocks = <&scmi_clk IMX95_CLK_LPSPI4>, 886 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 887 clock-names = "per", "ipg"; 888 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 889 dma-names = "tx", "rx"; 890 status = "disabled"; 891 }; 892 893 lpuart3: serial@42570000 { 894 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 895 "fsl,imx7ulp-lpuart"; 896 reg = <0x42570000 0x1000>; 897 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 898 clocks = <&scmi_clk IMX95_CLK_LPUART3>; 899 clock-names = "ipg"; 900 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 901 dma-names = "rx", "tx"; 902 status = "disabled"; 903 }; 904 905 lpuart4: serial@42580000 { 906 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 907 "fsl,imx7ulp-lpuart"; 908 reg = <0x42580000 0x1000>; 909 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 910 clocks = <&scmi_clk IMX95_CLK_LPUART4>; 911 clock-names = "ipg"; 912 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 913 dma-names = "rx", "tx"; 914 status = "disabled"; 915 }; 916 917 lpuart5: serial@42590000 { 918 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 919 "fsl,imx7ulp-lpuart"; 920 reg = <0x42590000 0x1000>; 921 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 922 clocks = <&scmi_clk IMX95_CLK_LPUART5>; 923 clock-names = "ipg"; 924 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 925 dma-names = "rx", "tx"; 926 status = "disabled"; 927 }; 928 929 lpuart6: serial@425a0000 { 930 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 931 "fsl,imx7ulp-lpuart"; 932 reg = <0x425a0000 0x1000>; 933 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 934 clocks = <&scmi_clk IMX95_CLK_LPUART6>; 935 clock-names = "ipg"; 936 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 937 dma-names = "rx", "tx"; 938 status = "disabled"; 939 }; 940 941 flexcan2: can@425b0000 { 942 compatible = "fsl,imx95-flexcan"; 943 reg = <0x425b0000 0x10000>; 944 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 945 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 946 <&scmi_clk IMX95_CLK_CAN2>; 947 clock-names = "ipg", "per"; 948 assigned-clocks = <&scmi_clk IMX95_CLK_CAN2>; 949 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 950 assigned-clock-rates = <40000000>; 951 fsl,clk-source = /bits/ 8 <0>; 952 status = "disabled"; 953 }; 954 955 flexcan3: can@42600000 { 956 compatible = "fsl,imx95-flexcan"; 957 reg = <0x42600000 0x10000>; 958 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 959 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 960 <&scmi_clk IMX95_CLK_CAN3>; 961 clock-names = "ipg", "per"; 962 assigned-clocks = <&scmi_clk IMX95_CLK_CAN3>; 963 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 964 assigned-clock-rates = <40000000>; 965 fsl,clk-source = /bits/ 8 <0>; 966 status = "disabled"; 967 }; 968 969 flexspi1: spi@425e0000 { 970 compatible = "nxp,imx95-fspi", "nxp,imx8mm-fspi"; 971 reg = <0x425e0000 0x10000>, <0x28000000 0x8000000>; 972 reg-names = "fspi_base", "fspi_mmap"; 973 #address-cells = <1>; 974 #size-cells = <0>; 975 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 976 clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>, 977 <&scmi_clk IMX95_CLK_FLEXSPI1>; 978 clock-names = "fspi_en", "fspi"; 979 assigned-clocks = <&scmi_clk IMX95_CLK_FLEXSPI1>; 980 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 981 assigned-clock-rates = <200000000>; 982 status = "disabled"; 983 }; 984 985 sai3: sai@42650000 { 986 compatible = "fsl,imx95-sai"; 987 reg = <0x42650000 0x10000>; 988 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 989 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 990 <&scmi_clk IMX95_CLK_SAI3>, <&dummy>, 991 <&dummy>; 992 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 993 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 994 dma-names = "rx", "tx"; 995 status = "disabled"; 996 }; 997 998 sai4: sai@42660000 { 999 compatible = "fsl,imx95-sai"; 1000 reg = <0x42660000 0x10000>; 1001 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 1003 <&scmi_clk IMX95_CLK_SAI4>, <&dummy>, 1004 <&dummy>; 1005 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1006 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; 1007 dma-names = "rx", "tx"; 1008 status = "disabled"; 1009 }; 1010 1011 sai5: sai@42670000 { 1012 compatible = "fsl,imx95-sai"; 1013 reg = <0x42670000 0x10000>; 1014 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1015 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, <&dummy>, 1016 <&scmi_clk IMX95_CLK_SAI5>, <&dummy>, 1017 <&dummy>; 1018 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1019 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; 1020 dma-names = "rx", "tx"; 1021 status = "disabled"; 1022 }; 1023 1024 xcvr: xcvr@42680000 { 1025 compatible = "fsl,imx95-xcvr"; 1026 reg = <0x42680000 0x800>, <0x42680800 0x400>, 1027 <0x42680c00 0x080>, <0x42680e00 0x080>; 1028 reg-names = "ram", "regs", "rxfifo", "txfifo"; 1029 interrupts = /* XCVR IRQ 0 */ 1030 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1031 /* XCVR IRQ 1 */ 1032 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1033 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1034 <&scmi_clk IMX95_CLK_SPDIF>, 1035 <&dummy>, 1036 <&scmi_clk IMX95_CLK_AUDIOXCVR>; 1037 clock-names = "ipg", "phy", "spba", "pll_ipg"; 1038 dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; 1039 dma-names = "rx", "tx"; 1040 status = "disabled"; 1041 }; 1042 1043 lpuart7: serial@42690000 { 1044 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1045 "fsl,imx7ulp-lpuart"; 1046 reg = <0x42690000 0x1000>; 1047 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 1048 clocks = <&scmi_clk IMX95_CLK_LPUART7>; 1049 clock-names = "ipg"; 1050 dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; 1051 dma-names = "rx", "tx"; 1052 status = "disabled"; 1053 }; 1054 1055 lpuart8: serial@426a0000 { 1056 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1057 "fsl,imx7ulp-lpuart"; 1058 reg = <0x426a0000 0x1000>; 1059 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 1060 clocks = <&scmi_clk IMX95_CLK_LPUART8>; 1061 clock-names = "ipg"; 1062 dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; 1063 dma-names = "rx", "tx"; 1064 status = "disabled"; 1065 }; 1066 1067 lpi2c5: i2c@426b0000 { 1068 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1069 reg = <0x426b0000 0x10000>; 1070 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 1071 clocks = <&scmi_clk IMX95_CLK_LPI2C5>, 1072 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1073 clock-names = "per", "ipg"; 1074 #address-cells = <1>; 1075 #size-cells = <0>; 1076 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 1077 dma-names = "tx", "rx"; 1078 status = "disabled"; 1079 }; 1080 1081 lpi2c6: i2c@426c0000 { 1082 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1083 reg = <0x426c0000 0x10000>; 1084 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 1085 clocks = <&scmi_clk IMX95_CLK_LPI2C6>, 1086 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1087 clock-names = "per", "ipg"; 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 1091 dma-names = "tx", "rx"; 1092 status = "disabled"; 1093 }; 1094 1095 lpi2c7: i2c@426d0000 { 1096 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1097 reg = <0x426d0000 0x10000>; 1098 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 1099 clocks = <&scmi_clk IMX95_CLK_LPI2C7>, 1100 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1101 clock-names = "per", "ipg"; 1102 #address-cells = <1>; 1103 #size-cells = <0>; 1104 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 1105 dma-names = "tx", "rx"; 1106 status = "disabled"; 1107 }; 1108 1109 lpi2c8: i2c@426e0000 { 1110 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1111 reg = <0x426e0000 0x10000>; 1112 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 1113 clocks = <&scmi_clk IMX95_CLK_LPI2C8>, 1114 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1115 clock-names = "per", "ipg"; 1116 #address-cells = <1>; 1117 #size-cells = <0>; 1118 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 1119 dma-names = "tx", "rx"; 1120 status = "disabled"; 1121 }; 1122 1123 lpspi5: spi@426f0000 { 1124 #address-cells = <1>; 1125 #size-cells = <0>; 1126 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1127 reg = <0x426f0000 0x10000>; 1128 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&scmi_clk IMX95_CLK_LPSPI5>, 1130 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1131 clock-names = "per", "ipg"; 1132 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 1133 dma-names = "tx", "rx"; 1134 status = "disabled"; 1135 }; 1136 1137 lpspi6: spi@42700000 { 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1141 reg = <0x42700000 0x10000>; 1142 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&scmi_clk IMX95_CLK_LPSPI6>, 1144 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1145 clock-names = "per", "ipg"; 1146 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 1147 dma-names = "tx", "rx"; 1148 status = "disabled"; 1149 }; 1150 1151 lpspi7: spi@42710000 { 1152 #address-cells = <1>; 1153 #size-cells = <0>; 1154 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1155 reg = <0x42710000 0x10000>; 1156 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&scmi_clk IMX95_CLK_LPSPI7>, 1158 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1159 clock-names = "per", "ipg"; 1160 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 1161 dma-names = "tx", "rx"; 1162 status = "disabled"; 1163 }; 1164 1165 lpspi8: spi@42720000 { 1166 #address-cells = <1>; 1167 #size-cells = <0>; 1168 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1169 reg = <0x42720000 0x10000>; 1170 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&scmi_clk IMX95_CLK_LPSPI8>, 1172 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1173 clock-names = "per", "ipg"; 1174 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 1175 dma-names = "tx", "rx"; 1176 status = "disabled"; 1177 }; 1178 1179 mu8: mailbox@42730000 { 1180 compatible = "fsl,imx95-mu"; 1181 reg = <0x42730000 0x10000>; 1182 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 1183 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1184 #mbox-cells = <2>; 1185 status = "disabled"; 1186 }; 1187 1188 flexcan4: can@427c0000 { 1189 compatible = "fsl,imx95-flexcan"; 1190 reg = <0x427c0000 0x10000>; 1191 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1192 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1193 <&scmi_clk IMX95_CLK_CAN4>; 1194 clock-names = "ipg", "per"; 1195 assigned-clocks = <&scmi_clk IMX95_CLK_CAN4>; 1196 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1197 assigned-clock-rates = <40000000>; 1198 fsl,clk-source = /bits/ 8 <0>; 1199 status = "disabled"; 1200 }; 1201 1202 flexcan5: can@427d0000 { 1203 compatible = "fsl,imx95-flexcan"; 1204 reg = <0x427d0000 0x10000>; 1205 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 1206 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1207 <&scmi_clk IMX95_CLK_CAN5>; 1208 clock-names = "ipg", "per"; 1209 assigned-clocks = <&scmi_clk IMX95_CLK_CAN5>; 1210 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1211 assigned-clock-rates = <40000000>; 1212 fsl,clk-source = /bits/ 8 <0>; 1213 status = "disabled"; 1214 }; 1215 }; 1216 1217 aips3: bus@42800000 { 1218 compatible = "fsl,aips-bus", "simple-bus"; 1219 reg = <0 0x42800000 0 0x800000>; 1220 #address-cells = <1>; 1221 #size-cells = <1>; 1222 ranges = <0x42800000 0x0 0x42800000 0x800000>; 1223 1224 usdhc1: mmc@42850000 { 1225 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1226 reg = <0x42850000 0x10000>; 1227 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1229 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1230 <&scmi_clk IMX95_CLK_USDHC1>; 1231 clock-names = "ipg", "ahb", "per"; 1232 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC1>; 1233 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1234 assigned-clock-rates = <400000000>; 1235 bus-width = <8>; 1236 fsl,tuning-start-tap = <1>; 1237 fsl,tuning-step = <2>; 1238 status = "disabled"; 1239 }; 1240 1241 usdhc2: mmc@42860000 { 1242 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1243 reg = <0x42860000 0x10000>; 1244 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1246 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1247 <&scmi_clk IMX95_CLK_USDHC2>; 1248 clock-names = "ipg", "ahb", "per"; 1249 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC2>; 1250 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1251 assigned-clock-rates = <400000000>; 1252 bus-width = <4>; 1253 fsl,tuning-start-tap = <1>; 1254 fsl,tuning-step = <2>; 1255 status = "disabled"; 1256 }; 1257 1258 usdhc3: mmc@428b0000 { 1259 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 1260 reg = <0x428b0000 0x10000>; 1261 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 1262 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1263 <&scmi_clk IMX95_CLK_WAKEUPAXI>, 1264 <&scmi_clk IMX95_CLK_USDHC3>; 1265 clock-names = "ipg", "ahb", "per"; 1266 assigned-clocks = <&scmi_clk IMX95_CLK_USDHC3>; 1267 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1>; 1268 assigned-clock-rates = <400000000>; 1269 bus-width = <4>; 1270 fsl,tuning-start-tap = <1>; 1271 fsl,tuning-step = <2>; 1272 status = "disabled"; 1273 }; 1274 }; 1275 1276 gpio2: gpio@43810000 { 1277 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1278 reg = <0x0 0x43810000 0x0 0x1000>; 1279 gpio-controller; 1280 #gpio-cells = <2>; 1281 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1282 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1283 interrupt-controller; 1284 #interrupt-cells = <2>; 1285 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1286 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1287 clock-names = "gpio", "port"; 1288 gpio-ranges = <&scmi_iomuxc 0 4 32>; 1289 ngpios = <32>; 1290 }; 1291 1292 gpio3: gpio@43820000 { 1293 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1294 reg = <0x0 0x43820000 0x0 0x1000>; 1295 gpio-controller; 1296 #gpio-cells = <2>; 1297 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1298 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1299 interrupt-controller; 1300 #interrupt-cells = <2>; 1301 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1302 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1303 clock-names = "gpio", "port"; 1304 gpio-ranges = <&scmi_iomuxc 0 104 8>, <&scmi_iomuxc 8 74 18>, 1305 <&scmi_iomuxc 26 42 2>, <&scmi_iomuxc 28 0 4>; 1306 ngpios = <32>; 1307 }; 1308 1309 gpio4: gpio@43840000 { 1310 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1311 reg = <0x0 0x43840000 0x0 0x1000>; 1312 gpio-controller; 1313 #gpio-cells = <2>; 1314 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1315 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1316 interrupt-controller; 1317 #interrupt-cells = <2>; 1318 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1319 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1320 clock-names = "gpio", "port"; 1321 gpio-ranges = <&scmi_iomuxc 0 46 28>, <&scmi_iomuxc 28 44 2>; 1322 ngpios = <30>; 1323 }; 1324 1325 gpio5: gpio@43850000 { 1326 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1327 reg = <0x0 0x43850000 0x0 0x1000>; 1328 gpio-controller; 1329 #gpio-cells = <2>; 1330 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1331 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1332 interrupt-controller; 1333 #interrupt-cells = <2>; 1334 clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>, 1335 <&scmi_clk IMX95_CLK_BUSWAKEUP>; 1336 clock-names = "gpio", "port"; 1337 gpio-ranges = <&scmi_iomuxc 0 92 12>, <&scmi_iomuxc 12 36 6>; 1338 ngpios = <18>; 1339 }; 1340 1341 aips1: bus@44000000 { 1342 compatible = "fsl,aips-bus", "simple-bus"; 1343 reg = <0x0 0x44000000 0x0 0x800000>; 1344 ranges = <0x44000000 0x0 0x44000000 0x800000>; 1345 #address-cells = <1>; 1346 #size-cells = <1>; 1347 1348 edma1: dma-controller@44000000 { 1349 compatible = "fsl,imx93-edma3"; 1350 reg = <0x44000000 0x200000>; 1351 #dma-cells = <3>; 1352 dma-channels = <31>; 1353 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1354 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1355 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1356 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1357 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1358 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1359 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1360 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1361 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1362 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1363 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1364 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1365 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1366 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1367 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1368 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1369 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1370 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1371 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1372 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1374 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1375 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1376 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1377 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1378 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1379 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1383 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 1384 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1385 clock-names = "dma"; 1386 }; 1387 1388 mu1: mailbox@44220000 { 1389 compatible = "fsl,imx95-mu"; 1390 reg = <0x44220000 0x10000>; 1391 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1392 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1393 #mbox-cells = <2>; 1394 status = "disabled"; 1395 }; 1396 1397 system_counter: timer@44290000 { 1398 compatible = "nxp,imx95-sysctr-timer"; 1399 reg = <0x44290000 0x30000>; 1400 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1401 clocks = <&osc_24m>; 1402 clock-names = "per"; 1403 nxp,no-divider; 1404 }; 1405 1406 tpm1: pwm@44310000 { 1407 compatible = "fsl,imx7ulp-pwm"; 1408 reg = <0x44310000 0x1000>; 1409 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1410 #pwm-cells = <3>; 1411 status = "disabled"; 1412 }; 1413 1414 tpm2: pwm@44320000 { 1415 compatible = "fsl,imx7ulp-pwm"; 1416 reg = <0x44320000 0x1000>; 1417 clocks = <&scmi_clk IMX95_CLK_TPM2>; 1418 #pwm-cells = <3>; 1419 status = "disabled"; 1420 }; 1421 1422 i3c1: i3c@44330000 { 1423 compatible = "nxp,imx95-i3c", "silvaco,i3c-master-v1"; 1424 reg = <0x44330000 0x10000>; 1425 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1426 #address-cells = <3>; 1427 #size-cells = <0>; 1428 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1429 <&scmi_clk IMX95_CLK_I3C1SLOW>; 1430 clock-names = "pclk", "fast_clk"; 1431 status = "disabled"; 1432 }; 1433 1434 lpi2c1: i2c@44340000 { 1435 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1436 reg = <0x44340000 0x10000>; 1437 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1438 clocks = <&scmi_clk IMX95_CLK_LPI2C1>, 1439 <&scmi_clk IMX95_CLK_BUSAON>; 1440 clock-names = "per", "ipg"; 1441 #address-cells = <1>; 1442 #size-cells = <0>; 1443 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; 1444 dma-names = "tx", "rx"; 1445 status = "disabled"; 1446 }; 1447 1448 lpi2c2: i2c@44350000 { 1449 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1450 reg = <0x44350000 0x10000>; 1451 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1452 clocks = <&scmi_clk IMX95_CLK_LPI2C2>, 1453 <&scmi_clk IMX95_CLK_BUSAON>; 1454 clock-names = "per", "ipg"; 1455 #address-cells = <1>; 1456 #size-cells = <0>; 1457 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; 1458 dma-names = "tx", "rx"; 1459 status = "disabled"; 1460 }; 1461 1462 lpspi1: spi@44360000 { 1463 #address-cells = <1>; 1464 #size-cells = <0>; 1465 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1466 reg = <0x44360000 0x10000>; 1467 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1468 clocks = <&scmi_clk IMX95_CLK_LPSPI1>, 1469 <&scmi_clk IMX95_CLK_BUSAON>; 1470 clock-names = "per", "ipg"; 1471 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; 1472 dma-names = "tx", "rx"; 1473 status = "disabled"; 1474 }; 1475 1476 lpspi2: spi@44370000 { 1477 #address-cells = <1>; 1478 #size-cells = <0>; 1479 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1480 reg = <0x44370000 0x10000>; 1481 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1482 clocks = <&scmi_clk IMX95_CLK_LPSPI2>, 1483 <&scmi_clk IMX95_CLK_BUSAON>; 1484 clock-names = "per", "ipg"; 1485 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; 1486 dma-names = "tx", "rx"; 1487 status = "disabled"; 1488 }; 1489 1490 lpuart1: serial@44380000 { 1491 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1492 "fsl,imx7ulp-lpuart"; 1493 reg = <0x44380000 0x1000>; 1494 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1495 clocks = <&scmi_clk IMX95_CLK_LPUART1>; 1496 clock-names = "ipg"; 1497 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1498 dma-names = "rx", "tx"; 1499 status = "disabled"; 1500 }; 1501 1502 lpuart2: serial@44390000 { 1503 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1504 "fsl,imx7ulp-lpuart"; 1505 reg = <0x44390000 0x1000>; 1506 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1507 clocks = <&scmi_clk IMX95_CLK_LPUART2>; 1508 clock-names = "ipg"; 1509 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1510 dma-names = "rx", "tx"; 1511 status = "disabled"; 1512 }; 1513 1514 flexcan1: can@443a0000 { 1515 compatible = "fsl,imx95-flexcan"; 1516 reg = <0x443a0000 0x10000>; 1517 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1518 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1519 <&scmi_clk IMX95_CLK_CAN1>; 1520 clock-names = "ipg", "per"; 1521 assigned-clocks = <&scmi_clk IMX95_CLK_CAN1>; 1522 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1523 assigned-clock-rates = <40000000>; 1524 fsl,clk-source = /bits/ 8 <0>; 1525 status = "disabled"; 1526 }; 1527 1528 sai1: sai@443b0000 { 1529 compatible = "fsl,imx95-sai"; 1530 reg = <0x443b0000 0x10000>; 1531 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1532 clocks = <&scmi_clk IMX95_CLK_BUSAON>, <&dummy>, 1533 <&scmi_clk IMX95_CLK_SAI1>, <&dummy>, 1534 <&dummy>; 1535 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1536 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1537 dma-names = "rx", "tx"; 1538 status = "disabled"; 1539 }; 1540 1541 micfil: micfil@44520000 { 1542 compatible = "fsl,imx95-micfil", "fsl,imx93-micfil"; 1543 reg = <0x44520000 0x10000>; 1544 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1545 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1546 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1547 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&scmi_clk IMX95_CLK_BUSAON>, 1549 <&scmi_clk IMX95_CLK_PDM>, 1550 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 1551 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 1552 <&dummy>; 1553 clock-names = "ipg_clk", "ipg_clk_app", 1554 "pll8k", "pll11k", "clkext3"; 1555 dmas = <&edma1 6 0 5>; 1556 dma-names = "rx"; 1557 status = "disabled"; 1558 }; 1559 1560 adc1: adc@44530000 { 1561 compatible = "nxp,imx93-adc"; 1562 reg = <0x44530000 0x10000>; 1563 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1564 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1565 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1566 clocks = <&scmi_clk IMX95_CLK_ADC>; 1567 clock-names = "ipg"; 1568 #io-channel-cells = <1>; 1569 status = "disabled"; 1570 }; 1571 1572 mu2: mailbox@445b0000 { 1573 compatible = "fsl,imx95-mu"; 1574 reg = <0x445b0000 0x1000>; 1575 ranges; 1576 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1577 #address-cells = <1>; 1578 #size-cells = <1>; 1579 #mbox-cells = <2>; 1580 1581 sram0: sram@445b1000 { 1582 compatible = "mmio-sram"; 1583 reg = <0x445b1000 0x400>; 1584 ranges = <0x0 0x445b1000 0x400>; 1585 #address-cells = <1>; 1586 #size-cells = <1>; 1587 1588 scmi_buf0: scmi-sram-section@0 { 1589 compatible = "arm,scmi-shmem"; 1590 reg = <0x0 0x80>; 1591 }; 1592 1593 scmi_buf1: scmi-sram-section@80 { 1594 compatible = "arm,scmi-shmem"; 1595 reg = <0x80 0x80>; 1596 }; 1597 }; 1598 1599 }; 1600 1601 mu3: mailbox@445d0000 { 1602 compatible = "fsl,imx95-mu"; 1603 reg = <0x445d0000 0x10000>; 1604 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1605 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1606 #mbox-cells = <2>; 1607 status = "disabled"; 1608 }; 1609 1610 mu4: mailbox@445f0000 { 1611 compatible = "fsl,imx95-mu"; 1612 reg = <0x445f0000 0x10000>; 1613 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1614 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1615 #mbox-cells = <2>; 1616 status = "disabled"; 1617 }; 1618 1619 mu6: mailbox@44630000 { 1620 compatible = "fsl,imx95-mu"; 1621 reg = <0x44630000 0x10000>; 1622 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1623 clocks = <&scmi_clk IMX95_CLK_BUSAON>; 1624 #mbox-cells = <2>; 1625 status = "disabled"; 1626 }; 1627 }; 1628 1629 mailbox@47300000 { 1630 compatible = "fsl,imx95-mu-v2x"; 1631 reg = <0x0 0x47300000 0x0 0x10000>; 1632 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1633 #mbox-cells = <2>; 1634 }; 1635 1636 mailbox@47320000 { 1637 compatible = "fsl,imx95-mu-v2x"; 1638 reg = <0x0 0x47320000 0x0 0x10000>; 1639 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1640 #mbox-cells = <2>; 1641 }; 1642 1643 mailbox@47330000 { 1644 compatible = "fsl,imx95-mu-v2x"; 1645 reg = <0x0 0x47330000 0x0 0x10000>; 1646 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1647 #mbox-cells = <2>; 1648 }; 1649 1650 mailbox@47340000 { 1651 compatible = "fsl,imx95-mu-v2x"; 1652 reg = <0x0 0x47340000 0x0 0x10000>; 1653 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1654 #mbox-cells = <2>; 1655 }; 1656 1657 mailbox@47350000 { 1658 compatible = "fsl,imx95-mu-v2x"; 1659 reg = <0x0 0x47350000 0x0 0x10000>; 1660 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1661 #mbox-cells = <2>; 1662 }; 1663 1664 /* GPIO1 is under exclusive control of System Manager */ 1665 gpio1: gpio@47400000 { 1666 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1667 reg = <0x0 0x47400000 0x0 0x1000>; 1668 gpio-controller; 1669 #gpio-cells = <2>; 1670 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1671 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1672 interrupt-controller; 1673 #interrupt-cells = <2>; 1674 clocks = <&scmi_clk IMX95_CLK_M33>, 1675 <&scmi_clk IMX95_CLK_M33>; 1676 clock-names = "gpio", "port"; 1677 gpio-ranges = <&scmi_iomuxc 0 112 16>; 1678 ngpios = <16>; 1679 status = "disabled"; 1680 }; 1681 1682 ocotp: efuse@47510000 { 1683 compatible = "fsl,imx95-ocotp", "syscon"; 1684 reg = <0x0 0x47510000 0x0 0x10000>; 1685 #address-cells = <1>; 1686 #size-cells = <1>; 1687 1688 eth_mac0: mac-address@0 { 1689 reg = <0x0514 0x6>; 1690 }; 1691 1692 eth_mac1: mac-address@1 { 1693 reg = <0x1514 0x6>; 1694 }; 1695 1696 eth_mac2: mac-address@2 { 1697 reg = <0x2514 0x6>; 1698 }; 1699 }; 1700 1701 elemu0: mailbox@47520000 { 1702 compatible = "fsl,imx95-mu-ele"; 1703 reg = <0x0 0x47520000 0x0 0x10000>; 1704 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1705 #mbox-cells = <2>; 1706 status = "disabled"; 1707 }; 1708 1709 elemu1: mailbox@47530000 { 1710 compatible = "fsl,imx95-mu-ele"; 1711 reg = <0x0 0x47530000 0x0 0x10000>; 1712 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1713 #mbox-cells = <2>; 1714 status = "disabled"; 1715 }; 1716 1717 elemu2: mailbox@47540000 { 1718 compatible = "fsl,imx95-mu-ele"; 1719 reg = <0x0 0x47540000 0x0 0x10000>; 1720 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1721 #mbox-cells = <2>; 1722 status = "disabled"; 1723 }; 1724 1725 elemu3: mailbox@47550000 { 1726 compatible = "fsl,imx95-mu-ele"; 1727 reg = <0x0 0x47550000 0x0 0x10000>; 1728 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1729 #mbox-cells = <2>; 1730 }; 1731 1732 elemu4: mailbox@47560000 { 1733 compatible = "fsl,imx95-mu-ele"; 1734 reg = <0x0 0x47560000 0x0 0x10000>; 1735 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1736 #mbox-cells = <2>; 1737 status = "disabled"; 1738 }; 1739 1740 elemu5: mailbox@47570000 { 1741 compatible = "fsl,imx95-mu-ele"; 1742 reg = <0x0 0x47570000 0x0 0x10000>; 1743 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1744 #mbox-cells = <2>; 1745 status = "disabled"; 1746 }; 1747 1748 aips4: bus@49000000 { 1749 compatible = "fsl,aips-bus", "simple-bus"; 1750 reg = <0x0 0x49000000 0x0 0x800000>; 1751 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1752 #address-cells = <1>; 1753 #size-cells = <1>; 1754 1755 smmu: iommu@490d0000 { 1756 compatible = "arm,smmu-v3"; 1757 reg = <0x490d0000 0x100000>; 1758 interrupts = <GIC_SPI 325 IRQ_TYPE_EDGE_RISING>, 1759 <GIC_SPI 328 IRQ_TYPE_EDGE_RISING>, 1760 <GIC_SPI 334 IRQ_TYPE_EDGE_RISING>, 1761 <GIC_SPI 326 IRQ_TYPE_EDGE_RISING>; 1762 interrupt-names = "eventq", "gerror", "priq", "cmdq-sync"; 1763 #iommu-cells = <1>; 1764 status = "disabled"; 1765 }; 1766 }; 1767 1768 usb3: usb@4c010010 { 1769 compatible = "fsl,imx95-dwc3", "fsl,imx8mp-dwc3"; 1770 reg = <0x0 0x4c010010 0x0 0x04>, 1771 <0x0 0x4c1f0000 0x0 0x20>; 1772 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1773 <&scmi_clk IMX95_CLK_32K>; 1774 clock-names = "hsio", "suspend"; 1775 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1776 #address-cells = <2>; 1777 #size-cells = <2>; 1778 ranges; 1779 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1780 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 1781 status = "disabled"; 1782 1783 usb3_dwc3: usb@4c100000 { 1784 compatible = "snps,dwc3"; 1785 reg = <0x0 0x4c100000 0x0 0x10000>; 1786 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1787 <&scmi_clk IMX95_CLK_24M>, 1788 <&scmi_clk IMX95_CLK_32K>; 1789 clock-names = "bus_early", "ref", "suspend"; 1790 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 1791 phys = <&usb3_phy>, <&usb3_phy>; 1792 phy-names = "usb2-phy", "usb3-phy"; 1793 snps,gfladj-refclk-lpm-sel-quirk; 1794 snps,parkmode-disable-ss-quirk; 1795 iommus = <&smmu 0xe>; 1796 }; 1797 }; 1798 1799 hsio_blk_ctl: syscon@4c0100c0 { 1800 compatible = "nxp,imx95-hsio-blk-ctl", "syscon"; 1801 reg = <0x0 0x4c0100c0 0x0 0x1>; 1802 #clock-cells = <1>; 1803 clocks = <&clk_sys100m>; 1804 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1805 }; 1806 1807 usb3_phy: phy@4c1f0040 { 1808 compatible = "fsl,imx95-usb-phy", "fsl,imx8mp-usb-phy"; 1809 reg = <0x0 0x4c1f0040 0x0 0x40>, 1810 <0x0 0x4c1fc000 0x0 0x100>; 1811 clocks = <&scmi_clk IMX95_CLK_HSIO>; 1812 clock-names = "phy"; 1813 #phy-cells = <0>; 1814 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1815 status = "disabled"; 1816 }; 1817 1818 usb2: usb@4c200000 { 1819 compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1820 reg = <0x0 0x4c200000 0x0 0x200>; 1821 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1822 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1823 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1824 <&scmi_clk IMX95_CLK_32K>; 1825 clock-names = "usb_ctrl_root", "usb_wakeup"; 1826 iommus = <&smmu 0xf>; 1827 phys = <&usbphynop>; 1828 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1829 fsl,usbmisc = <&usbmisc 0>; 1830 status = "disabled"; 1831 }; 1832 1833 usbmisc: usbmisc@4c200200 { 1834 compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", 1835 "fsl,imx6q-usbmisc"; 1836 reg = <0x0 0x4c200200 0x0 0x200>, 1837 <0x0 0x4c010014 0x0 0x04>; 1838 #index-cells = <1>; 1839 }; 1840 1841 pcie0: pcie@4c300000 { 1842 compatible = "fsl,imx95-pcie"; 1843 reg = <0 0x4c300000 0 0x10000>, 1844 <0 0x60100000 0 0xfe00000>, 1845 <0 0x4c360000 0 0x10000>, 1846 <0 0x4c340000 0 0x4000>; 1847 reg-names = "dbi", "config", "atu", "app"; 1848 ranges = <0x81000000 0x0 0x00000000 0x0 0x6ff00000 0 0x00100000>, 1849 <0x82000000 0x0 0x10000000 0x9 0x10000000 0 0x10000000>; 1850 #address-cells = <3>; 1851 #size-cells = <2>; 1852 device_type = "pci"; 1853 linux,pci-domain = <0>; 1854 bus-range = <0x00 0xff>; 1855 num-lanes = <1>; 1856 num-viewport = <8>; 1857 interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>; 1858 interrupt-names = "msi"; 1859 #interrupt-cells = <1>; 1860 interrupt-map-mask = <0 0 0 0x7>; 1861 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 1862 <0 0 0 2 &gic 0 0 GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 1863 <0 0 0 3 &gic 0 0 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 1864 <0 0 0 4 &gic 0 0 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 1865 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1866 <&scmi_clk IMX95_CLK_HSIOPLL>, 1867 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1868 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1869 <&hsio_blk_ctl 0>; 1870 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1871 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1872 <&scmi_clk IMX95_CLK_HSIOPLL>, 1873 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1874 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1875 assigned-clock-parents = <0>, <0>, 1876 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1877 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1878 /* pcie0's Devid(BIT[7:6]) is 0x00, stream id(BIT[5:0]) is 0x10~0x17 */ 1879 msi-map = <0x0 &its 0x10 0x1>, 1880 <0x100 &its 0x11 0x7>; 1881 iommu-map = <0x000 &smmu 0x10 0x1>, 1882 <0x100 &smmu 0x11 0x7>; 1883 iommu-map-mask = <0x1ff>; 1884 fsl,max-link-speed = <3>; 1885 status = "disabled"; 1886 }; 1887 1888 pcie0_ep: pcie-ep@4c300000 { 1889 compatible = "fsl,imx95-pcie-ep"; 1890 reg = <0 0x4c300000 0 0x10000>, 1891 <0 0x4c360000 0 0x1000>, 1892 <0 0x4c320000 0 0x1000>, 1893 <0 0x4c340000 0 0x4000>, 1894 <0 0x4c370000 0 0x10000>, 1895 <0x9 0 1 0>; 1896 reg-names = "dbi","atu", "dbi2", "app", "dma", "addr_space"; 1897 num-lanes = <1>; 1898 interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>; 1899 interrupt-names = "dma"; 1900 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1901 <&scmi_clk IMX95_CLK_HSIOPLL>, 1902 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1903 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1904 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1905 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1906 <&scmi_clk IMX95_CLK_HSIOPLL>, 1907 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1908 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1909 assigned-clock-parents = <0>, <0>, 1910 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1911 msi-map = <0x0 &its 0x10 0x1>; 1912 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1913 status = "disabled"; 1914 }; 1915 1916 pcie1: pcie@4c380000 { 1917 compatible = "fsl,imx95-pcie"; 1918 reg = <0 0x4c380000 0 0x10000>, 1919 <8 0x80100000 0 0xfe00000>, 1920 <0 0x4c3e0000 0 0x10000>, 1921 <0 0x4c3c0000 0 0x4000>; 1922 reg-names = "dbi", "config", "atu", "app"; 1923 ranges = <0x81000000 0 0x00000000 0x8 0x8ff00000 0 0x00100000>, 1924 <0x82000000 0 0x10000000 0xa 0x10000000 0 0x10000000>; 1925 #address-cells = <3>; 1926 #size-cells = <2>; 1927 device_type = "pci"; 1928 linux,pci-domain = <1>; 1929 bus-range = <0x00 0xff>; 1930 num-lanes = <1>; 1931 num-viewport = <8>; 1932 interrupts = <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>; 1933 interrupt-names = "msi"; 1934 #interrupt-cells = <1>; 1935 interrupt-map-mask = <0 0 0 0x7>; 1936 interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 1937 <0 0 0 2 &gic 0 0 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 1938 <0 0 0 3 &gic 0 0 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 1939 <0 0 0 4 &gic 0 0 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; 1940 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1941 <&scmi_clk IMX95_CLK_HSIOPLL>, 1942 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1943 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>, 1944 <&hsio_blk_ctl 0>; 1945 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux", "ref"; 1946 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1947 <&scmi_clk IMX95_CLK_HSIOPLL>, 1948 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1949 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1950 assigned-clock-parents = <0>, <0>, 1951 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1952 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1953 /* pcie1's Devid(BIT[7:6]) is 0x10, stream id(BIT[5:0]) is 0x18~0x1f */ 1954 msi-map = <0x0 &its 0x98 0x1>, 1955 <0x100 &its 0x99 0x7>; 1956 msi-map-mask = <0x1ff>; 1957 /* smmu have not Devid(BIT[7:6]) */ 1958 iommu-map = <0x000 &smmu 0x18 0x1>, 1959 <0x100 &smmu 0x19 0x7>; 1960 iommu-map-mask = <0x1ff>; 1961 fsl,max-link-speed = <3>; 1962 status = "disabled"; 1963 }; 1964 1965 pcie1_ep: pcie-ep@4c380000 { 1966 compatible = "fsl,imx95-pcie-ep"; 1967 reg = <0 0x4c380000 0 0x10000>, 1968 <0 0x4c3e0000 0 0x1000>, 1969 <0 0x4c3a0000 0 0x1000>, 1970 <0 0x4c3c0000 0 0x4000>, 1971 <0 0x4c3f0000 0 0x10000>, 1972 <0xa 0 1 0>; 1973 reg-names = "dbi", "atu", "dbi2", "app", "dma", "addr_space"; 1974 num-lanes = <1>; 1975 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 1976 interrupt-names = "dma"; 1977 clocks = <&scmi_clk IMX95_CLK_HSIO>, 1978 <&scmi_clk IMX95_CLK_HSIOPLL>, 1979 <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1980 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1981 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1982 assigned-clocks = <&scmi_clk IMX95_CLK_HSIOPLL_VCO>, 1983 <&scmi_clk IMX95_CLK_HSIOPLL>, 1984 <&scmi_clk IMX95_CLK_HSIOPCIEAUX>; 1985 assigned-clock-rates = <3600000000>, <100000000>, <10000000>; 1986 assigned-clock-parents = <0>, <0>, 1987 <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 1988 msi-map = <0x0 &its 0x98 0x1>; 1989 power-domains = <&scmi_devpd IMX95_PD_HSIO_TOP>; 1990 status = "disabled"; 1991 }; 1992 1993 vpu_blk_ctrl: clock-controller@4c410000 { 1994 compatible = "nxp,imx95-vpu-csr", "syscon"; 1995 reg = <0x0 0x4c410000 0x0 0x10000>; 1996 #clock-cells = <1>; 1997 clocks = <&scmi_clk IMX95_CLK_VPUAPB>; 1998 power-domains = <&scmi_devpd IMX95_PD_VPU>; 1999 assigned-clocks = <&scmi_clk IMX95_CLK_VPUAPB>, 2000 <&scmi_clk IMX95_CLK_VPU>, 2001 <&scmi_clk IMX95_CLK_VPUJPEG>; 2002 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>, 2003 <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, 2004 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; 2005 assigned-clock-rates = <133333333>, <667000000>, <500000000>; 2006 }; 2007 2008 jpegdec: jpegdec@4c500000 { 2009 compatible = "nxp,imx95-jpgdec", "nxp,imx8qxp-jpgdec"; 2010 reg = <0x0 0x4C500000 0x0 0x00050000>; 2011 interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 2012 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 2013 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 2014 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 2015 clocks = <&scmi_clk IMX95_CLK_VPU>, 2016 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 2017 assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_DEC>; 2018 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; 2019 power-domains = <&scmi_devpd IMX95_PD_VPU>; 2020 }; 2021 2022 jpegenc: jpegenc@4c550000 { 2023 compatible = "nxp,imx95-jpgenc", "nxp,imx8qxp-jpgenc"; 2024 reg = <0x0 0x4C550000 0x0 0x00050000>; 2025 interrupts = <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 2026 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 2027 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 2028 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>; 2029 clocks = <&scmi_clk IMX95_CLK_VPU>, 2030 <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 2031 assigned-clocks = <&vpu_blk_ctrl IMX95_CLK_VPUBLK_JPEG_ENC>; 2032 assigned-clock-parents = <&scmi_clk IMX95_CLK_VPUJPEG>; 2033 power-domains = <&scmi_devpd IMX95_PD_VPU>; 2034 }; 2035 2036 netcmix_blk_ctrl: syscon@4c810000 { 2037 compatible = "nxp,imx95-netcmix-blk-ctrl", "syscon"; 2038 reg = <0x0 0x4c810000 0x0 0x8>; 2039 #clock-cells = <1>; 2040 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 2041 assigned-clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>; 2042 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD1_DIV2>; 2043 assigned-clock-rates = <133333333>; 2044 power-domains = <&scmi_devpd IMX95_PD_NETC>; 2045 status = "disabled"; 2046 }; 2047 2048 sai2: sai@4c880000 { 2049 compatible = "fsl,imx95-sai"; 2050 reg = <0x0 0x4c880000 0x0 0x10000>; 2051 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 2052 clocks = <&scmi_clk IMX95_CLK_BUSNETCMIX>, <&dummy>, 2053 <&scmi_clk IMX95_CLK_SAI2>, <&dummy>, 2054 <&dummy>; 2055 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 2056 power-domains = <&scmi_devpd IMX95_PD_NETC>; 2057 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 2058 dma-names = "rx", "tx"; 2059 status = "disabled"; 2060 }; 2061 2062 netc_blk_ctrl: system-controller@4cde0000 { 2063 compatible = "nxp,imx95-netc-blk-ctrl"; 2064 reg = <0x0 0x4cde0000 0x0 0x10000>, 2065 <0x0 0x4cdf0000 0x0 0x10000>, 2066 <0x0 0x4c81000c 0x0 0x18>; 2067 reg-names = "ierb", "prb", "netcmix"; 2068 #address-cells = <2>; 2069 #size-cells = <2>; 2070 ranges; 2071 power-domains = <&scmi_devpd IMX95_PD_NETC>; 2072 assigned-clocks = <&scmi_clk IMX95_CLK_ENET>, 2073 <&scmi_clk IMX95_CLK_ENETREF>; 2074 assigned-clock-parents = <&scmi_clk IMX95_CLK_SYSPLL1_PFD2>, 2075 <&scmi_clk IMX95_CLK_SYSPLL1_PFD0>; 2076 assigned-clock-rates = <666666666>, <250000000>; 2077 clocks = <&scmi_clk IMX95_CLK_ENET>; 2078 clock-names = "ipg"; 2079 status = "disabled"; 2080 2081 netc_bus0: pcie@4ca00000 { 2082 compatible = "pci-host-ecam-generic"; 2083 reg = <0x0 0x4ca00000 0x0 0x100000>; 2084 #address-cells = <3>; 2085 #size-cells = <2>; 2086 device_type = "pci"; 2087 bus-range = <0x0 0x0>; 2088 msi-map = <0x0 &its 0x60 0x1>, //ENETC0 PF 2089 <0x10 &its 0x61 0x1>, //ENETC0 VF0 2090 <0x20 &its 0x62 0x1>, //ENETC0 VF1 2091 <0x40 &its 0x63 0x1>, //ENETC1 PF 2092 <0x80 &its 0x64 0x1>, //ENETC2 PF 2093 <0x90 &its 0x65 0x1>, //ENETC2 VF0 2094 <0xa0 &its 0x66 0x1>, //ENETC2 VF1 2095 <0xc0 &its 0x67 0x1>; //NETC Timer 2096 iommu-map = <0x0 &smmu 0x20 0x1>, 2097 <0x10 &smmu 0x21 0x1>, 2098 <0x20 &smmu 0x22 0x1>, 2099 <0x40 &smmu 0x23 0x1>, 2100 <0x80 &smmu 0x24 0x1>, 2101 <0x90 &smmu 0x25 0x1>, 2102 <0xa0 &smmu 0x26 0x1>, 2103 <0xc0 &smmu 0x27 0x1>; 2104 /* ENETC0~2 and Timer BAR0 - non-prefetchable memory */ 2105 ranges = <0x82000000 0x0 0x4cc00000 0x0 0x4cc00000 0x0 0xe0000 2106 /* Timer BAR2 - prefetchable memory */ 2107 0xc2000000 0x0 0x4cd00000 0x0 0x4cd00000 0x0 0x10000 2108 /* ENETC0~2: VF0-1 BAR0 - non-prefetchable memory */ 2109 0x82000000 0x0 0x4cd20000 0x0 0x4cd20000 0x0 0x60000 2110 /* ENETC0~2: VF0-1 BAR2 - prefetchable memory */ 2111 0xc2000000 0x0 0x4cd80000 0x0 0x4cd80000 0x0 0x60000>; 2112 2113 enetc_port0: ethernet@0,0 { 2114 compatible = "pci1131,e101"; 2115 reg = <0x000000 0 0 0 0>; 2116 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 2117 clock-names = "ref"; 2118 status = "disabled"; 2119 }; 2120 2121 enetc_port1: ethernet@8,0 { 2122 compatible = "pci1131,e101"; 2123 reg = <0x004000 0 0 0 0>; 2124 clocks = <&scmi_clk IMX95_CLK_ENETREF>; 2125 clock-names = "ref"; 2126 status = "disabled"; 2127 }; 2128 2129 enetc_port2: ethernet@10,0 { 2130 compatible = "pci1131,e101"; 2131 reg = <0x008000 0 0 0 0>; 2132 status = "disabled"; 2133 }; 2134 2135 netc_timer: ethernet@18,0 { 2136 compatible = "pci1131,ee02"; 2137 reg = <0x00c000 0 0 0 0>; 2138 status = "disabled"; 2139 }; 2140 }; 2141 2142 netc_bus1: pcie@4cb00000 { 2143 compatible = "pci-host-ecam-generic"; 2144 reg = <0x0 0x4cb00000 0x0 0x100000>; 2145 #address-cells = <3>; 2146 #size-cells = <2>; 2147 device_type = "pci"; 2148 bus-range = <0x1 0x1>; 2149 /* EMDIO BAR0 - non-prefetchable memory */ 2150 ranges = <0x82000000 0x0 0x4cce0000 0x0 0x4cce0000 0x0 0x20000 2151 /* EMDIO BAR2 - prefetchable memory */ 2152 0xc2000000 0x0 0x4cd10000 0x0 0x4cd10000 0x0 0x10000>; 2153 2154 netc_emdio: mdio@0,0 { 2155 compatible = "pci1131,ee00"; 2156 reg = <0x010000 0 0 0 0>; 2157 #address-cells = <1>; 2158 #size-cells = <0>; 2159 status = "disabled"; 2160 }; 2161 }; 2162 }; 2163 2164 gpu: gpu@4d900000 { 2165 compatible = "nxp,imx95-mali", "arm,mali-valhall-csf"; 2166 reg = <0 0x4d900000 0 0x480000>; 2167 clocks = <&scmi_clk IMX95_CLK_GPU_CGC>, <&scmi_clk IMX95_CLK_GPUAPB>; 2168 clock-names = "core", "coregroup"; 2169 interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 2170 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 2171 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 2172 interrupt-names = "job", "mmu", "gpu"; 2173 operating-points-v2 = <&gpu_opp_table>; 2174 power-domains = <&scmi_devpd IMX95_PD_GPU>; 2175 #cooling-cells = <2>; 2176 dynamic-power-coefficient = <1013>; 2177 }; 2178 2179 ddr-pmu@4e090dc0 { 2180 compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu"; 2181 reg = <0x0 0x4e090dc0 0x0 0x200>; 2182 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 2183 }; 2184 }; 2185};
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