imx95-toradex-smarc.dtsi

   1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2/*
   3 * Copyright (C) 2025 Toradex
   4 *
   5 * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95
   6 */
   7
   8#include <dt-bindings/input/input.h>
   9#include <dt-bindings/net/ti-dp83867.h>
  10#include "imx95.dtsi"
  11
  12/ {
  13	aliases {
  14		can0 = &flexcan1;
  15		can1 = &flexcan2;
  16		ethernet0 = &enetc_port0;
  17		ethernet1 = &enetc_port1;
  18		mmc0 = &usdhc1;
  19		mmc1 = &usdhc2;
  20		mmc2 = &usdhc3;
  21		rtc0 = &rtc_i2c;
  22		rtc1 = &scmi_bbm;
  23		serial0 = &lpuart2;
  24		serial1 = &lpuart1;
  25		serial3 = &lpuart3;
  26	};
  27
  28	chosen {
  29		stdout-path = "serial1:115200n8";
  30	};
  31
  32	clk_dsi2dp_bridge: clock-dsi2dp-bridge {
  33		compatible = "fixed-clock";
  34		#clock-cells = <0>;
  35		clock-frequency = <27000000>;
  36	};
  37
  38	clk_serdes_eth_ref: clock-eth-ref {
  39		compatible = "gpio-gate-clock";
  40		#clock-cells = <0>;
  41		/* CTRL_ETH_REF_CLK_STBY# */
  42		enable-gpios = <&som_gpio_expander_1 13 GPIO_ACTIVE_HIGH>;
  43	};
  44
  45	connector {
  46		compatible = "gpio-usb-b-connector", "usb-b-connector";
  47		/* SMARC P64 - USB0_OTG_ID */
  48		id-gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>;
  49		label = "USB0";
  50		self-powered;
  51		type = "micro";
  52		vbus-supply = <&reg_usb0_vbus>;
  53
  54		port {
  55			usb_dr_connector: endpoint {
  56				remote-endpoint = <&usb0_otg_id>;
  57			};
  58		};
  59	};
  60
  61	gpio-keys {
  62		compatible = "gpio-keys";
  63
  64		smarc_key_sleep: key-sleep {
  65			gpios = <&som_ec_gpio_expander 4 GPIO_ACTIVE_LOW>;
  66			label = "SMARC_SLEEP#";
  67			wakeup-source;
  68			linux,code = <KEY_SLEEP>;
  69		};
  70
  71		smarc_switch_lid: switch-lid {
  72			gpios = <&som_ec_gpio_expander 2 GPIO_ACTIVE_LOW>;
  73			label = "SMARC_LID#";
  74			linux,code = <SW_LID>;
  75			linux,input-type = <EV_SW>;
  76		};
  77	};
  78
  79	reg_module_1p8v: regulator-module-1p8v {
  80		compatible = "regulator-fixed";
  81		regulator-max-microvolt = <1800000>;
  82		regulator-min-microvolt = <1800000>;
  83		regulator-name = "On-module +V1.8";
  84	};
  85
  86	/* Non PMIC On-module Supplies */
  87	reg_module_dp_1p2v: regulator-module-dp-1p2v {
  88		compatible = "regulator-fixed";
  89		regulator-max-microvolt = <1200000>;
  90		regulator-min-microvolt = <1200000>;
  91		regulator-name = "On-module +V1.2_DP";
  92		vin-supply = <&reg_module_1p8v>;
  93	};
  94
  95	reg_usb0_vbus: regulator-usb0-vbus {
  96		compatible = "regulator-fixed";
  97		/* SMARC P62 - USB0_EN_OC# */
  98		gpios = <&som_gpio_expander_0 4 GPIO_ACTIVE_HIGH>;
  99		enable-active-high;
 100		regulator-name = "USB0_EN_OC#";
 101	};
 102
 103	reg_usb1_vbus: regulator-usb1-vbus {
 104		compatible = "regulator-fixed";
 105		/* CTRL_V_BUS_USB_HUB or SMARC P71 - USB2_EN_OC# */
 106		gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_HIGH>;
 107		enable-active-high;
 108		regulator-name = "CTRL_V_BUS_USB_HUB";
 109	};
 110
 111	reg_usdhc2_vmmc: regulator-vmmc-usdhc2 {
 112		compatible = "regulator-fixed";
 113		pinctrl-names = "default";
 114		pinctrl-0 = <&pinctrl_usdhc2_pwr_en>;
 115		gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>;
 116		enable-active-high;
 117		off-on-delay-us = <100000>;
 118		regulator-max-microvolt = <3300000>;
 119		regulator-min-microvolt = <3300000>;
 120		regulator-name = "SDIO_PWR_EN";
 121		startup-delay-us = <20000>;
 122	};
 123
 124	reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc {
 125		compatible = "regulator-gpio";
 126		pinctrl-names = "default";
 127		pinctrl-0 = <&pinctrl_usdhc2_vsel>;
 128		gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
 129		regulator-max-microvolt = <3300000>;
 130		regulator-min-microvolt = <1800000>;
 131		states = <1800000 0x1>,
 132			 <3300000 0x0>;
 133		regulator-name = "PMIC_SD2_VSEL";
 134	};
 135
 136	reg_wifi_en: regulator-wifi-en {
 137		compatible = "regulator-fixed";
 138		/* CTRL_EN_WIFI */
 139		gpios = <&som_gpio_expander_1 7 GPIO_ACTIVE_HIGH>;
 140		enable-active-high;
 141		regulator-max-microvolt = <3300000>;
 142		regulator-min-microvolt = <3300000>;
 143		regulator-name = "CTRL_EN_WIFI";
 144		startup-delay-us = <2000>;
 145	};
 146
 147	reserved-memory {
 148		#address-cells = <2>;
 149		#size-cells = <2>;
 150		ranges;
 151
 152		linux_cma: linux,cma {
 153			compatible = "shared-dma-pool";
 154			reusable;
 155			size = <0 0x3c000000>;
 156			alloc-ranges = <0 0x80000000 0 0x7F000000>;
 157			linux,cma-default;
 158		};
 159	};
 160};
 161
 162/* SMARC GBE0 */
 163&enetc_port0 {
 164	pinctrl-names = "default";
 165	pinctrl-0 = <&pinctrl_enetc0>, <&pinctrl_enetc0_1588_tmr>;
 166	phy-handle = <&ethphy1>;
 167	phy-mode = "rgmii-id";
 168};
 169
 170/* SMARC GBE1 */
 171&enetc_port1 {
 172	pinctrl-names = "default";
 173	pinctrl-0 = <&pinctrl_enetc1>, <&pinctrl_enetc1_1588_tmr>;
 174	phy-handle = <&ethphy2>;
 175	phy-mode = "rgmii-id";
 176};
 177
 178/* SMARC CAN0 */
 179&flexcan1 {
 180	pinctrl-names = "default";
 181	pinctrl-0 = <&pinctrl_flexcan1>;
 182};
 183
 184/* SMARC CAN1 */
 185&flexcan2 {
 186	pinctrl-names = "default";
 187	pinctrl-0 = <&pinctrl_flexcan2>;
 188};
 189
 190&gpio1 {
 191	gpio-line-names = "", /* 0 */
 192			  "",
 193			  "SMARC_I2C_GP_CK",
 194			  "SMARC_I2C_GP_DAT",
 195			  "",
 196			  "",
 197			  "",
 198			  "",
 199			  "",
 200			  "",
 201			  "", /* 10 */
 202			  "",
 203			  "",
 204			  "",
 205			  "CTRL_IO_EXP_INT_B";
 206	status = "okay";
 207};
 208
 209&gpio2 {
 210	gpio-line-names = "SMARC_SPI0_CS0#", /* 0 */
 211			  "",
 212			  "",
 213			  "",
 214			  "",
 215			  "",
 216			  "SMARC_GPIO5",
 217			  "",
 218			  "I2C_CAM_DAT",
 219			  "I2C_CAM_CK",
 220			  "SMARC_GPIO12", /* 10 */
 221			  "SMARC_GPIO13",
 222			  "",
 223			  "",
 224			  "",
 225			  "",
 226			  "",
 227			  "",
 228			  "SMARC_SPI1_CS0#",
 229			  "",
 230			  "", /* 20 */
 231			  "",
 232			  "SMARC_I2C_LCD_DAT",
 233			  "SMARC_I2C_LCD_CK",
 234			  "SMARC_SPI0_CS1#",
 235			  "",
 236			  "",
 237			  "",
 238			  "SMARC_I2C_PM_DAT",
 239			  "SMARC_I2C_PM_CK",
 240			  "I2C_SOM_DAT", /* 30 */
 241			  "I2C_SOM_CK";
 242	status = "okay";
 243};
 244
 245&gpio3 {
 246	gpio-line-names = "SMARC_SDIO_CD#", /* 0 */
 247			  "",
 248			  "",
 249			  "",
 250			  "",
 251			  "",
 252			  "",
 253			  "SMARC_SDIO_PWR_EN",
 254			  "",
 255			  "",
 256			  "", /* 10 */
 257			  "",
 258			  "",
 259			  "",
 260			  "",
 261			  "",
 262			  "",
 263			  "",
 264			  "",
 265			  "",
 266			  "PMIC_SD2_VSEL";
 267	status = "okay";
 268};
 269
 270&gpio4 {
 271	gpio-line-names = "", /* 0 */
 272			  "",
 273			  "",
 274			  "",
 275			  "",
 276			  "",
 277			  "",
 278			  "",
 279			  "",
 280			  "",
 281			  "", /* 10 */
 282			  "",
 283			  "",
 284			  "",
 285			  "SMARC_GPIO11",
 286			  "SMARC_GPIO10",
 287			  "",
 288			  "",
 289			  "",
 290			  "",
 291			  "", /* 20 */
 292			  "",
 293			  "",
 294			  "",
 295			  "",
 296			  "",
 297			  "",
 298			  "",
 299			  "SMARC_SMB_ALERT#";
 300	status = "okay";
 301};
 302
 303&gpio5 {
 304	gpio-line-names = "SMARC_GPIO2", /* 0 */
 305			  "SMARC_GPIO3",
 306			  "SMARC_GPIO4",
 307			  "SMARC_GPIO6",
 308			  "",
 309			  "",
 310			  "",
 311			  "",
 312			  "SMARC_GPIO9",
 313			  "SMARC_GPIO7",
 314			  "SMARC_GPIO8", /* 10 */
 315			  "SMARC_SPI1_CS1#",
 316			  "",
 317			  "SPI1_TPM_CS#";
 318	status = "okay";
 319};
 320
 321/* SMARC I2C_GP */
 322&lpi2c2 {
 323	pinctrl-names = "default", "gpio";
 324	pinctrl-0 = <&pinctrl_lpi2c2>;
 325	pinctrl-1 = <&pinctrl_lpi2c2_gpio>;
 326	#address-cells = <1>;
 327	#size-cells = <0>;
 328	clock-frequency = <400000>;
 329	scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 330	sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 331	status = "okay";
 332
 333	eeprom@50 {
 334		compatible = "st,24c32", "atmel,24c32";
 335		reg = <0x50>;
 336		pagesize = <32>;
 337	};
 338};
 339
 340/* SMARC I2C_PM */
 341&lpi2c3 {
 342	pinctrl-names = "default", "gpio";
 343	pinctrl-0 = <&pinctrl_lpi2c3>;
 344	pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
 345	#address-cells = <1>;
 346	#size-cells = <0>;
 347	clock-frequency = <400000>;
 348	scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 349	sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 350};
 351
 352/* I2C_SOM */
 353&lpi2c4 {
 354	pinctrl-names = "default", "gpio";
 355	pinctrl-0 = <&pinctrl_lpi2c4>, <&pinctrl_ctrl_io_exp_int_b>;
 356	pinctrl-1 = <&pinctrl_lpi2c4_gpio>, <&pinctrl_ctrl_io_exp_int_b>;
 357	#address-cells = <1>;
 358	#size-cells = <0>;
 359	clock-frequency = <400000>;
 360	scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 361	sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 362	status = "okay";
 363
 364	som_gpio_expander_0: gpio@20 {
 365		compatible = "nxp,pcal6408";
 366		reg = <0x20>;
 367		#interrupt-cells = <2>;
 368		interrupt-controller;
 369		interrupt-parent = <&gpio1>;
 370		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
 371		#gpio-cells = <2>;
 372		gpio-controller;
 373		gpio-line-names =
 374			"SMARC_PCIE_WAKE#", /* 0 */
 375			"SMARC_PCIE_B_RST#",
 376			"SMARC_PCIE_A_RST#",
 377			"SMARC_USB0_OTG_ID",
 378			"SMARC_USB0_EN", /* SMARC USB0_EN_OC# - Open Drain Output */
 379			"SMARC_USB0_OC#", /* SMARC USB0_EN_OC# - Over-Current Sense Input */
 380			"",
 381			"SMARC_PCIE_C_RST#";
 382	};
 383
 384	som_gpio_expander_1: gpio@21 {
 385		compatible = "nxp,pcal6416";
 386		reg = <0x21>;
 387		#interrupt-cells = <2>;
 388		interrupt-controller;
 389		interrupt-parent = <&gpio1>;
 390		interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
 391		#gpio-cells = <2>;
 392		gpio-controller;
 393		gpio-line-names =
 394			"SMARC_GPIO0", /* 0 */
 395			"SMARC_GPIO1",
 396			"SMARC_LCD0_VDD_EN",
 397			"SMARC_LCD0_BKLT_EN",
 398			"SMARC_LCD1_VDD_EN",
 399			"SMARC_LCD1_BKLT_EN",
 400			"",
 401			"",
 402			"",
 403			"",
 404			"", /* 10 */
 405			"",
 406			"",
 407			"",
 408			"",
 409			"SMARC_SDIO_WP";
 410	};
 411
 412	embedded-controller@28 {
 413		compatible = "toradex,smarc-imx95-ec", "toradex,smarc-ec";
 414		reg = <0x28>;
 415	};
 416
 417	som_ec_gpio_expander: gpio@29 {
 418		compatible = "toradex,ecgpiol16", "nxp,pcal6416";
 419		reg = <0x29>;
 420		pinctrl-names = "default";
 421		pinctrl-0 = <&pinctrl_ec_int>;
 422		#interrupt-cells = <2>;
 423		interrupt-controller;
 424		interrupt-parent = <&gpio1>;
 425		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
 426		#gpio-cells = <2>;
 427		gpio-controller;
 428		gpio-line-names =
 429			"SMARC_CHARGER_PRSNT#",
 430			"SMARC_CHARGING#",
 431			"SMARC_LID#",
 432			"SMARC_BATLOW#",
 433			"SMARC_SLEEP#";
 434	};
 435
 436	/* SMARC DP0 */
 437	som_dsi2dp_bridge: bridge@2c {
 438		compatible = "ti,sn65dsi86";
 439		reg = <0x2c>;
 440		clocks = <&clk_dsi2dp_bridge>;
 441		clock-names = "refclk";
 442		vcc-supply = <&reg_module_dp_1p2v>;
 443		vcca-supply = <&reg_module_dp_1p2v>;
 444		vccio-supply = <&reg_module_1p8v>;
 445		vpll-supply = <&reg_module_1p8v>;
 446		status = "disabled";
 447
 448		ports {
 449			#address-cells = <1>;
 450			#size-cells = <0>;
 451
 452			port@0 {
 453				reg = <0>;
 454
 455				sn65dsi86_in: endpoint {
 456				};
 457			};
 458
 459			port@1 {
 460				reg = <1>;
 461
 462				sn65dsi86_out: endpoint {
 463					data-lanes = <3 2 1 0>;
 464				};
 465			};
 466		};
 467	};
 468
 469	rtc_i2c: rtc@32 {
 470		compatible = "epson,rx8130";
 471		reg = <0x32>;
 472	};
 473
 474	temperature-sensor@48 {
 475		compatible = "ti,tmp1075";
 476		reg = <0x48>;
 477	};
 478
 479	eeprom@50 {
 480		compatible = "st,24c02", "atmel,24c02";
 481		reg = <0x50>;
 482		pagesize = <16>;
 483	};
 484};
 485
 486/* SMARC I2C_LCD */
 487&lpi2c5 {
 488	pinctrl-names = "default", "gpio";
 489	pinctrl-0 = <&pinctrl_lpi2c5>;
 490	pinctrl-1 = <&pinctrl_lpi2c5_gpio>;
 491	#address-cells = <1>;
 492	#size-cells = <0>;
 493	clock-frequency = <100000>;
 494	scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 495	sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 496};
 497
 498/* I2C_CAM */
 499&lpi2c7 {
 500	pinctrl-names = "default", "gpio";
 501	pinctrl-0 = <&pinctrl_lpi2c7>;
 502	pinctrl-1 = <&pinctrl_lpi2c7_gpio>;
 503	#address-cells = <1>;
 504	#size-cells = <0>;
 505	clock-frequency = <400000>;
 506	scl-gpios = <&gpio2 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 507	sda-gpios = <&gpio2 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 508	status = "okay";
 509
 510	i2c-mux@70 {
 511		compatible = "nxp,pca9543";
 512		reg = <0x70>;
 513		#address-cells = <1>;
 514		#size-cells = <0>;
 515
 516		/* SMARC I2C_CAM0 */
 517		i2c_cam0: i2c@0 {
 518			reg = <0>;
 519			#address-cells = <1>;
 520			#size-cells = <0>;
 521		};
 522
 523		/* SMARC I2C_CAM1 */
 524		i2c_cam1: i2c@1 {
 525			reg = <1>;
 526			#address-cells = <1>;
 527			#size-cells = <0>;
 528		};
 529	};
 530};
 531
 532/* SMARC SPI1 */
 533&lpspi4 {
 534	pinctrl-names = "default";
 535	pinctrl-0 = <&pinctrl_lpspi4>;
 536	cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>,
 537		   <&gpio5 11 GPIO_ACTIVE_LOW>,
 538		   <&gpio5 13 GPIO_ACTIVE_LOW>;
 539	status = "okay";
 540
 541	som_tpm: tpm@2 {
 542		compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
 543		reg = <0x2>;
 544		spi-max-frequency = <18500000>;
 545	};
 546};
 547
 548/* SMARC SPI0 */
 549&lpspi6 {
 550	pinctrl-names = "default";
 551	pinctrl-0 = <&pinctrl_lpspi6>;
 552	cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>,
 553		   <&gpio2 24 GPIO_ACTIVE_LOW>;
 554};
 555
 556/* SMARC SER1, used as the Linux Console */
 557&lpuart1 {
 558	pinctrl-names = "default";
 559	pinctrl-0 = <&pinctrl_uart1>;
 560};
 561
 562/* SMARC SER0 */
 563&lpuart2 {
 564	pinctrl-names = "default";
 565	pinctrl-0 = <&pinctrl_uart2>;
 566	uart-has-rtscts;
 567};
 568
 569/* SMARC SER3 */
 570&lpuart3 {
 571	pinctrl-names = "default";
 572	pinctrl-0 = <&pinctrl_uart3>;
 573};
 574
 575/* SMARC MDIO, shared between all ethernet ports */
 576&netc_emdio {
 577	pinctrl-names = "default";
 578	pinctrl-0 = <&pinctrl_emdio>;
 579
 580	ethphy1: ethernet-phy@1 {
 581		reg = <1>;
 582		interrupt-parent = <&som_gpio_expander_1>;
 583		interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
 584		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 585		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 586	};
 587
 588	ethphy2: ethernet-phy@2 {
 589		reg = <2>;
 590		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 591		ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
 592	};
 593};
 594
 595&netcmix_blk_ctrl {
 596	status = "okay";
 597};
 598
 599&netc_blk_ctrl {
 600	status = "okay";
 601};
 602
 603&netc_timer {
 604	status = "okay";
 605};
 606
 607/* SMARC PCIE_A */
 608&pcie0 {
 609	pinctrl-0 = <&pinctrl_pcie0>;
 610	pinctrl-names = "default";
 611	reset-gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_LOW>;
 612};
 613
 614/* SMARC PCIE_B */
 615&pcie1 {
 616	pinctrl-0 = <&pinctrl_pcie1>;
 617	pinctrl-names = "default";
 618	reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>;
 619};
 620
 621/* SMARC I2S0 */
 622&sai3 {
 623	#sound-dai-cells = <0>;
 624	assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>,
 625			  <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>,
 626			  <&scmi_clk IMX95_CLK_AUDIOPLL1>,
 627			  <&scmi_clk IMX95_CLK_AUDIOPLL2>,
 628			  <&scmi_clk IMX95_CLK_SAI3>;
 629	assigned-clock-parents = <0>, <0>, <0>, <0>,
 630				 <&scmi_clk IMX95_CLK_AUDIOPLL1>;
 631	assigned-clock-rates = <3932160000>,
 632			       <3612672000>, <393216000>,
 633			       <361267200>, <12288000>;
 634	fsl,sai-mclk-direction-output;
 635};
 636
 637&thermal_zones {
 638	/* PF09 Main PMIC */
 639	pf09-thermal {
 640		polling-delay = <2000>;
 641		polling-delay-passive = <250>;
 642		thermal-sensors = <&scmi_sensor 2>;
 643
 644		trips {
 645			trip0 {
 646				hysteresis = <2000>;
 647				temperature = <155000>;
 648				type = "critical";
 649			};
 650		};
 651	};
 652
 653	/* PF53 VDD_ARM PMIC */
 654	pf53-arm-thermal {
 655		polling-delay = <2000>;
 656		polling-delay-passive = <250>;
 657		thermal-sensors = <&scmi_sensor 4>;
 658
 659		trips {
 660			trip0 {
 661				hysteresis = <2000>;
 662				temperature = <155000>;
 663				type = "critical";
 664			};
 665		};
 666	};
 667
 668	/* PF53 VDD_SOC PMIC */
 669	pf53-soc-thermal {
 670		polling-delay = <2000>;
 671		polling-delay-passive = <250>;
 672		thermal-sensors = <&scmi_sensor 3>;
 673
 674		trips {
 675			trip0 {
 676				hysteresis = <2000>;
 677				temperature = <155000>;
 678				type = "critical";
 679			};
 680		};
 681	};
 682};
 683
 684/* SMARC LCD0_BKLT_PWM */
 685&tpm3 {
 686	pinctrl-names = "default";
 687	pinctrl-0 = <&pinctrl_lcd0_bklt_pwm>;
 688};
 689
 690/* SMARC LCD1_BKLT_PWM */
 691&tpm4 {
 692	pinctrl-names = "default";
 693	pinctrl-0 = <&pinctrl_lcd1_bklt_pwm>;
 694};
 695
 696/* SMARC GPIO5 as PWM */
 697&tpm5 {
 698	pinctrl-names = "default";
 699	pinctrl-0 = <&pinctrl_gpio5_pwm>;
 700};
 701
 702/* SMARC USB0 */
 703&usb2 {
 704	adp-disable;
 705	dr_mode = "otg";
 706	hnp-disable;
 707	srp-disable;
 708	usb-role-switch;
 709	vbus-supply = <&reg_usb0_vbus>;
 710
 711	port {
 712		usb0_otg_id: endpoint {
 713			remote-endpoint = <&usb_dr_connector>;
 714		};
 715	};
 716};
 717
 718&usb3 {
 719	fsl,disable-port-power-control;
 720};
 721
 722/* SMARC USB1..4  */
 723&usb3_dwc3 {
 724	dr_mode = "host";
 725};
 726
 727&usb3_phy {
 728	vbus-supply = <&reg_usb1_vbus>;
 729};
 730
 731/* On-module eMMC */
 732&usdhc1 {
 733	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 734	pinctrl-0 = <&pinctrl_usdhc1>;
 735	pinctrl-1 = <&pinctrl_usdhc1>;
 736	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
 737	bus-width = <8>;
 738	non-removable;
 739	no-sdio;
 740	no-sd;
 741	status = "okay";
 742};
 743
 744/* SMARC SDIO */
 745&usdhc2 {
 746	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
 747	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
 748	pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>;
 749	pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>;
 750	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>;
 751	cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 752	vmmc-supply = <&reg_usdhc2_vmmc>;
 753	vqmmc-supply = <&reg_usdhc2_vqmmc>;
 754	wp-gpios = <&som_gpio_expander_1 15 GPIO_ACTIVE_HIGH>;
 755};
 756
 757/* On-module Wi-Fi */
 758&usdhc3 {
 759	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 760	pinctrl-0 = <&pinctrl_usdhc3>;
 761	pinctrl-1 = <&pinctrl_usdhc3>;
 762	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
 763	keep-power-in-suspend;
 764	non-removable;
 765	vmmc-supply = <&reg_wifi_en>;
 766};
 767
 768&scmi_bbm {
 769	linux,code = <KEY_POWER>;
 770};
 771
 772&wdog3 {
 773	fsl,ext-reset-output;
 774	status = "okay";
 775};
 776
 777&scmi_iomuxc {
 778	/* SMARC CAM_MCK */
 779	pinctrl_cam_mck: cammckgrp {
 780		fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1	0x51e>; /* SMARC S6 - CAM_MCK */
 781	};
 782
 783	pinctrl_ec_int: ecintgrp {
 784		fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11	0x31e>; /* SAI1_TXFS - EC_MCU_INT# */
 785	};
 786
 787	/* SMARC MDIO, shared between all ethernet ports */
 788	pinctrl_emdio: emdiogrp {
 789		fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC		0x50e>, /* SMARC S45 - MDIO_CLK */
 790			   <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO		0x90e>; /* SMARC S46 - MDIO_DAT */
 791	};
 792
 793	/* SMARC GBE0 */
 794	pinctrl_enetc0: enetc0grp {
 795		fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL	0x57e>, /* ENET1_TX_CTL */
 796			   <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK		0x58e>, /* ENET1_TXC    */
 797			   <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0		0x50e>, /* ENET1_TDO    */
 798			   <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1		0x50e>, /* ENET1_TD1    */
 799			   <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2		0x50e>, /* ENET1_TD2    */
 800			   <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3		0x50e>, /* ENET1_TD3    */
 801			   <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL	0x57e>, /* ENET1_RX_CTL */
 802			   <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK		0x58e>, /* ENET1_RXC    */
 803			   <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0		0x57e>, /* ENET1_RD0    */
 804			   <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1		0x57e>, /* ENET1_RD1    */
 805			   <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2		0x57e>, /* ENET1_RD2    */
 806			   <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3		0x57e>; /* ENET1_RD3    */
 807	};
 808
 809	/* SMARC GBE0_SDP */
 810	pinctrl_enetc0_1588_tmr: enetc01588tmrgrp {
 811		fsl,pins = <IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1	0x51e>; /* SMARC P6 - GBE0_SDP */
 812	};
 813
 814	/* SMARC GBE1 */
 815	pinctrl_enetc1: enetc1grp {
 816		fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL	0x57e>, /* ENET2_TX_CTL */
 817			   <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK		0x58e>, /* ENET2_TXC    */
 818			   <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0		0x50e>, /* ENET2_TD0    */
 819			   <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1		0x50e>, /* ENET2_TD1    */
 820			   <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2		0x50e>, /* ENET2_TD2    */
 821			   <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3		0x50e>, /* ENET2_TD3    */
 822			   <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL	0x57e>, /* ENET2_RX_CTL */
 823			   <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK		0x58e>, /* ENET2_RXC    */
 824			   <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0		0x57e>, /* ENET2_RD0    */
 825			   <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1		0x57e>, /* ENET2_RD1    */
 826			   <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2		0x57e>, /* ENET2_RD2    */
 827			   <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3		0x57e>; /* ENET2_RD3    */
 828	};
 829
 830	/* SMARC GBE1_SDP */
 831	pinctrl_enetc1_1588_tmr: enetc11588tmrgrp {
 832		fsl,pins = <IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2	0x51e>; /* SMARC P5 - GBE1_SDP */
 833	};
 834
 835	/* SMARC CAN0 */
 836	pinctrl_flexcan1: flexcan1grp {
 837		fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX		0x39e>, /* SMARC P143 - CAN0_TX */
 838			   <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX	0x39e>; /* SMARC P144 - CAN0_RX */
 839	};
 840
 841	/* SMARC CAN1 */
 842	pinctrl_flexcan2: flexcan2grp {
 843		fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX	0x39e>, /* SMARC P145 - CAN1_TX */
 844			   <IMX95_PAD_GPIO_IO27__CAN2_RX	0x39e>; /* SMARC P146 - CAN1_RX */
 845	};
 846
 847	/* SMARC GPIO2 */
 848	pinctrl_gpio2: gpio2grp {
 849		fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0	0x31e>; /* SMARC P110 - GPIO2 */
 850	};
 851
 852	/* SMARC GPIO3 */
 853	pinctrl_gpio3: gpio3grp {
 854		fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1	0x31e>; /* SMARC P111 - GPIO3 */
 855	};
 856
 857	/* SMARC GPIO4 */
 858	pinctrl_gpio4: gpio4grp {
 859		fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2	0x31e>; /* SMARC P112 - GPIO4 */
 860	};
 861
 862	/* SMARC GPIO5 */
 863	pinctrl_gpio5: gpio5grp {
 864		fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6	0x31e>; /* SMARC P113 - GPIO5 */
 865	};
 866
 867	/* SMARC GPIO5 as PWM */
 868	pinctrl_gpio5_pwm: gpio5pwmgrp {
 869		fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0	0x11e>; /* SMARC P113 - PWM_OUT */
 870	};
 871
 872	/* SMARC GPIO6 */
 873	pinctrl_gpio6: gpio6grp {
 874		fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3	0x31e>; /* SMARC P114 - GPIO6 */
 875	};
 876
 877	/* SMARC GPIO7 */
 878	pinctrl_gpio7: gpio7grp {
 879		fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e>; /* SMARC P115 - GPIO7 */
 880	};
 881
 882	/* SMARC GPIO8 */
 883	pinctrl_gpio8: gpio8grp {
 884		fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10	0x31e>; /* SMARC P116 - GPIO8 */
 885	};
 886
 887	/* SMARC GPIO9 */
 888	pinctrl_gpio9: gpio9grp {
 889		fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8	0x31e>; /* SMARC P117 - GPIO9 */
 890	};
 891
 892	/* SMARC GPIO10 */
 893	pinctrl_gpio10: gpio10grp {
 894		fsl,pins = <IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15	0x31e>; /* SMARC P118 - GPIO10 */
 895	};
 896
 897	/* SMARC GPIO11 */
 898	pinctrl_gpio11: gpio11grp {
 899		fsl,pins = <IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14	0x31e>; /* SMARC P119 - GPIO11 */
 900	};
 901
 902	/* SMARC GPIO12 */
 903	pinctrl_gpio12: gpio12grp {
 904		fsl,pins = <IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10	0x31e>; /* SMARC S142 - GPIO12 */
 905	};
 906
 907	/* SMARC GPIO13 */
 908	pinctrl_gpio13: gpio13grp {
 909		fsl,pins = <IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11	0x31e>; /* SMARC S123 - GPIO13 */
 910	};
 911
 912	pinctrl_ctrl_io_exp_int_b: ioexpintgrp {
 913		fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* CTRL_IO_EXP_INT_B */
 914	};
 915
 916	/* SMARC LCD0_BKLT_PWM */
 917	pinctrl_lcd0_bklt_pwm: lcd0bkltpwmgrp {
 918		fsl,pins = <IMX95_PAD_GPIO_IO12__TPM3_CH2	0x51e>; /* SMARC S141 - LCD0_BKLT_PWM */
 919	};
 920
 921	/* SMARC LCD1_BKLT_PWM */
 922	pinctrl_lcd1_bklt_pwm: lcd1bkltpwmgrp {
 923		fsl,pins = <IMX95_PAD_GPIO_IO13__TPM4_CH2	0x51e>; /* SMARC S122 - LCD1_BKLT_PWM */
 924	};
 925
 926	/* SMARC I2C_GP */
 927	pinctrl_lpi2c2: lpi2c2grp {
 928		fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL	0x40001b9e>, /* SMARC S48 - I2C_GP_CK  */
 929			   <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA	0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */
 930	};
 931
 932	/* SMARC I2C_GP as GPIOs */
 933	pinctrl_lpi2c2_gpio: lpi2c2gpiogrp {
 934		fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2	0x40001b9e>, /* SMARC S48 - I2C_GP_CK  */
 935			   <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3	0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */
 936	};
 937
 938	/* SMARC I2C_PM */
 939	pinctrl_lpi2c3: lpi2c3grp {
 940		fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA	0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */
 941			   <IMX95_PAD_GPIO_IO29__LPI2C3_SCL	0x40001b9e>; /* SMARC P121 - I2C_PM_CK  */
 942	};
 943
 944	/* SMARC I2C_PM as GPIOs */
 945	pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
 946		fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28	0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */
 947			   <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29	0x40001b9e>; /* SMARC P121 - I2C_PM_CK  */
 948	};
 949
 950	/* I2C_SOM */
 951	pinctrl_lpi2c4: lpi2c4grp {
 952		fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL	0x40001b9e>, /* I2C_SOM_CK  */
 953			   <IMX95_PAD_GPIO_IO30__LPI2C4_SDA	0x40001b9e>; /* I2C_SOM_DAT */
 954	};
 955
 956	/* I2C_SOM as GPIOs */
 957	pinctrl_lpi2c4_gpio: lpi2c4gpiogrp {
 958		fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31	0x40001b9e>, /* I2C_SOM_CK  */
 959			   <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30	0x40001b9e>; /* I2C_SOM_DAT */
 960	};
 961
 962	/* SMARC I2C_LCD */
 963	pinctrl_lpi2c5: lpi2c5grp {
 964		fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA	0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */
 965			   <IMX95_PAD_GPIO_IO23__LPI2C5_SCL	0x40001b9e>; /* SMARC S139 - I2C_LCD_CK  */
 966	};
 967
 968	/* SMARC I2C_LCD as GPIOs */
 969	pinctrl_lpi2c5_gpio: lpi2c5gpiogrp {
 970		fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22	0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */
 971			   <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23	0x40001b9e>; /* SMARC S139 - I2C_LCD_CK  */
 972	};
 973
 974	/* I2C_CAM */
 975	pinctrl_lpi2c7: lpi2c7grp {
 976		fsl,pins = <IMX95_PAD_GPIO_IO08__LPI2C7_SDA	0x40001b9e>, /* I2C_CAM_DAT */
 977			   <IMX95_PAD_GPIO_IO09__LPI2C7_SCL	0x40001b9e>; /* I2C_CAM_CK  */
 978	};
 979
 980	/* I2C_CAM as GPIOs */
 981	pinctrl_lpi2c7_gpio: lpi2c7gpiogrp {
 982		fsl,pins = <IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8	0x40001b9e>, /* I2C_CAM_DAT */
 983			   <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9	0x40001b9e>; /* I2C_CAM_CK  */
 984	};
 985
 986	/* SMARC SPI1 */
 987	pinctrl_lpspi4: lpspi4grp {
 988		fsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK		0x3fe>, /* SMARC P56 - SPI1_CK   */
 989			   <IMX95_PAD_GPIO_IO36__LPSPI4_SOUT		0x3fe>, /* SMARC P58 - SPI1_DO   */
 990			   <IMX95_PAD_GPIO_IO19__LPSPI4_SIN		0x3fe>, /* SMARC P57 - SPI1_DIN  */
 991			   <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13		0x3fe>, /* SPI1_TPM_CS#          */
 992			   <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18		0x3fe>, /* SMARC P54 - SPI1_CS0# */
 993			   <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11	0x3fe>; /* SMARC P55 - SPI1_CS1# */
 994	};
 995
 996	/* SMARC SPI0 */
 997	pinctrl_lpspi6: lpspi6grp {
 998		fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0		0x3fe>, /* SMARC P43 - SPI0_CS0# */
 999			   <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24		0x3fe>, /* SMARC P31 - SPI0_CS1# */
1000			   <IMX95_PAD_GPIO_IO01__LPSPI6_SIN		0x3fe>, /* SMARC P45 - SPI0_DIN  */
1001			   <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT		0x3fe>, /* SMARC P46 - SPI0_DO   */
1002			   <IMX95_PAD_GPIO_IO03__LPSPI6_SCK		0x3fe>; /* SMARC P44 - SPI0_CK   */
1003	};
1004
1005	/* SMARC PCIE_A */
1006	pinctrl_pcie0: pcie0grp {
1007		fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B	0x40001b1e>; /* SMARC P78 - PCIE_A_CKREQ# */
1008	};
1009
1010	/* SMARC PCIE_B */
1011	pinctrl_pcie1: pcie1grp {
1012		fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B	0x40001b1e>; /* SMARC P77 - PCIE_B_CKREQ# */
1013	};
1014
1015	/* SMARC I2S0 */
1016	pinctrl_sai3: sai3grp {
1017		fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK		0x11e>, /* SMARC S38 - I2S0_CK */
1018			   <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0	0x11e>, /* SMARC S41 - I2S0_SDIN */
1019			   <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0	0x11e>, /* SMARC S40 - I2S0_SDOUT */
1020			   <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC		0x11e>; /* SMARC S39 - I2S0_LRCK */
1021	};
1022
1023	/* SMARC AUDIO_MCK */
1024	pinctrl_sai3_mclk: sai3mclkgrp {
1025		fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK	0x31e>; /* SMARC S42 - AUDIO_MCK */
1026	};
1027
1028	/* SMARC I2S2 */
1029	pinctrl_sai5: sai5grp {
1030		fsl,pins = <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK		0x11e>, /* SMARC S53 - I2S2_CK */
1031			   <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0	0x11e>, /* SMARC S51 - I2S2_SDOUT */
1032			   <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0	0x11e>, /* SMARC S52 - I2S2_SDIN */
1033			   <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC		0x11e>; /* SMARC S50 - I2S2_LRCK */
1034	};
1035
1036	/* SMARC SMB_ALERT# */
1037	pinctrl_smb_alert_gpio: smbalertgrp {
1038		fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28	0x31e>; /* SMARC P1 - SMB_ALERT# */
1039	};
1040
1041	/* SMARC SER1, used as the Linux Console */
1042	pinctrl_uart1: uart1grp {
1043		fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX	0x31e>, /* SMARC P134 - SER1_TX */
1044			   <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX	0x31e>; /* SMARC P135 - SER1_RX */
1045	};
1046
1047	/* SMARC SER0 */
1048	pinctrl_uart2: uart2grp {
1049		fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B	0x31e>, /* SMARC P132 - SER0_CTS# */
1050			   <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B	0x31e>, /* SMARC P131 - SER0_RTS# */
1051			   <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX		0x31e>, /* SMARC P130 - SER0_RX   */
1052			   <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX		0x31e>; /* SMARC P129 - SER0_TX   */
1053	};
1054
1055	/* SMARC SER3 */
1056	pinctrl_uart3: uart3grp {
1057		fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX	0x31e>, /* SMARC P140 - SER3_TX */
1058			   <IMX95_PAD_GPIO_IO15__LPUART3_RX	0x31e>; /* SMARC P141 - SER3_RX */
1059	};
1060
1061	/* On-module eMMC */
1062	pinctrl_usdhc1: usdhc1grp {
1063		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x158e>, /* SD1_CLK    */
1064			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x138e>, /* SD1_CMD    */
1065			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x138e>, /* SD1_DATA0  */
1066			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x138e>, /* SD1_DATA1  */
1067			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x138e>, /* SD1_DATA2  */
1068			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x138e>, /* SD1_DATA3  */
1069			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x138e>, /* SD1_DATA4  */
1070			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x138e>, /* SD1_DATA5  */
1071			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x138e>, /* SD1_DATA6  */
1072			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x138e>, /* SD1_DATA7  */
1073			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x158e>; /* SD1_STROBE */
1074	};
1075
1076	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
1077		fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK	0x15fe>, /* SD1_CLK    */
1078			   <IMX95_PAD_SD1_CMD__USDHC1_CMD	0x13fe>, /* SD1_CMD    */
1079			   <IMX95_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe>, /* SD1_DATA0  */
1080			   <IMX95_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe>, /* SD1_DATA1  */
1081			   <IMX95_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe>, /* SD1_DATA2  */
1082			   <IMX95_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe>, /* SD1_DATA3  */
1083			   <IMX95_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe>, /* SD1_DATA4  */
1084			   <IMX95_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe>, /* SD1_DATA5  */
1085			   <IMX95_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe>, /* SD1_DATA6  */
1086			   <IMX95_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe>, /* SD1_DATA7  */
1087			   <IMX95_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe>; /* SD1_STROBE */
1088	};
1089
1090	/* SMARC SDIO */
1091	pinctrl_usdhc2: usdhc2grp {
1092		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK		0x158e>, /* SMARC P36 - SDIO_CK  */
1093			   <IMX95_PAD_SD2_CMD__USDHC2_CMD		0x138e>, /* SMARC P34 - SDIO_CMD */
1094			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x138e>, /* SMARC P39 - SDIO_D0  */
1095			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x138e>, /* SMARC P40 - SDIO_D1  */
1096			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x138e>, /* SMARC P41 - SDIO_D2  */
1097			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x138e>; /* SMARC P42 - SDIO_D3  */
1098	};
1099
1100	/* SMARC SDIO */
1101	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
1102		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK		0x15fe>, /* SMARC P36 - SDIO_CK  */
1103			   <IMX95_PAD_SD2_CMD__USDHC2_CMD		0x13fe>, /* SMARC P34 - SDIO_CMD */
1104			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x13fe>, /* SMARC P39 - SDIO_D0  */
1105			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x13fe>, /* SMARC P40 - SDIO_D1  */
1106			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x13fe>, /* SMARC P41 - SDIO_D2  */
1107			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x13fe>; /* SMARC P42 - SDIO_D3  */
1108	};
1109
1110	/* SMARC SDIO */
1111	pinctrl_usdhc2_sleep: usdhc2-sleepgrp {
1112		fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK		0x400>, /* SMARC P36 - SDIO_CK  */
1113			   <IMX95_PAD_SD2_CMD__USDHC2_CMD		0x400>, /* SMARC P34 - SDIO_CMD */
1114			   <IMX95_PAD_SD2_DATA0__USDHC2_DATA0		0x400>, /* SMARC P39 - SDIO_D0  */
1115			   <IMX95_PAD_SD2_DATA1__USDHC2_DATA1		0x400>, /* SMARC P40 - SDIO_D1  */
1116			   <IMX95_PAD_SD2_DATA2__USDHC2_DATA2		0x400>, /* SMARC P41 - SDIO_D2  */
1117			   <IMX95_PAD_SD2_DATA3__USDHC2_DATA3		0x400>; /* SMARC P42 - SDIO_D3  */
1118	};
1119
1120	/* SMARC SDIO_CD# */
1121	pinctrl_usdhc2_cd: usdhc2-cdgrp {
1122		fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0	0x1100>; /* SMARC P35 - SDIO_CD# */
1123	};
1124
1125	/* SMARC SDIO_PWR_EN */
1126	pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp {
1127		fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7	0x11e>; /* SMARC P37 - SDIO_PWR_EN */
1128	};
1129
1130	pinctrl_usdhc2_vsel: usdhc2-vselgrp {
1131		fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19	0x4>; /* PMIC_SD2_VSEL */
1132	};
1133
1134	/* On-module Wi-Fi */
1135	pinctrl_usdhc3: usdhc3grp {
1136		fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK	0x158e>, /* SD3_CLK   */
1137			   <IMX95_PAD_SD3_CMD__USDHC3_CMD	0x138e>, /* SD3_CMD   */
1138			   <IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x138e>, /* SD3_DATA0 */
1139			   <IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x138e>, /* SD3_DATA1 */
1140			   <IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x138e>, /* SD3_DATA2 */
1141			   <IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x138e>; /* SD3_DATA3 */
1142	};
1143
1144	/* On-module Wi-Fi */
1145	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
1146		fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK	0x15fe>, /* SD3_CLK   */
1147			   <IMX95_PAD_SD3_CMD__USDHC3_CMD	0x13fe>, /* SD3_CMD   */
1148			   <IMX95_PAD_SD3_DATA0__USDHC3_DATA0	0x13fe>, /* SD3_DATA1 */
1149			   <IMX95_PAD_SD3_DATA1__USDHC3_DATA1	0x13fe>, /* SD3_DATA2 */
1150			   <IMX95_PAD_SD3_DATA2__USDHC3_DATA2	0x13fe>, /* SD3_DATA3 */
1151			   <IMX95_PAD_SD3_DATA3__USDHC3_DATA3	0x13fe>; /* SD3_DATA4 */
1152	};
1153};