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imx94.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/imx94.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2024-2025 NXP 4 */ 5 6#include <dt-bindings/dma/fsl-edma.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11#include "imx94-clock.h" 12#include "imx94-pinfunc.h" 13#include "imx94-power.h" 14 15/ { 16 #address-cells = <2>; 17 #size-cells = <2>; 18 interrupt-parent = <&gic>; 19 20 osc_24m: clock-24m { 21 compatible = "fixed-clock"; 22 #clock-cells = <0>; 23 clock-frequency = <24000000>; 24 clock-output-names = "osc_24m"; 25 }; 26 27 dummy: clock-dummy { 28 compatible = "fixed-clock"; 29 #clock-cells = <0>; 30 clock-frequency = <0>; 31 clock-output-names = "dummy"; 32 }; 33 34 clk_ext1: clock-ext1 { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <133000000>; 38 clock-output-names = "clk_ext1"; 39 }; 40 41 sai1_mclk: clock-sai1-mclk1 { 42 compatible = "fixed-clock"; 43 #clock-cells = <0>; 44 clock-frequency = <0>; 45 clock-output-names = "sai1_mclk"; 46 }; 47 48 sai2_mclk: clock-sai2-mclk1 { 49 compatible = "fixed-clock"; 50 #clock-cells = <0>; 51 clock-frequency = <0>; 52 clock-output-names = "sai2_mclk"; 53 }; 54 55 sai3_mclk: clock-sai3-mclk1 { 56 compatible = "fixed-clock"; 57 #clock-cells = <0>; 58 clock-frequency = <0>; 59 clock-output-names = "sai3_mclk"; 60 }; 61 62 sai4_mclk: clock-sai4-mclk1 { 63 compatible = "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 clock-output-names = "sai4_mclk"; 67 }; 68 69 firmware { 70 scmi { 71 compatible = "arm,scmi"; 72 #address-cells = <1>; 73 #size-cells = <0>; 74 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 75 shmem = <&scmi_buf0>, <&scmi_buf1>; 76 arm,max-rx-timeout-ms = <5000>; 77 78 scmi_devpd: protocol@11 { 79 reg = <0x11>; 80 #power-domain-cells = <1>; 81 }; 82 83 scmi_sys_power: protocol@12 { 84 reg = <0x12>; 85 }; 86 87 scmi_perf: protocol@13 { 88 reg = <0x13>; 89 #power-domain-cells = <1>; 90 }; 91 92 scmi_clk: protocol@14 { 93 reg = <0x14>; 94 #clock-cells = <1>; 95 }; 96 97 scmi_iomuxc: protocol@19 { 98 reg = <0x19>; 99 }; 100 101 scmi_bbm: protocol@81 { 102 reg = <0x81>; 103 }; 104 105 scmi_misc: protocol@84 { 106 reg = <0x84>; 107 }; 108 }; 109 }; 110 111 mqs1: mqs1 { 112 compatible = "fsl,imx943-aonmix-mqs"; 113 status = "disabled"; 114 }; 115 116 mqs2: mqs2 { 117 compatible = "fsl,imx943-wakeupmix-mqs"; 118 status = "disabled"; 119 }; 120 121 pmu { 122 compatible = "arm,cortex-a55-pmu"; 123 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; 124 }; 125 126 psci { 127 compatible = "arm,psci-1.0"; 128 method = "smc"; 129 }; 130 131 timer { 132 compatible = "arm,armv8-timer"; 133 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 134 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 135 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 136 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 137 clock-frequency = <24000000>; 138 interrupt-parent = <&gic>; 139 arm,no-tick-in-suspend; 140 }; 141 142 gic: interrupt-controller@48000000 { 143 compatible = "arm,gic-v3"; 144 reg = <0 0x48000000 0 0x10000>, 145 <0 0x48060000 0 0xc0000>; 146 ranges; 147 #interrupt-cells = <3>; 148 interrupt-controller; 149 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 150 #address-cells = <2>; 151 #size-cells = <2>; 152 dma-noncoherent; 153 interrupt-parent = <&gic>; 154 155 its: msi-controller@48040000 { 156 compatible = "arm,gic-v3-its"; 157 reg = <0 0x48040000 0 0x20000>; 158 #msi-cells = <1>; 159 dma-noncoherent; 160 msi-controller; 161 }; 162 }; 163 164 soc { 165 compatible = "simple-bus"; 166 ranges; 167 #address-cells = <2>; 168 #size-cells = <2>; 169 170 aips2: bus@42000000 { 171 compatible = "fsl,aips-bus", "simple-bus"; 172 reg = <0x0 0x42000000 0x0 0x800000>; 173 ranges = <0x42000000 0x0 0x42000000 0x8000000>; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 177 edma2: dma-controller@42000000 { 178 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; 179 reg = <0x42000000 0x210000>; 180 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 181 clock-names = "dma"; 182 #dma-cells = <3>; 183 dma-channels = <64>; 184 interrupts-extended = <&a55_irqsteer 0>, <&a55_irqsteer 1>, 185 <&a55_irqsteer 2>, <&a55_irqsteer 3>, 186 <&a55_irqsteer 4>, <&a55_irqsteer 5>, 187 <&a55_irqsteer 6>, <&a55_irqsteer 7>, 188 <&a55_irqsteer 8>, <&a55_irqsteer 9>, 189 <&a55_irqsteer 10>, <&a55_irqsteer 11>, 190 <&a55_irqsteer 12>, <&a55_irqsteer 13>, 191 <&a55_irqsteer 14>, <&a55_irqsteer 15>, 192 <&a55_irqsteer 16>, <&a55_irqsteer 17>, 193 <&a55_irqsteer 18>, <&a55_irqsteer 19>, 194 <&a55_irqsteer 20>, <&a55_irqsteer 21>, 195 <&a55_irqsteer 22>, <&a55_irqsteer 23>, 196 <&a55_irqsteer 24>, <&a55_irqsteer 25>, 197 <&a55_irqsteer 26>, <&a55_irqsteer 27>, 198 <&a55_irqsteer 28>, <&a55_irqsteer 29>, 199 <&a55_irqsteer 30>, <&a55_irqsteer 31>, 200 <&a55_irqsteer 64>, <&a55_irqsteer 65>, 201 <&a55_irqsteer 66>, <&a55_irqsteer 67>, 202 <&a55_irqsteer 68>, <&a55_irqsteer 69>, 203 <&a55_irqsteer 70>, <&a55_irqsteer 71>, 204 <&a55_irqsteer 72>, <&a55_irqsteer 73>, 205 <&a55_irqsteer 74>, <&a55_irqsteer 75>, 206 <&a55_irqsteer 76>, <&a55_irqsteer 77>, 207 <&a55_irqsteer 78>, <&a55_irqsteer 79>, 208 <&a55_irqsteer 80>, <&a55_irqsteer 81>, 209 <&a55_irqsteer 82>, <&a55_irqsteer 83>, 210 <&a55_irqsteer 84>, <&a55_irqsteer 85>, 211 <&a55_irqsteer 86>, <&a55_irqsteer 87>, 212 <&a55_irqsteer 88>, <&a55_irqsteer 89>, 213 <&a55_irqsteer 90>, <&a55_irqsteer 91>, 214 <&a55_irqsteer 92>, <&a55_irqsteer 93>, 215 <&a55_irqsteer 94>, <&a55_irqsteer 95>, 216 <&gic GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 217 }; 218 219 mu10: mailbox@42430000 { 220 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 221 reg = <0x42430000 0x10000>; 222 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>; 223 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 224 #mbox-cells = <2>; 225 status = "disabled"; 226 }; 227 228 i3c2: i3c@42520000 { 229 compatible = "silvaco,i3c-master-v1"; 230 reg = <0x42520000 0x10000>; 231 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 232 #address-cells = <3>; 233 #size-cells = <0>; 234 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 235 <&scmi_clk IMX94_CLK_I3C2SLOW>, 236 <&dummy>; 237 clock-names = "pclk", "fast_clk", "slow_clk"; 238 status = "disabled"; 239 }; 240 241 lpi2c3: i2c@42530000 { 242 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 243 reg = <0x42530000 0x10000>; 244 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 245 #address-cells = <1>; 246 #size-cells = <0>; 247 clocks = <&scmi_clk IMX94_CLK_LPI2C3>, 248 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 249 clock-names = "per", "ipg"; 250 dmas = <&edma2 5 0 0>, <&edma2 6 0 FSL_EDMA_RX>; 251 dma-names = "tx", "rx"; 252 status = "disabled"; 253 }; 254 255 lpi2c4: i2c@42540000 { 256 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 257 reg = <0x42540000 0x10000>; 258 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 259 #address-cells = <1>; 260 #size-cells = <0>; 261 clocks = <&scmi_clk IMX94_CLK_LPI2C4>, 262 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 263 clock-names = "per", "ipg"; 264 dmas = <&edma4 4 0 0>, <&edma4 5 0 FSL_EDMA_RX>; 265 dma-names = "tx", "rx"; 266 status = "disabled"; 267 }; 268 269 lpspi3: spi@42550000 { 270 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 271 reg = <0x42550000 0x10000>; 272 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 273 #address-cells = <1>; 274 #size-cells = <0>; 275 clocks = <&scmi_clk IMX94_CLK_LPSPI3>, 276 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 277 clock-names = "per", "ipg"; 278 dmas = <&edma2 7 0 0>, <&edma2 8 0 FSL_EDMA_RX>; 279 dma-names = "tx", "rx"; 280 status = "disabled"; 281 }; 282 283 lpspi4: spi@42560000 { 284 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 285 reg = <0x42560000 0x10000>; 286 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 287 #address-cells = <1>; 288 #size-cells = <0>; 289 clocks = <&scmi_clk IMX94_CLK_LPSPI4>, 290 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 291 clock-names = "per", "ipg"; 292 dmas = <&edma4 6 0 0>, <&edma4 7 0 FSL_EDMA_RX>; 293 dma-names = "tx", "rx"; 294 status = "disabled"; 295 }; 296 297 lpuart3: serial@42570000 { 298 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 299 "fsl,imx7ulp-lpuart"; 300 reg = <0x42570000 0x1000>; 301 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&scmi_clk IMX94_CLK_LPUART3>; 303 clock-names = "ipg"; 304 dmas = <&edma2 10 0 FSL_EDMA_RX>, <&edma2 9 0 0>; 305 dma-names = "rx", "tx"; 306 status = "disabled"; 307 }; 308 309 lpuart4: serial@42580000 { 310 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 311 "fsl,imx7ulp-lpuart"; 312 reg = <0x42580000 0x1000>; 313 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&scmi_clk IMX94_CLK_LPUART4>; 315 clock-names = "ipg"; 316 dmas = <&edma4 10 0 FSL_EDMA_RX>, <&edma4 9 0 0>; 317 dma-names = "rx", "tx"; 318 status = "disabled"; 319 }; 320 321 lpuart5: serial@42590000 { 322 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 323 "fsl,imx7ulp-lpuart"; 324 reg = <0x42590000 0x1000>; 325 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 326 clocks = <&scmi_clk IMX94_CLK_LPUART5>; 327 clock-names = "ipg"; 328 dmas = <&edma2 12 0 FSL_EDMA_RX>, <&edma2 11 0 0>; 329 dma-names = "rx", "tx"; 330 status = "disabled"; 331 }; 332 333 lpuart6: serial@425a0000 { 334 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 335 "fsl,imx7ulp-lpuart"; 336 reg = <0x425a0000 0x1000>; 337 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 338 clocks = <&scmi_clk IMX94_CLK_LPUART6>; 339 clock-names = "ipg"; 340 dmas = <&edma4 12 0 FSL_EDMA_RX>, <&edma4 11 0 0>; 341 dma-names = "rx", "tx"; 342 status = "disabled"; 343 }; 344 345 flexcan2: can@425b0000 { 346 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 347 reg = <0x425b0000 0x10000>; 348 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 350 <&scmi_clk IMX94_CLK_CAN2>; 351 clock-names = "ipg", "per"; 352 assigned-clocks = <&scmi_clk IMX94_CLK_CAN2>; 353 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 354 assigned-clock-rates = <80000000>; 355 fsl,clk-source = /bits/ 8 <0>; 356 status = "disabled"; 357 }; 358 359 flexcan3: can@425e0000 { 360 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 361 reg = <0x425e0000 0x10000>; 362 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 363 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 364 <&scmi_clk IMX94_CLK_CAN3>; 365 clock-names = "ipg", "per"; 366 assigned-clocks = <&scmi_clk IMX94_CLK_CAN3>; 367 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 368 assigned-clock-rates = <80000000>; 369 fsl,clk-source = /bits/ 8 <0>; 370 status = "disabled"; 371 }; 372 373 flexcan4: can@425f0000 { 374 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 375 reg = <0x425f0000 0x10000>; 376 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 378 <&scmi_clk IMX94_CLK_CAN4>; 379 clock-names = "ipg", "per"; 380 assigned-clocks = <&scmi_clk IMX94_CLK_CAN4>; 381 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 382 assigned-clock-rates = <80000000>; 383 fsl,clk-source = /bits/ 8 <0>; 384 status = "disabled"; 385 }; 386 387 flexcan5: can@42600000 { 388 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 389 reg = <0x42600000 0x10000>; 390 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 391 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 392 <&scmi_clk IMX94_CLK_CAN5>; 393 clock-names = "ipg", "per"; 394 assigned-clocks = <&scmi_clk IMX94_CLK_CAN5>; 395 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 396 assigned-clock-rates = <80000000>; 397 fsl,clk-source = /bits/ 8 <0>; 398 status = "disabled"; 399 }; 400 401 sai2: sai@42650000 { 402 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 403 reg = <0x42650000 0x10000>; 404 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 405 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, 406 <&scmi_clk IMX94_CLK_SAI2>, <&dummy>, <&dummy>; 407 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 408 dmas = <&edma2 30 0 FSL_EDMA_RX>, <&edma2 29 0 0>; 409 dma-names = "rx", "tx"; 410 #sound-dai-cells = <0>; 411 status = "disabled"; 412 }; 413 414 sai3: sai@42660000 { 415 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 416 reg = <0x42660000 0x10000>; 417 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 418 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, 419 <&scmi_clk IMX94_CLK_SAI3>, <&dummy>, <&dummy>; 420 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 421 dmas = <&edma2 32 0 FSL_EDMA_RX>, <&edma2 31 0 0>; 422 dma-names = "rx", "tx"; 423 #sound-dai-cells = <0>; 424 status = "disabled"; 425 }; 426 427 sai4: sai@42670000 { 428 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 429 reg = <0x42670000 0x10000>; 430 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 431 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, <&dummy>, 432 <&scmi_clk IMX94_CLK_SAI4>, <&dummy>, <&dummy>; 433 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 434 dmas = <&edma2 36 0 FSL_EDMA_RX>, <&edma2 35 0 0>; 435 dma-names = "rx", "tx"; 436 #sound-dai-cells = <0>; 437 status = "disabled"; 438 }; 439 440 lpuart7: serial@42690000 { 441 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 442 "fsl,imx7ulp-lpuart"; 443 reg = <0x42690000 0x1000>; 444 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&scmi_clk IMX94_CLK_LPUART7>; 446 clock-names = "ipg"; 447 dmas = <&edma2 46 0 FSL_EDMA_RX>, <&edma2 45 0 0>; 448 dma-names = "rx", "tx"; 449 status = "disabled"; 450 }; 451 452 lpuart8: serial@426a0000 { 453 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 454 "fsl,imx7ulp-lpuart"; 455 reg = <0x426a0000 0x1000>; 456 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 457 clocks = <&scmi_clk IMX94_CLK_LPUART8>; 458 clock-names = "ipg"; 459 dmas = <&edma4 39 0 FSL_EDMA_RX>, <&edma4 38 0 0>; 460 dma-names = "rx", "tx"; 461 status = "disabled"; 462 }; 463 464 lpi2c5: i2c@426b0000 { 465 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 466 reg = <0x426b0000 0x10000>; 467 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 clocks = <&scmi_clk IMX94_CLK_LPI2C5>, 471 <&scmi_clk IMX94_CLK_BUSAON>; 472 clock-names = "per", "ipg"; 473 dmas = <&edma2 37 0 0>, <&edma2 38 0 FSL_EDMA_RX>; 474 dma-names = "tx", "rx"; 475 status = "disabled"; 476 }; 477 478 lpi2c6: i2c@426c0000 { 479 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 480 reg = <0x426c0000 0x10000>; 481 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 482 #address-cells = <1>; 483 #size-cells = <0>; 484 clocks = <&scmi_clk IMX94_CLK_LPI2C6>, 485 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 486 clock-names = "per", "ipg"; 487 dmas = <&edma4 30 0 0>, <&edma4 31 0 FSL_EDMA_RX>; 488 dma-names = "tx", "rx"; 489 status = "disabled"; 490 }; 491 492 lpi2c7: i2c@426d0000 { 493 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 494 reg = <0x426d0000 0x10000>; 495 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 496 #address-cells = <1>; 497 #size-cells = <0>; 498 clocks = <&scmi_clk IMX94_CLK_LPI2C7>, 499 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 500 clock-names = "per", "ipg"; 501 dmas = <&edma2 39 0 0>, <&edma2 40 0 FSL_EDMA_RX>; 502 dma-names = "tx", "rx"; 503 status = "disabled"; 504 }; 505 506 lpi2c8: i2c@426e0000 { 507 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 508 reg = <0x426e0000 0x10000>; 509 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 510 #address-cells = <1>; 511 #size-cells = <0>; 512 clocks = <&scmi_clk IMX94_CLK_LPI2C8>, 513 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 514 clock-names = "per", "ipg"; 515 dmas = <&edma4 32 0 0>, <&edma4 33 0 FSL_EDMA_RX>; 516 dma-names = "tx", "rx"; 517 status = "disabled"; 518 }; 519 520 lpspi5: spi@426f0000 { 521 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 522 reg = <0x426f0000 0x10000>; 523 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 524 #address-cells = <1>; 525 #size-cells = <0>; 526 clocks = <&scmi_clk IMX94_CLK_LPSPI5>, 527 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 528 clock-names = "per", "ipg"; 529 dmas = <&edma2 41 0 0>, <&edma2 42 0 FSL_EDMA_RX>; 530 dma-names = "tx", "rx"; 531 status = "disabled"; 532 }; 533 534 lpspi6: spi@42700000 { 535 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 536 reg = <0x42700000 0x10000>; 537 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 538 #address-cells = <1>; 539 #size-cells = <0>; 540 clocks = <&scmi_clk IMX94_CLK_LPSPI6>, 541 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 542 clock-names = "per", "ipg"; 543 dmas = <&edma4 34 0 0>, <&edma4 35 0 FSL_EDMA_RX>; 544 dma-names = "tx", "rx"; 545 status = "disabled"; 546 }; 547 548 lpspi7: spi@42710000 { 549 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 550 reg = <0x42710000 0x10000>; 551 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 552 #address-cells = <1>; 553 #size-cells = <0>; 554 clocks = <&scmi_clk IMX94_CLK_LPSPI7>, 555 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 556 clock-names = "per", "ipg"; 557 dmas = <&edma2 43 0 0>, <&edma2 44 0 FSL_EDMA_RX>; 558 dma-names = "tx", "rx"; 559 status = "disabled"; 560 }; 561 562 lpspi8: spi@42720000 { 563 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 564 reg = <0x42720000 0x10000>; 565 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 566 #address-cells = <1>; 567 #size-cells = <0>; 568 clocks = <&scmi_clk IMX94_CLK_LPSPI8>, 569 <&scmi_clk IMX94_CLK_BUSWAKEUP>; 570 clock-names = "per", "ipg"; 571 dmas = <&edma4 36 0 0>, <&edma4 37 0 FSL_EDMA_RX>; 572 dma-names = "tx", "rx"; 573 status = "disabled"; 574 }; 575 576 mu11: mailbox@42730000 { 577 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 578 reg = <0x42730000 0x10000>; 579 interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>; 580 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 581 #mbox-cells = <2>; 582 status = "disabled"; 583 }; 584 585 edma4: dma-controller@42df0000 { 586 compatible = "fsl,imx94-edma5", "fsl,imx95-edma5"; 587 reg = <0x42df0000 0x210000>; 588 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 589 clock-names = "dma"; 590 #dma-cells = <3>; 591 dma-channels = <64>; 592 interrupts-extended = <&a55_irqsteer 128>, <&a55_irqsteer 129>, 593 <&a55_irqsteer 130>, <&a55_irqsteer 131>, 594 <&a55_irqsteer 132>, <&a55_irqsteer 133>, 595 <&a55_irqsteer 134>, <&a55_irqsteer 135>, 596 <&a55_irqsteer 136>, <&a55_irqsteer 137>, 597 <&a55_irqsteer 138>, <&a55_irqsteer 139>, 598 <&a55_irqsteer 140>, <&a55_irqsteer 141>, 599 <&a55_irqsteer 142>, <&a55_irqsteer 143>, 600 <&a55_irqsteer 144>, <&a55_irqsteer 145>, 601 <&a55_irqsteer 146>, <&a55_irqsteer 147>, 602 <&a55_irqsteer 148>, <&a55_irqsteer 149>, 603 <&a55_irqsteer 150>, <&a55_irqsteer 151>, 604 <&a55_irqsteer 152>, <&a55_irqsteer 153>, 605 <&a55_irqsteer 154>, <&a55_irqsteer 155>, 606 <&a55_irqsteer 156>, <&a55_irqsteer 157>, 607 <&a55_irqsteer 158>, <&a55_irqsteer 159>, 608 <&a55_irqsteer 192>, <&a55_irqsteer 193>, 609 <&a55_irqsteer 194>, <&a55_irqsteer 195>, 610 <&a55_irqsteer 196>, <&a55_irqsteer 197>, 611 <&a55_irqsteer 198>, <&a55_irqsteer 199>, 612 <&a55_irqsteer 200>, <&a55_irqsteer 201>, 613 <&a55_irqsteer 202>, <&a55_irqsteer 203>, 614 <&a55_irqsteer 204>, <&a55_irqsteer 205>, 615 <&a55_irqsteer 206>, <&a55_irqsteer 207>, 616 <&a55_irqsteer 208>, <&a55_irqsteer 209>, 617 <&a55_irqsteer 210>, <&a55_irqsteer 211>, 618 <&a55_irqsteer 212>, <&a55_irqsteer 213>, 619 <&a55_irqsteer 214>, <&a55_irqsteer 215>, 620 <&a55_irqsteer 216>, <&a55_irqsteer 217>, 621 <&a55_irqsteer 218>, <&a55_irqsteer 219>, 622 <&a55_irqsteer 220>, <&a55_irqsteer 221>, 623 <&a55_irqsteer 222>, <&a55_irqsteer 223>, 624 <&gic GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 625 }; 626 }; 627 628 aips3: bus@42800000 { 629 compatible = "fsl,aips-bus", "simple-bus"; 630 reg = <0 0x42800000 0 0x800000>; 631 ranges = <0x42800000 0x0 0x42800000 0x800000>, 632 <0x28000000 0x0 0x28000000 0x1000000>; 633 #address-cells = <1>; 634 #size-cells = <1>; 635 636 usdhc1: mmc@42850000 { 637 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; 638 reg = <0x42850000 0x10000>; 639 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 640 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 641 <&scmi_clk IMX94_CLK_WAKEUPAXI>, 642 <&scmi_clk IMX94_CLK_USDHC1>; 643 clock-names = "ipg", "ahb", "per"; 644 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC1>; 645 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; 646 assigned-clock-rates = <400000000>; 647 bus-width = <8>; 648 fsl,tuning-start-tap = <1>; 649 fsl,tuning-step = <2>; 650 status = "disabled"; 651 }; 652 653 usdhc2: mmc@42860000 { 654 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; 655 reg = <0x42860000 0x10000>; 656 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 657 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 658 <&scmi_clk IMX94_CLK_WAKEUPAXI>, 659 <&scmi_clk IMX94_CLK_USDHC2>; 660 clock-names = "ipg", "ahb", "per"; 661 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC2>; 662 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; 663 assigned-clock-rates = <200000000>; 664 bus-width = <4>; 665 fsl,tuning-start-tap = <1>; 666 fsl,tuning-step = <2>; 667 status = "disabled"; 668 }; 669 670 usdhc3: mmc@42880000 { 671 compatible = "fsl,imx94-usdhc", "fsl,imx8mm-usdhc"; 672 reg = <0x42880000 0x10000>; 673 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 674 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>, 675 <&scmi_clk IMX94_CLK_WAKEUPAXI>, 676 <&scmi_clk IMX94_CLK_USDHC3>; 677 clock-names = "ipg", "ahb", "per"; 678 assigned-clocks = <&scmi_clk IMX94_CLK_USDHC3>; 679 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1>; 680 assigned-clock-rates = <200000000>; 681 bus-width = <4>; 682 fsl,tuning-start-tap = <1>; 683 fsl,tuning-step = <2>; 684 status = "disabled"; 685 }; 686 687 lpuart9: serial@42a50000 { 688 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 689 "fsl,imx7ulp-lpuart"; 690 reg = <0x42a50000 0x1000>; 691 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 692 clocks = <&scmi_clk IMX94_CLK_LPUART10>; 693 clock-names = "ipg"; 694 dmas = <&edma2 51 0 FSL_EDMA_RX>, <&edma2 50 0 0>; 695 dma-names = "rx", "tx"; 696 status = "disabled"; 697 }; 698 699 lpuart10: serial@42a60000 { 700 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 701 "fsl,imx7ulp-lpuart"; 702 reg = <0x42a60000 0x1000>; 703 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 704 clocks = <&scmi_clk IMX94_CLK_LPUART10>; 705 clock-names = "ipg"; 706 dmas = <&edma4 47 0 FSL_EDMA_RX>, <&edma4 46 0 0>; 707 dma-names = "rx", "tx"; 708 status = "disabled"; 709 }; 710 711 lpuart11: serial@42a70000 { 712 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 713 "fsl,imx7ulp-lpuart"; 714 reg = <0x42a70000 0x1000>; 715 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 716 clocks = <&scmi_clk IMX94_CLK_LPUART11>; 717 clock-names = "ipg"; 718 dmas = <&edma2 53 0 FSL_EDMA_RX>, <&edma2 52 0 0>; 719 dma-names = "rx", "tx"; 720 status = "disabled"; 721 }; 722 723 lpuart12: serial@42a80000 { 724 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 725 "fsl,imx7ulp-lpuart"; 726 reg = <0x42a80000 0x1000>; 727 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 728 clocks = <&scmi_clk IMX94_CLK_LPUART12>; 729 clock-names = "ipg"; 730 dmas = <&edma4 49 0 FSL_EDMA_RX>, <&edma4 48 0 0>; 731 dma-names = "rx", "tx"; 732 status = "disabled"; 733 }; 734 735 mu12: mailbox@42ac0000 { 736 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 737 reg = <0x42ac0000 0x10000>; 738 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 740 #mbox-cells = <2>; 741 status = "disabled"; 742 }; 743 744 mu13: mailbox@42ae0000 { 745 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 746 reg = <0x42ae0000 0x10000>; 747 interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 748 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 749 #mbox-cells = <2>; 750 status = "disabled"; 751 }; 752 753 mu14: mailbox@42b00000 { 754 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 755 reg = <0x42b00000 0x10000>; 756 interrupts = <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>; 757 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 758 #mbox-cells = <2>; 759 status = "disabled"; 760 }; 761 762 mu15: mailbox@42b20000 { 763 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 764 reg = <0x42b20000 0x10000>; 765 interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>; 766 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 767 #mbox-cells = <2>; 768 status = "disabled"; 769 }; 770 771 mu16: mailbox@42b40000 { 772 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 773 reg = <0x42b40000 0x10000>; 774 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 776 #mbox-cells = <2>; 777 status = "disabled"; 778 }; 779 780 mu17: mailbox@42b60000 { 781 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 782 reg = <0x42b60000 0x10000>; 783 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; 784 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 785 #mbox-cells = <2>; 786 status = "disabled"; 787 }; 788 }; 789 790 gpio2: gpio@43810000 { 791 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 792 reg = <0x0 0x43810000 0x0 0x1000>; 793 #interrupt-cells = <2>; 794 interrupt-controller; 795 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 797 #gpio-cells = <2>; 798 gpio-controller; 799 gpio-ranges = <&scmi_iomuxc 0 4 32>; 800 ngpios = <32>; 801 }; 802 803 gpio3: gpio@43820000 { 804 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 805 reg = <0x0 0x43820000 0x0 0x1000>; 806 #interrupt-cells = <2>; 807 interrupt-controller; 808 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 809 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 810 #gpio-cells = <2>; 811 gpio-controller; 812 gpio-ranges = <&scmi_iomuxc 0 36 26>; 813 ngpios = <26>; 814 }; 815 816 gpio4: gpio@43840000 { 817 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 818 reg = <0x0 0x43840000 0x0 0x1000>; 819 #interrupt-cells = <2>; 820 interrupt-controller; 821 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 822 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 823 #gpio-cells = <2>; 824 gpio-controller; 825 gpio-ranges = <&scmi_iomuxc 0 62 4>, <&scmi_iomuxc 4 0 4>, 826 <&scmi_iomuxc 8 140 12>, <&scmi_iomuxc 20 164 12>; 827 ngpios = <32>; 828 }; 829 830 gpio5: gpio@43850000 { 831 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 832 reg = <0x0 0x43850000 0x0 0x1000>; 833 #interrupt-cells = <2>; 834 interrupt-controller; 835 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 837 #gpio-cells = <2>; 838 gpio-controller; 839 gpio-ranges = <&scmi_iomuxc 0 108 32>; 840 ngpios = <32>; 841 }; 842 843 gpio6: gpio@43860000 { 844 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 845 reg = <0x0 0x43860000 0x0 0x1000>; 846 #interrupt-cells = <2>; 847 interrupt-controller; 848 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 850 #gpio-cells = <2>; 851 gpio-controller; 852 gpio-ranges = <&scmi_iomuxc 0 66 32>; 853 ngpios = <32>; 854 }; 855 856 gpio7: gpio@43870000 { 857 compatible = "fsl,imx94-gpio", "fsl,imx8ulp-gpio"; 858 reg = <0x0 0x43870000 0x0 0x1000>; 859 #interrupt-cells = <2>; 860 interrupt-controller; 861 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 863 #gpio-cells = <2>; 864 gpio-controller; 865 gpio-ranges = <&scmi_iomuxc 0 98 10>, <&scmi_iomuxc 16 152 12>; 866 gpio-reserved-ranges = <10 6>; 867 ngpios = <28>; 868 }; 869 870 aips1: bus@44000000 { 871 compatible = "fsl,aips-bus", "simple-bus"; 872 reg = <0x0 0x44000000 0x0 0x800000>; 873 ranges = <0x44000000 0x0 0x44000000 0x800000>; 874 #address-cells = <1>; 875 #size-cells = <1>; 876 877 edma1: dma-controller@44000000 { 878 compatible = "fsl,imx94-edma3", "fsl,imx93-edma3"; 879 reg = <0x44000000 0x210000>; 880 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>, 881 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>, 882 <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>, 883 <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>, 884 <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>, 885 <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>, 886 <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>, 887 <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 891 <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 892 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 893 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 894 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 895 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 896 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 897 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 898 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 899 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 900 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 901 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 902 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 903 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 904 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 905 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 906 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 907 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 908 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 909 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 910 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 911 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 912 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; 913 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 914 clock-names = "dma"; 915 #dma-cells = <3>; 916 dma-channels = <32>; 917 }; 918 919 mu1: mailbox@44220000 { 920 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 921 reg = <0x44220000 0x10000>; 922 interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>; 923 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 924 #mbox-cells = <2>; 925 status = "disabled"; 926 }; 927 928 system_counter: timer@44290000 { 929 compatible = "nxp,imx94-sysctr-timer", "nxp,imx95-sysctr-timer"; 930 reg = <0x44290000 0x30000>; 931 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 932 clocks = <&osc_24m>; 933 clock-names = "per"; 934 nxp,no-divider; 935 }; 936 937 tpm1: pwm@44310000 { 938 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; 939 reg = <0x44310000 0x1000>; 940 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 941 #pwm-cells = <3>; 942 status = "disabled"; 943 }; 944 945 tpm2: pwm@44320000 { 946 compatible = "fsl,imx94-pwm", "fsl,imx7ulp-pwm"; 947 reg = <0x44320000 0x1000>; 948 clocks = <&scmi_clk IMX94_CLK_TPM2>; 949 #pwm-cells = <3>; 950 status = "disabled"; 951 }; 952 953 i3c1: i3c@44330000 { 954 compatible = "silvaco,i3c-master-v1"; 955 reg = <0x44330000 0x10000>; 956 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 957 #address-cells = <3>; 958 #size-cells = <0>; 959 clocks = <&scmi_clk IMX94_CLK_BUSAON>, 960 <&scmi_clk IMX94_CLK_I3C1SLOW>, 961 <&dummy>; 962 clock-names = "pclk", "fast_clk", "slow_clk"; 963 status = "disabled"; 964 }; 965 966 lpi2c1: i2c@44340000 { 967 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 968 reg = <0x44340000 0x10000>; 969 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 clocks = <&scmi_clk IMX94_CLK_LPI2C1>, 973 <&scmi_clk IMX94_CLK_BUSAON>; 974 clock-names = "per", "ipg"; 975 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX>; 976 dma-names = "tx", "rx"; 977 status = "disabled"; 978 }; 979 980 lpi2c2: i2c@44350000 { 981 compatible = "fsl,imx94-lpi2c", "fsl,imx7ulp-lpi2c"; 982 reg = <0x44350000 0x10000>; 983 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 984 #address-cells = <1>; 985 #size-cells = <0>; 986 clocks = <&scmi_clk IMX94_CLK_LPI2C2>, 987 <&scmi_clk IMX94_CLK_BUSAON>; 988 clock-names = "per", "ipg"; 989 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX>; 990 dma-names = "tx", "rx"; 991 status = "disabled"; 992 }; 993 994 lpspi1: spi@44360000 { 995 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 996 reg = <0x44360000 0x10000>; 997 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 998 #address-cells = <1>; 999 #size-cells = <0>; 1000 clocks = <&scmi_clk IMX94_CLK_LPSPI2>, 1001 <&scmi_clk IMX94_CLK_BUSAON>; 1002 clock-names = "per", "ipg"; 1003 dmas = <&edma1 16 0 0>, <&edma1 17 0 FSL_EDMA_RX>; 1004 dma-names = "tx", "rx"; 1005 status = "disabled"; 1006 }; 1007 1008 lpspi2: spi@44370000 { 1009 compatible = "fsl,imx94-spi", "fsl,imx7ulp-spi"; 1010 reg = <0x44370000 0x10000>; 1011 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1012 #address-cells = <1>; 1013 #size-cells = <0>; 1014 clocks = <&scmi_clk IMX94_CLK_LPSPI2>, 1015 <&scmi_clk IMX94_CLK_BUSAON>; 1016 clock-names = "per", "ipg"; 1017 dmas = <&edma1 18 0 0>, <&edma1 19 0 FSL_EDMA_RX>; 1018 dma-names = "tx", "rx"; 1019 status = "disabled"; 1020 }; 1021 1022 lpuart1: serial@44380000 { 1023 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 1024 "fsl,imx7ulp-lpuart"; 1025 reg = <0x44380000 0x1000>; 1026 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&scmi_clk IMX94_CLK_LPUART1>; 1028 clock-names = "ipg"; 1029 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1030 dma-names = "rx", "tx"; 1031 status = "disabled"; 1032 }; 1033 1034 lpuart2: serial@44390000 { 1035 compatible = "fsl,imx94-lpuart", "fsl,imx8ulp-lpuart", 1036 "fsl,imx7ulp-lpuart"; 1037 reg = <0x44390000 0x1000>; 1038 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1039 clocks = <&scmi_clk IMX94_CLK_LPUART2>; 1040 clock-names = "ipg"; 1041 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1042 dma-names = "rx", "tx"; 1043 status = "disabled"; 1044 }; 1045 1046 flexcan1: can@443a0000 { 1047 compatible = "fsl,imx94-flexcan", "fsl,imx95-flexcan"; 1048 reg = <0x443a0000 0x10000>; 1049 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1050 clocks = <&scmi_clk IMX94_CLK_BUSAON>, 1051 <&scmi_clk IMX94_CLK_CAN1>; 1052 clock-names = "ipg", "per"; 1053 assigned-clocks = <&scmi_clk IMX94_CLK_CAN1>; 1054 assigned-clock-parents = <&scmi_clk IMX94_CLK_SYSPLL1_PFD1_DIV2>; 1055 assigned-clock-rates = <80000000>; 1056 fsl,clk-source = /bits/ 8 <0>; 1057 status = "disabled"; 1058 }; 1059 1060 sai1: sai@443b0000 { 1061 compatible = "fsl,imx94-sai", "fsl,imx95-sai"; 1062 reg = <0x443b0000 0x10000>; 1063 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1064 clocks = <&scmi_clk IMX94_CLK_BUSAON>, <&dummy>, 1065 <&scmi_clk IMX94_CLK_SAI1>, <&dummy>, 1066 <&dummy>, <&dummy>; 1067 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1068 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1069 dma-names = "rx", "tx"; 1070 #sound-dai-cells = <0>; 1071 status = "disabled"; 1072 }; 1073 1074 micfil: micfil@44520000 { 1075 compatible = "fsl,imx943-micfil"; 1076 reg = <0x44520000 0x10000>; 1077 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 1081 clocks = <&scmi_clk IMX94_CLK_BUSAON>, 1082 <&scmi_clk IMX94_CLK_PDM>, 1083 <&scmi_clk IMX94_CLK_AUDIOPLL1>, 1084 <&scmi_clk IMX94_CLK_AUDIOPLL2>, 1085 <&dummy>; 1086 clock-names = "ipg_clk", "ipg_clk_app", 1087 "pll8k", "pll11k", "clkext3"; 1088 dmas = <&edma1 6 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>; 1089 dma-names = "rx"; 1090 #sound-dai-cells = <0>; 1091 status = "disabled"; 1092 }; 1093 1094 adc1: adc@44530000 { 1095 compatible = "nxp,imx94-adc", "nxp,imx93-adc"; 1096 reg = <0x44530000 0x10000>; 1097 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; 1100 clocks = <&scmi_clk IMX94_CLK_ADC>; 1101 clock-names = "ipg"; 1102 #io-channel-cells = <1>; 1103 status = "disabled"; 1104 }; 1105 1106 mu2: mailbox@445b0000 { 1107 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1108 reg = <0x445b0000 0x1000>; 1109 ranges; 1110 interrupts = <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 1111 #address-cells = <1>; 1112 #size-cells = <1>; 1113 #mbox-cells = <2>; 1114 1115 sram0: sram@445b1000 { 1116 compatible = "mmio-sram"; 1117 reg = <0x445b1000 0x400>; 1118 ranges = <0x0 0x445b1000 0x400>; 1119 #address-cells = <1>; 1120 #size-cells = <1>; 1121 1122 scmi_buf0: scmi-sram-section@0 { 1123 compatible = "arm,scmi-shmem"; 1124 reg = <0x0 0x80>; 1125 }; 1126 1127 scmi_buf1: scmi-sram-section@80 { 1128 compatible = "arm,scmi-shmem"; 1129 reg = <0x80 0x80>; 1130 }; 1131 }; 1132 }; 1133 1134 mu3: mailbox@445d0000 { 1135 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1136 reg = <0x445d0000 0x10000>; 1137 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 1138 #mbox-cells = <2>; 1139 status = "disabled"; 1140 }; 1141 1142 mu4: mailbox@445f0000 { 1143 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1144 reg = <0x445f0000 0x10000>; 1145 interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 1146 #mbox-cells = <2>; 1147 status = "disabled"; 1148 }; 1149 1150 mu6: mailbox@44630000 { 1151 compatible = "fsl,imx94-mu", "fsl,imx95-mu"; 1152 reg = <0x44630000 0x10000>; 1153 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 1154 #mbox-cells = <2>; 1155 status = "disabled"; 1156 }; 1157 1158 a55_irqsteer: interrupt-controller@446a0000 { 1159 compatible = "fsl,imx94-irqsteer", "fsl,imx-irqsteer"; 1160 reg = <0x446a0000 0x1000>; 1161 #interrupt-cells = <1>; 1162 interrupt-controller; 1163 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, 1164 <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>, 1165 <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>, 1166 <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>, 1167 <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>, 1168 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 1169 clocks = <&scmi_clk IMX94_CLK_BUSAON>; 1170 clock-names = "ipg"; 1171 fsl,channel = <0>; 1172 fsl,num-irqs = <960>; 1173 }; 1174 }; 1175 1176 aips4: bus@49000000 { 1177 compatible = "fsl,aips-bus", "simple-bus"; 1178 reg = <0x0 0x49000000 0x0 0x800000>; 1179 ranges = <0x49000000 0x0 0x49000000 0x800000>; 1180 #address-cells = <1>; 1181 #size-cells = <1>; 1182 1183 wdog3: watchdog@49220000 { 1184 compatible = "fsl,imx94-wdt", "fsl,imx93-wdt"; 1185 reg = <0x49220000 0x10000>; 1186 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1187 clocks = <&scmi_clk IMX94_CLK_BUSWAKEUP>; 1188 timeout-sec = <40>; 1189 fsl,ext-reset-output; 1190 status = "disabled"; 1191 }; 1192 }; 1193 1194 ddr-pmu@4e090dc0 { 1195 compatible = "fsl,imx94-ddr-pmu", "fsl,imx93-ddr-pmu"; 1196 reg = <0x0 0x4e090dc0 0x0 0x200>; 1197 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1198 }; 1199 }; 1200};
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