imx93.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2022,2025 NXP
  4 */
  5
  6#include "imx91_93_common.dtsi"
  7
  8/{
  9	cm33: remoteproc-cm33 {
 10		compatible = "fsl,imx93-cm33";
 11		clocks = <&clk IMX93_CLK_CM33_GATE>;
 12		status = "disabled";
 13	};
 14
 15	thermal-zones {
 16		cpu-thermal {
 17			polling-delay-passive = <250>;
 18			polling-delay = <2000>;
 19
 20			thermal-sensors = <&tmu 0>;
 21
 22			trips {
 23				cpu_alert: cpu-alert {
 24					temperature = <80000>;
 25					hysteresis = <2000>;
 26					type = "passive";
 27				};
 28
 29				cpu_crit: cpu-crit {
 30					temperature = <90000>;
 31					hysteresis = <2000>;
 32					type = "critical";
 33				};
 34			};
 35
 36			cooling-maps {
 37				map0 {
 38					trip = <&cpu_alert>;
 39					cooling-device =
 40						<&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 41						<&A55_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 42				};
 43			};
 44		};
 45	};
 46};
 47
 48&aips1 {
 49	mu1: mailbox@44230000 {
 50		compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
 51		reg = <0x44230000 0x10000>;
 52		interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 53		clocks = <&clk IMX93_CLK_MU1_B_GATE>;
 54		#mbox-cells = <2>;
 55		status = "disabled";
 56	};
 57
 58	tmu: tmu@44482000 {
 59		compatible = "fsl,qoriq-tmu";
 60		reg = <0x44482000 0x1000>;
 61		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 62		clocks = <&clk IMX93_CLK_TMC_GATE>;
 63		#thermal-sensor-cells = <1>;
 64		little-endian;
 65		fsl,tmu-range = <0x800000da 0x800000e9
 66				 0x80000102 0x8000012a
 67				 0x80000166 0x800001a7
 68				 0x800001b6>;
 69		fsl,tmu-calibration = <0x00000000 0x0000000e
 70				       0x00000001 0x00000029
 71				       0x00000002 0x00000056
 72				       0x00000003 0x000000a2
 73				       0x00000004 0x00000116
 74				       0x00000005 0x00000195
 75				       0x00000006 0x000001b2>;
 76	};
 77};
 78
 79&aips2 {
 80	mu2: mailbox@42440000 {
 81		compatible = "fsl,imx93-mu", "fsl,imx8ulp-mu";
 82		reg = <0x42440000 0x10000>;
 83		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
 84		clocks = <&clk IMX93_CLK_MU2_B_GATE>;
 85		#mbox-cells = <2>;
 86		status = "disabled";
 87	};
 88};
 89
 90&cpus {
 91	A55_0: cpu@0 {
 92		device_type = "cpu";
 93		compatible = "arm,cortex-a55";
 94		reg = <0x0>;
 95		enable-method = "psci";
 96		#cooling-cells = <2>;
 97		cpu-idle-states = <&cpu_pd_wait>;
 98		i-cache-size = <32768>;
 99		i-cache-line-size = <64>;
100		i-cache-sets = <128>;
101		d-cache-size = <32768>;
102		d-cache-line-size = <64>;
103		d-cache-sets = <128>;
104		next-level-cache = <&l2_cache_l0>;
105	};
106
107	A55_1: cpu@100 {
108		device_type = "cpu";
109		compatible = "arm,cortex-a55";
110		reg = <0x100>;
111		enable-method = "psci";
112		#cooling-cells = <2>;
113		cpu-idle-states = <&cpu_pd_wait>;
114		i-cache-size = <32768>;
115		i-cache-line-size = <64>;
116		i-cache-sets = <128>;
117		d-cache-size = <32768>;
118		d-cache-line-size = <64>;
119		d-cache-sets = <128>;
120		next-level-cache = <&l2_cache_l1>;
121	};
122
123	l2_cache_l0: l2-cache-l0 {
124		compatible = "cache";
125		cache-size = <65536>;
126		cache-line-size = <64>;
127		cache-sets = <256>;
128		cache-level = <2>;
129		cache-unified;
130		next-level-cache = <&l3_cache>;
131	};
132
133	l2_cache_l1: l2-cache-l1 {
134		compatible = "cache";
135		cache-size = <65536>;
136		cache-line-size = <64>;
137		cache-sets = <256>;
138		cache-level = <2>;
139		cache-unified;
140		next-level-cache = <&l3_cache>;
141	};
142
143	l3_cache: l3-cache {
144		compatible = "cache";
145		cache-size = <262144>;
146		cache-line-size = <64>;
147		cache-sets = <256>;
148		cache-level = <3>;
149		cache-unified;
150	};
151};
152
153&src {
154	mlmix: power-domain@44461800 {
155		compatible = "fsl,imx93-src-slice";
156		reg = <0x44461800 0x400>, <0x44464800 0x400>;
157		clocks = <&clk IMX93_CLK_ML_APB>,
158			 <&clk IMX93_CLK_ML>;
159		#power-domain-cells = <0>;
160	};
161};