imx93-var-som.dtsi

  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright 2022 NXP
  4 * Copyright 2023 Variscite Ltd.
  5 */
  6
  7/dts-v1/;
  8
  9#include "imx93.dtsi"
 10
 11/{
 12	model = "Variscite VAR-SOM-MX93 module";
 13	compatible = "variscite,var-som-mx93", "fsl,imx93";
 14
 15	sound {
 16		compatible = "simple-audio-card";
 17		simple-audio-card,bitclock-master = <&codec_dai>;
 18		simple-audio-card,format = "i2s";
 19		simple-audio-card,frame-master = <&codec_dai>;
 20		simple-audio-card,name = "wm8904-audio";
 21		simple-audio-card,routing =
 22			"Headphone Jack", "HPOUTL",
 23			"Headphone Jack", "HPOUTR",
 24			"IN2L", "Line In Jack",
 25			"IN2R", "Line In Jack",
 26			"IN1L", "Microphone Jack",
 27			"IN1R", "Microphone Jack";
 28		simple-audio-card,widgets =
 29			"Microphone", "Microphone Jack",
 30			"Headphone", "Headphone Jack",
 31			"Line", "Line In Jack";
 32		simple-audio-card,mclk-fs = <256>;
 33
 34		codec_dai: simple-audio-card,codec {
 35			sound-dai = <&wm8904>;
 36		};
 37
 38		simple-audio-card,cpu {
 39			sound-dai = <&sai1>;
 40		};
 41	};
 42
 43	usdhc3_pwrseq: mmc-pwrseq {
 44		compatible = "mmc-pwrseq-simple";
 45		post-power-on-delay-ms = <100>;
 46		power-off-delay-us = <10000>;
 47		reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>,	/* WIFI_RESET */
 48			      <&gpio3 7 GPIO_ACTIVE_LOW>;	/* WIFI_PWR_EN */
 49	};
 50};
 51
 52&eqos {
 53	pinctrl-names = "default";
 54	pinctrl-0 = <&pinctrl_eqos>;
 55	/*
 56	 * The required RGMII TX and RX 2ns delays are implemented directly
 57	 * in hardware via passive delay elements on the SOM PCB.
 58	 * No delay configuration is needed in software via PHY driver.
 59	 */
 60	phy-mode = "rgmii";
 61	phy-handle = <&ethphy0>;
 62	snps,clk-csr = <5>;
 63	status = "okay";
 64
 65	mdio {
 66		compatible = "snps,dwmac-mdio";
 67		#address-cells = <1>;
 68		#size-cells = <0>;
 69		clock-frequency = <1000000>;
 70
 71		ethphy0: ethernet-phy@0 {
 72			compatible = "ethernet-phy-ieee802.3-c22";
 73			reg = <0>;
 74			eee-broken-1000t;
 75			reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
 76			reset-assert-us = <10000>;
 77			reset-deassert-us = <100000>;
 78
 79			leds {
 80				#address-cells = <1>;
 81				#size-cells = <0>;
 82
 83				led@0 {
 84					reg = <0>;
 85					color = <LED_COLOR_ID_YELLOW>;
 86					function = LED_FUNCTION_LAN;
 87					linux,default-trigger = "netdev";
 88				};
 89
 90				led@1 {
 91					reg = <1>;
 92					color = <LED_COLOR_ID_GREEN>;
 93					function = LED_FUNCTION_LAN;
 94					linux,default-trigger = "netdev";
 95				};
 96			};
 97		};
 98	};
 99};
100
101&lpi2c3 {
102	clock-frequency = <400000>;
103	pinctrl-names = "default", "sleep", "gpio";
104	pinctrl-0 = <&pinctrl_lpi2c3>;
105	pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
106	pinctrl-2 = <&pinctrl_lpi2c3_gpio>;
107	scl-gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
108	sda-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
109	status = "okay";
110
111	pmic@25 {
112		compatible = "nxp,pca9451a";
113		reg = <0x25>;
114
115		regulators {
116			buck1: BUCK1 {
117				regulator-name = "BUCK1";
118				regulator-min-microvolt = <650000>;
119				regulator-max-microvolt = <2237500>;
120				regulator-boot-on;
121				regulator-always-on;
122				regulator-ramp-delay = <3125>;
123			};
124
125			buck2: BUCK2 {
126				regulator-name = "BUCK2";
127				regulator-min-microvolt = <600000>;
128				regulator-max-microvolt = <2187500>;
129				regulator-boot-on;
130				regulator-always-on;
131				regulator-ramp-delay = <3125>;
132			};
133
134			buck4: BUCK4{
135				regulator-name = "BUCK4";
136				regulator-min-microvolt = <600000>;
137				regulator-max-microvolt = <3400000>;
138				regulator-boot-on;
139				regulator-always-on;
140			};
141
142			buck5: BUCK5{
143				regulator-name = "BUCK5";
144				regulator-min-microvolt = <600000>;
145				regulator-max-microvolt = <3400000>;
146				regulator-boot-on;
147				regulator-always-on;
148			};
149
150			buck6: BUCK6 {
151				regulator-name = "BUCK6";
152				regulator-min-microvolt = <600000>;
153				regulator-max-microvolt = <3400000>;
154				regulator-boot-on;
155				regulator-always-on;
156			};
157
158			ldo1: LDO1 {
159				regulator-name = "LDO1";
160				regulator-min-microvolt = <1600000>;
161				regulator-max-microvolt = <3300000>;
162				regulator-boot-on;
163				regulator-always-on;
164			};
165
166			ldo4: LDO4 {
167				regulator-name = "LDO4";
168				regulator-min-microvolt = <800000>;
169				regulator-max-microvolt = <3300000>;
170				regulator-boot-on;
171				regulator-always-on;
172			};
173
174			ldo5: LDO5 {
175				regulator-name = "LDO5";
176				regulator-min-microvolt = <1800000>;
177				regulator-max-microvolt = <3300000>;
178				regulator-boot-on;
179				regulator-always-on;
180			};
181		};
182	};
183
184	wm8904: audio-codec@1a {
185		compatible = "wlf,wm8904";
186		reg = <0x1a>;
187		#sound-dai-cells = <0>;
188		clocks = <&clk IMX93_CLK_SAI1_GATE>;
189		clock-names = "mclk";
190		AVDD-supply = <&buck5>;
191		CPVDD-supply = <&buck5>;
192		DBVDD-supply = <&buck4>;
193		DCVDD-supply = <&buck5>;
194		MICVDD-supply = <&buck5>;
195		wlf,drc-cfg-names = "default", "peaklimiter", "tradition",
196				    "soft", "music";
197		/*
198		 * Config registers per name, respectively:
199		 * KNEE_IP = 0,   KNEE_OP = 0,     HI_COMP = 1,   LO_COMP = 1
200		 * KNEE_IP = -24, KNEE_OP = -6,    HI_COMP = 1/4, LO_COMP = 1
201		 * KNEE_IP = -42, KNEE_OP = -3,    HI_COMP = 0,   LO_COMP = 1
202		 * KNEE_IP = -45, KNEE_OP = -9,    HI_COMP = 1/8, LO_COMP = 1
203		 * KNEE_IP = -30, KNEE_OP = -10.5, HI_COMP = 1/4, LO_COMP = 1
204		 */
205		wlf,drc-cfg-regs = /bits/ 16 <0x01af 0x3248 0x0000 0x0000>,
206				   /bits/ 16 <0x04af 0x324b 0x0010 0x0408>,
207				   /bits/ 16 <0x04af 0x324b 0x0028 0x0704>,
208				   /bits/ 16 <0x04af 0x324b 0x0018 0x078c>,
209				   /bits/ 16 <0x04af 0x324b 0x0010 0x050e>;
210		/* GPIO1 = DMIC_CLK, don't touch others */
211		wlf,gpio-cfg = <0x0018>, <0xffff>, <0xffff>, <0xffff>;
212	};
213};
214
215&lpspi8 {
216	pinctrl-names = "default";
217	pinctrl-0 = <&pinctrl_lpspi8>;
218	cs-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
219	status = "okay";
220
221	/* Resistive touch controller */
222	ads7846: touchscreen@0 {
223		compatible = "ti,ads7846";
224		reg = <0>;
225		pinctrl-names = "default";
226		pinctrl-0 = <&pinctrl_restouch>;
227		interrupt-parent = <&gpio4>;
228		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
229		spi-max-frequency = <1000000>;
230		pendown-gpio = <&gpio4 29 0>;
231		vcc-supply = <&buck5>;
232		ti,x-min = /bits/ 16 <125>;
233		ti,x-max = /bits/ 16 <4008>;
234		ti,y-min = /bits/ 16 <282>;
235		ti,y-max = /bits/ 16 <3864>;
236		ti,x-plate-ohms = /bits/ 16 <180>;
237		ti,pressure-max = /bits/ 16 <255>;
238		ti,debounce-max = /bits/ 16 <10>;
239		ti,debounce-tol = /bits/ 16 <3>;
240		ti,debounce-rep = /bits/ 16 <1>;
241		ti,settle-delay-usec = /bits/ 16 <150>;
242		ti,keep-vref-on;
243		wakeup-source;
244	};
245};
246
247/* BT module */
248&lpuart5 {
249	pinctrl-names = "default";
250	pinctrl-0 = <&pinctrl_lpuart5>, <&pinctrl_bluetooth>;
251	uart-has-rtscts;
252	status = "okay";
253
254	bluetooth {
255		compatible = "nxp,88w8987-bt";
256	};
257};
258
259&sai1 {
260	pinctrl-names = "default", "sleep";
261	pinctrl-0 = <&pinctrl_sai1>;
262	pinctrl-1 = <&pinctrl_sai1_sleep>;
263	assigned-clocks = <&clk IMX93_CLK_SAI1>;
264	assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>;
265	assigned-clock-rates = <12288000>;
266	fsl,sai-mclk-direction-output;
267	status = "okay";
268};
269
270/* eMMC */
271&usdhc1 {
272	pinctrl-names = "default", "state_100mhz", "state_200mhz";
273	pinctrl-0 = <&pinctrl_usdhc1>;
274	pinctrl-1 = <&pinctrl_usdhc1>;
275	pinctrl-2 = <&pinctrl_usdhc1>;
276	bus-width = <8>;
277	non-removable;
278	status = "okay";
279};
280
281/* WiFi */
282&usdhc3 {
283	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
284	pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_wlan>;
285	pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_wlan>;
286	pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_wlan>;
287	pinctrl-3 = <&pinctrl_usdhc3_sleep>, <&pinctrl_usdhc3_wlan>;
288	bus-width = <4>;
289	mmc-pwrseq = <&usdhc3_pwrseq>;
290	non-removable;
291	wakeup-source;
292	status = "okay";
293};
294
295&iomuxc {
296	pinctrl_bluetooth: bluetoothgrp {
297		fsl,pins = <
298			MX93_PAD_ENET2_MDIO__GPIO4_IO15		0x51e
299		>;
300	};
301
302	pinctrl_eqos: eqosgrp {
303		fsl,pins = <
304			MX93_PAD_ENET1_MDC__ENET_QOS_MDC			0x57e
305			MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO			0x57e
306			MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0			0x57e
307			MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1			0x57e
308			MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2			0x57e
309			MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3			0x57e
310			MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x58e
311			MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x57e
312			MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0			0x57e
313			MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1			0x57e
314			MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2			0x57e
315			MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3			0x57e
316			MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x58e
317			MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x57e
318			MX93_PAD_UART2_TXD__GPIO1_IO07				0x51e
319		>;
320	};
321
322	pinctrl_reg_eqos_phy: regeqosgrp {
323		fsl,pins = <
324			MX93_PAD_UART2_TXD__GPIO1_IO07			0x51e
325		>;
326	};
327
328	pinctrl_lpi2c3: lpi2c3grp {
329		fsl,pins = <
330			MX93_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e
331			MX93_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e
332		>;
333	};
334
335	pinctrl_lpi2c3_gpio: lpi2c3-gpiogrp {
336		fsl,pins = <
337			MX93_PAD_GPIO_IO28__GPIO2_IO28		0x40000b9e
338			MX93_PAD_GPIO_IO29__GPIO2_IO29		0x40000b9e
339		>;
340	};
341
342	pinctrl_lpspi8: lpspi8grp {
343		fsl,pins = <
344			MX93_PAD_GPIO_IO12__GPIO2_IO12		0x31e
345			MX93_PAD_GPIO_IO13__LPSPI8_SIN		0x31e
346			MX93_PAD_GPIO_IO14__LPSPI8_SOUT		0x31e
347			MX93_PAD_GPIO_IO15__LPSPI8_SCK		0x31e
348		>;
349	};
350
351	pinctrl_lpuart5: lpuart5grp {
352		fsl,pins = <
353			MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX   0x31e
354			MX93_PAD_DAP_TDI__LPUART5_RX            0x31e
355			MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B   0x31e
356			MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B  0x31e
357		>;
358	};
359
360	pinctrl_restouch: restouchgrp {
361		fsl,pins = <
362			MX93_PAD_CCM_CLKO4__GPIO4_IO29		0x31e
363		>;
364	};
365
366	pinctrl_sai1: sai1grp {
367		fsl,pins = <
368			MX93_PAD_SAI1_TXC__SAI1_TX_BCLK		0x31e
369			MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC	0x31e
370			MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00	0x31e
371			MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00	0x31e
372			MX93_PAD_I2C2_SDA__SAI1_RX_BCLK		0x31e
373			MX93_PAD_I2C2_SCL__SAI1_RX_SYNC		0x31e
374			MX93_PAD_UART2_RXD__SAI1_MCLK		0x31e
375		>;
376	};
377
378	pinctrl_sai1_sleep: sai1-sleepgrp {
379		fsl,pins = <
380			MX93_PAD_SAI1_TXC__GPIO1_IO12		0x31e
381			MX93_PAD_SAI1_TXFS__GPIO1_IO11		0x31e
382			MX93_PAD_SAI1_TXD0__GPIO1_IO13		0x31e
383			MX93_PAD_SAI1_RXD0__GPIO1_IO14		0x31e
384			MX93_PAD_UART2_RXD__GPIO1_IO06		0x31e
385			MX93_PAD_I2C2_SDA__GPIO1_IO03		0x31e
386			MX93_PAD_I2C2_SCL__GPIO1_IO02		0x31e
387		>;
388	};
389
390	pinctrl_usdhc1: usdhc1grp {
391		fsl,pins = <
392			MX93_PAD_SD1_CLK__USDHC1_CLK		0x15fe
393			MX93_PAD_SD1_CMD__USDHC1_CMD		0x13fe
394			MX93_PAD_SD1_DATA0__USDHC1_DATA0	0x13fe
395			MX93_PAD_SD1_DATA1__USDHC1_DATA1	0x13fe
396			MX93_PAD_SD1_DATA2__USDHC1_DATA2	0x13fe
397			MX93_PAD_SD1_DATA3__USDHC1_DATA3	0x13fe
398			MX93_PAD_SD1_DATA4__USDHC1_DATA4	0x13fe
399			MX93_PAD_SD1_DATA5__USDHC1_DATA5	0x13fe
400			MX93_PAD_SD1_DATA6__USDHC1_DATA6	0x13fe
401			MX93_PAD_SD1_DATA7__USDHC1_DATA7	0x13fe
402			MX93_PAD_SD1_STROBE__USDHC1_STROBE	0x15fe
403		>;
404	};
405
406	pinctrl_usdhc3: usdhc3grp {
407		fsl,pins = <
408			MX93_PAD_SD3_CLK__USDHC3_CLK		0x1582 /* SDIO_B_CLK */
409			MX93_PAD_SD3_CMD__USDHC3_CMD		0x40001382 /* SDIO_B_CMD */
410			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x40001382 /* SDIO_B_D0 */
411			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x40001382 /* SDIO_B_D1 */
412			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x40001382 /* SDIO_B_D2 */
413			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x40001382 /* SDIO_B_D3 */
414		>;
415	};
416
417	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
418		fsl,pins = <
419			MX93_PAD_SD3_CLK__USDHC3_CLK		0x158e /* SDIO_B_CLK */
420			MX93_PAD_SD3_CMD__USDHC3_CMD		0x4000138e /* SDIO_B_CMD */
421			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x4000138e /* SDIO_B_D0 */
422			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x4000138e /* SDIO_B_D1 */
423			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x4000138e /* SDIO_B_D2 */
424			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x4000138e /* SDIO_B_D3 */
425		>;
426	};
427
428	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
429		fsl,pins = <
430			MX93_PAD_SD3_CLK__USDHC3_CLK		0x15fe /* SDIO_B_CLK */
431			MX93_PAD_SD3_CMD__USDHC3_CMD		0x400013fe /* SDIO_B_CMD */
432			MX93_PAD_SD3_DATA0__USDHC3_DATA0	0x400013fe /* SDIO_B_D0 */
433			MX93_PAD_SD3_DATA1__USDHC3_DATA1	0x400013fe /* SDIO_B_D1 */
434			MX93_PAD_SD3_DATA2__USDHC3_DATA2	0x400013fe /* SDIO_B_D2 */
435			MX93_PAD_SD3_DATA3__USDHC3_DATA3	0x400013fe /* SDIO_B_D3 */
436		>;
437	};
438
439	pinctrl_usdhc3_sleep: usdhc3-sleepgrp {
440		fsl,pins = <
441			MX93_PAD_SD3_CLK__GPIO3_IO20		0x400
442			MX93_PAD_SD3_CMD__GPIO3_IO21		0x400
443			MX93_PAD_SD3_DATA0__GPIO3_IO22		0x400
444			MX93_PAD_SD3_DATA1__GPIO3_IO23		0x400
445			MX93_PAD_SD3_DATA2__GPIO3_IO24		0x400
446			MX93_PAD_SD3_DATA3__GPIO3_IO25		0x400
447		>;
448	};
449
450	pinctrl_usdhc3_wlan: usdhc3-wlangrp {
451		fsl,pins = <
452			MX93_PAD_ENET2_MDC__GPIO4_IO14		0x51e /* WIFI_REG_ON     */
453			MX93_PAD_SD2_RESET_B__GPIO3_IO07	0x51e /* WIFI_PWR_EN     */
454		>;
455	};
456};