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imx91_93_common.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/imx91_93_common.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2022,2025 NXP 4 */ 5 6#include <dt-bindings/clock/imx93-clock.h> 7#include <dt-bindings/dma/fsl-edma.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/power/fsl,imx93-power.h> 12#include <dt-bindings/thermal/thermal.h> 13 14#include "imx93-pinfunc.h" 15 16/ { 17 interrupt-parent = <&gic>; 18 #address-cells = <2>; 19 #size-cells = <2>; 20 21 cpus: cpus { 22 #address-cells = <1>; 23 #size-cells = <0>; 24 25 idle-states { 26 entry-method = "psci"; 27 28 cpu_pd_wait: cpu-pd-wait { 29 compatible = "arm,idle-state"; 30 arm,psci-suspend-param = <0x0010033>; 31 local-timer-stop; 32 entry-latency-us = <10000>; 33 exit-latency-us = <7000>; 34 min-residency-us = <27000>; 35 wakeup-latency-us = <15000>; 36 }; 37 }; 38 39 A55_0: cpu@0 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a55"; 42 reg = <0x0>; 43 enable-method = "psci"; 44 #cooling-cells = <2>; 45 cpu-idle-states = <&cpu_pd_wait>; 46 }; 47 }; 48 49 osc_32k: clock-osc-32k { 50 compatible = "fixed-clock"; 51 #clock-cells = <0>; 52 clock-frequency = <32768>; 53 clock-output-names = "osc_32k"; 54 }; 55 56 osc_24m: clock-osc-24m { 57 compatible = "fixed-clock"; 58 #clock-cells = <0>; 59 clock-frequency = <24000000>; 60 clock-output-names = "osc_24m"; 61 }; 62 63 clk_ext1: clock-ext1 { 64 compatible = "fixed-clock"; 65 #clock-cells = <0>; 66 clock-frequency = <133000000>; 67 clock-output-names = "clk_ext1"; 68 }; 69 70 pmu { 71 compatible = "arm,cortex-a55-pmu"; 72 interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 73 }; 74 75 psci { 76 compatible = "arm,psci-1.0"; 77 method = "smc"; 78 }; 79 80 timer { 81 compatible = "arm,armv8-timer"; 82 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 83 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 84 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, 85 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; 86 clock-frequency = <24000000>; 87 arm,no-tick-in-suspend; 88 interrupt-parent = <&gic>; 89 }; 90 91 gic: interrupt-controller@48000000 { 92 compatible = "arm,gic-v3"; 93 reg = <0 0x48000000 0 0x10000>, 94 <0 0x48040000 0 0xc0000>; 95 #interrupt-cells = <3>; 96 interrupt-controller; 97 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 98 interrupt-parent = <&gic>; 99 }; 100 101 mqs1: mqs1 { 102 compatible = "fsl,imx93-mqs"; 103 gpr = <&aonmix_ns_gpr>; 104 status = "disabled"; 105 }; 106 107 mqs2: mqs2 { 108 compatible = "fsl,imx93-mqs"; 109 gpr = <&wakeupmix_gpr>; 110 status = "disabled"; 111 }; 112 113 usbphynop1: usbphynop1 { 114 compatible = "usb-nop-xceiv"; 115 #phy-cells = <0>; 116 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; 117 clock-names = "main_clk"; 118 }; 119 120 usbphynop2: usbphynop2 { 121 compatible = "usb-nop-xceiv"; 122 #phy-cells = <0>; 123 clocks = <&clk IMX93_CLK_USB_PHY_BURUNIN>; 124 clock-names = "main_clk"; 125 }; 126 127 soc@0 { 128 compatible = "simple-bus"; 129 #address-cells = <1>; 130 #size-cells = <1>; 131 ranges = <0x0 0x0 0x0 0x80000000>, 132 <0x28000000 0x0 0x28000000 0x10000000>; 133 134 aips1: bus@44000000 { 135 compatible = "fsl,aips-bus", "simple-bus"; 136 reg = <0x44000000 0x800000>; 137 #address-cells = <1>; 138 #size-cells = <1>; 139 ranges; 140 141 edma1: dma-controller@44000000 { 142 compatible = "fsl,imx93-edma3"; 143 reg = <0x44000000 0x200000>; 144 #dma-cells = <3>; 145 dma-channels = <31>; 146 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved 147 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1 148 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved 149 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0 150 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1 151 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus 152 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus 153 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX 154 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX 155 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX 156 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX 157 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX 158 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX 159 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX 160 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX 161 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1 162 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX 163 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX 164 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX 165 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX 166 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400 167 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX 168 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX 169 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2 170 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3 171 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow 172 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2 173 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3 174 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow 175 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM 176 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, // 30: ADC1 177 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; // err 178 clocks = <&clk IMX93_CLK_EDMA1_GATE>; 179 clock-names = "dma"; 180 }; 181 182 aonmix_ns_gpr: syscon@44210000 { 183 compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; 184 reg = <0x44210000 0x1000>; 185 }; 186 187 system_counter: timer@44290000 { 188 compatible = "nxp,sysctr-timer"; 189 reg = <0x44290000 0x30000>; 190 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 191 clocks = <&osc_24m>; 192 clock-names = "per"; 193 nxp,no-divider; 194 }; 195 196 wdog1: watchdog@442d0000 { 197 compatible = "fsl,imx93-wdt"; 198 reg = <0x442d0000 0x10000>; 199 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 200 clocks = <&clk IMX93_CLK_WDOG1_GATE>; 201 timeout-sec = <40>; 202 status = "disabled"; 203 }; 204 205 wdog2: watchdog@442e0000 { 206 compatible = "fsl,imx93-wdt"; 207 reg = <0x442e0000 0x10000>; 208 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 209 clocks = <&clk IMX93_CLK_WDOG2_GATE>; 210 timeout-sec = <40>; 211 status = "disabled"; 212 }; 213 214 tpm1: pwm@44310000 { 215 compatible = "fsl,imx7ulp-pwm"; 216 reg = <0x44310000 0x1000>; 217 clocks = <&clk IMX93_CLK_TPM1_GATE>; 218 #pwm-cells = <3>; 219 status = "disabled"; 220 }; 221 222 tpm2: pwm@44320000 { 223 compatible = "fsl,imx7ulp-pwm"; 224 reg = <0x44320000 0x10000>; 225 clocks = <&clk IMX93_CLK_TPM2_GATE>; 226 #pwm-cells = <3>; 227 status = "disabled"; 228 }; 229 230 i3c1: i3c@44330000 { 231 compatible = "silvaco,i3c-master-v1"; 232 reg = <0x44330000 0x10000>; 233 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 234 #address-cells = <3>; 235 #size-cells = <0>; 236 clocks = <&clk IMX93_CLK_BUS_AON>, 237 <&clk IMX93_CLK_I3C1_GATE>, 238 <&clk IMX93_CLK_I3C1_SLOW>; 239 clock-names = "pclk", "fast_clk", "slow_clk"; 240 status = "disabled"; 241 }; 242 243 lpi2c1: i2c@44340000 { 244 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 245 reg = <0x44340000 0x10000>; 246 #address-cells = <1>; 247 #size-cells = <0>; 248 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 249 clocks = <&clk IMX93_CLK_LPI2C1_GATE>, 250 <&clk IMX93_CLK_BUS_AON>; 251 clock-names = "per", "ipg"; 252 dmas = <&edma1 7 0 0>, <&edma1 8 0 FSL_EDMA_RX>; 253 dma-names = "tx", "rx"; 254 status = "disabled"; 255 }; 256 257 lpi2c2: i2c@44350000 { 258 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 259 reg = <0x44350000 0x10000>; 260 #address-cells = <1>; 261 #size-cells = <0>; 262 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 263 clocks = <&clk IMX93_CLK_LPI2C2_GATE>, 264 <&clk IMX93_CLK_BUS_AON>; 265 clock-names = "per", "ipg"; 266 dmas = <&edma1 9 0 0>, <&edma1 10 0 FSL_EDMA_RX>; 267 dma-names = "tx", "rx"; 268 status = "disabled"; 269 }; 270 271 lpspi1: spi@44360000 { 272 #address-cells = <1>; 273 #size-cells = <0>; 274 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 275 reg = <0x44360000 0x10000>; 276 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 277 clocks = <&clk IMX93_CLK_LPSPI1_GATE>, 278 <&clk IMX93_CLK_BUS_AON>; 279 clock-names = "per", "ipg"; 280 dmas = <&edma1 11 0 0>, <&edma1 12 0 FSL_EDMA_RX>; 281 dma-names = "tx", "rx"; 282 status = "disabled"; 283 }; 284 285 lpspi2: spi@44370000 { 286 #address-cells = <1>; 287 #size-cells = <0>; 288 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 289 reg = <0x44370000 0x10000>; 290 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&clk IMX93_CLK_LPSPI2_GATE>, 292 <&clk IMX93_CLK_BUS_AON>; 293 clock-names = "per", "ipg"; 294 dmas = <&edma1 13 0 0>, <&edma1 14 0 FSL_EDMA_RX>; 295 dma-names = "tx", "rx"; 296 status = "disabled"; 297 }; 298 299 lpuart1: serial@44380000 { 300 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 301 reg = <0x44380000 0x1000>; 302 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 303 clocks = <&clk IMX93_CLK_LPUART1_GATE>; 304 clock-names = "ipg"; 305 dmas = <&edma1 17 0 FSL_EDMA_RX>, <&edma1 16 0 0>; 306 dma-names = "rx", "tx"; 307 status = "disabled"; 308 }; 309 310 lpuart2: serial@44390000 { 311 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 312 reg = <0x44390000 0x1000>; 313 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&clk IMX93_CLK_LPUART2_GATE>; 315 clock-names = "ipg"; 316 dmas = <&edma1 19 0 FSL_EDMA_RX>, <&edma1 18 0 0>; 317 dma-names = "rx", "tx"; 318 status = "disabled"; 319 }; 320 321 flexcan1: can@443a0000 { 322 compatible = "fsl,imx93-flexcan"; 323 reg = <0x443a0000 0x10000>; 324 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 325 clocks = <&clk IMX93_CLK_BUS_AON>, 326 <&clk IMX93_CLK_CAN1_GATE>; 327 clock-names = "ipg", "per"; 328 assigned-clocks = <&clk IMX93_CLK_CAN1>; 329 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 330 assigned-clock-rates = <40000000>; 331 fsl,clk-source = /bits/ 8 <0>; 332 fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; 333 status = "disabled"; 334 }; 335 336 sai1: sai@443b0000 { 337 compatible = "fsl,imx93-sai"; 338 reg = <0x443b0000 0x10000>; 339 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, 341 <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, 342 <&clk IMX93_CLK_DUMMY>; 343 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 344 dmas = <&edma1 22 0 FSL_EDMA_RX>, <&edma1 21 0 0>; 345 dma-names = "rx", "tx"; 346 #sound-dai-cells = <0>; 347 status = "disabled"; 348 }; 349 350 iomuxc: pinctrl@443c0000 { 351 compatible = "fsl,imx93-iomuxc"; 352 reg = <0x443c0000 0x10000>; 353 status = "okay"; 354 }; 355 356 bbnsm: bbnsm@44440000 { 357 compatible = "nxp,imx93-bbnsm", "syscon", "simple-mfd"; 358 reg = <0x44440000 0x10000>; 359 360 bbnsm_rtc: rtc { 361 compatible = "nxp,imx93-bbnsm-rtc"; 362 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 363 }; 364 365 bbnsm_pwrkey: pwrkey { 366 compatible = "nxp,imx93-bbnsm-pwrkey"; 367 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 368 linux,code = <KEY_POWER>; 369 }; 370 }; 371 372 clk: clock-controller@44450000 { 373 compatible = "fsl,imx93-ccm"; 374 reg = <0x44450000 0x10000>; 375 #clock-cells = <1>; 376 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; 377 clock-names = "osc_32k", "osc_24m", "clk_ext1"; 378 assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; 379 assigned-clock-rates = <393216000>; 380 status = "okay"; 381 }; 382 383 src: system-controller@44460000 { 384 compatible = "fsl,imx93-src", "syscon"; 385 reg = <0x44460000 0x10000>; 386 #address-cells = <1>; 387 #size-cells = <1>; 388 ranges; 389 390 mediamix: power-domain@44462400 { 391 compatible = "fsl,imx93-src-slice"; 392 reg = <0x44462400 0x400>, <0x44465800 0x400>; 393 #power-domain-cells = <0>; 394 clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, 395 <&clk IMX93_CLK_MEDIA_APB>; 396 }; 397 }; 398 399 clock-controller@44480000 { 400 compatible = "fsl,imx93-anatop"; 401 reg = <0x44480000 0x2000>; 402 #clock-cells = <1>; 403 }; 404 405 micfil: micfil@44520000 { 406 compatible = "fsl,imx93-micfil"; 407 reg = <0x44520000 0x10000>; 408 interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, 409 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, 410 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 411 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; 412 clocks = <&clk IMX93_CLK_PDM_IPG>, 413 <&clk IMX93_CLK_PDM_GATE>, 414 <&clk IMX93_CLK_AUDIO_PLL>; 415 clock-names = "ipg_clk", "ipg_clk_app", "pll8k"; 416 dmas = <&edma1 29 0 5>; 417 dma-names = "rx"; 418 #sound-dai-cells = <0>; 419 status = "disabled"; 420 }; 421 422 adc1: adc@44530000 { 423 compatible = "nxp,imx93-adc"; 424 reg = <0x44530000 0x10000>; 425 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 426 <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>, 427 <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 428 clocks = <&clk IMX93_CLK_ADC1_GATE>; 429 clock-names = "ipg"; 430 #io-channel-cells = <1>; 431 status = "disabled"; 432 }; 433 }; 434 435 aips2: bus@42000000 { 436 compatible = "fsl,aips-bus", "simple-bus"; 437 reg = <0x42000000 0x800000>; 438 #address-cells = <1>; 439 #size-cells = <1>; 440 ranges; 441 442 edma2: dma-controller@42000000 { 443 compatible = "fsl,imx93-edma4"; 444 reg = <0x42000000 0x210000>; 445 #dma-cells = <3>; 446 dma-channels = <64>; 447 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 448 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 449 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 450 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 451 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 452 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 453 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 454 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 455 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 456 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 457 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 458 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 459 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 460 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 461 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 462 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 463 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 464 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 465 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 466 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 467 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 468 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 469 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 470 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 471 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 472 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 473 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 474 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 475 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 476 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 477 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 478 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 482 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 483 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 484 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 485 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 486 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 487 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 488 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 489 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 490 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 491 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 492 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 493 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 496 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 497 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 498 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 499 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 500 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 501 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 502 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 503 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 504 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 505 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 506 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 507 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 508 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 509 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 510 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 511 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 512 clocks = <&clk IMX93_CLK_EDMA2_GATE>; 513 clock-names = "dma"; 514 }; 515 516 wakeupmix_gpr: syscon@42420000 { 517 compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; 518 reg = <0x42420000 0x1000>; 519 }; 520 521 wdog3: watchdog@42490000 { 522 compatible = "fsl,imx93-wdt"; 523 reg = <0x42490000 0x10000>; 524 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&clk IMX93_CLK_WDOG3_GATE>; 526 timeout-sec = <40>; 527 status = "disabled"; 528 }; 529 530 wdog4: watchdog@424a0000 { 531 compatible = "fsl,imx93-wdt"; 532 reg = <0x424a0000 0x10000>; 533 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 534 clocks = <&clk IMX93_CLK_WDOG4_GATE>; 535 timeout-sec = <40>; 536 status = "disabled"; 537 }; 538 539 wdog5: watchdog@424b0000 { 540 compatible = "fsl,imx93-wdt"; 541 reg = <0x424b0000 0x10000>; 542 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 543 clocks = <&clk IMX93_CLK_WDOG5_GATE>; 544 timeout-sec = <40>; 545 status = "disabled"; 546 }; 547 548 tpm3: pwm@424e0000 { 549 compatible = "fsl,imx7ulp-pwm"; 550 reg = <0x424e0000 0x1000>; 551 clocks = <&clk IMX93_CLK_TPM3_GATE>; 552 #pwm-cells = <3>; 553 status = "disabled"; 554 }; 555 556 tpm4: pwm@424f0000 { 557 compatible = "fsl,imx7ulp-pwm"; 558 reg = <0x424f0000 0x10000>; 559 clocks = <&clk IMX93_CLK_TPM4_GATE>; 560 #pwm-cells = <3>; 561 status = "disabled"; 562 }; 563 564 tpm5: pwm@42500000 { 565 compatible = "fsl,imx7ulp-pwm"; 566 reg = <0x42500000 0x10000>; 567 clocks = <&clk IMX93_CLK_TPM5_GATE>; 568 #pwm-cells = <3>; 569 status = "disabled"; 570 }; 571 572 tpm6: pwm@42510000 { 573 compatible = "fsl,imx7ulp-pwm"; 574 reg = <0x42510000 0x10000>; 575 clocks = <&clk IMX93_CLK_TPM6_GATE>; 576 #pwm-cells = <3>; 577 status = "disabled"; 578 }; 579 580 i3c2: i3c@42520000 { 581 compatible = "silvaco,i3c-master-v1"; 582 reg = <0x42520000 0x10000>; 583 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 584 #address-cells = <3>; 585 #size-cells = <0>; 586 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 587 <&clk IMX93_CLK_I3C2_GATE>, 588 <&clk IMX93_CLK_I3C2_SLOW>; 589 clock-names = "pclk", "fast_clk", "slow_clk"; 590 status = "disabled"; 591 }; 592 593 lpi2c3: i2c@42530000 { 594 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 595 reg = <0x42530000 0x10000>; 596 #address-cells = <1>; 597 #size-cells = <0>; 598 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 599 clocks = <&clk IMX93_CLK_LPI2C3_GATE>, 600 <&clk IMX93_CLK_BUS_WAKEUP>; 601 clock-names = "per", "ipg"; 602 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 603 dma-names = "tx", "rx"; 604 status = "disabled"; 605 }; 606 607 lpi2c4: i2c@42540000 { 608 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 609 reg = <0x42540000 0x10000>; 610 #address-cells = <1>; 611 #size-cells = <0>; 612 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; 613 clocks = <&clk IMX93_CLK_LPI2C4_GATE>, 614 <&clk IMX93_CLK_BUS_WAKEUP>; 615 clock-names = "per", "ipg"; 616 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 617 dma-names = "tx", "rx"; 618 status = "disabled"; 619 }; 620 621 lpspi3: spi@42550000 { 622 #address-cells = <1>; 623 #size-cells = <0>; 624 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 625 reg = <0x42550000 0x10000>; 626 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&clk IMX93_CLK_LPSPI3_GATE>, 628 <&clk IMX93_CLK_BUS_WAKEUP>; 629 clock-names = "per", "ipg"; 630 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 631 dma-names = "tx", "rx"; 632 status = "disabled"; 633 }; 634 635 lpspi4: spi@42560000 { 636 #address-cells = <1>; 637 #size-cells = <0>; 638 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 639 reg = <0x42560000 0x10000>; 640 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&clk IMX93_CLK_LPSPI4_GATE>, 642 <&clk IMX93_CLK_BUS_WAKEUP>; 643 clock-names = "per", "ipg"; 644 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 645 dma-names = "tx", "rx"; 646 status = "disabled"; 647 }; 648 649 lpuart3: serial@42570000 { 650 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 651 reg = <0x42570000 0x1000>; 652 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&clk IMX93_CLK_LPUART3_GATE>; 654 clock-names = "ipg"; 655 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 656 dma-names = "rx", "tx"; 657 status = "disabled"; 658 }; 659 660 lpuart4: serial@42580000 { 661 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 662 reg = <0x42580000 0x1000>; 663 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&clk IMX93_CLK_LPUART4_GATE>; 665 clock-names = "ipg"; 666 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 667 dma-names = "rx", "tx"; 668 status = "disabled"; 669 }; 670 671 lpuart5: serial@42590000 { 672 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 673 reg = <0x42590000 0x1000>; 674 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 675 clocks = <&clk IMX93_CLK_LPUART5_GATE>; 676 clock-names = "ipg"; 677 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 678 dma-names = "rx", "tx"; 679 status = "disabled"; 680 }; 681 682 lpuart6: serial@425a0000 { 683 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 684 reg = <0x425a0000 0x1000>; 685 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 686 clocks = <&clk IMX93_CLK_LPUART6_GATE>; 687 clock-names = "ipg"; 688 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 689 dma-names = "rx", "tx"; 690 status = "disabled"; 691 }; 692 693 flexcan2: can@425b0000 { 694 compatible = "fsl,imx93-flexcan"; 695 reg = <0x425b0000 0x10000>; 696 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 697 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 698 <&clk IMX93_CLK_CAN2_GATE>; 699 clock-names = "ipg", "per"; 700 assigned-clocks = <&clk IMX93_CLK_CAN2>; 701 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 702 assigned-clock-rates = <40000000>; 703 fsl,clk-source = /bits/ 8 <0>; 704 fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; 705 status = "disabled"; 706 }; 707 708 flexspi1: spi@425e0000 { 709 compatible = "nxp,imx93-fspi", "nxp,imx8mm-fspi"; 710 reg = <0x425e0000 0x10000>, <0x28000000 0x10000000>; 711 reg-names = "fspi_base", "fspi_mmap"; 712 #address-cells = <1>; 713 #size-cells = <0>; 714 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 715 clocks = <&clk IMX93_CLK_FLEXSPI1_GATE>, 716 <&clk IMX93_CLK_FLEXSPI1_GATE>; 717 clock-names = "fspi_en", "fspi"; 718 assigned-clocks = <&clk IMX93_CLK_FLEXSPI1>; 719 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 720 status = "disabled"; 721 }; 722 723 sai2: sai@42650000 { 724 compatible = "fsl,imx93-sai"; 725 reg = <0x42650000 0x10000>; 726 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 727 clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, 728 <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, 729 <&clk IMX93_CLK_DUMMY>; 730 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 731 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 732 dma-names = "rx", "tx"; 733 #sound-dai-cells = <0>; 734 status = "disabled"; 735 }; 736 737 sai3: sai@42660000 { 738 compatible = "fsl,imx93-sai"; 739 reg = <0x42660000 0x10000>; 740 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, 742 <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, 743 <&clk IMX93_CLK_DUMMY>; 744 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 745 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 746 dma-names = "rx", "tx"; 747 #sound-dai-cells = <0>; 748 status = "disabled"; 749 }; 750 751 xcvr: xcvr@42680000 { 752 compatible = "fsl,imx93-xcvr"; 753 reg = <0x42680000 0x800>, 754 <0x42680800 0x400>, 755 <0x42680c00 0x080>, 756 <0x42680e00 0x080>; 757 reg-names = "ram", "regs", "rxfifo", "txfifo"; 758 interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&clk IMX93_CLK_SPDIF_IPG>, 761 <&clk IMX93_CLK_SPDIF_GATE>, 762 <&clk IMX93_CLK_DUMMY>, 763 <&clk IMX93_CLK_AUD_XCVR_GATE>; 764 clock-names = "ipg", "phy", "spba", "pll_ipg"; 765 dmas = <&edma2 65 0 FSL_EDMA_RX>, <&edma2 66 0 0>; 766 dma-names = "rx", "tx"; 767 #sound-dai-cells = <0>; 768 status = "disabled"; 769 }; 770 771 lpuart7: serial@42690000 { 772 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 773 reg = <0x42690000 0x1000>; 774 interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; 775 clocks = <&clk IMX93_CLK_LPUART7_GATE>; 776 clock-names = "ipg"; 777 dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; 778 dma-names = "rx", "tx"; 779 status = "disabled"; 780 }; 781 782 lpuart8: serial@426a0000 { 783 compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; 784 reg = <0x426a0000 0x1000>; 785 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; 786 clocks = <&clk IMX93_CLK_LPUART8_GATE>; 787 clock-names = "ipg"; 788 dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; 789 dma-names = "rx", "tx"; 790 status = "disabled"; 791 }; 792 793 lpi2c5: i2c@426b0000 { 794 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 795 reg = <0x426b0000 0x10000>; 796 #address-cells = <1>; 797 #size-cells = <0>; 798 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; 799 clocks = <&clk IMX93_CLK_LPI2C5_GATE>, 800 <&clk IMX93_CLK_BUS_WAKEUP>; 801 clock-names = "per", "ipg"; 802 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 803 dma-names = "tx", "rx"; 804 status = "disabled"; 805 }; 806 807 lpi2c6: i2c@426c0000 { 808 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 809 reg = <0x426c0000 0x10000>; 810 #address-cells = <1>; 811 #size-cells = <0>; 812 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>; 813 clocks = <&clk IMX93_CLK_LPI2C6_GATE>, 814 <&clk IMX93_CLK_BUS_WAKEUP>; 815 clock-names = "per", "ipg"; 816 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 817 dma-names = "tx", "rx"; 818 status = "disabled"; 819 }; 820 821 lpi2c7: i2c@426d0000 { 822 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 823 reg = <0x426d0000 0x10000>; 824 #address-cells = <1>; 825 #size-cells = <0>; 826 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>; 827 clocks = <&clk IMX93_CLK_LPI2C7_GATE>, 828 <&clk IMX93_CLK_BUS_WAKEUP>; 829 clock-names = "per", "ipg"; 830 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 831 dma-names = "tx", "rx"; 832 status = "disabled"; 833 }; 834 835 lpi2c8: i2c@426e0000 { 836 compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; 837 reg = <0x426e0000 0x10000>; 838 #address-cells = <1>; 839 #size-cells = <0>; 840 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>; 841 clocks = <&clk IMX93_CLK_LPI2C8_GATE>, 842 <&clk IMX93_CLK_BUS_WAKEUP>; 843 clock-names = "per", "ipg"; 844 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 845 dma-names = "tx", "rx"; 846 status = "disabled"; 847 }; 848 849 lpspi5: spi@426f0000 { 850 #address-cells = <1>; 851 #size-cells = <0>; 852 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 853 reg = <0x426f0000 0x10000>; 854 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 855 clocks = <&clk IMX93_CLK_LPSPI5_GATE>, 856 <&clk IMX93_CLK_BUS_WAKEUP>; 857 clock-names = "per", "ipg"; 858 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 859 dma-names = "tx", "rx"; 860 status = "disabled"; 861 }; 862 863 lpspi6: spi@42700000 { 864 #address-cells = <1>; 865 #size-cells = <0>; 866 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 867 reg = <0x42700000 0x10000>; 868 interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&clk IMX93_CLK_LPSPI6_GATE>, 870 <&clk IMX93_CLK_BUS_WAKEUP>; 871 clock-names = "per", "ipg"; 872 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 873 dma-names = "tx", "rx"; 874 status = "disabled"; 875 }; 876 877 lpspi7: spi@42710000 { 878 #address-cells = <1>; 879 #size-cells = <0>; 880 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 881 reg = <0x42710000 0x10000>; 882 interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; 883 clocks = <&clk IMX93_CLK_LPSPI7_GATE>, 884 <&clk IMX93_CLK_BUS_WAKEUP>; 885 clock-names = "per", "ipg"; 886 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 887 dma-names = "tx", "rx"; 888 status = "disabled"; 889 }; 890 891 lpspi8: spi@42720000 { 892 #address-cells = <1>; 893 #size-cells = <0>; 894 compatible = "fsl,imx93-spi", "fsl,imx7ulp-spi"; 895 reg = <0x42720000 0x10000>; 896 interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>; 897 clocks = <&clk IMX93_CLK_LPSPI8_GATE>, 898 <&clk IMX93_CLK_BUS_WAKEUP>; 899 clock-names = "per", "ipg"; 900 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 901 dma-names = "tx", "rx"; 902 status = "disabled"; 903 }; 904 905 }; 906 907 aips3: bus@42800000 { 908 compatible = "fsl,aips-bus", "simple-bus"; 909 reg = <0x42800000 0x800000>; 910 #address-cells = <1>; 911 #size-cells = <1>; 912 ranges; 913 914 usdhc1: mmc@42850000 { 915 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 916 reg = <0x42850000 0x10000>; 917 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 918 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 919 <&clk IMX93_CLK_WAKEUP_AXI>, 920 <&clk IMX93_CLK_USDHC1_GATE>; 921 clock-names = "ipg", "ahb", "per"; 922 assigned-clocks = <&clk IMX93_CLK_USDHC1>; 923 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 924 assigned-clock-rates = <400000000>; 925 bus-width = <8>; 926 fsl,tuning-start-tap = <1>; 927 fsl,tuning-step = <2>; 928 status = "disabled"; 929 }; 930 931 usdhc2: mmc@42860000 { 932 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 933 reg = <0x42860000 0x10000>; 934 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 936 <&clk IMX93_CLK_WAKEUP_AXI>, 937 <&clk IMX93_CLK_USDHC2_GATE>; 938 clock-names = "ipg", "ahb", "per"; 939 assigned-clocks = <&clk IMX93_CLK_USDHC2>; 940 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 941 assigned-clock-rates = <400000000>; 942 bus-width = <4>; 943 fsl,tuning-start-tap = <1>; 944 fsl,tuning-step = <2>; 945 status = "disabled"; 946 }; 947 948 fec: ethernet@42890000 { 949 compatible = "fsl,imx93-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 950 reg = <0x42890000 0x10000>; 951 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, 952 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, 953 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 954 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&clk IMX93_CLK_ENET1_GATE>, 956 <&clk IMX93_CLK_ENET1_GATE>, 957 <&clk IMX93_CLK_ENET_TIMER1>, 958 <&clk IMX93_CLK_ENET_REF>, 959 <&clk IMX93_CLK_ENET_REF_PHY>; 960 clock-names = "ipg", "ahb", "ptp", 961 "enet_clk_ref", "enet_out"; 962 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER1>, 963 <&clk IMX93_CLK_ENET_REF>, 964 <&clk IMX93_CLK_ENET_REF_PHY>; 965 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 966 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>, 967 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 968 assigned-clock-rates = <100000000>, <250000000>, <50000000>; 969 fsl,num-tx-queues = <3>; 970 fsl,num-rx-queues = <3>; 971 fsl,stop-mode = <&wakeupmix_gpr 0x0c 1>; 972 nvmem-cells = <ð_mac1>; 973 nvmem-cell-names = "mac-address"; 974 status = "disabled"; 975 }; 976 977 eqos: ethernet@428a0000 { 978 compatible = "nxp,imx93-dwmac-eqos", "snps,dwmac-5.10a"; 979 reg = <0x428a0000 0x10000>; 980 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 981 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 982 interrupt-names = "macirq", "eth_wake_irq"; 983 clocks = <&clk IMX93_CLK_ENET_QOS_GATE>, 984 <&clk IMX93_CLK_ENET_QOS_GATE>, 985 <&clk IMX93_CLK_ENET_TIMER2>, 986 <&clk IMX93_CLK_ENET>, 987 <&clk IMX93_CLK_ENET_QOS_GATE>; 988 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx", "mem"; 989 assigned-clocks = <&clk IMX93_CLK_ENET_TIMER2>, 990 <&clk IMX93_CLK_ENET>; 991 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 992 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 993 assigned-clock-rates = <100000000>, <250000000>; 994 intf_mode = <&wakeupmix_gpr 0x28>; 995 snps,clk-csr = <6>; 996 nvmem-cells = <ð_mac2>; 997 nvmem-cell-names = "mac-address"; 998 status = "disabled"; 999 }; 1000 1001 usdhc3: mmc@428b0000 { 1002 compatible = "fsl,imx93-usdhc", "fsl,imx8mm-usdhc"; 1003 reg = <0x428b0000 0x10000>; 1004 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 1006 <&clk IMX93_CLK_WAKEUP_AXI>, 1007 <&clk IMX93_CLK_USDHC3_GATE>; 1008 clock-names = "ipg", "ahb", "per"; 1009 assigned-clocks = <&clk IMX93_CLK_USDHC3>; 1010 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1>; 1011 assigned-clock-rates = <400000000>; 1012 bus-width = <4>; 1013 fsl,tuning-start-tap = <1>; 1014 fsl,tuning-step = <2>; 1015 status = "disabled"; 1016 }; 1017 }; 1018 1019 gpio2: gpio@43810000 { 1020 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1021 reg = <0x43810000 0x1000>; 1022 gpio-controller; 1023 #gpio-cells = <2>; 1024 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 1026 interrupt-controller; 1027 #interrupt-cells = <2>; 1028 clocks = <&clk IMX93_CLK_GPIO2_GATE>, 1029 <&clk IMX93_CLK_GPIO2_GATE>; 1030 clock-names = "gpio", "port"; 1031 gpio-ranges = <&iomuxc 0 4 30>; 1032 ngpios = <30>; 1033 }; 1034 1035 gpio3: gpio@43820000 { 1036 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1037 reg = <0x43820000 0x1000>; 1038 gpio-controller; 1039 #gpio-cells = <2>; 1040 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1042 interrupt-controller; 1043 #interrupt-cells = <2>; 1044 clocks = <&clk IMX93_CLK_GPIO3_GATE>, 1045 <&clk IMX93_CLK_GPIO3_GATE>; 1046 clock-names = "gpio", "port"; 1047 gpio-ranges = <&iomuxc 0 84 8>, <&iomuxc 8 66 18>, 1048 <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; 1049 ngpios = <32>; 1050 }; 1051 1052 gpio4: gpio@43830000 { 1053 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1054 reg = <0x43830000 0x1000>; 1055 gpio-controller; 1056 #gpio-cells = <2>; 1057 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; 1059 interrupt-controller; 1060 #interrupt-cells = <2>; 1061 clocks = <&clk IMX93_CLK_GPIO4_GATE>, 1062 <&clk IMX93_CLK_GPIO4_GATE>; 1063 clock-names = "gpio", "port"; 1064 gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; 1065 ngpios = <30>; 1066 }; 1067 1068 gpio1: gpio@47400000 { 1069 compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; 1070 reg = <0x47400000 0x1000>; 1071 gpio-controller; 1072 #gpio-cells = <2>; 1073 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1075 interrupt-controller; 1076 #interrupt-cells = <2>; 1077 clocks = <&clk IMX93_CLK_GPIO1_GATE>, 1078 <&clk IMX93_CLK_GPIO1_GATE>; 1079 clock-names = "gpio", "port"; 1080 gpio-ranges = <&iomuxc 0 92 16>; 1081 ngpios = <16>; 1082 }; 1083 1084 ocotp: efuse@47510000 { 1085 compatible = "fsl,imx93-ocotp", "syscon"; 1086 reg = <0x47510000 0x10000>; 1087 #address-cells = <1>; 1088 #size-cells = <1>; 1089 1090 eth_mac1: mac-address@4ec { 1091 reg = <0x4ec 0x6>; 1092 }; 1093 1094 eth_mac2: mac-address@4f2 { 1095 reg = <0x4f2 0x6>; 1096 }; 1097 1098 }; 1099 1100 s4muap: mailbox@47520000 { 1101 compatible = "fsl,imx93-mu-s4"; 1102 reg = <0x47520000 0x10000>; 1103 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 1105 interrupt-names = "tx", "rx"; 1106 #mbox-cells = <2>; 1107 }; 1108 1109 media_blk_ctrl: system-controller@4ac10000 { 1110 compatible = "fsl,imx93-media-blk-ctrl", "syscon"; 1111 reg = <0x4ac10000 0x10000>; 1112 power-domains = <&mediamix>; 1113 clocks = <&clk IMX93_CLK_MEDIA_APB>, 1114 <&clk IMX93_CLK_MEDIA_AXI>, 1115 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 1116 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 1117 <&clk IMX93_CLK_CAM_PIX>, 1118 <&clk IMX93_CLK_PXP_GATE>, 1119 <&clk IMX93_CLK_LCDIF_GATE>, 1120 <&clk IMX93_CLK_ISI_GATE>, 1121 <&clk IMX93_CLK_MIPI_CSI_GATE>, 1122 <&clk IMX93_CLK_MIPI_DSI_GATE>; 1123 clock-names = "apb", "axi", "nic", "disp", "cam", 1124 "pxp", "lcdif", "isi", "csi", "dsi"; 1125 #power-domain-cells = <1>; 1126 status = "disabled"; 1127 }; 1128 1129 usbotg1: usb@4c100000 { 1130 compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1131 reg = <0x4c100000 0x200>; 1132 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, 1134 <&clk IMX93_CLK_HSIO_32K_GATE>; 1135 clock-names = "usb_ctrl_root", "usb_wakeup"; 1136 assigned-clocks = <&clk IMX93_CLK_HSIO>; 1137 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1138 assigned-clock-rates = <133000000>; 1139 phys = <&usbphynop1>; 1140 fsl,usbmisc = <&usbmisc1 0>; 1141 status = "disabled"; 1142 }; 1143 1144 usbmisc1: usbmisc@4c100200 { 1145 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1146 "fsl,imx6q-usbmisc"; 1147 reg = <0x4c100200 0x200>; 1148 #index-cells = <1>; 1149 }; 1150 1151 usbotg2: usb@4c200000 { 1152 compatible = "fsl,imx93-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1153 reg = <0x4c200000 0x200>; 1154 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; 1155 clocks = <&clk IMX93_CLK_USB_CONTROLLER_GATE>, 1156 <&clk IMX93_CLK_HSIO_32K_GATE>; 1157 clock-names = "usb_ctrl_root", "usb_wakeup"; 1158 assigned-clocks = <&clk IMX93_CLK_HSIO>; 1159 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 1160 assigned-clock-rates = <133000000>; 1161 phys = <&usbphynop2>; 1162 fsl,usbmisc = <&usbmisc2 0>; 1163 status = "disabled"; 1164 }; 1165 1166 usbmisc2: usbmisc@4c200200 { 1167 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc", 1168 "fsl,imx6q-usbmisc"; 1169 reg = <0x4c200200 0x200>; 1170 #index-cells = <1>; 1171 }; 1172 1173 memory-controller@4e300000 { 1174 compatible = "nxp,imx9-memory-controller"; 1175 reg = <0x4e300000 0x800>, <0x4e301000 0x1000>; 1176 reg-names = "ctrl", "inject"; 1177 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1178 little-endian; 1179 }; 1180 1181 ddr_pmu: ddr-pmu@4e300dc0 { 1182 compatible = "fsl,imx93-ddr-pmu"; 1183 reg = <0x4e300dc0 0x200>; 1184 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1185 }; 1186 }; 1187};
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