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imx91-phycore-som.dtsi

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linux-6.19.14/arch/arm64/boot/dts/freescale/imx91-phycore-som.dtsi DEVICETREE 
  1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  2/*
  3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH
  4 * Author: Christoph Stoidner <c.stoidner@phytec.de>
  5 *
  6 * Product homepage:
  7 * https://www.phytec.eu/en/produkte/system-on-modules/phycore-imx-91-93/
  8 */
  9
 10#include <dt-bindings/leds/common.h>
 11
 12#include "imx91.dtsi"
 13
 14/ {
 15	model = "PHYTEC phyCORE-i.MX91";
 16	compatible = "phytec,imx91-phycore-som", "fsl,imx91";
 17
 18	aliases {
 19		ethernet0 = &fec;
 20	};
 21
 22	reserved-memory {
 23		ranges;
 24		#address-cells = <2>;
 25		#size-cells = <2>;
 26
 27		linux,cma {
 28			compatible = "shared-dma-pool";
 29			reusable;
 30			alloc-ranges = <0 0x80000000 0 0x40000000>;
 31			size = <0 0x10000000>;
 32			linux,cma-default;
 33		};
 34	};
 35
 36	leds {
 37		compatible = "gpio-leds";
 38		pinctrl-names = "default";
 39		pinctrl-0 = <&pinctrl_leds>;
 40
 41		led-0 {
 42			color = <LED_COLOR_ID_GREEN>;
 43			function = LED_FUNCTION_HEARTBEAT;
 44			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
 45			linux,default-trigger = "heartbeat";
 46		};
 47	};
 48
 49	reg_vdda_1v8: regulator-vdda-1v8 {
 50		compatible = "regulator-fixed";
 51		regulator-name = "VDDA_1V8";
 52		regulator-max-microvolt = <1800000>;
 53		regulator-min-microvolt = <1800000>;
 54		vin-supply = <&buck5>;
 55	};
 56};
 57
 58/* ADC */
 59&adc1 {
 60	vref-supply = <&reg_vdda_1v8>;
 61};
 62
 63/* Ethernet */
 64&fec {
 65	pinctrl-names = "default";
 66	pinctrl-0 = <&pinctrl_fec>;
 67	phy-mode = "rmii";
 68	phy-handle = <&ethphy1>;
 69
 70	assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>,
 71			  <&clk IMX91_CLK_ENET2_REGULAR>;
 72	assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>,
 73				 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>;
 74	assigned-clock-rates = <100000000>, <50000000>;
 75	status = "okay";
 76
 77	mdio: mdio {
 78		clock-frequency = <5000000>;
 79		#address-cells = <1>;
 80		#size-cells = <0>;
 81
 82		ethphy1: ethernet-phy@1 {
 83			compatible = "ethernet-phy-ieee802.3-c22";
 84			reg = <1>;
 85			reset-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
 86			reset-assert-us = <30>;
 87		};
 88	};
 89};
 90
 91/* I2C3 */
 92&lpi2c3 {
 93	clock-frequency = <400000>;
 94	pinctrl-names = "default", "gpio";
 95	pinctrl-0 = <&pinctrl_lpi2c3>;
 96	pinctrl-1 = <&pinctrl_lpi2c3_gpio>;
 97	scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 98	sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 99	status = "okay";
100
101	pmic@25 {
102		compatible = "nxp,pca9451a";
103		reg = <0x25>;
104		pinctrl-names = "default";
105		pinctrl-0 = <&pinctrl_pmic>;
106		interrupt-parent = <&gpio4>;
107		interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
108
109		regulators {
110			buck1: BUCK1 {
111				regulator-name = "VDD_SOC";
112				regulator-max-microvolt = <950000>;
113				regulator-min-microvolt = <610000>;
114				regulator-boot-on;
115				regulator-always-on;
116				regulator-ramp-delay = <3125>;
117			};
118
119			buck2: BUCK2 {
120				regulator-name = "VDDQ_0V6";
121				regulator-max-microvolt = <600000>;
122				regulator-min-microvolt = <600000>;
123				regulator-boot-on;
124				regulator-always-on;
125			};
126
127			buck4: BUCK4 {
128				regulator-name = "VDD_3V3_BUCK";
129				regulator-max-microvolt = <3300000>;
130				regulator-min-microvolt = <3300000>;
131				regulator-boot-on;
132				regulator-always-on;
133			};
134
135			buck5: BUCK5 {
136				regulator-name = "VDD_1V8";
137				regulator-max-microvolt = <1800000>;
138				regulator-min-microvolt = <1800000>;
139				regulator-boot-on;
140				regulator-always-on;
141			};
142
143			buck6: BUCK6 {
144				regulator-name = "VDD_1V1";
145				regulator-max-microvolt = <1100000>;
146				regulator-min-microvolt = <1100000>;
147				regulator-boot-on;
148				regulator-always-on;
149			};
150
151			ldo1: LDO1 {
152				regulator-name = "PMIC_SNVS_1V8";
153				regulator-max-microvolt = <1800000>;
154				regulator-min-microvolt = <1800000>;
155				regulator-boot-on;
156				regulator-always-on;
157			};
158
159			ldo4: LDO4 {
160				regulator-name = "VDD_0V8";
161				regulator-max-microvolt = <800000>;
162				regulator-min-microvolt = <800000>;
163				regulator-boot-on;
164				regulator-always-on;
165			};
166
167			ldo5: LDO5 {
168				regulator-name = "NVCC_SD2";
169				regulator-max-microvolt = <3300000>;
170				regulator-min-microvolt = <1800000>;
171				regulator-boot-on;
172				regulator-always-on;
173			};
174		};
175	};
176
177	/* EEPROM */
178	eeprom@50 {
179		compatible = "atmel,24c32";
180		reg = <0x50>;
181		pagesize = <32>;
182		vcc-supply = <&buck4>;
183	};
184};
185
186/* eMMC */
187&usdhc1 {
188	pinctrl-names = "default", "state_100mhz", "state_200mhz";
189	pinctrl-0 = <&pinctrl_usdhc1>;
190	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
191	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
192	bus-width = <8>;
193	non-removable;
194	no-1-8-v;
195	status = "okay";
196};
197
198/* Watchdog */
199&wdog3 {
200	pinctrl-names = "default";
201	pinctrl-0 = <&pinctrl_wdog>;
202	fsl,ext-reset-output;
203	status = "okay";
204};
205
206&iomuxc {
207	pinctrl_fec: fecgrp {
208		fsl,pins = <
209			MX91_PAD_ENET2_MDC__ENET2_MDC			0x50e
210			MX91_PAD_ENET2_MDIO__ENET2_MDIO			0x502
211			/* the three pins below are connected to PHYs straps,
212			 * that is what the pull-up/down setting is for.
213			 */
214			MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0		0x37e
215			MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1		0x37e
216			MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL	0x57e
217			MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0		0x50e
218			MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1		0x50e
219			MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL	0x50e
220			MX91_PAD_ENET2_TD2__ENET2_TX_CLK2		0x4000050e
221			MX91_PAD_ENET2_RXC__GPIO4_IO23			0x51e
222		>;
223	};
224
225	pinctrl_leds: ledsgrp {
226		fsl,pins = <
227			MX91_PAD_I2C1_SDA__GPIO1_IO1		0x11e
228		>;
229	};
230
231	pinctrl_lpi2c3: lpi2c3grp {
232		fsl,pins = <
233			MX91_PAD_GPIO_IO28__LPI2C3_SDA		0x40000b9e
234			MX91_PAD_GPIO_IO29__LPI2C3_SCL		0x40000b9e
235		>;
236	};
237
238	pinctrl_lpi2c3_gpio: lpi2c3gpiogrp {
239		fsl,pins = <
240			MX91_PAD_GPIO_IO28__GPIO2_IO28		0x31e
241			MX91_PAD_GPIO_IO29__GPIO2_IO29		0x31e
242		>;
243	};
244
245	pinctrl_pmic: pmicgrp {
246		fsl,pins = <
247			MX91_PAD_ENET2_RD3__GPIO4_IO27		0x31e
248		>;
249	};
250
251	pinctrl_usdhc1: usdhc1grp {
252		fsl,pins = <
253			MX91_PAD_SD1_CLK__USDHC1_CLK		0x179e
254			MX91_PAD_SD1_CMD__USDHC1_CMD		0x1386
255			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
256			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x1386
257			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x138e
258			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x1386
259			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x1386
260			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x1386
261			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x1386
262			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x1386
263			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
264		>;
265	};
266
267	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
268		fsl,pins = <
269			MX91_PAD_SD1_CLK__USDHC1_CLK		0x17be
270			MX91_PAD_SD1_CMD__USDHC1_CMD		0x139e
271			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x138e
272			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x139e
273			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x13be
274			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x139e
275			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x139e
276			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x139e
277			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x139e
278			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x139e
279			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
280		>;
281	};
282
283	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
284		fsl,pins = <
285			MX91_PAD_SD1_CLK__USDHC1_CLK		0x17be
286			MX91_PAD_SD1_CMD__USDHC1_CMD		0x139e
287			MX91_PAD_SD1_DATA0__USDHC1_DATA0	0x139e
288			MX91_PAD_SD1_DATA1__USDHC1_DATA1	0x13be
289			MX91_PAD_SD1_DATA2__USDHC1_DATA2	0x13be
290			MX91_PAD_SD1_DATA3__USDHC1_DATA3	0x13be
291			MX91_PAD_SD1_DATA4__USDHC1_DATA4	0x13be
292			MX91_PAD_SD1_DATA5__USDHC1_DATA5	0x13be
293			MX91_PAD_SD1_DATA6__USDHC1_DATA6	0x13be
294			MX91_PAD_SD1_DATA7__USDHC1_DATA7	0x13be
295			MX91_PAD_SD1_STROBE__USDHC1_STROBE	0x179e
296		>;
297	};
298
299	pinctrl_wdog: wdoggrp {
300		fsl,pins = <
301			MX91_PAD_WDOG_ANY__WDOG1_WDOG_ANY	0x31e
302		>;
303	};
304};
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