FILE
imx8mq.dtsi
File preview with syntax highlighting.
linux-6.19.14/arch/arm64/boot/dts/freescale/imx8mq.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2017 NXP 4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de> 5 */ 6 7#include <dt-bindings/clock/imx8mq-clock.h> 8#include <dt-bindings/power/imx8mq-power.h> 9#include <dt-bindings/reset/imx8mq-reset.h> 10#include <dt-bindings/gpio/gpio.h> 11#include "dt-bindings/input/input.h" 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/thermal/thermal.h> 14#include <dt-bindings/interconnect/imx8mq.h> 15#include "imx8mq-pinfunc.h" 16 17/ { 18 interrupt-parent = <&gpc>; 19 20 #address-cells = <2>; 21 #size-cells = <2>; 22 23 aliases { 24 ethernet0 = &fec1; 25 gpio0 = &gpio1; 26 gpio1 = &gpio2; 27 gpio2 = &gpio3; 28 gpio3 = &gpio4; 29 gpio4 = &gpio5; 30 i2c0 = &i2c1; 31 i2c1 = &i2c2; 32 i2c2 = &i2c3; 33 i2c3 = &i2c4; 34 mmc0 = &usdhc1; 35 mmc1 = &usdhc2; 36 serial0 = &uart1; 37 serial1 = &uart2; 38 serial2 = &uart3; 39 serial3 = &uart4; 40 spi0 = &ecspi1; 41 spi1 = &ecspi2; 42 spi2 = &ecspi3; 43 }; 44 45 ckil: clock-ckil { 46 compatible = "fixed-clock"; 47 #clock-cells = <0>; 48 clock-frequency = <32768>; 49 clock-output-names = "ckil"; 50 }; 51 52 osc_25m: clock-osc-25m { 53 compatible = "fixed-clock"; 54 #clock-cells = <0>; 55 clock-frequency = <25000000>; 56 clock-output-names = "osc_25m"; 57 }; 58 59 osc_27m: clock-osc-27m { 60 compatible = "fixed-clock"; 61 #clock-cells = <0>; 62 clock-frequency = <27000000>; 63 clock-output-names = "osc_27m"; 64 }; 65 66 hdmi_phy_27m: clock-hdmi-phy-27m { 67 compatible = "fixed-clock"; 68 #clock-cells = <0>; 69 clock-frequency = <27000000>; 70 clock-output-names = "hdmi_phy_27m"; 71 }; 72 73 clk_ext1: clock-ext1 { 74 compatible = "fixed-clock"; 75 #clock-cells = <0>; 76 clock-frequency = <133000000>; 77 clock-output-names = "clk_ext1"; 78 }; 79 80 clk_ext2: clock-ext2 { 81 compatible = "fixed-clock"; 82 #clock-cells = <0>; 83 clock-frequency = <133000000>; 84 clock-output-names = "clk_ext2"; 85 }; 86 87 clk_ext3: clock-ext3 { 88 compatible = "fixed-clock"; 89 #clock-cells = <0>; 90 clock-frequency = <133000000>; 91 clock-output-names = "clk_ext3"; 92 }; 93 94 clk_ext4: clock-ext4 { 95 compatible = "fixed-clock"; 96 #clock-cells = <0>; 97 clock-frequency = <133000000>; 98 clock-output-names = "clk_ext4"; 99 }; 100 101 cpus { 102 #address-cells = <1>; 103 #size-cells = <0>; 104 105 A53_0: cpu@0 { 106 device_type = "cpu"; 107 compatible = "arm,cortex-a53"; 108 reg = <0x0>; 109 clocks = <&clk IMX8MQ_CLK_ARM>; 110 enable-method = "psci"; 111 i-cache-size = <0x8000>; 112 i-cache-line-size = <64>; 113 i-cache-sets = <256>; 114 d-cache-size = <0x8000>; 115 d-cache-line-size = <64>; 116 d-cache-sets = <128>; 117 next-level-cache = <&A53_L2>; 118 operating-points-v2 = <&a53_opp_table>; 119 #cooling-cells = <2>; 120 nvmem-cells = <&cpu_speed_grade>; 121 nvmem-cell-names = "speed_grade"; 122 }; 123 124 A53_1: cpu@1 { 125 device_type = "cpu"; 126 compatible = "arm,cortex-a53"; 127 reg = <0x1>; 128 clocks = <&clk IMX8MQ_CLK_ARM>; 129 enable-method = "psci"; 130 i-cache-size = <0x8000>; 131 i-cache-line-size = <64>; 132 i-cache-sets = <256>; 133 d-cache-size = <0x8000>; 134 d-cache-line-size = <64>; 135 d-cache-sets = <128>; 136 next-level-cache = <&A53_L2>; 137 operating-points-v2 = <&a53_opp_table>; 138 #cooling-cells = <2>; 139 }; 140 141 A53_2: cpu@2 { 142 device_type = "cpu"; 143 compatible = "arm,cortex-a53"; 144 reg = <0x2>; 145 clocks = <&clk IMX8MQ_CLK_ARM>; 146 enable-method = "psci"; 147 i-cache-size = <0x8000>; 148 i-cache-line-size = <64>; 149 i-cache-sets = <256>; 150 d-cache-size = <0x8000>; 151 d-cache-line-size = <64>; 152 d-cache-sets = <128>; 153 next-level-cache = <&A53_L2>; 154 operating-points-v2 = <&a53_opp_table>; 155 #cooling-cells = <2>; 156 }; 157 158 A53_3: cpu@3 { 159 device_type = "cpu"; 160 compatible = "arm,cortex-a53"; 161 reg = <0x3>; 162 clocks = <&clk IMX8MQ_CLK_ARM>; 163 enable-method = "psci"; 164 i-cache-size = <0x8000>; 165 i-cache-line-size = <64>; 166 i-cache-sets = <256>; 167 d-cache-size = <0x8000>; 168 d-cache-line-size = <64>; 169 d-cache-sets = <128>; 170 next-level-cache = <&A53_L2>; 171 operating-points-v2 = <&a53_opp_table>; 172 #cooling-cells = <2>; 173 }; 174 175 A53_L2: l2-cache0 { 176 compatible = "cache"; 177 cache-level = <2>; 178 cache-unified; 179 cache-size = <0x100000>; 180 cache-line-size = <64>; 181 cache-sets = <1024>; 182 }; 183 }; 184 185 a53_opp_table: opp-table { 186 compatible = "operating-points-v2"; 187 opp-shared; 188 189 opp-800000000 { 190 opp-hz = /bits/ 64 <800000000>; 191 opp-microvolt = <900000>; 192 /* Industrial only */ 193 opp-supported-hw = <0xf>, <0x4>; 194 clock-latency-ns = <150000>; 195 opp-suspend; 196 }; 197 198 opp-1000000000 { 199 opp-hz = /bits/ 64 <1000000000>; 200 opp-microvolt = <900000>; 201 /* Consumer only */ 202 opp-supported-hw = <0xe>, <0x3>; 203 clock-latency-ns = <150000>; 204 opp-suspend; 205 }; 206 207 opp-1300000000 { 208 opp-hz = /bits/ 64 <1300000000>; 209 opp-microvolt = <1000000>; 210 opp-supported-hw = <0xc>, <0x4>; 211 clock-latency-ns = <150000>; 212 opp-suspend; 213 }; 214 215 opp-1500000000 { 216 opp-hz = /bits/ 64 <1500000000>; 217 opp-microvolt = <1000000>; 218 opp-supported-hw = <0x8>, <0x3>; 219 clock-latency-ns = <150000>; 220 opp-suspend; 221 }; 222 }; 223 224 funnel { 225 /* 226 * non-configurable funnel don't show up on the AMBA 227 * bus. As such no need to add "arm,primecell". 228 */ 229 compatible = "arm,coresight-static-funnel"; 230 231 in-ports { 232 #address-cells = <1>; 233 #size-cells = <0>; 234 235 port@0 { 236 reg = <0>; 237 238 ca_funnel_in_port0: endpoint { 239 remote-endpoint = <&etm0_out_port>; 240 }; 241 }; 242 243 port@1 { 244 reg = <1>; 245 246 ca_funnel_in_port1: endpoint { 247 remote-endpoint = <&etm1_out_port>; 248 }; 249 }; 250 251 port@2 { 252 reg = <2>; 253 254 ca_funnel_in_port2: endpoint { 255 remote-endpoint = <&etm2_out_port>; 256 }; 257 }; 258 259 port@3 { 260 reg = <3>; 261 262 ca_funnel_in_port3: endpoint { 263 remote-endpoint = <&etm3_out_port>; 264 }; 265 }; 266 }; 267 268 out-ports { 269 port { 270 ca_funnel_out_port0: endpoint { 271 remote-endpoint = <&hugo_funnel_in_port0>; 272 }; 273 }; 274 }; 275 }; 276 277 pmu { 278 compatible = "arm,cortex-a53-pmu"; 279 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 280 interrupt-parent = <&gic>; 281 }; 282 283 psci { 284 compatible = "arm,psci-1.0"; 285 method = "smc"; 286 }; 287 288 thermal-zones { 289 cpu_thermal: cpu-thermal { 290 polling-delay-passive = <250>; 291 polling-delay = <2000>; 292 thermal-sensors = <&tmu 0>; 293 294 trips { 295 cpu_alert: cpu-alert { 296 temperature = <80000>; 297 hysteresis = <2000>; 298 type = "passive"; 299 }; 300 301 cpu-crit { 302 temperature = <90000>; 303 hysteresis = <2000>; 304 type = "critical"; 305 }; 306 }; 307 308 cooling-maps { 309 map0 { 310 trip = <&cpu_alert>; 311 cooling-device = 312 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 313 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 314 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 315 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 316 }; 317 }; 318 }; 319 320 gpu-thermal { 321 polling-delay-passive = <250>; 322 polling-delay = <2000>; 323 thermal-sensors = <&tmu 1>; 324 325 trips { 326 gpu_alert: gpu-alert { 327 temperature = <80000>; 328 hysteresis = <2000>; 329 type = "passive"; 330 }; 331 332 gpu-crit { 333 temperature = <90000>; 334 hysteresis = <2000>; 335 type = "critical"; 336 }; 337 }; 338 339 cooling-maps { 340 map0 { 341 trip = <&gpu_alert>; 342 cooling-device = 343 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 344 }; 345 }; 346 }; 347 348 vpu-thermal { 349 polling-delay-passive = <250>; 350 polling-delay = <2000>; 351 thermal-sensors = <&tmu 2>; 352 353 trips { 354 vpu-crit { 355 temperature = <90000>; 356 hysteresis = <2000>; 357 type = "critical"; 358 }; 359 }; 360 }; 361 }; 362 363 timer { 364 compatible = "arm,armv8-timer"; 365 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */ 366 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */ 367 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual */ 368 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor */ 369 interrupt-parent = <&gic>; 370 arm,no-tick-in-suspend; 371 }; 372 373 soc: soc@0 { 374 compatible = "fsl,imx8mq-soc", "simple-bus"; 375 #address-cells = <1>; 376 #size-cells = <1>; 377 ranges = <0x0 0x0 0x0 0x3e000000>; 378 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>; 379 nvmem-cells = <&imx8mq_uid>; 380 nvmem-cell-names = "soc_unique_id"; 381 382 etm0: etm@28440000 { 383 compatible = "arm,coresight-etm4x", "arm,primecell"; 384 reg = <0x28440000 0x1000>; 385 cpu = <&A53_0>; 386 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 387 clock-names = "apb_pclk"; 388 389 out-ports { 390 port { 391 etm0_out_port: endpoint { 392 remote-endpoint = <&ca_funnel_in_port0>; 393 }; 394 }; 395 }; 396 }; 397 398 etm1: etm@28540000 { 399 compatible = "arm,coresight-etm4x", "arm,primecell"; 400 reg = <0x28540000 0x1000>; 401 cpu = <&A53_1>; 402 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 403 clock-names = "apb_pclk"; 404 405 out-ports { 406 port { 407 etm1_out_port: endpoint { 408 remote-endpoint = <&ca_funnel_in_port1>; 409 }; 410 }; 411 }; 412 }; 413 414 etm2: etm@28640000 { 415 compatible = "arm,coresight-etm4x", "arm,primecell"; 416 reg = <0x28640000 0x1000>; 417 cpu = <&A53_2>; 418 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 419 clock-names = "apb_pclk"; 420 421 out-ports { 422 port { 423 etm2_out_port: endpoint { 424 remote-endpoint = <&ca_funnel_in_port2>; 425 }; 426 }; 427 }; 428 }; 429 430 etm3: etm@28740000 { 431 compatible = "arm,coresight-etm4x", "arm,primecell"; 432 reg = <0x28740000 0x1000>; 433 cpu = <&A53_3>; 434 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 435 clock-names = "apb_pclk"; 436 437 out-ports { 438 port { 439 etm3_out_port: endpoint { 440 remote-endpoint = <&ca_funnel_in_port3>; 441 }; 442 }; 443 }; 444 }; 445 446 funnel@28c03000 { 447 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 448 reg = <0x28c03000 0x1000>; 449 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 450 clock-names = "apb_pclk"; 451 452 in-ports { 453 #address-cells = <1>; 454 #size-cells = <0>; 455 456 port@0 { 457 reg = <0>; 458 459 hugo_funnel_in_port0: endpoint { 460 remote-endpoint = <&ca_funnel_out_port0>; 461 }; 462 }; 463 464 port@1 { 465 reg = <1>; 466 467 hugo_funnel_in_port1: endpoint { 468 /* M4 input */ 469 }; 470 }; 471 /* the other input ports are not connect to anything */ 472 }; 473 474 out-ports { 475 port { 476 hugo_funnel_out_port0: endpoint { 477 remote-endpoint = <&etf_in_port>; 478 }; 479 }; 480 }; 481 }; 482 483 etf@28c04000 { 484 compatible = "arm,coresight-tmc", "arm,primecell"; 485 reg = <0x28c04000 0x1000>; 486 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 487 clock-names = "apb_pclk"; 488 489 in-ports { 490 port { 491 etf_in_port: endpoint { 492 remote-endpoint = <&hugo_funnel_out_port0>; 493 }; 494 }; 495 }; 496 497 out-ports { 498 port { 499 etf_out_port: endpoint { 500 remote-endpoint = <&etr_in_port>; 501 }; 502 }; 503 }; 504 }; 505 506 etr@28c06000 { 507 compatible = "arm,coresight-tmc", "arm,primecell"; 508 reg = <0x28c06000 0x1000>; 509 clocks = <&clk IMX8MQ_CLK_MAIN_AXI>; 510 clock-names = "apb_pclk"; 511 512 in-ports { 513 port { 514 etr_in_port: endpoint { 515 remote-endpoint = <&etf_out_port>; 516 }; 517 }; 518 }; 519 }; 520 521 aips1: bus@30000000 { /* AIPS1 */ 522 compatible = "fsl,aips-bus", "simple-bus"; 523 reg = <0x30000000 0x400000>; 524 #address-cells = <1>; 525 #size-cells = <1>; 526 ranges = <0x30000000 0x30000000 0x400000>; 527 528 sai1: sai@30010000 { 529 #sound-dai-cells = <0>; 530 compatible = "fsl,imx8mq-sai"; 531 reg = <0x30010000 0x10000>; 532 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 533 clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, 534 <&clk IMX8MQ_CLK_SAI1_ROOT>, 535 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 536 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 537 dmas = <&sdma2 8 24 0>, <&sdma1 9 24 0>; 538 dma-names = "rx", "tx"; 539 status = "disabled"; 540 }; 541 542 sai6: sai@30030000 { 543 #sound-dai-cells = <0>; 544 compatible = "fsl,imx8mq-sai"; 545 reg = <0x30030000 0x10000>; 546 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 547 clocks = <&clk IMX8MQ_CLK_SAI6_IPG>, 548 <&clk IMX8MQ_CLK_SAI6_ROOT>, 549 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 550 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 551 dmas = <&sdma2 4 24 0>, <&sdma2 5 24 0>; 552 dma-names = "rx", "tx"; 553 status = "disabled"; 554 }; 555 556 sai5: sai@30040000 { 557 #sound-dai-cells = <0>; 558 compatible = "fsl,imx8mq-sai"; 559 reg = <0x30040000 0x10000>; 560 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 561 clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, 562 <&clk IMX8MQ_CLK_SAI5_ROOT>, 563 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 564 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 565 dmas = <&sdma2 2 24 0>, <&sdma2 3 24 0>; 566 dma-names = "rx", "tx"; 567 status = "disabled"; 568 }; 569 570 sai4: sai@30050000 { 571 #sound-dai-cells = <0>; 572 compatible = "fsl,imx8mq-sai"; 573 reg = <0x30050000 0x10000>; 574 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, 576 <&clk IMX8MQ_CLK_SAI4_ROOT>, 577 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 578 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 579 dmas = <&sdma2 0 24 0>, <&sdma2 1 24 0>; 580 dma-names = "rx", "tx"; 581 status = "disabled"; 582 }; 583 584 gpio1: gpio@30200000 { 585 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 586 reg = <0x30200000 0x10000>; 587 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 588 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 589 clocks = <&clk IMX8MQ_CLK_GPIO1_ROOT>; 590 gpio-controller; 591 #gpio-cells = <2>; 592 interrupt-controller; 593 #interrupt-cells = <2>; 594 gpio-ranges = <&iomuxc 0 10 30>; 595 }; 596 597 gpio2: gpio@30210000 { 598 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 599 reg = <0x30210000 0x10000>; 600 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 602 clocks = <&clk IMX8MQ_CLK_GPIO2_ROOT>; 603 gpio-controller; 604 #gpio-cells = <2>; 605 interrupt-controller; 606 #interrupt-cells = <2>; 607 gpio-ranges = <&iomuxc 0 40 21>; 608 }; 609 610 gpio3: gpio@30220000 { 611 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 612 reg = <0x30220000 0x10000>; 613 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 614 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 615 clocks = <&clk IMX8MQ_CLK_GPIO3_ROOT>; 616 gpio-controller; 617 #gpio-cells = <2>; 618 interrupt-controller; 619 #interrupt-cells = <2>; 620 gpio-ranges = <&iomuxc 0 61 26>; 621 }; 622 623 gpio4: gpio@30230000 { 624 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 625 reg = <0x30230000 0x10000>; 626 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 627 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 628 clocks = <&clk IMX8MQ_CLK_GPIO4_ROOT>; 629 gpio-controller; 630 #gpio-cells = <2>; 631 interrupt-controller; 632 #interrupt-cells = <2>; 633 gpio-ranges = <&iomuxc 0 87 32>; 634 }; 635 636 gpio5: gpio@30240000 { 637 compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio"; 638 reg = <0x30240000 0x10000>; 639 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 641 clocks = <&clk IMX8MQ_CLK_GPIO5_ROOT>; 642 gpio-controller; 643 #gpio-cells = <2>; 644 interrupt-controller; 645 #interrupt-cells = <2>; 646 gpio-ranges = <&iomuxc 0 119 30>; 647 }; 648 649 tmu: tmu@30260000 { 650 compatible = "fsl,imx8mq-tmu"; 651 reg = <0x30260000 0x10000>; 652 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 653 clocks = <&clk IMX8MQ_CLK_TMU_ROOT>; 654 little-endian; 655 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; 656 fsl,tmu-calibration = <0x00000000 0x00000023>, 657 <0x00000001 0x00000029>, 658 <0x00000002 0x0000002f>, 659 <0x00000003 0x00000035>, 660 <0x00000004 0x0000003d>, 661 <0x00000005 0x00000043>, 662 <0x00000006 0x0000004b>, 663 <0x00000007 0x00000051>, 664 <0x00000008 0x00000057>, 665 <0x00000009 0x0000005f>, 666 <0x0000000a 0x00000067>, 667 <0x0000000b 0x0000006f>, 668 669 <0x00010000 0x0000001b>, 670 <0x00010001 0x00000023>, 671 <0x00010002 0x0000002b>, 672 <0x00010003 0x00000033>, 673 <0x00010004 0x0000003b>, 674 <0x00010005 0x00000043>, 675 <0x00010006 0x0000004b>, 676 <0x00010007 0x00000055>, 677 <0x00010008 0x0000005d>, 678 <0x00010009 0x00000067>, 679 <0x0001000a 0x00000070>, 680 681 <0x00020000 0x00000017>, 682 <0x00020001 0x00000023>, 683 <0x00020002 0x0000002d>, 684 <0x00020003 0x00000037>, 685 <0x00020004 0x00000041>, 686 <0x00020005 0x0000004b>, 687 <0x00020006 0x00000057>, 688 <0x00020007 0x00000063>, 689 <0x00020008 0x0000006f>, 690 691 <0x00030000 0x00000015>, 692 <0x00030001 0x00000021>, 693 <0x00030002 0x0000002d>, 694 <0x00030003 0x00000039>, 695 <0x00030004 0x00000045>, 696 <0x00030005 0x00000053>, 697 <0x00030006 0x0000005f>, 698 <0x00030007 0x00000071>; 699 #thermal-sensor-cells = <1>; 700 }; 701 702 wdog1: watchdog@30280000 { 703 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 704 reg = <0x30280000 0x10000>; 705 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 706 clocks = <&clk IMX8MQ_CLK_WDOG1_ROOT>; 707 status = "disabled"; 708 }; 709 710 wdog2: watchdog@30290000 { 711 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 712 reg = <0x30290000 0x10000>; 713 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 714 clocks = <&clk IMX8MQ_CLK_WDOG2_ROOT>; 715 status = "disabled"; 716 }; 717 718 wdog3: watchdog@302a0000 { 719 compatible = "fsl,imx8mq-wdt", "fsl,imx21-wdt"; 720 reg = <0x302a0000 0x10000>; 721 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 722 clocks = <&clk IMX8MQ_CLK_WDOG3_ROOT>; 723 status = "disabled"; 724 }; 725 726 sdma2: dma-controller@302c0000 { 727 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 728 reg = <0x302c0000 0x10000>; 729 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 730 clocks = <&clk IMX8MQ_CLK_SDMA2_ROOT>, 731 <&clk IMX8MQ_CLK_SDMA2_ROOT>; 732 clock-names = "ipg", "ahb"; 733 #dma-cells = <3>; 734 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 735 }; 736 737 lcdif: lcd-controller@30320000 { 738 compatible = "fsl,imx8mq-lcdif", "fsl,imx6sx-lcdif"; 739 reg = <0x30320000 0x10000>; 740 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 741 clocks = <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 742 <&clk IMX8MQ_CLK_DISP_APB_ROOT>, 743 <&clk IMX8MQ_CLK_DISP_AXI_ROOT>; 744 clock-names = "pix", "axi", "disp_axi"; 745 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 746 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 747 <&clk IMX8MQ_CLK_LCDIF_PIXEL>, 748 <&clk IMX8MQ_VIDEO_PLL1>; 749 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 750 <&clk IMX8MQ_VIDEO_PLL1>, 751 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 752 assigned-clock-rates = <0>, <0>, <0>, <594000000>; 753 status = "disabled"; 754 755 port { 756 lcdif_mipi_dsi: endpoint { 757 remote-endpoint = <&mipi_dsi_lcdif_in>; 758 }; 759 }; 760 }; 761 762 iomuxc: pinctrl@30330000 { 763 compatible = "fsl,imx8mq-iomuxc"; 764 reg = <0x30330000 0x10000>; 765 }; 766 767 iomuxc_gpr: syscon@30340000 { 768 compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd"; 769 reg = <0x30340000 0x10000>; 770 771 mux: mux-controller { 772 compatible = "mmio-mux"; 773 #mux-control-cells = <1>; 774 mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ 775 }; 776 }; 777 778 ocotp: efuse@30350000 { 779 compatible = "fsl,imx8mq-ocotp", "syscon"; 780 reg = <0x30350000 0x10000>; 781 clocks = <&clk IMX8MQ_CLK_OCOTP_ROOT>; 782 #address-cells = <1>; 783 #size-cells = <1>; 784 785 /* 786 * The register address below maps to the MX8M 787 * Fusemap Description Table entries this way. 788 * Assuming 789 * reg = <ADDR SIZE>; 790 * then 791 * Fuse Address = (ADDR * 4) + 0x400 792 * Note that if SIZE is greater than 4, then 793 * each subsequent fuse is located at offset 794 * +0x10 in Fusemap Description Table (e.g. 795 * reg = <0x4 0x8> describes fuses 0x410 and 796 * 0x420). 797 */ 798 imx8mq_uid: soc-uid@4 { /* 0x410-0x420 */ 799 reg = <0x4 0x8>; 800 }; 801 802 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 803 reg = <0x10 4>; 804 }; 805 806 fec_mac_address: mac-address@90 { /* 0x640 */ 807 reg = <0x90 6>; 808 }; 809 }; 810 811 anatop: clock-controller@30360000 { 812 compatible = "fsl,imx8mq-anatop"; 813 reg = <0x30360000 0x10000>; 814 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 815 #clock-cells = <1>; 816 }; 817 818 snvs: snvs@30370000 { 819 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 820 reg = <0x30370000 0x10000>; 821 822 snvs_rtc: snvs-rtc-lp { 823 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 824 regmap = <&snvs>; 825 offset = <0x34>; 826 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 828 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 829 clock-names = "snvs-rtc"; 830 }; 831 832 snvs_pwrkey: snvs-powerkey { 833 compatible = "fsl,sec-v4.0-pwrkey"; 834 regmap = <&snvs>; 835 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 836 clocks = <&clk IMX8MQ_CLK_SNVS_ROOT>; 837 clock-names = "snvs-pwrkey"; 838 linux,keycode = <KEY_POWER>; 839 wakeup-source; 840 status = "disabled"; 841 }; 842 }; 843 844 clk: clock-controller@30380000 { 845 compatible = "fsl,imx8mq-ccm"; 846 reg = <0x30380000 0x10000>; 847 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 849 #clock-cells = <1>; 850 clocks = <&ckil>, <&osc_25m>, <&osc_27m>, 851 <&clk_ext1>, <&clk_ext2>, 852 <&clk_ext3>, <&clk_ext4>; 853 clock-names = "ckil", "osc_25m", "osc_27m", 854 "clk_ext1", "clk_ext2", 855 "clk_ext3", "clk_ext4"; 856 assigned-clocks = <&clk IMX8MQ_CLK_A53_SRC>, 857 <&clk IMX8MQ_CLK_A53_CORE>, 858 <&clk IMX8MQ_CLK_NOC>, 859 <&clk IMX8MQ_CLK_AUDIO_AHB>, 860 <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, 861 <&clk IMX8MQ_AUDIO_PLL2_BYPASS>, 862 <&clk IMX8MQ_AUDIO_PLL1>, 863 <&clk IMX8MQ_AUDIO_PLL2>; 864 assigned-clock-rates = <0>, <0>, 865 <800000000>, 866 <0>, 867 <0>, 868 <0>, 869 <786432000>, 870 <722534400>; 871 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, 872 <&clk IMX8MQ_ARM_PLL_OUT>, 873 <0>, 874 <&clk IMX8MQ_SYS2_PLL_500M>, 875 <&clk IMX8MQ_AUDIO_PLL1>, 876 <&clk IMX8MQ_AUDIO_PLL2>; 877 }; 878 879 src: reset-controller@30390000 { 880 compatible = "fsl,imx8mq-src", "syscon"; 881 reg = <0x30390000 0x10000>; 882 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 883 #reset-cells = <1>; 884 }; 885 886 gpc: gpc@303a0000 { 887 compatible = "fsl,imx8mq-gpc"; 888 reg = <0x303a0000 0x10000>; 889 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 890 interrupt-parent = <&gic>; 891 interrupt-controller; 892 #interrupt-cells = <3>; 893 894 pgc { 895 #address-cells = <1>; 896 #size-cells = <0>; 897 898 pgc_mipi: power-domain@0 { 899 #power-domain-cells = <0>; 900 reg = <IMX8M_POWER_DOMAIN_MIPI>; 901 }; 902 903 /* 904 * As per comment in ATF source code: 905 * 906 * PCIE1 and PCIE2 share the 907 * same reset signal, if we 908 * power down PCIE2, PCIE1 909 * will be held in reset too. 910 * 911 * So instead of creating two 912 * separate power domains for 913 * PCIE1 and PCIE2 we create a 914 * link between both and use 915 * it as a shared PCIE power 916 * domain. 917 */ 918 pgc_pcie: power-domain@1 { 919 #power-domain-cells = <0>; 920 reg = <IMX8M_POWER_DOMAIN_PCIE1>; 921 power-domains = <&pgc_pcie2>; 922 }; 923 924 pgc_otg1: power-domain@2 { 925 #power-domain-cells = <0>; 926 reg = <IMX8M_POWER_DOMAIN_USB_OTG1>; 927 }; 928 929 pgc_otg2: power-domain@3 { 930 #power-domain-cells = <0>; 931 reg = <IMX8M_POWER_DOMAIN_USB_OTG2>; 932 }; 933 934 pgc_ddr1: power-domain@4 { 935 #power-domain-cells = <0>; 936 reg = <IMX8M_POWER_DOMAIN_DDR1>; 937 }; 938 939 pgc_gpu: power-domain@5 { 940 #power-domain-cells = <0>; 941 reg = <IMX8M_POWER_DOMAIN_GPU>; 942 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 943 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 944 <&clk IMX8MQ_CLK_GPU_AXI>, 945 <&clk IMX8MQ_CLK_GPU_AHB>; 946 }; 947 948 pgc_vpu: power-domain@6 { 949 #power-domain-cells = <0>; 950 reg = <IMX8M_POWER_DOMAIN_VPU>; 951 clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, 952 <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 953 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 954 assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, 955 <&clk IMX8MQ_CLK_VPU_G2>, 956 <&clk IMX8MQ_CLK_VPU_BUS>, 957 <&clk IMX8MQ_VPU_PLL_BYPASS>; 958 assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, 959 <&clk IMX8MQ_VPU_PLL_OUT>, 960 <&clk IMX8MQ_SYS1_PLL_800M>, 961 <&clk IMX8MQ_VPU_PLL>; 962 assigned-clock-rates = <600000000>, 963 <300000000>, 964 <800000000>, 965 <0>; 966 }; 967 968 pgc_disp: power-domain@7 { 969 #power-domain-cells = <0>; 970 reg = <IMX8M_POWER_DOMAIN_DISP>; 971 }; 972 973 pgc_mipi_csi1: power-domain@8 { 974 #power-domain-cells = <0>; 975 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI1>; 976 }; 977 978 pgc_mipi_csi2: power-domain@9 { 979 #power-domain-cells = <0>; 980 reg = <IMX8M_POWER_DOMAIN_MIPI_CSI2>; 981 }; 982 983 pgc_pcie2: power-domain@a { 984 #power-domain-cells = <0>; 985 reg = <IMX8M_POWER_DOMAIN_PCIE2>; 986 }; 987 }; 988 }; 989 }; 990 991 aips2: bus@30400000 { /* AIPS2 */ 992 compatible = "fsl,aips-bus", "simple-bus"; 993 reg = <0x30400000 0x400000>; 994 #address-cells = <1>; 995 #size-cells = <1>; 996 ranges = <0x30400000 0x30400000 0x400000>; 997 998 pwm1: pwm@30660000 { 999 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 1000 reg = <0x30660000 0x10000>; 1001 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1002 clocks = <&clk IMX8MQ_CLK_PWM1_ROOT>, 1003 <&clk IMX8MQ_CLK_PWM1_ROOT>; 1004 clock-names = "ipg", "per"; 1005 #pwm-cells = <3>; 1006 status = "disabled"; 1007 }; 1008 1009 pwm2: pwm@30670000 { 1010 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 1011 reg = <0x30670000 0x10000>; 1012 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 1013 clocks = <&clk IMX8MQ_CLK_PWM2_ROOT>, 1014 <&clk IMX8MQ_CLK_PWM2_ROOT>; 1015 clock-names = "ipg", "per"; 1016 #pwm-cells = <3>; 1017 status = "disabled"; 1018 }; 1019 1020 pwm3: pwm@30680000 { 1021 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 1022 reg = <0x30680000 0x10000>; 1023 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1024 clocks = <&clk IMX8MQ_CLK_PWM3_ROOT>, 1025 <&clk IMX8MQ_CLK_PWM3_ROOT>; 1026 clock-names = "ipg", "per"; 1027 #pwm-cells = <3>; 1028 status = "disabled"; 1029 }; 1030 1031 pwm4: pwm@30690000 { 1032 compatible = "fsl,imx8mq-pwm", "fsl,imx27-pwm"; 1033 reg = <0x30690000 0x10000>; 1034 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&clk IMX8MQ_CLK_PWM4_ROOT>, 1036 <&clk IMX8MQ_CLK_PWM4_ROOT>; 1037 clock-names = "ipg", "per"; 1038 #pwm-cells = <3>; 1039 status = "disabled"; 1040 }; 1041 1042 system_counter: timer@306a0000 { 1043 compatible = "nxp,sysctr-timer"; 1044 reg = <0x306a0000 0x20000>; 1045 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1046 clocks = <&osc_25m>; 1047 clock-names = "per"; 1048 }; 1049 }; 1050 1051 aips3: bus@30800000 { /* AIPS3 */ 1052 compatible = "fsl,aips-bus", "simple-bus"; 1053 reg = <0x30800000 0x400000>; 1054 #address-cells = <1>; 1055 #size-cells = <1>; 1056 ranges = <0x30800000 0x30800000 0x400000>, 1057 <0x08000000 0x08000000 0x10000000>; 1058 1059 spdif1: spdif@30810000 { 1060 compatible = "fsl,imx35-spdif"; 1061 reg = <0x30810000 0x10000>; 1062 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1063 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 1064 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 1065 <&clk IMX8MQ_CLK_SPDIF1>, /* rxtx1 */ 1066 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 1067 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 1068 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 1069 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 1070 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 1071 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 1072 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 1073 clock-names = "core", "rxtx0", 1074 "rxtx1", "rxtx2", 1075 "rxtx3", "rxtx4", 1076 "rxtx5", "rxtx6", 1077 "rxtx7", "spba"; 1078 dmas = <&sdma1 8 18 0>, <&sdma1 9 18 0>; 1079 dma-names = "rx", "tx"; 1080 status = "disabled"; 1081 }; 1082 1083 ecspi1: spi@30820000 { 1084 #address-cells = <1>; 1085 #size-cells = <0>; 1086 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 1087 reg = <0x30820000 0x10000>; 1088 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1089 clocks = <&clk IMX8MQ_CLK_ECSPI1_ROOT>, 1090 <&clk IMX8MQ_CLK_ECSPI1_ROOT>; 1091 clock-names = "ipg", "per"; 1092 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 1093 dma-names = "rx", "tx"; 1094 status = "disabled"; 1095 }; 1096 1097 ecspi2: spi@30830000 { 1098 #address-cells = <1>; 1099 #size-cells = <0>; 1100 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 1101 reg = <0x30830000 0x10000>; 1102 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1103 clocks = <&clk IMX8MQ_CLK_ECSPI2_ROOT>, 1104 <&clk IMX8MQ_CLK_ECSPI2_ROOT>; 1105 clock-names = "ipg", "per"; 1106 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 1107 dma-names = "rx", "tx"; 1108 status = "disabled"; 1109 }; 1110 1111 ecspi3: spi@30840000 { 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 compatible = "fsl,imx8mq-ecspi", "fsl,imx51-ecspi"; 1115 reg = <0x30840000 0x10000>; 1116 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1117 clocks = <&clk IMX8MQ_CLK_ECSPI3_ROOT>, 1118 <&clk IMX8MQ_CLK_ECSPI3_ROOT>; 1119 clock-names = "ipg", "per"; 1120 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 1121 dma-names = "rx", "tx"; 1122 status = "disabled"; 1123 }; 1124 1125 uart1: serial@30860000 { 1126 compatible = "fsl,imx8mq-uart", 1127 "fsl,imx6q-uart"; 1128 reg = <0x30860000 0x10000>; 1129 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1130 clocks = <&clk IMX8MQ_CLK_UART1_ROOT>, 1131 <&clk IMX8MQ_CLK_UART1_ROOT>; 1132 clock-names = "ipg", "per"; 1133 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 1134 dma-names = "rx", "tx"; 1135 status = "disabled"; 1136 }; 1137 1138 uart3: serial@30880000 { 1139 compatible = "fsl,imx8mq-uart", 1140 "fsl,imx6q-uart"; 1141 reg = <0x30880000 0x10000>; 1142 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&clk IMX8MQ_CLK_UART3_ROOT>, 1144 <&clk IMX8MQ_CLK_UART3_ROOT>; 1145 clock-names = "ipg", "per"; 1146 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 1147 dma-names = "rx", "tx"; 1148 status = "disabled"; 1149 }; 1150 1151 uart2: serial@30890000 { 1152 compatible = "fsl,imx8mq-uart", 1153 "fsl,imx6q-uart"; 1154 reg = <0x30890000 0x10000>; 1155 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1156 clocks = <&clk IMX8MQ_CLK_UART2_ROOT>, 1157 <&clk IMX8MQ_CLK_UART2_ROOT>; 1158 clock-names = "ipg", "per"; 1159 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 1160 dma-names = "rx", "tx"; 1161 status = "disabled"; 1162 }; 1163 1164 spdif2: spdif@308a0000 { 1165 compatible = "fsl,imx35-spdif"; 1166 reg = <0x308a0000 0x10000>; 1167 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1168 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, /* core */ 1169 <&clk IMX8MQ_CLK_25M>, /* rxtx0 */ 1170 <&clk IMX8MQ_CLK_SPDIF2>, /* rxtx1 */ 1171 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx2 */ 1172 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx3 */ 1173 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx4 */ 1174 <&clk IMX8MQ_CLK_IPG_ROOT>, /* rxtx5 */ 1175 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx6 */ 1176 <&clk IMX8MQ_CLK_DUMMY>, /* rxtx7 */ 1177 <&clk IMX8MQ_CLK_DUMMY>; /* spba */ 1178 clock-names = "core", "rxtx0", 1179 "rxtx1", "rxtx2", 1180 "rxtx3", "rxtx4", 1181 "rxtx5", "rxtx6", 1182 "rxtx7", "spba"; 1183 dmas = <&sdma1 16 18 0>, <&sdma1 17 18 0>; 1184 dma-names = "rx", "tx"; 1185 status = "disabled"; 1186 }; 1187 1188 sai2: sai@308b0000 { 1189 #sound-dai-cells = <0>; 1190 compatible = "fsl,imx8mq-sai"; 1191 reg = <0x308b0000 0x10000>; 1192 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1193 clocks = <&clk IMX8MQ_CLK_SAI2_IPG>, 1194 <&clk IMX8MQ_CLK_SAI2_ROOT>, 1195 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 1196 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1197 dmas = <&sdma1 10 24 0>, <&sdma1 11 24 0>; 1198 dma-names = "rx", "tx"; 1199 status = "disabled"; 1200 }; 1201 1202 sai3: sai@308c0000 { 1203 #sound-dai-cells = <0>; 1204 compatible = "fsl,imx8mq-sai"; 1205 reg = <0x308c0000 0x10000>; 1206 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1207 clocks = <&clk IMX8MQ_CLK_SAI3_IPG>, 1208 <&clk IMX8MQ_CLK_SAI3_ROOT>, 1209 <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_CLK_DUMMY>; 1210 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 1211 dmas = <&sdma1 12 24 0>, <&sdma1 13 24 0>; 1212 dma-names = "rx", "tx"; 1213 status = "disabled"; 1214 }; 1215 1216 crypto: crypto@30900000 { 1217 compatible = "fsl,sec-v4.0"; 1218 #address-cells = <1>; 1219 #size-cells = <1>; 1220 reg = <0x30900000 0x40000>; 1221 ranges = <0 0x30900000 0x40000>; 1222 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&clk IMX8MQ_CLK_AHB>, 1224 <&clk IMX8MQ_CLK_IPG_ROOT>; 1225 clock-names = "aclk", "ipg"; 1226 1227 sec_jr0: jr@1000 { 1228 compatible = "fsl,sec-v4.0-job-ring"; 1229 reg = <0x1000 0x1000>; 1230 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1231 status = "disabled"; 1232 }; 1233 1234 sec_jr1: jr@2000 { 1235 compatible = "fsl,sec-v4.0-job-ring"; 1236 reg = <0x2000 0x1000>; 1237 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1238 }; 1239 1240 sec_jr2: jr@3000 { 1241 compatible = "fsl,sec-v4.0-job-ring"; 1242 reg = <0x3000 0x1000>; 1243 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1244 }; 1245 }; 1246 1247 mipi_dsi: dsi@30a00000 { 1248 compatible = "fsl,imx8mq-nwl-dsi"; 1249 reg = <0x30a00000 0x300>; 1250 #address-cells = <1>; 1251 #size-cells = <0>; 1252 clocks = <&clk IMX8MQ_CLK_DSI_CORE>, 1253 <&clk IMX8MQ_CLK_DSI_AHB>, 1254 <&clk IMX8MQ_CLK_DSI_IPG_DIV>, 1255 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1256 <&clk IMX8MQ_CLK_LCDIF_PIXEL>; 1257 clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif"; 1258 assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>, 1259 <&clk IMX8MQ_CLK_DSI_CORE>, 1260 <&clk IMX8MQ_CLK_DSI_IPG_DIV>; 1261 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>, 1262 <&clk IMX8MQ_SYS1_PLL_266M>; 1263 assigned-clock-rates = <80000000>, <266000000>, <20000000>; 1264 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1265 mux-controls = <&mux 0>; 1266 power-domains = <&pgc_mipi>; 1267 phys = <&dphy>; 1268 phy-names = "dphy"; 1269 resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>, 1270 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>, 1271 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>, 1272 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>; 1273 reset-names = "byte", "dpi", "esc", "pclk"; 1274 status = "disabled"; 1275 1276 ports { 1277 #address-cells = <1>; 1278 #size-cells = <0>; 1279 1280 port@0 { 1281 reg = <0>; 1282 #address-cells = <1>; 1283 #size-cells = <0>; 1284 mipi_dsi_lcdif_in: endpoint@0 { 1285 reg = <0>; 1286 remote-endpoint = <&lcdif_mipi_dsi>; 1287 }; 1288 }; 1289 1290 port@1 { 1291 reg = <1>; 1292 1293 mipi_dsi_out: endpoint { 1294 }; 1295 }; 1296 }; 1297 }; 1298 1299 dphy: dphy@30a00300 { 1300 compatible = "fsl,imx8mq-mipi-dphy"; 1301 reg = <0x30a00300 0x100>; 1302 clocks = <&clk IMX8MQ_CLK_DSI_PHY_REF>; 1303 clock-names = "phy_ref"; 1304 assigned-clocks = <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>, 1305 <&clk IMX8MQ_VIDEO_PLL1_BYPASS>, 1306 <&clk IMX8MQ_CLK_DSI_PHY_REF>, 1307 <&clk IMX8MQ_VIDEO_PLL1>; 1308 assigned-clock-parents = <&clk IMX8MQ_CLK_25M>, 1309 <&clk IMX8MQ_VIDEO_PLL1>, 1310 <&clk IMX8MQ_VIDEO_PLL1_OUT>; 1311 assigned-clock-rates = <0>, <0>, <24000000>, <594000000>; 1312 #phy-cells = <0>; 1313 power-domains = <&pgc_mipi>; 1314 status = "disabled"; 1315 }; 1316 1317 i2c1: i2c@30a20000 { 1318 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1319 reg = <0x30a20000 0x10000>; 1320 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1321 clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>; 1322 #address-cells = <1>; 1323 #size-cells = <0>; 1324 status = "disabled"; 1325 }; 1326 1327 i2c2: i2c@30a30000 { 1328 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1329 reg = <0x30a30000 0x10000>; 1330 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1331 clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>; 1332 #address-cells = <1>; 1333 #size-cells = <0>; 1334 status = "disabled"; 1335 }; 1336 1337 i2c3: i2c@30a40000 { 1338 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1339 reg = <0x30a40000 0x10000>; 1340 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1341 clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>; 1342 #address-cells = <1>; 1343 #size-cells = <0>; 1344 status = "disabled"; 1345 }; 1346 1347 i2c4: i2c@30a50000 { 1348 compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c"; 1349 reg = <0x30a50000 0x10000>; 1350 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1351 clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>; 1352 #address-cells = <1>; 1353 #size-cells = <0>; 1354 status = "disabled"; 1355 }; 1356 1357 uart4: serial@30a60000 { 1358 compatible = "fsl,imx8mq-uart", 1359 "fsl,imx6q-uart"; 1360 reg = <0x30a60000 0x10000>; 1361 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1362 clocks = <&clk IMX8MQ_CLK_UART4_ROOT>, 1363 <&clk IMX8MQ_CLK_UART4_ROOT>; 1364 clock-names = "ipg", "per"; 1365 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1366 dma-names = "rx", "tx"; 1367 status = "disabled"; 1368 }; 1369 1370 mipi_csi1: csi@30a70000 { 1371 compatible = "fsl,imx8mq-mipi-csi2"; 1372 reg = <0x30a70000 0x1000>; 1373 clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1374 <&clk IMX8MQ_CLK_CSI1_ESC>, 1375 <&clk IMX8MQ_CLK_CSI1_PHY_REF>; 1376 clock-names = "core", "esc", "ui"; 1377 assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>, 1378 <&clk IMX8MQ_CLK_CSI1_PHY_REF>, 1379 <&clk IMX8MQ_CLK_CSI1_ESC>; 1380 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1381 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1382 <&clk IMX8MQ_SYS2_PLL_1000M>, 1383 <&clk IMX8MQ_SYS1_PLL_800M>; 1384 power-domains = <&pgc_mipi_csi1>; 1385 resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>, 1386 <&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>, 1387 <&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>; 1388 fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>; 1389 interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>; 1390 interconnect-names = "dram"; 1391 status = "disabled"; 1392 1393 ports { 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 1397 port@1 { 1398 reg = <1>; 1399 1400 csi1_mipi_ep: endpoint { 1401 remote-endpoint = <&csi1_ep>; 1402 }; 1403 }; 1404 }; 1405 }; 1406 1407 csi1: csi@30a90000 { 1408 compatible = "fsl,imx8mq-csi"; 1409 reg = <0x30a90000 0x10000>; 1410 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1411 clocks = <&clk IMX8MQ_CLK_CSI1_ROOT>; 1412 clock-names = "mclk"; 1413 status = "disabled"; 1414 1415 port { 1416 csi1_ep: endpoint { 1417 remote-endpoint = <&csi1_mipi_ep>; 1418 }; 1419 }; 1420 }; 1421 1422 mipi_csi2: csi@30b60000 { 1423 compatible = "fsl,imx8mq-mipi-csi2"; 1424 reg = <0x30b60000 0x1000>; 1425 clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1426 <&clk IMX8MQ_CLK_CSI2_ESC>, 1427 <&clk IMX8MQ_CLK_CSI2_PHY_REF>; 1428 clock-names = "core", "esc", "ui"; 1429 assigned-clocks = <&clk IMX8MQ_CLK_CSI2_CORE>, 1430 <&clk IMX8MQ_CLK_CSI2_PHY_REF>, 1431 <&clk IMX8MQ_CLK_CSI2_ESC>; 1432 assigned-clock-rates = <266000000>, <333000000>, <66000000>; 1433 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1434 <&clk IMX8MQ_SYS2_PLL_1000M>, 1435 <&clk IMX8MQ_SYS1_PLL_800M>; 1436 power-domains = <&pgc_mipi_csi2>; 1437 resets = <&src IMX8MQ_RESET_MIPI_CSI2_CORE_RESET>, 1438 <&src IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET>, 1439 <&src IMX8MQ_RESET_MIPI_CSI2_ESC_RESET>; 1440 fsl,mipi-phy-gpr = <&iomuxc_gpr 0xa4>; 1441 interconnects = <&noc IMX8MQ_ICM_CSI2 &noc IMX8MQ_ICS_DRAM>; 1442 interconnect-names = "dram"; 1443 status = "disabled"; 1444 1445 ports { 1446 #address-cells = <1>; 1447 #size-cells = <0>; 1448 1449 port@1 { 1450 reg = <1>; 1451 1452 csi2_mipi_ep: endpoint { 1453 remote-endpoint = <&csi2_ep>; 1454 }; 1455 }; 1456 }; 1457 }; 1458 1459 csi2: csi@30b80000 { 1460 compatible = "fsl,imx8mq-csi"; 1461 reg = <0x30b80000 0x10000>; 1462 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1463 clocks = <&clk IMX8MQ_CLK_CSI2_ROOT>; 1464 clock-names = "mclk"; 1465 status = "disabled"; 1466 1467 port { 1468 csi2_ep: endpoint { 1469 remote-endpoint = <&csi2_mipi_ep>; 1470 }; 1471 }; 1472 }; 1473 1474 mu: mailbox@30aa0000 { 1475 compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu"; 1476 reg = <0x30aa0000 0x10000>; 1477 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1478 clocks = <&clk IMX8MQ_CLK_MU_ROOT>; 1479 #mbox-cells = <2>; 1480 }; 1481 1482 usdhc1: mmc@30b40000 { 1483 compatible = "fsl,imx8mq-usdhc", 1484 "fsl,imx7d-usdhc"; 1485 reg = <0x30b40000 0x10000>; 1486 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1487 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1488 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1489 <&clk IMX8MQ_CLK_USDHC1_ROOT>; 1490 clock-names = "ipg", "ahb", "per"; 1491 fsl,tuning-start-tap = <20>; 1492 fsl,tuning-step = <2>; 1493 bus-width = <4>; 1494 status = "disabled"; 1495 }; 1496 1497 usdhc2: mmc@30b50000 { 1498 compatible = "fsl,imx8mq-usdhc", 1499 "fsl,imx7d-usdhc"; 1500 reg = <0x30b50000 0x10000>; 1501 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1502 clocks = <&clk IMX8MQ_CLK_IPG_ROOT>, 1503 <&clk IMX8MQ_CLK_NAND_USDHC_BUS>, 1504 <&clk IMX8MQ_CLK_USDHC2_ROOT>; 1505 clock-names = "ipg", "ahb", "per"; 1506 fsl,tuning-start-tap = <20>; 1507 fsl,tuning-step = <2>; 1508 bus-width = <4>; 1509 status = "disabled"; 1510 }; 1511 1512 qspi0: spi@30bb0000 { 1513 #address-cells = <1>; 1514 #size-cells = <0>; 1515 compatible = "fsl,imx8mq-qspi", "fsl,imx7d-qspi"; 1516 reg = <0x30bb0000 0x10000>, 1517 <0x08000000 0x10000000>; 1518 reg-names = "QuadSPI", "QuadSPI-memory"; 1519 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1520 clocks = <&clk IMX8MQ_CLK_QSPI_ROOT>, 1521 <&clk IMX8MQ_CLK_QSPI_ROOT>; 1522 clock-names = "qspi_en", "qspi"; 1523 status = "disabled"; 1524 }; 1525 1526 sdma1: dma-controller@30bd0000 { 1527 compatible = "fsl,imx8mq-sdma","fsl,imx7d-sdma"; 1528 reg = <0x30bd0000 0x10000>; 1529 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1530 clocks = <&clk IMX8MQ_CLK_SDMA1_ROOT>, 1531 <&clk IMX8MQ_CLK_AHB>; 1532 clock-names = "ipg", "ahb"; 1533 #dma-cells = <3>; 1534 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1535 }; 1536 1537 fec1: ethernet@30be0000 { 1538 compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1539 reg = <0x30be0000 0x10000>; 1540 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1541 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1542 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1543 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1544 clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>, 1545 <&clk IMX8MQ_CLK_ENET1_ROOT>, 1546 <&clk IMX8MQ_CLK_ENET_TIMER>, 1547 <&clk IMX8MQ_CLK_ENET_REF>, 1548 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1549 clock-names = "ipg", "ahb", "ptp", 1550 "enet_clk_ref", "enet_out"; 1551 assigned-clocks = <&clk IMX8MQ_CLK_ENET_AXI>, 1552 <&clk IMX8MQ_CLK_ENET_TIMER>, 1553 <&clk IMX8MQ_CLK_ENET_REF>, 1554 <&clk IMX8MQ_CLK_ENET_PHY_REF>; 1555 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>, 1556 <&clk IMX8MQ_SYS2_PLL_100M>, 1557 <&clk IMX8MQ_SYS2_PLL_125M>, 1558 <&clk IMX8MQ_SYS2_PLL_50M>; 1559 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1560 fsl,num-tx-queues = <3>; 1561 fsl,num-rx-queues = <3>; 1562 nvmem-cells = <&fec_mac_address>; 1563 nvmem-cell-names = "mac-address"; 1564 fsl,stop-mode = <&iomuxc_gpr 0x10 3>; 1565 status = "disabled"; 1566 }; 1567 }; 1568 1569 noc: interconnect@32700000 { 1570 compatible = "fsl,imx8mq-noc", "fsl,imx8m-noc"; 1571 reg = <0x32700000 0x100000>; 1572 clocks = <&clk IMX8MQ_CLK_NOC>; 1573 fsl,ddrc = <&ddrc>; 1574 #interconnect-cells = <1>; 1575 operating-points-v2 = <&noc_opp_table>; 1576 1577 noc_opp_table: opp-table { 1578 compatible = "operating-points-v2"; 1579 1580 opp-133000000 { 1581 opp-hz = /bits/ 64 <133333333>; 1582 }; 1583 1584 opp-400000000 { 1585 opp-hz = /bits/ 64 <400000000>; 1586 }; 1587 1588 opp-800000000 { 1589 opp-hz = /bits/ 64 <800000000>; 1590 }; 1591 }; 1592 }; 1593 1594 aips4: bus@32c00000 { /* AIPS4 */ 1595 compatible = "fsl,aips-bus", "simple-bus"; 1596 reg = <0x32c00000 0x400000>; 1597 #address-cells = <1>; 1598 #size-cells = <1>; 1599 ranges = <0x32c00000 0x32c00000 0x400000>; 1600 1601 irqsteer: interrupt-controller@32e2d000 { 1602 compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer"; 1603 reg = <0x32e2d000 0x1000>; 1604 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1605 clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>; 1606 clock-names = "ipg"; 1607 fsl,channel = <0>; 1608 fsl,num-irqs = <64>; 1609 interrupt-controller; 1610 #interrupt-cells = <1>; 1611 }; 1612 }; 1613 1614 gpu: gpu@38000000 { 1615 compatible = "vivante,gc"; 1616 reg = <0x38000000 0x40000>; 1617 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1618 clocks = <&clk IMX8MQ_CLK_GPU_ROOT>, 1619 <&clk IMX8MQ_CLK_GPU_SHADER_DIV>, 1620 <&clk IMX8MQ_CLK_GPU_AXI>, 1621 <&clk IMX8MQ_CLK_GPU_AHB>; 1622 clock-names = "core", "shader", "bus", "reg"; 1623 #cooling-cells = <2>; 1624 assigned-clocks = <&clk IMX8MQ_CLK_GPU_CORE_SRC>, 1625 <&clk IMX8MQ_CLK_GPU_SHADER_SRC>, 1626 <&clk IMX8MQ_CLK_GPU_AXI>, 1627 <&clk IMX8MQ_CLK_GPU_AHB>, 1628 <&clk IMX8MQ_GPU_PLL_BYPASS>; 1629 assigned-clock-parents = <&clk IMX8MQ_GPU_PLL_OUT>, 1630 <&clk IMX8MQ_GPU_PLL_OUT>, 1631 <&clk IMX8MQ_GPU_PLL_OUT>, 1632 <&clk IMX8MQ_GPU_PLL_OUT>, 1633 <&clk IMX8MQ_GPU_PLL>; 1634 assigned-clock-rates = <800000000>, <800000000>, 1635 <800000000>, <400000000>, <0>; 1636 power-domains = <&pgc_gpu>; 1637 }; 1638 1639 usb_dwc3_0: usb@38100000 { 1640 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1641 reg = <0x38100000 0x10000>; 1642 clocks = <&clk IMX8MQ_CLK_USB1_CTRL_ROOT>, 1643 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1644 <&clk IMX8MQ_CLK_32K>; 1645 clock-names = "bus_early", "ref", "suspend"; 1646 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1647 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1648 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1649 <&clk IMX8MQ_SYS1_PLL_100M>; 1650 assigned-clock-rates = <500000000>, <100000000>; 1651 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 1652 phys = <&usb3_phy0>, <&usb3_phy0>; 1653 phy-names = "usb2-phy", "usb3-phy"; 1654 power-domains = <&pgc_otg1>; 1655 snps,parkmode-disable-ss-quirk; 1656 status = "disabled"; 1657 }; 1658 1659 usb3_phy0: usb-phy@381f0040 { 1660 compatible = "fsl,imx8mq-usb-phy"; 1661 reg = <0x381f0040 0x40>; 1662 clocks = <&clk IMX8MQ_CLK_USB1_PHY_ROOT>; 1663 clock-names = "phy"; 1664 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1665 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1666 assigned-clock-rates = <100000000>; 1667 #phy-cells = <0>; 1668 status = "disabled"; 1669 }; 1670 1671 usb_dwc3_1: usb@38200000 { 1672 compatible = "fsl,imx8mq-dwc3", "snps,dwc3"; 1673 reg = <0x38200000 0x10000>; 1674 clocks = <&clk IMX8MQ_CLK_USB2_CTRL_ROOT>, 1675 <&clk IMX8MQ_CLK_USB_CORE_REF>, 1676 <&clk IMX8MQ_CLK_32K>; 1677 clock-names = "bus_early", "ref", "suspend"; 1678 assigned-clocks = <&clk IMX8MQ_CLK_USB_BUS>, 1679 <&clk IMX8MQ_CLK_USB_CORE_REF>; 1680 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_500M>, 1681 <&clk IMX8MQ_SYS1_PLL_100M>; 1682 assigned-clock-rates = <500000000>, <100000000>; 1683 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 1684 phys = <&usb3_phy1>, <&usb3_phy1>; 1685 phy-names = "usb2-phy", "usb3-phy"; 1686 power-domains = <&pgc_otg2>; 1687 snps,parkmode-disable-ss-quirk; 1688 status = "disabled"; 1689 }; 1690 1691 usb3_phy1: usb-phy@382f0040 { 1692 compatible = "fsl,imx8mq-usb-phy"; 1693 reg = <0x382f0040 0x40>; 1694 clocks = <&clk IMX8MQ_CLK_USB2_PHY_ROOT>; 1695 clock-names = "phy"; 1696 assigned-clocks = <&clk IMX8MQ_CLK_USB_PHY_REF>; 1697 assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_100M>; 1698 assigned-clock-rates = <100000000>; 1699 #phy-cells = <0>; 1700 status = "disabled"; 1701 }; 1702 1703 vpu_g1: video-codec@38300000 { 1704 compatible = "nxp,imx8mq-vpu-g1"; 1705 reg = <0x38300000 0x10000>; 1706 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 1707 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; 1708 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; 1709 }; 1710 1711 vpu_g2: video-codec@38310000 { 1712 compatible = "nxp,imx8mq-vpu-g2"; 1713 reg = <0x38310000 0x10000>; 1714 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1715 clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1716 power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; 1717 }; 1718 1719 vpu_blk_ctrl: blk-ctrl@38320000 { 1720 compatible = "fsl,imx8mq-vpu-blk-ctrl"; 1721 reg = <0x38320000 0x100>; 1722 power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; 1723 power-domain-names = "bus", "g1", "g2"; 1724 clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, 1725 <&clk IMX8MQ_CLK_VPU_G2_ROOT>; 1726 clock-names = "g1", "g2"; 1727 #power-domain-cells = <1>; 1728 }; 1729 1730 pcie0: pcie@33800000 { 1731 compatible = "fsl,imx8mq-pcie"; 1732 reg = <0x33800000 0x400000>, 1733 <0x1ff00000 0x80000>; 1734 reg-names = "dbi", "config"; 1735 #address-cells = <3>; 1736 #size-cells = <2>; 1737 device_type = "pci"; 1738 bus-range = <0x00 0xff>; 1739 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 1740 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 1741 num-lanes = <1>; 1742 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1743 interrupt-names = "msi"; 1744 #interrupt-cells = <1>; 1745 interrupt-map-mask = <0 0 0 0x7>; 1746 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1747 <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1748 <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1749 <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1750 fsl,max-link-speed = <2>; 1751 linux,pci-domain = <0>; 1752 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>, 1753 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1754 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1755 <&clk IMX8MQ_CLK_PCIE1_AUX>; 1756 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1757 power-domains = <&pgc_pcie>; 1758 resets = <&src IMX8MQ_RESET_PCIEPHY>, 1759 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, 1760 <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; 1761 reset-names = "pciephy", "apps", "turnoff"; 1762 assigned-clocks = <&clk IMX8MQ_CLK_PCIE1_CTRL>, 1763 <&clk IMX8MQ_CLK_PCIE1_PHY>, 1764 <&clk IMX8MQ_CLK_PCIE1_AUX>; 1765 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1766 <&clk IMX8MQ_SYS2_PLL_100M>, 1767 <&clk IMX8MQ_SYS1_PLL_80M>; 1768 assigned-clock-rates = <250000000>, <100000000>, 1769 <10000000>; 1770 status = "disabled"; 1771 }; 1772 1773 pcie0_ep: pcie-ep@33800000 { 1774 compatible = "fsl,imx8mq-pcie-ep"; 1775 reg = <0x33800000 0x100000>, 1776 <0x18000000 0x8000000>, 1777 <0x33900000 0x100000>, 1778 <0x33b00000 0x100000>; 1779 reg-names = "dbi", "addr_space", "dbi2", "atu"; 1780 num-lanes = <1>; 1781 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1782 interrupt-names = "dma"; 1783 linux,pci-domain = <0>; 1784 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 1785 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1786 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1787 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1788 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1789 power-domains = <&pgc_pcie>; 1790 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1791 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1792 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1793 reset-names = "pciephy", "apps", "turnoff"; 1794 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, 1795 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1796 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1797 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1798 <&clk IMX8MQ_SYS2_PLL_100M>, 1799 <&clk IMX8MQ_SYS1_PLL_80M>; 1800 assigned-clock-rates = <250000000>, <100000000>, 1801 <10000000>; 1802 num-ib-windows = <4>; 1803 num-ob-windows = <4>; 1804 fsl,max-link-speed = <2>; 1805 status = "disabled"; 1806 }; 1807 1808 pcie1: pcie@33c00000 { 1809 compatible = "fsl,imx8mq-pcie"; 1810 reg = <0x33c00000 0x400000>, 1811 <0x27f00000 0x80000>; 1812 reg-names = "dbi", "config"; 1813 #address-cells = <3>; 1814 #size-cells = <2>; 1815 device_type = "pci"; 1816 bus-range = <0x00 0xff>; 1817 ranges = <0x81000000 0 0x00000000 0x27f80000 0 0x00010000>, /* downstream I/O 64KB */ 1818 <0x82000000 0 0x20000000 0x20000000 0 0x07f00000>; /* non-prefetchable memory */ 1819 num-lanes = <1>; 1820 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1821 interrupt-names = "msi"; 1822 #interrupt-cells = <1>; 1823 interrupt-map-mask = <0 0 0 0x7>; 1824 interrupt-map = <0 0 0 1 &gic GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>, 1825 <0 0 0 2 &gic GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>, 1826 <0 0 0 3 &gic GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>, 1827 <0 0 0 4 &gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1828 fsl,max-link-speed = <2>; 1829 linux,pci-domain = <1>; 1830 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 1831 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1832 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1833 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1834 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1835 power-domains = <&pgc_pcie>; 1836 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1837 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1838 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1839 reset-names = "pciephy", "apps", "turnoff"; 1840 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, 1841 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1842 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1843 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1844 <&clk IMX8MQ_SYS2_PLL_100M>, 1845 <&clk IMX8MQ_SYS1_PLL_80M>; 1846 assigned-clock-rates = <250000000>, <100000000>, 1847 <10000000>; 1848 status = "disabled"; 1849 }; 1850 1851 pcie1_ep: pcie-ep@33c00000 { 1852 compatible = "fsl,imx8mq-pcie-ep"; 1853 reg = <0x33c00000 0x100000>, 1854 <0x20000000 0x8000000>, 1855 <0x33d00000 0x100000>, 1856 <0x33f00000 0x100000>; 1857 reg-names = "dbi", "addr_space", "dbi2", "atu"; 1858 num-lanes = <1>; 1859 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1860 interrupt-names = "dma"; 1861 fsl,max-link-speed = <2>; 1862 linux,pci-domain = <1>; 1863 clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, 1864 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1865 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1866 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1867 clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux"; 1868 power-domains = <&pgc_pcie>; 1869 resets = <&src IMX8MQ_RESET_PCIEPHY2>, 1870 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, 1871 <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; 1872 reset-names = "pciephy", "apps", "turnoff"; 1873 assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>, 1874 <&clk IMX8MQ_CLK_PCIE2_PHY>, 1875 <&clk IMX8MQ_CLK_PCIE2_AUX>; 1876 assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>, 1877 <&clk IMX8MQ_SYS2_PLL_100M>, 1878 <&clk IMX8MQ_SYS1_PLL_80M>; 1879 assigned-clock-rates = <250000000>, <100000000>, 1880 <10000000>; 1881 num-ib-windows = <4>; 1882 num-ob-windows = <4>; 1883 status = "disabled"; 1884 }; 1885 1886 gic: interrupt-controller@38800000 { 1887 compatible = "arm,gic-v3"; 1888 reg = <0x38800000 0x10000>, /* GIC Dist */ 1889 <0x38880000 0xc0000>, /* GICR */ 1890 <0x31000000 0x2000>, /* GICC */ 1891 <0x31010000 0x2000>, /* GICV */ 1892 <0x31020000 0x2000>; /* GICH */ 1893 #address-cells = <0>; 1894 #interrupt-cells = <3>; 1895 interrupt-controller; 1896 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1897 interrupt-parent = <&gic>; 1898 }; 1899 1900 ddrc: memory-controller@3d400000 { 1901 compatible = "fsl,imx8mq-ddrc", "fsl,imx8m-ddrc"; 1902 reg = <0x3d400000 0x400000>; 1903 clock-names = "core", "pll", "alt", "apb"; 1904 clocks = <&clk IMX8MQ_CLK_DRAM_CORE>, 1905 <&clk IMX8MQ_DRAM_PLL_OUT>, 1906 <&clk IMX8MQ_CLK_DRAM_ALT>, 1907 <&clk IMX8MQ_CLK_DRAM_APB>; 1908 status = "disabled"; 1909 }; 1910 1911 ddr-pmu@3d800000 { 1912 compatible = "fsl,imx8mq-ddr-pmu", "fsl,imx8m-ddr-pmu"; 1913 reg = <0x3d800000 0x400000>; 1914 interrupt-parent = <&gic>; 1915 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 1916 }; 1917 }; 1918};
~/
Read-only file preview.