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imx8mp.dtsi
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linux-6.19.14/arch/arm64/boot/dts/freescale/imx8mp.dtsi
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6#include <dt-bindings/clock/imx8mp-clock.h> 7#include <dt-bindings/power/imx8mp-power.h> 8#include <dt-bindings/reset/imx8mp-reset.h> 9#include <dt-bindings/reset/imx8mp-reset-audiomix.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/input/input.h> 12#include <dt-bindings/interconnect/fsl,imx8mp.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/thermal/thermal.h> 15 16#include "imx8mp-aipstz.h" 17#include "imx8mp-pinfunc.h" 18 19/ { 20 interrupt-parent = <&gic>; 21 #address-cells = <2>; 22 #size-cells = <2>; 23 24 aliases { 25 ethernet0 = &fec; 26 ethernet1 = &eqos; 27 gpio0 = &gpio1; 28 gpio1 = &gpio2; 29 gpio2 = &gpio3; 30 gpio3 = &gpio4; 31 gpio4 = &gpio5; 32 i2c0 = &i2c1; 33 i2c1 = &i2c2; 34 i2c2 = &i2c3; 35 i2c3 = &i2c4; 36 i2c4 = &i2c5; 37 i2c5 = &i2c6; 38 mmc0 = &usdhc1; 39 mmc1 = &usdhc2; 40 mmc2 = &usdhc3; 41 serial0 = &uart1; 42 serial1 = &uart2; 43 serial2 = &uart3; 44 serial3 = &uart4; 45 spi0 = &flexspi; 46 }; 47 48 cpus { 49 #address-cells = <1>; 50 #size-cells = <0>; 51 52 idle-states { 53 entry-method = "psci"; 54 55 cpu_pd_wait: cpu-pd-wait { 56 compatible = "arm,idle-state"; 57 arm,psci-suspend-param = <0x0010033>; 58 local-timer-stop; 59 entry-latency-us = <1000>; 60 exit-latency-us = <700>; 61 min-residency-us = <2700>; 62 wakeup-latency-us = <1500>; 63 }; 64 }; 65 66 A53_0: cpu@0 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a53"; 69 reg = <0x0>; 70 clocks = <&clk IMX8MP_CLK_ARM>; 71 enable-method = "psci"; 72 i-cache-size = <0x8000>; 73 i-cache-line-size = <64>; 74 i-cache-sets = <256>; 75 d-cache-size = <0x8000>; 76 d-cache-line-size = <64>; 77 d-cache-sets = <128>; 78 next-level-cache = <&A53_L2>; 79 nvmem-cells = <&cpu_speed_grade>; 80 nvmem-cell-names = "speed_grade"; 81 operating-points-v2 = <&a53_opp_table>; 82 #cooling-cells = <2>; 83 cpu-idle-states = <&cpu_pd_wait>; 84 85 cpu0_therm: thermal-idle { 86 #cooling-cells = <2>; 87 duration-us = <10000>; 88 exit-latency-us = <700>; 89 }; 90 }; 91 92 A53_1: cpu@1 { 93 device_type = "cpu"; 94 compatible = "arm,cortex-a53"; 95 reg = <0x1>; 96 clocks = <&clk IMX8MP_CLK_ARM>; 97 enable-method = "psci"; 98 i-cache-size = <0x8000>; 99 i-cache-line-size = <64>; 100 i-cache-sets = <256>; 101 d-cache-size = <0x8000>; 102 d-cache-line-size = <64>; 103 d-cache-sets = <128>; 104 next-level-cache = <&A53_L2>; 105 operating-points-v2 = <&a53_opp_table>; 106 #cooling-cells = <2>; 107 cpu-idle-states = <&cpu_pd_wait>; 108 109 cpu1_therm: thermal-idle { 110 #cooling-cells = <2>; 111 duration-us = <10000>; 112 exit-latency-us = <700>; 113 }; 114 }; 115 116 A53_2: cpu@2 { 117 device_type = "cpu"; 118 compatible = "arm,cortex-a53"; 119 reg = <0x2>; 120 clocks = <&clk IMX8MP_CLK_ARM>; 121 enable-method = "psci"; 122 i-cache-size = <0x8000>; 123 i-cache-line-size = <64>; 124 i-cache-sets = <256>; 125 d-cache-size = <0x8000>; 126 d-cache-line-size = <64>; 127 d-cache-sets = <128>; 128 next-level-cache = <&A53_L2>; 129 operating-points-v2 = <&a53_opp_table>; 130 #cooling-cells = <2>; 131 cpu-idle-states = <&cpu_pd_wait>; 132 133 cpu2_therm: thermal-idle { 134 #cooling-cells = <2>; 135 duration-us = <10000>; 136 exit-latency-us = <700>; 137 }; 138 }; 139 140 A53_3: cpu@3 { 141 device_type = "cpu"; 142 compatible = "arm,cortex-a53"; 143 reg = <0x3>; 144 clocks = <&clk IMX8MP_CLK_ARM>; 145 enable-method = "psci"; 146 i-cache-size = <0x8000>; 147 i-cache-line-size = <64>; 148 i-cache-sets = <256>; 149 d-cache-size = <0x8000>; 150 d-cache-line-size = <64>; 151 d-cache-sets = <128>; 152 next-level-cache = <&A53_L2>; 153 operating-points-v2 = <&a53_opp_table>; 154 #cooling-cells = <2>; 155 cpu-idle-states = <&cpu_pd_wait>; 156 157 cpu3_therm: thermal-idle { 158 #cooling-cells = <2>; 159 duration-us = <10000>; 160 exit-latency-us = <700>; 161 }; 162 }; 163 164 A53_L2: l2-cache0 { 165 compatible = "cache"; 166 cache-unified; 167 cache-level = <2>; 168 cache-size = <0x80000>; 169 cache-line-size = <64>; 170 cache-sets = <512>; 171 }; 172 }; 173 174 a53_opp_table: opp-table { 175 compatible = "operating-points-v2"; 176 opp-shared; 177 178 opp-1200000000 { 179 opp-hz = /bits/ 64 <1200000000>; 180 opp-microvolt = <850000>; 181 opp-supported-hw = <0x8a0>, <0x7>; 182 clock-latency-ns = <150000>; 183 opp-suspend; 184 }; 185 186 opp-1600000000 { 187 opp-hz = /bits/ 64 <1600000000>; 188 opp-microvolt = <950000>; 189 opp-supported-hw = <0xa0>, <0x7>; 190 clock-latency-ns = <150000>; 191 opp-suspend; 192 }; 193 194 opp-1800000000 { 195 opp-hz = /bits/ 64 <1800000000>; 196 opp-microvolt = <1000000>; 197 opp-supported-hw = <0x20>, <0x3>; 198 clock-latency-ns = <150000>; 199 opp-suspend; 200 }; 201 }; 202 203 osc_32k: clock-osc-32k { 204 compatible = "fixed-clock"; 205 #clock-cells = <0>; 206 clock-frequency = <32768>; 207 clock-output-names = "osc_32k"; 208 }; 209 210 osc_24m: clock-osc-24m { 211 compatible = "fixed-clock"; 212 #clock-cells = <0>; 213 clock-frequency = <24000000>; 214 clock-output-names = "osc_24m"; 215 }; 216 217 clk_ext1: clock-ext1 { 218 compatible = "fixed-clock"; 219 #clock-cells = <0>; 220 clock-frequency = <133000000>; 221 clock-output-names = "clk_ext1"; 222 }; 223 224 clk_ext2: clock-ext2 { 225 compatible = "fixed-clock"; 226 #clock-cells = <0>; 227 clock-frequency = <133000000>; 228 clock-output-names = "clk_ext2"; 229 }; 230 231 clk_ext3: clock-ext3 { 232 compatible = "fixed-clock"; 233 #clock-cells = <0>; 234 clock-frequency = <133000000>; 235 clock-output-names = "clk_ext3"; 236 }; 237 238 clk_ext4: clock-ext4 { 239 compatible = "fixed-clock"; 240 #clock-cells = <0>; 241 clock-frequency = <133000000>; 242 clock-output-names = "clk_ext4"; 243 }; 244 245 funnel { 246 /* 247 * non-configurable funnel don't show up on the AMBA 248 * bus. As such no need to add "arm,primecell". 249 */ 250 compatible = "arm,coresight-static-funnel"; 251 252 in-ports { 253 #address-cells = <1>; 254 #size-cells = <0>; 255 256 port@0 { 257 reg = <0>; 258 259 ca_funnel_in_port0: endpoint { 260 remote-endpoint = <&etm0_out_port>; 261 }; 262 }; 263 264 port@1 { 265 reg = <1>; 266 267 ca_funnel_in_port1: endpoint { 268 remote-endpoint = <&etm1_out_port>; 269 }; 270 }; 271 272 port@2 { 273 reg = <2>; 274 275 ca_funnel_in_port2: endpoint { 276 remote-endpoint = <&etm2_out_port>; 277 }; 278 }; 279 280 port@3 { 281 reg = <3>; 282 283 ca_funnel_in_port3: endpoint { 284 remote-endpoint = <&etm3_out_port>; 285 }; 286 }; 287 }; 288 289 out-ports { 290 port { 291 292 ca_funnel_out_port0: endpoint { 293 remote-endpoint = <&hugo_funnel_in_port0>; 294 }; 295 }; 296 }; 297 }; 298 299 reserved-memory { 300 #address-cells = <2>; 301 #size-cells = <2>; 302 ranges; 303 304 dsp_reserved: dsp@92400000 { 305 reg = <0 0x92400000 0 0x1000000>; 306 no-map; 307 status = "disabled"; 308 }; 309 }; 310 311 pmu { 312 compatible = "arm,cortex-a53-pmu"; 313 interrupts = <GIC_PPI 7 314 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 315 }; 316 317 psci { 318 compatible = "arm,psci-1.0"; 319 method = "smc"; 320 }; 321 322 thermal-zones { 323 cpu-thermal { 324 polling-delay-passive = <250>; 325 polling-delay = <2000>; 326 thermal-sensors = <&tmu 1>; 327 trips { 328 cpu_alert0: trip0 { 329 temperature = <85000>; 330 hysteresis = <2000>; 331 type = "passive"; 332 }; 333 334 cpu_crit0: trip1 { 335 temperature = <95000>; 336 hysteresis = <2000>; 337 type = "critical"; 338 }; 339 }; 340 341 cooling-maps { 342 map0 { 343 trip = <&cpu_alert0>; 344 cooling-device = 345 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 346 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 347 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 348 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 349 <&gpu3d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 350 <&gpu2d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 351 <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 352 <&cpu0_therm 0 50>, 353 <&cpu1_therm 0 50>, 354 <&cpu2_therm 0 50>, 355 <&cpu3_therm 0 50>; 356 }; 357 }; 358 }; 359 360 soc-thermal { 361 polling-delay-passive = <250>; 362 polling-delay = <2000>; 363 thermal-sensors = <&tmu 0>; 364 trips { 365 soc_alert0: trip0 { 366 temperature = <85000>; 367 hysteresis = <2000>; 368 type = "passive"; 369 }; 370 371 soc_crit0: trip1 { 372 temperature = <95000>; 373 hysteresis = <2000>; 374 type = "critical"; 375 }; 376 }; 377 378 cooling-maps { 379 map0 { 380 trip = <&soc_alert0>; 381 cooling-device = 382 <&A53_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 383 <&A53_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 384 <&A53_2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 385 <&A53_3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 386 <&gpu3d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 387 <&gpu2d THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 388 <&npu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 389 <&cpu0_therm 0 50>, 390 <&cpu1_therm 0 50>, 391 <&cpu2_therm 0 50>, 392 <&cpu3_therm 0 50>; 393 }; 394 }; 395 }; 396 }; 397 398 timer { 399 compatible = "arm,armv8-timer"; 400 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 401 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 402 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 403 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 404 clock-frequency = <8000000>; 405 arm,no-tick-in-suspend; 406 }; 407 408 soc: soc@0 { 409 compatible = "fsl,imx8mp-soc", "simple-bus"; 410 #address-cells = <1>; 411 #size-cells = <1>; 412 ranges = <0x0 0x0 0x0 0x3e000000>; 413 nvmem-cells = <&imx8mp_uid>; 414 nvmem-cell-names = "soc_unique_id"; 415 416 etm0: etm@28440000 { 417 compatible = "arm,coresight-etm4x", "arm,primecell"; 418 reg = <0x28440000 0x1000>; 419 cpu = <&A53_0>; 420 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 421 clock-names = "apb_pclk"; 422 423 out-ports { 424 port { 425 etm0_out_port: endpoint { 426 remote-endpoint = <&ca_funnel_in_port0>; 427 }; 428 }; 429 }; 430 }; 431 432 etm1: etm@28540000 { 433 compatible = "arm,coresight-etm4x", "arm,primecell"; 434 reg = <0x28540000 0x1000>; 435 cpu = <&A53_1>; 436 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 437 clock-names = "apb_pclk"; 438 439 out-ports { 440 port { 441 etm1_out_port: endpoint { 442 remote-endpoint = <&ca_funnel_in_port1>; 443 }; 444 }; 445 }; 446 }; 447 448 etm2: etm@28640000 { 449 compatible = "arm,coresight-etm4x", "arm,primecell"; 450 reg = <0x28640000 0x1000>; 451 cpu = <&A53_2>; 452 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 453 clock-names = "apb_pclk"; 454 455 out-ports { 456 port { 457 etm2_out_port: endpoint { 458 remote-endpoint = <&ca_funnel_in_port2>; 459 }; 460 }; 461 }; 462 }; 463 464 etm3: etm@28740000 { 465 compatible = "arm,coresight-etm4x", "arm,primecell"; 466 reg = <0x28740000 0x1000>; 467 cpu = <&A53_3>; 468 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 469 clock-names = "apb_pclk"; 470 471 out-ports { 472 port { 473 etm3_out_port: endpoint { 474 remote-endpoint = <&ca_funnel_in_port3>; 475 }; 476 }; 477 }; 478 }; 479 480 funnel@28c03000 { 481 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 482 reg = <0x28c03000 0x1000>; 483 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 484 clock-names = "apb_pclk"; 485 486 in-ports { 487 #address-cells = <1>; 488 #size-cells = <0>; 489 490 port@0 { 491 reg = <0>; 492 493 hugo_funnel_in_port0: endpoint { 494 remote-endpoint = <&ca_funnel_out_port0>; 495 }; 496 }; 497 498 port@1 { 499 reg = <1>; 500 501 hugo_funnel_in_port1: endpoint { 502 /* M7 input */ 503 }; 504 }; 505 506 port@2 { 507 reg = <2>; 508 509 hugo_funnel_in_port2: endpoint { 510 /* DSP input */ 511 }; 512 }; 513 /* the other input ports are not connect to anything */ 514 }; 515 516 out-ports { 517 port { 518 hugo_funnel_out_port0: endpoint { 519 remote-endpoint = <&etf_in_port>; 520 }; 521 }; 522 }; 523 }; 524 525 etf@28c04000 { 526 compatible = "arm,coresight-tmc", "arm,primecell"; 527 reg = <0x28c04000 0x1000>; 528 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 529 clock-names = "apb_pclk"; 530 531 in-ports { 532 port { 533 etf_in_port: endpoint { 534 remote-endpoint = <&hugo_funnel_out_port0>; 535 }; 536 }; 537 }; 538 539 out-ports { 540 port { 541 etf_out_port: endpoint { 542 remote-endpoint = <&etr_in_port>; 543 }; 544 }; 545 }; 546 }; 547 548 etr@28c06000 { 549 compatible = "arm,coresight-tmc", "arm,primecell"; 550 reg = <0x28c06000 0x1000>; 551 clocks = <&clk IMX8MP_CLK_MAIN_AXI>; 552 clock-names = "apb_pclk"; 553 554 in-ports { 555 port { 556 etr_in_port: endpoint { 557 remote-endpoint = <&etf_out_port>; 558 }; 559 }; 560 }; 561 }; 562 563 aips1: bus@30000000 { 564 compatible = "fsl,aips-bus", "simple-bus"; 565 reg = <0x30000000 0x400000>; 566 #address-cells = <1>; 567 #size-cells = <1>; 568 ranges; 569 570 gpio1: gpio@30200000 { 571 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 572 reg = <0x30200000 0x10000>; 573 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>, 574 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 575 clocks = <&clk IMX8MP_CLK_GPIO1_ROOT>; 576 gpio-controller; 577 #gpio-cells = <2>; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 gpio-ranges = <&iomuxc 0 5 30>; 581 }; 582 583 gpio2: gpio@30210000 { 584 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 585 reg = <0x30210000 0x10000>; 586 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 587 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 588 clocks = <&clk IMX8MP_CLK_GPIO2_ROOT>; 589 gpio-controller; 590 #gpio-cells = <2>; 591 interrupt-controller; 592 #interrupt-cells = <2>; 593 gpio-ranges = <&iomuxc 0 35 21>; 594 }; 595 596 gpio3: gpio@30220000 { 597 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 598 reg = <0x30220000 0x10000>; 599 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&clk IMX8MP_CLK_GPIO3_ROOT>; 602 gpio-controller; 603 #gpio-cells = <2>; 604 interrupt-controller; 605 #interrupt-cells = <2>; 606 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>; 607 }; 608 609 gpio4: gpio@30230000 { 610 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 611 reg = <0x30230000 0x10000>; 612 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, 613 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 614 clocks = <&clk IMX8MP_CLK_GPIO4_ROOT>; 615 gpio-controller; 616 #gpio-cells = <2>; 617 interrupt-controller; 618 #interrupt-cells = <2>; 619 gpio-ranges = <&iomuxc 0 82 32>; 620 }; 621 622 gpio5: gpio@30240000 { 623 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio"; 624 reg = <0x30240000 0x10000>; 625 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, 626 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 627 clocks = <&clk IMX8MP_CLK_GPIO5_ROOT>; 628 gpio-controller; 629 #gpio-cells = <2>; 630 interrupt-controller; 631 #interrupt-cells = <2>; 632 gpio-ranges = <&iomuxc 0 114 30>; 633 }; 634 635 tmu: tmu@30260000 { 636 compatible = "fsl,imx8mp-tmu"; 637 reg = <0x30260000 0x10000>; 638 clocks = <&clk IMX8MP_CLK_TSENSOR_ROOT>; 639 nvmem-cells = <&tmu_calib>; 640 nvmem-cell-names = "calib"; 641 #thermal-sensor-cells = <1>; 642 }; 643 644 wdog1: watchdog@30280000 { 645 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 646 reg = <0x30280000 0x10000>; 647 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 648 clocks = <&clk IMX8MP_CLK_WDOG1_ROOT>; 649 status = "disabled"; 650 }; 651 652 wdog2: watchdog@30290000 { 653 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 654 reg = <0x30290000 0x10000>; 655 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 656 clocks = <&clk IMX8MP_CLK_WDOG2_ROOT>; 657 status = "disabled"; 658 }; 659 660 wdog3: watchdog@302a0000 { 661 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt"; 662 reg = <0x302a0000 0x10000>; 663 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 664 clocks = <&clk IMX8MP_CLK_WDOG3_ROOT>; 665 status = "disabled"; 666 }; 667 668 gpt1: timer@302d0000 { 669 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 670 reg = <0x302d0000 0x10000>; 671 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 672 clocks = <&clk IMX8MP_CLK_GPT1_ROOT>, <&clk IMX8MP_CLK_GPT1>; 673 clock-names = "ipg", "per"; 674 }; 675 676 gpt2: timer@302e0000 { 677 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 678 reg = <0x302e0000 0x10000>; 679 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 680 clocks = <&clk IMX8MP_CLK_GPT2_ROOT>, <&clk IMX8MP_CLK_GPT2>; 681 clock-names = "ipg", "per"; 682 }; 683 684 gpt3: timer@302f0000 { 685 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 686 reg = <0x302f0000 0x10000>; 687 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 688 clocks = <&clk IMX8MP_CLK_GPT3_ROOT>, <&clk IMX8MP_CLK_GPT3>; 689 clock-names = "ipg", "per"; 690 }; 691 692 iomuxc: pinctrl@30330000 { 693 compatible = "fsl,imx8mp-iomuxc"; 694 reg = <0x30330000 0x10000>; 695 }; 696 697 gpr: syscon@30340000 { 698 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon"; 699 reg = <0x30340000 0x10000>; 700 }; 701 702 ocotp: efuse@30350000 { 703 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon"; 704 reg = <0x30350000 0x10000>; 705 clocks = <&clk IMX8MP_CLK_OCOTP_ROOT>; 706 /* For nvmem subnodes */ 707 #address-cells = <1>; 708 #size-cells = <1>; 709 710 /* 711 * The register address below maps to the MX8M 712 * Fusemap Description Table entries this way. 713 * Assuming 714 * reg = <ADDR SIZE>; 715 * then 716 * Fuse Address = (ADDR * 4) + 0x400 717 * Note that if SIZE is greater than 4, then 718 * each subsequent fuse is located at offset 719 * +0x10 in Fusemap Description Table (e.g. 720 * reg = <0x8 0x8> describes fuses 0x420 and 721 * 0x430). 722 */ 723 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */ 724 reg = <0x8 0x8>; 725 }; 726 727 cpu_speed_grade: speed-grade@10 { /* 0x440 */ 728 reg = <0x10 4>; 729 }; 730 731 eth_mac1: mac-address@90 { /* 0x640 */ 732 reg = <0x90 6>; 733 }; 734 735 eth_mac2: mac-address@96 { /* 0x658 */ 736 reg = <0x96 6>; 737 }; 738 739 tmu_calib: calib@264 { /* 0xd90-0xdc0 */ 740 reg = <0x264 0x10>; 741 }; 742 }; 743 744 anatop: clock-controller@30360000 { 745 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop"; 746 reg = <0x30360000 0x10000>; 747 #clock-cells = <1>; 748 }; 749 750 snvs: snvs@30370000 { 751 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd"; 752 reg = <0x30370000 0x10000>; 753 754 snvs_rtc: snvs-rtc-lp { 755 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 756 regmap = <&snvs>; 757 offset = <0x34>; 758 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 761 clock-names = "snvs-rtc"; 762 }; 763 764 snvs_pwrkey: snvs-powerkey { 765 compatible = "fsl,sec-v4.0-pwrkey"; 766 regmap = <&snvs>; 767 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 768 clocks = <&clk IMX8MP_CLK_SNVS_ROOT>; 769 clock-names = "snvs-pwrkey"; 770 linux,keycode = <KEY_POWER>; 771 wakeup-source; 772 status = "disabled"; 773 }; 774 775 snvs_lpgpr: snvs-lpgpr { 776 compatible = "fsl,imx8mp-snvs-lpgpr", 777 "fsl,imx7d-snvs-lpgpr"; 778 }; 779 }; 780 781 clk: clock-controller@30380000 { 782 compatible = "fsl,imx8mp-ccm"; 783 reg = <0x30380000 0x10000>; 784 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 786 #clock-cells = <1>; 787 clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, 788 <&clk_ext3>, <&clk_ext4>; 789 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2", 790 "clk_ext3", "clk_ext4"; 791 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>, 792 <&clk IMX8MP_CLK_A53_CORE>, 793 <&clk IMX8MP_CLK_NOC>, 794 <&clk IMX8MP_CLK_NOC_IO>, 795 <&clk IMX8MP_CLK_GIC>; 796 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 797 <&clk IMX8MP_ARM_PLL_OUT>, 798 <&clk IMX8MP_SYS_PLL2_1000M>, 799 <&clk IMX8MP_SYS_PLL1_800M>, 800 <&clk IMX8MP_SYS_PLL2_500M>; 801 assigned-clock-rates = <0>, <0>, 802 <1000000000>, 803 <800000000>, 804 <500000000>; 805 }; 806 807 src: reset-controller@30390000 { 808 compatible = "fsl,imx8mp-src", "syscon"; 809 reg = <0x30390000 0x10000>; 810 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 811 #reset-cells = <1>; 812 }; 813 814 gpc: gpc@303a0000 { 815 compatible = "fsl,imx8mp-gpc"; 816 reg = <0x303a0000 0x1000>; 817 interrupt-parent = <&gic>; 818 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 819 interrupt-controller; 820 #interrupt-cells = <3>; 821 822 pgc { 823 #address-cells = <1>; 824 #size-cells = <0>; 825 826 pgc_mipi_phy1: power-domain@0 { 827 #power-domain-cells = <0>; 828 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY1>; 829 }; 830 831 pgc_pcie_phy: power-domain@1 { 832 #power-domain-cells = <0>; 833 reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>; 834 }; 835 836 pgc_usb1_phy: power-domain@2 { 837 #power-domain-cells = <0>; 838 reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>; 839 }; 840 841 pgc_usb2_phy: power-domain@3 { 842 #power-domain-cells = <0>; 843 reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>; 844 }; 845 846 pgc_mlmix: power-domain@4 { 847 #power-domain-cells = <0>; 848 reg = <IMX8MP_POWER_DOMAIN_MLMIX>; 849 clocks = <&clk IMX8MP_CLK_ML_AXI>, 850 <&clk IMX8MP_CLK_ML_AHB>, 851 <&clk IMX8MP_CLK_NPU_ROOT>; 852 assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, 853 <&clk IMX8MP_CLK_ML_AXI>, 854 <&clk IMX8MP_CLK_ML_AHB>; 855 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 856 <&clk IMX8MP_SYS_PLL1_800M>, 857 <&clk IMX8MP_SYS_PLL1_800M>; 858 assigned-clock-rates = <1000000000>, 859 <800000000>, 860 <400000000>; 861 }; 862 863 pgc_audio: power-domain@5 { 864 #power-domain-cells = <0>; 865 reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; 866 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 867 <&clk IMX8MP_CLK_AUDIO_AXI>; 868 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, 869 <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; 870 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 871 <&clk IMX8MP_SYS_PLL1_800M>; 872 assigned-clock-rates = <400000000>, 873 <800000000>; 874 }; 875 876 pgc_gpu2d: power-domain@6 { 877 #power-domain-cells = <0>; 878 reg = <IMX8MP_POWER_DOMAIN_GPU2D>; 879 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>; 880 power-domains = <&pgc_gpumix>; 881 }; 882 883 pgc_gpumix: power-domain@7 { 884 #power-domain-cells = <0>; 885 reg = <IMX8MP_POWER_DOMAIN_GPUMIX>; 886 clocks = <&clk IMX8MP_CLK_GPU_ROOT>, 887 <&clk IMX8MP_CLK_GPU_AHB>; 888 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>, 889 <&clk IMX8MP_CLK_GPU_AHB>; 890 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 891 <&clk IMX8MP_SYS_PLL1_800M>; 892 assigned-clock-rates = <800000000>, <400000000>; 893 }; 894 895 pgc_vpumix: power-domain@8 { 896 #power-domain-cells = <0>; 897 reg = <IMX8MP_POWER_DOMAIN_VPUMIX>; 898 clocks = <&clk IMX8MP_CLK_VPU_ROOT>; 899 }; 900 901 pgc_gpu3d: power-domain@9 { 902 #power-domain-cells = <0>; 903 reg = <IMX8MP_POWER_DOMAIN_GPU3D>; 904 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 905 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 906 power-domains = <&pgc_gpumix>; 907 }; 908 909 pgc_mediamix: power-domain@10 { 910 #power-domain-cells = <0>; 911 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX>; 912 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 913 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 914 }; 915 916 pgc_vpu_g1: power-domain@11 { 917 #power-domain-cells = <0>; 918 reg = <IMX8MP_POWER_DOMAIN_VPU_G1>; 919 }; 920 921 pgc_vpu_g2: power-domain@12 { 922 #power-domain-cells = <0>; 923 reg = <IMX8MP_POWER_DOMAIN_VPU_G2>; 924 }; 925 926 pgc_vpu_vc8000e: power-domain@13 { 927 #power-domain-cells = <0>; 928 reg = <IMX8MP_POWER_DOMAIN_VPU_VC8000E>; 929 }; 930 931 pgc_hdmimix: power-domain@14 { 932 #power-domain-cells = <0>; 933 reg = <IMX8MP_POWER_DOMAIN_HDMIMIX>; 934 clocks = <&clk IMX8MP_CLK_HDMI_ROOT>, 935 <&clk IMX8MP_CLK_HDMI_APB>; 936 assigned-clocks = <&clk IMX8MP_CLK_HDMI_AXI>, 937 <&clk IMX8MP_CLK_HDMI_APB>; 938 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>, 939 <&clk IMX8MP_SYS_PLL1_133M>; 940 assigned-clock-rates = <500000000>, <133000000>; 941 }; 942 943 pgc_hdmi_phy: power-domain@15 { 944 #power-domain-cells = <0>; 945 reg = <IMX8MP_POWER_DOMAIN_HDMI_PHY>; 946 }; 947 948 pgc_mipi_phy2: power-domain@16 { 949 #power-domain-cells = <0>; 950 reg = <IMX8MP_POWER_DOMAIN_MIPI_PHY2>; 951 }; 952 953 pgc_hsiomix: power-domain@17 { 954 #power-domain-cells = <0>; 955 reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>; 956 clocks = <&clk IMX8MP_CLK_HSIO_AXI>, 957 <&clk IMX8MP_CLK_HSIO_ROOT>; 958 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>; 959 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>; 960 assigned-clock-rates = <500000000>; 961 }; 962 963 pgc_ispdwp: power-domain@18 { 964 #power-domain-cells = <0>; 965 reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; 966 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>; 967 }; 968 }; 969 }; 970 }; 971 972 aips2: bus@30400000 { 973 compatible = "fsl,aips-bus", "simple-bus"; 974 reg = <0x30400000 0x400000>; 975 #address-cells = <1>; 976 #size-cells = <1>; 977 ranges; 978 979 pwm1: pwm@30660000 { 980 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 981 reg = <0x30660000 0x10000>; 982 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 983 clocks = <&clk IMX8MP_CLK_PWM1_ROOT>, 984 <&clk IMX8MP_CLK_PWM1_ROOT>; 985 clock-names = "ipg", "per"; 986 #pwm-cells = <3>; 987 status = "disabled"; 988 }; 989 990 pwm2: pwm@30670000 { 991 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 992 reg = <0x30670000 0x10000>; 993 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 994 clocks = <&clk IMX8MP_CLK_PWM2_ROOT>, 995 <&clk IMX8MP_CLK_PWM2_ROOT>; 996 clock-names = "ipg", "per"; 997 #pwm-cells = <3>; 998 status = "disabled"; 999 }; 1000 1001 pwm3: pwm@30680000 { 1002 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 1003 reg = <0x30680000 0x10000>; 1004 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 1005 clocks = <&clk IMX8MP_CLK_PWM3_ROOT>, 1006 <&clk IMX8MP_CLK_PWM3_ROOT>; 1007 clock-names = "ipg", "per"; 1008 #pwm-cells = <3>; 1009 status = "disabled"; 1010 }; 1011 1012 pwm4: pwm@30690000 { 1013 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm"; 1014 reg = <0x30690000 0x10000>; 1015 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 1016 clocks = <&clk IMX8MP_CLK_PWM4_ROOT>, 1017 <&clk IMX8MP_CLK_PWM4_ROOT>; 1018 clock-names = "ipg", "per"; 1019 #pwm-cells = <3>; 1020 status = "disabled"; 1021 }; 1022 1023 system_counter: timer@306a0000 { 1024 compatible = "nxp,sysctr-timer"; 1025 reg = <0x306a0000 0x20000>; 1026 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1027 clocks = <&osc_24m>; 1028 clock-names = "per"; 1029 }; 1030 1031 gpt6: timer@306e0000 { 1032 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1033 reg = <0x306e0000 0x10000>; 1034 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1035 clocks = <&clk IMX8MP_CLK_GPT6_ROOT>, <&clk IMX8MP_CLK_GPT6>; 1036 clock-names = "ipg", "per"; 1037 }; 1038 1039 gpt5: timer@306f0000 { 1040 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1041 reg = <0x306f0000 0x10000>; 1042 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1043 clocks = <&clk IMX8MP_CLK_GPT5_ROOT>, <&clk IMX8MP_CLK_GPT5>; 1044 clock-names = "ipg", "per"; 1045 }; 1046 1047 gpt4: timer@30700000 { 1048 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt"; 1049 reg = <0x30700000 0x10000>; 1050 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1051 clocks = <&clk IMX8MP_CLK_GPT4_ROOT>, <&clk IMX8MP_CLK_GPT4>; 1052 clock-names = "ipg", "per"; 1053 }; 1054 }; 1055 1056 aips3: bus@30800000 { 1057 compatible = "fsl,aips-bus", "simple-bus"; 1058 reg = <0x30800000 0x400000>; 1059 #address-cells = <1>; 1060 #size-cells = <1>; 1061 ranges; 1062 1063 spba-bus@30800000 { 1064 compatible = "fsl,spba-bus", "simple-bus"; 1065 reg = <0x30800000 0x100000>; 1066 #address-cells = <1>; 1067 #size-cells = <1>; 1068 ranges; 1069 1070 ecspi1: spi@30820000 { 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1074 reg = <0x30820000 0x10000>; 1075 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 1076 clocks = <&clk IMX8MP_CLK_ECSPI1_ROOT>, 1077 <&clk IMX8MP_CLK_ECSPI1_ROOT>; 1078 clock-names = "ipg", "per"; 1079 assigned-clock-rates = <80000000>; 1080 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>; 1081 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1082 dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>; 1083 dma-names = "rx", "tx"; 1084 status = "disabled"; 1085 }; 1086 1087 ecspi2: spi@30830000 { 1088 #address-cells = <1>; 1089 #size-cells = <0>; 1090 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1091 reg = <0x30830000 0x10000>; 1092 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 1093 clocks = <&clk IMX8MP_CLK_ECSPI2_ROOT>, 1094 <&clk IMX8MP_CLK_ECSPI2_ROOT>; 1095 clock-names = "ipg", "per"; 1096 assigned-clock-rates = <80000000>; 1097 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>; 1098 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1099 dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>; 1100 dma-names = "rx", "tx"; 1101 status = "disabled"; 1102 }; 1103 1104 ecspi3: spi@30840000 { 1105 #address-cells = <1>; 1106 #size-cells = <0>; 1107 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi"; 1108 reg = <0x30840000 0x10000>; 1109 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 1110 clocks = <&clk IMX8MP_CLK_ECSPI3_ROOT>, 1111 <&clk IMX8MP_CLK_ECSPI3_ROOT>; 1112 clock-names = "ipg", "per"; 1113 assigned-clock-rates = <80000000>; 1114 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>; 1115 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 1116 dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>; 1117 dma-names = "rx", "tx"; 1118 status = "disabled"; 1119 }; 1120 1121 uart1: serial@30860000 { 1122 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1123 reg = <0x30860000 0x10000>; 1124 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1125 clocks = <&clk IMX8MP_CLK_UART1_ROOT>, 1126 <&clk IMX8MP_CLK_UART1_ROOT>; 1127 clock-names = "ipg", "per"; 1128 dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>; 1129 dma-names = "rx", "tx"; 1130 status = "disabled"; 1131 }; 1132 1133 uart3: serial@30880000 { 1134 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1135 reg = <0x30880000 0x10000>; 1136 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1137 clocks = <&clk IMX8MP_CLK_UART3_ROOT>, 1138 <&clk IMX8MP_CLK_UART3_ROOT>; 1139 clock-names = "ipg", "per"; 1140 dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>; 1141 dma-names = "rx", "tx"; 1142 status = "disabled"; 1143 }; 1144 1145 uart2: serial@30890000 { 1146 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1147 reg = <0x30890000 0x10000>; 1148 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1149 clocks = <&clk IMX8MP_CLK_UART2_ROOT>, 1150 <&clk IMX8MP_CLK_UART2_ROOT>; 1151 clock-names = "ipg", "per"; 1152 dmas = <&sdma1 24 4 0>, <&sdma1 25 4 0>; 1153 dma-names = "rx", "tx"; 1154 status = "disabled"; 1155 }; 1156 1157 flexcan1: can@308c0000 { 1158 compatible = "fsl,imx8mp-flexcan"; 1159 reg = <0x308c0000 0x10000>; 1160 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 1161 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1162 <&clk IMX8MP_CLK_CAN1_ROOT>; 1163 clock-names = "ipg", "per"; 1164 assigned-clocks = <&clk IMX8MP_CLK_CAN1>; 1165 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1166 assigned-clock-rates = <40000000>; 1167 fsl,clk-source = /bits/ 8 <0>; 1168 fsl,stop-mode = <&gpr 0x10 4>; 1169 status = "disabled"; 1170 }; 1171 1172 flexcan2: can@308d0000 { 1173 compatible = "fsl,imx8mp-flexcan"; 1174 reg = <0x308d0000 0x10000>; 1175 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 1176 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1177 <&clk IMX8MP_CLK_CAN2_ROOT>; 1178 clock-names = "ipg", "per"; 1179 assigned-clocks = <&clk IMX8MP_CLK_CAN2>; 1180 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>; 1181 assigned-clock-rates = <40000000>; 1182 fsl,clk-source = /bits/ 8 <0>; 1183 fsl,stop-mode = <&gpr 0x10 5>; 1184 status = "disabled"; 1185 }; 1186 }; 1187 1188 crypto: crypto@30900000 { 1189 compatible = "fsl,sec-v4.0"; 1190 #address-cells = <1>; 1191 #size-cells = <1>; 1192 reg = <0x30900000 0x40000>; 1193 ranges = <0 0x30900000 0x40000>; 1194 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1195 clocks = <&clk IMX8MP_CLK_AHB>, 1196 <&clk IMX8MP_CLK_IPG_ROOT>; 1197 clock-names = "aclk", "ipg"; 1198 1199 sec_jr0: jr@1000 { 1200 compatible = "fsl,sec-v4.0-job-ring"; 1201 reg = <0x1000 0x1000>; 1202 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 1203 status = "disabled"; 1204 }; 1205 1206 sec_jr1: jr@2000 { 1207 compatible = "fsl,sec-v4.0-job-ring"; 1208 reg = <0x2000 0x1000>; 1209 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 1210 }; 1211 1212 sec_jr2: jr@3000 { 1213 compatible = "fsl,sec-v4.0-job-ring"; 1214 reg = <0x3000 0x1000>; 1215 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 1216 }; 1217 }; 1218 1219 i2c1: i2c@30a20000 { 1220 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1221 #address-cells = <1>; 1222 #size-cells = <0>; 1223 reg = <0x30a20000 0x10000>; 1224 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 1225 clocks = <&clk IMX8MP_CLK_I2C1_ROOT>; 1226 status = "disabled"; 1227 }; 1228 1229 i2c2: i2c@30a30000 { 1230 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1231 #address-cells = <1>; 1232 #size-cells = <0>; 1233 reg = <0x30a30000 0x10000>; 1234 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 1235 clocks = <&clk IMX8MP_CLK_I2C2_ROOT>; 1236 status = "disabled"; 1237 }; 1238 1239 i2c3: i2c@30a40000 { 1240 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 reg = <0x30a40000 0x10000>; 1244 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 1245 clocks = <&clk IMX8MP_CLK_I2C3_ROOT>; 1246 status = "disabled"; 1247 }; 1248 1249 i2c4: i2c@30a50000 { 1250 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1251 #address-cells = <1>; 1252 #size-cells = <0>; 1253 reg = <0x30a50000 0x10000>; 1254 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 1255 clocks = <&clk IMX8MP_CLK_I2C4_ROOT>; 1256 status = "disabled"; 1257 }; 1258 1259 uart4: serial@30a60000 { 1260 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart"; 1261 reg = <0x30a60000 0x10000>; 1262 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&clk IMX8MP_CLK_UART4_ROOT>, 1264 <&clk IMX8MP_CLK_UART4_ROOT>; 1265 clock-names = "ipg", "per"; 1266 dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>; 1267 dma-names = "rx", "tx"; 1268 status = "disabled"; 1269 }; 1270 1271 mu: mailbox@30aa0000 { 1272 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1273 reg = <0x30aa0000 0x10000>; 1274 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&clk IMX8MP_CLK_MU_ROOT>; 1276 #mbox-cells = <2>; 1277 }; 1278 1279 mu2: mailbox@30e60000 { 1280 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu"; 1281 reg = <0x30e60000 0x10000>; 1282 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 1283 #mbox-cells = <2>; 1284 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_MU2_ROOT>; 1285 status = "disabled"; 1286 }; 1287 1288 i2c5: i2c@30ad0000 { 1289 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1290 #address-cells = <1>; 1291 #size-cells = <0>; 1292 reg = <0x30ad0000 0x10000>; 1293 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 1294 clocks = <&clk IMX8MP_CLK_I2C5_ROOT>; 1295 status = "disabled"; 1296 }; 1297 1298 i2c6: i2c@30ae0000 { 1299 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c"; 1300 #address-cells = <1>; 1301 #size-cells = <0>; 1302 reg = <0x30ae0000 0x10000>; 1303 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1304 clocks = <&clk IMX8MP_CLK_I2C6_ROOT>; 1305 status = "disabled"; 1306 }; 1307 1308 usdhc1: mmc@30b40000 { 1309 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1310 reg = <0x30b40000 0x10000>; 1311 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1312 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1313 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1314 <&clk IMX8MP_CLK_USDHC1_ROOT>; 1315 clock-names = "ipg", "ahb", "per"; 1316 fsl,tuning-start-tap = <20>; 1317 fsl,tuning-step = <2>; 1318 bus-width = <4>; 1319 status = "disabled"; 1320 }; 1321 1322 usdhc2: mmc@30b50000 { 1323 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1324 reg = <0x30b50000 0x10000>; 1325 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1326 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1327 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1328 <&clk IMX8MP_CLK_USDHC2_ROOT>; 1329 clock-names = "ipg", "ahb", "per"; 1330 fsl,tuning-start-tap = <20>; 1331 fsl,tuning-step = <2>; 1332 bus-width = <4>; 1333 status = "disabled"; 1334 }; 1335 1336 usdhc3: mmc@30b60000 { 1337 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc"; 1338 reg = <0x30b60000 0x10000>; 1339 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1340 clocks = <&clk IMX8MP_CLK_IPG_ROOT>, 1341 <&clk IMX8MP_CLK_NAND_USDHC_BUS>, 1342 <&clk IMX8MP_CLK_USDHC3_ROOT>; 1343 clock-names = "ipg", "ahb", "per"; 1344 fsl,tuning-start-tap = <20>; 1345 fsl,tuning-step = <2>; 1346 bus-width = <4>; 1347 status = "disabled"; 1348 }; 1349 1350 flexspi: spi@30bb0000 { 1351 compatible = "nxp,imx8mp-fspi"; 1352 reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>; 1353 reg-names = "fspi_base", "fspi_mmap"; 1354 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 1355 clocks = <&clk IMX8MP_CLK_QSPI_ROOT>, 1356 <&clk IMX8MP_CLK_QSPI_ROOT>; 1357 clock-names = "fspi_en", "fspi"; 1358 assigned-clock-rates = <80000000>; 1359 assigned-clocks = <&clk IMX8MP_CLK_QSPI>; 1360 #address-cells = <1>; 1361 #size-cells = <0>; 1362 status = "disabled"; 1363 }; 1364 1365 sdma1: dma-controller@30bd0000 { 1366 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1367 reg = <0x30bd0000 0x10000>; 1368 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 1369 clocks = <&clk IMX8MP_CLK_SDMA1_ROOT>, 1370 <&clk IMX8MP_CLK_AHB>; 1371 clock-names = "ipg", "ahb"; 1372 #dma-cells = <3>; 1373 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1374 }; 1375 1376 fec: ethernet@30be0000 { 1377 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec"; 1378 reg = <0x30be0000 0x10000>; 1379 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1380 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1381 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1382 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 1383 clocks = <&clk IMX8MP_CLK_ENET1_ROOT>, 1384 <&clk IMX8MP_CLK_SIM_ENET_ROOT>, 1385 <&clk IMX8MP_CLK_ENET_TIMER>, 1386 <&clk IMX8MP_CLK_ENET_REF>, 1387 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1388 clock-names = "ipg", "ahb", "ptp", 1389 "enet_clk_ref", "enet_out"; 1390 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1391 <&clk IMX8MP_CLK_ENET_TIMER>, 1392 <&clk IMX8MP_CLK_ENET_REF>, 1393 <&clk IMX8MP_CLK_ENET_PHY_REF>; 1394 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1395 <&clk IMX8MP_SYS_PLL2_100M>, 1396 <&clk IMX8MP_SYS_PLL2_125M>, 1397 <&clk IMX8MP_SYS_PLL2_50M>; 1398 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>; 1399 fsl,num-tx-queues = <3>; 1400 fsl,num-rx-queues = <3>; 1401 nvmem-cells = <ð_mac1>; 1402 nvmem-cell-names = "mac-address"; 1403 fsl,stop-mode = <&gpr 0x10 3>; 1404 status = "disabled"; 1405 }; 1406 1407 eqos: ethernet@30bf0000 { 1408 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; 1409 reg = <0x30bf0000 0x10000>; 1410 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 1411 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 1412 interrupt-names = "macirq", "eth_wake_irq"; 1413 clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, 1414 <&clk IMX8MP_CLK_QOS_ENET_ROOT>, 1415 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1416 <&clk IMX8MP_CLK_ENET_QOS>; 1417 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; 1418 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, 1419 <&clk IMX8MP_CLK_ENET_QOS_TIMER>, 1420 <&clk IMX8MP_CLK_ENET_QOS>; 1421 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, 1422 <&clk IMX8MP_SYS_PLL2_100M>, 1423 <&clk IMX8MP_SYS_PLL2_125M>; 1424 assigned-clock-rates = <0>, <100000000>, <125000000>; 1425 nvmem-cells = <ð_mac2>; 1426 nvmem-cell-names = "mac-address"; 1427 intf_mode = <&gpr 0x4>; 1428 status = "disabled"; 1429 }; 1430 }; 1431 1432 aips5: bus@30df0000 { 1433 compatible = "fsl,imx8mp-aipstz"; 1434 reg = <0x30df0000 0x10000>; 1435 power-domains = <&pgc_audio>; 1436 #address-cells = <1>; 1437 #size-cells = <1>; 1438 #access-controller-cells = <3>; 1439 ranges = <0x30c00000 0x30c00000 0x400000>; 1440 1441 spba-bus@30c00000 { 1442 compatible = "fsl,spba-bus", "simple-bus"; 1443 reg = <0x30c00000 0x100000>; 1444 #address-cells = <1>; 1445 #size-cells = <1>; 1446 ranges; 1447 1448 sai1: sai@30c10000 { 1449 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1450 reg = <0x30c10000 0x10000>; 1451 #sound-dai-cells = <0>; 1452 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_IPG>, 1453 <&clk IMX8MP_CLK_DUMMY>, 1454 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK1>, 1455 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK2>, 1456 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI1_MCLK3>; 1457 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1458 dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>; 1459 dma-names = "rx", "tx"; 1460 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 1461 status = "disabled"; 1462 }; 1463 1464 sai2: sai@30c20000 { 1465 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1466 reg = <0x30c20000 0x10000>; 1467 #sound-dai-cells = <0>; 1468 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_IPG>, 1469 <&clk IMX8MP_CLK_DUMMY>, 1470 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK1>, 1471 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK2>, 1472 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI2_MCLK3>; 1473 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1474 dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>; 1475 dma-names = "rx", "tx"; 1476 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1477 status = "disabled"; 1478 }; 1479 1480 sai3: sai@30c30000 { 1481 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1482 reg = <0x30c30000 0x10000>; 1483 #sound-dai-cells = <0>; 1484 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_IPG>, 1485 <&clk IMX8MP_CLK_DUMMY>, 1486 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK1>, 1487 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK2>, 1488 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI3_MCLK3>; 1489 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1490 dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>; 1491 dma-names = "rx", "tx"; 1492 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1493 status = "disabled"; 1494 }; 1495 1496 sai5: sai@30c50000 { 1497 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1498 reg = <0x30c50000 0x10000>; 1499 #sound-dai-cells = <0>; 1500 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_IPG>, 1501 <&clk IMX8MP_CLK_DUMMY>, 1502 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK1>, 1503 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK2>, 1504 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI5_MCLK3>; 1505 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1506 dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>; 1507 dma-names = "rx", "tx"; 1508 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1509 status = "disabled"; 1510 }; 1511 1512 sai6: sai@30c60000 { 1513 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1514 reg = <0x30c60000 0x10000>; 1515 #sound-dai-cells = <0>; 1516 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_IPG>, 1517 <&clk IMX8MP_CLK_DUMMY>, 1518 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK1>, 1519 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK2>, 1520 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI6_MCLK3>; 1521 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1522 dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>; 1523 dma-names = "rx", "tx"; 1524 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 1525 status = "disabled"; 1526 }; 1527 1528 sai7: sai@30c80000 { 1529 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai"; 1530 reg = <0x30c80000 0x10000>; 1531 #sound-dai-cells = <0>; 1532 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_IPG>, 1533 <&clk IMX8MP_CLK_DUMMY>, 1534 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK1>, 1535 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK2>, 1536 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SAI7_MCLK3>; 1537 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1538 dmas = <&sdma2 12 2 0>, <&sdma2 13 2 0>; 1539 dma-names = "rx", "tx"; 1540 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 1541 status = "disabled"; 1542 }; 1543 1544 easrc: easrc@30c90000 { 1545 compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc"; 1546 reg = <0x30c90000 0x10000>; 1547 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; 1548 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; 1549 clock-names = "mem"; 1550 dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, 1551 <&sdma2 18 23 0> , <&sdma2 19 23 0>, 1552 <&sdma2 20 23 0> , <&sdma2 21 23 0>, 1553 <&sdma2 22 23 0> , <&sdma2 23 23 0>; 1554 dma-names = "ctx0_rx", "ctx0_tx", 1555 "ctx1_rx", "ctx1_tx", 1556 "ctx2_rx", "ctx2_tx", 1557 "ctx3_rx", "ctx3_tx"; 1558 firmware-name = "imx/easrc/easrc-imx8mn.bin"; 1559 fsl,asrc-rate = <8000>; 1560 fsl,asrc-format = <2>; 1561 status = "disabled"; 1562 }; 1563 1564 micfil: audio-controller@30ca0000 { 1565 compatible = "fsl,imx8mp-micfil"; 1566 reg = <0x30ca0000 0x10000>; 1567 #sound-dai-cells = <0>; 1568 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1569 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1570 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1571 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1572 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>, 1573 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>, 1574 <&clk IMX8MP_AUDIO_PLL1_OUT>, 1575 <&clk IMX8MP_AUDIO_PLL2_OUT>, 1576 <&clk IMX8MP_CLK_EXT3>; 1577 clock-names = "ipg_clk", "ipg_clk_app", 1578 "pll8k", "pll11k", "clkext3"; 1579 dmas = <&sdma2 24 25 0x80000000>; 1580 dma-names = "rx"; 1581 status = "disabled"; 1582 }; 1583 1584 aud2htx: aud2htx@30cb0000 { 1585 compatible = "fsl,imx8mp-aud2htx"; 1586 reg = <0x30cb0000 0x10000>; 1587 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 1588 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUD2HTX_IPG>; 1589 clock-names = "bus"; 1590 dmas = <&sdma2 26 2 0>; 1591 dma-names = "tx"; 1592 status = "disabled"; 1593 }; 1594 1595 xcvr: xcvr@30cc0000 { 1596 compatible = "fsl,imx8mp-xcvr"; 1597 reg = <0x30cc0000 0x800>, 1598 <0x30cc0800 0x400>, 1599 <0x30cc0c00 0x080>, 1600 <0x30cc0e00 0x080>; 1601 reg-names = "ram", "regs", "rxfifo", 1602 "txfifo"; 1603 interrupts = /* XCVR IRQ 0 */ 1604 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 1605 /* XCVR IRQ 1 */ 1606 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 1607 /* XCVR PHY - SPDIF wakeup IRQ */ 1608 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 1609 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_IPG>, 1610 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_EARC_PHY>, 1611 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SPBA2_ROOT>, 1612 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_AUDPLL_ROOT>; 1613 clock-names = "ipg", "phy", "spba", "pll_ipg"; 1614 dmas = <&sdma2 30 2 0>, <&sdma2 31 2 0>; 1615 dma-names = "rx", "tx"; 1616 resets = <&audio_blk_ctrl 0>; 1617 status = "disabled"; 1618 }; 1619 }; 1620 1621 sdma3: dma-controller@30e00000 { 1622 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1623 reg = <0x30e00000 0x10000>; 1624 #dma-cells = <3>; 1625 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA3_ROOT>, 1626 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1627 clock-names = "ipg", "ahb"; 1628 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1629 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1630 }; 1631 1632 sdma2: dma-controller@30e10000 { 1633 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma"; 1634 reg = <0x30e10000 0x10000>; 1635 #dma-cells = <3>; 1636 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_SDMA2_ROOT>, 1637 <&clk IMX8MP_CLK_AUDIO_ROOT>; 1638 clock-names = "ipg", "ahb"; 1639 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1640 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin"; 1641 }; 1642 1643 audio_blk_ctrl: clock-controller@30e20000 { 1644 compatible = "fsl,imx8mp-audio-blk-ctrl"; 1645 reg = <0x30e20000 0x10000>; 1646 #clock-cells = <1>; 1647 #reset-cells = <1>; 1648 clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, 1649 <&clk IMX8MP_CLK_SAI1>, 1650 <&clk IMX8MP_CLK_SAI2>, 1651 <&clk IMX8MP_CLK_SAI3>, 1652 <&clk IMX8MP_CLK_SAI5>, 1653 <&clk IMX8MP_CLK_SAI6>, 1654 <&clk IMX8MP_CLK_SAI7>, 1655 <&clk IMX8MP_CLK_AUDIO_AXI_ROOT>; 1656 clock-names = "ahb", 1657 "sai1", "sai2", "sai3", 1658 "sai5", "sai6", "sai7", "axi"; 1659 power-domains = <&pgc_audio>; 1660 assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, 1661 <&clk IMX8MP_AUDIO_PLL2>; 1662 assigned-clock-rates = <393216000>, <361267200>; 1663 }; 1664 }; 1665 1666 noc: interconnect@32700000 { 1667 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc"; 1668 reg = <0x32700000 0x100000>; 1669 clocks = <&clk IMX8MP_CLK_NOC>; 1670 #interconnect-cells = <1>; 1671 operating-points-v2 = <&noc_opp_table>; 1672 1673 noc_opp_table: opp-table { 1674 compatible = "operating-points-v2"; 1675 1676 opp-200000000 { 1677 opp-hz = /bits/ 64 <200000000>; 1678 }; 1679 1680 /* Nominal drive mode maximum */ 1681 opp-800000000 { 1682 opp-hz = /bits/ 64 <800000000>; 1683 }; 1684 1685 /* Overdrive mode maximum */ 1686 opp-1000000000 { 1687 opp-hz = /bits/ 64 <1000000000>; 1688 }; 1689 }; 1690 }; 1691 1692 aips4: bus@32c00000 { 1693 compatible = "fsl,aips-bus", "simple-bus"; 1694 reg = <0x32c00000 0x400000>; 1695 #address-cells = <1>; 1696 #size-cells = <1>; 1697 ranges; 1698 1699 isi_0: isi@32e00000 { 1700 compatible = "fsl,imx8mp-isi"; 1701 reg = <0x32e00000 0x4000>; 1702 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 1703 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 1704 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1705 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1706 clock-names = "axi", "apb"; 1707 fsl,blk-ctrl = <&media_blk_ctrl>; 1708 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>; 1709 status = "disabled"; 1710 1711 ports { 1712 #address-cells = <1>; 1713 #size-cells = <0>; 1714 1715 port@0 { 1716 reg = <0>; 1717 1718 isi_in_0: endpoint { 1719 remote-endpoint = <&mipi_csi_0_out>; 1720 }; 1721 }; 1722 1723 port@1 { 1724 reg = <1>; 1725 1726 isi_in_1: endpoint { 1727 remote-endpoint = <&mipi_csi_1_out>; 1728 }; 1729 }; 1730 }; 1731 }; 1732 1733 isp_0: isp@32e10000 { 1734 compatible = "fsl,imx8mp-isp"; 1735 reg = <0x32e10000 0x10000>; 1736 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 1737 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1738 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1739 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1740 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>; 1741 clock-names = "isp", "aclk", "hclk", "pclk"; 1742 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>, 1743 <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; 1744 power-domain-names = "isp", "csi2"; 1745 fsl,blk-ctrl = <&media_blk_ctrl 0>; 1746 status = "disabled"; 1747 1748 ports { 1749 #address-cells = <1>; 1750 #size-cells = <0>; 1751 1752 port@1 { 1753 reg = <1>; 1754 }; 1755 }; 1756 }; 1757 1758 isp_1: isp@32e20000 { 1759 compatible = "fsl,imx8mp-isp"; 1760 reg = <0x32e20000 0x10000>; 1761 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1762 clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1763 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1764 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1765 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>; 1766 clock-names = "isp", "aclk", "hclk", "pclk"; 1767 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISP>, 1768 <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; 1769 power-domain-names = "isp", "csi2"; 1770 fsl,blk-ctrl = <&media_blk_ctrl 1>; 1771 status = "disabled"; 1772 1773 ports { 1774 #address-cells = <1>; 1775 #size-cells = <0>; 1776 1777 port@1 { 1778 reg = <1>; 1779 }; 1780 }; 1781 }; 1782 1783 dewarp: dwe@32e30000 { 1784 compatible = "nxp,imx8mp-dw100"; 1785 reg = <0x32e30000 0x10000>; 1786 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 1787 clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1788 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>; 1789 clock-names = "axi", "ahb"; 1790 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>; 1791 }; 1792 1793 mipi_csi_0: csi@32e40000 { 1794 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1795 reg = <0x32e40000 0x10000>; 1796 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1797 clock-frequency = <250000000>; 1798 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1799 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1800 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1801 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1802 clock-names = "pclk", "wrap", "phy", "axi"; 1803 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>, 1804 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1805 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, 1806 <&clk IMX8MP_CLK_24M>; 1807 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>; 1808 fsl,num-channels = <3>; 1809 status = "disabled"; 1810 1811 ports { 1812 #address-cells = <1>; 1813 #size-cells = <0>; 1814 1815 port@0 { 1816 reg = <0>; 1817 }; 1818 1819 port@1 { 1820 reg = <1>; 1821 1822 mipi_csi_0_out: endpoint { 1823 remote-endpoint = <&isi_in_0>; 1824 }; 1825 }; 1826 }; 1827 }; 1828 1829 mipi_csi_1: csi@32e50000 { 1830 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2"; 1831 reg = <0x32e50000 0x10000>; 1832 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 1833 clock-frequency = <250000000>; 1834 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1835 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1836 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>, 1837 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1838 clock-names = "pclk", "wrap", "phy", "axi"; 1839 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>, 1840 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1841 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_250M>, 1842 <&clk IMX8MP_CLK_24M>; 1843 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>; 1844 fsl,num-channels = <3>; 1845 status = "disabled"; 1846 1847 ports { 1848 #address-cells = <1>; 1849 #size-cells = <0>; 1850 1851 port@0 { 1852 reg = <0>; 1853 }; 1854 1855 port@1 { 1856 reg = <1>; 1857 1858 mipi_csi_1_out: endpoint { 1859 remote-endpoint = <&isi_in_1>; 1860 }; 1861 }; 1862 }; 1863 }; 1864 1865 mipi_dsi: dsi@32e60000 { 1866 compatible = "fsl,imx8mp-mipi-dsim"; 1867 reg = <0x32e60000 0x400>; 1868 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1869 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1870 clock-names = "bus_clk", "sclk_mipi"; 1871 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>, 1872 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF>; 1873 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, 1874 <&clk IMX8MP_CLK_24M>; 1875 assigned-clock-rates = <200000000>, <24000000>; 1876 samsung,pll-clock-frequency = <24000000>; 1877 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 1878 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>; 1879 status = "disabled"; 1880 1881 ports { 1882 #address-cells = <1>; 1883 #size-cells = <0>; 1884 1885 port@0 { 1886 reg = <0>; 1887 1888 dsim_from_lcdif1: endpoint { 1889 remote-endpoint = <&lcdif1_to_dsim>; 1890 }; 1891 }; 1892 1893 port@1 { 1894 reg = <1>; 1895 1896 mipi_dsi_out: endpoint { 1897 }; 1898 }; 1899 }; 1900 }; 1901 1902 lcdif1: display-controller@32e80000 { 1903 compatible = "fsl,imx8mp-lcdif"; 1904 reg = <0x32e80000 0x10000>; 1905 clocks = <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1906 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1907 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1908 clock-names = "pix", "axi", "disp_axi"; 1909 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1910 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>; 1911 status = "disabled"; 1912 1913 port { 1914 lcdif1_to_dsim: endpoint { 1915 remote-endpoint = <&dsim_from_lcdif1>; 1916 }; 1917 }; 1918 }; 1919 1920 lcdif2: display-controller@32e90000 { 1921 compatible = "fsl,imx8mp-lcdif"; 1922 reg = <0x32e90000 0x10000>; 1923 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1924 clocks = <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1925 <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1926 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>; 1927 clock-names = "pix", "axi", "disp_axi"; 1928 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>; 1929 status = "disabled"; 1930 1931 port { 1932 lcdif2_to_ldb: endpoint { 1933 remote-endpoint = <&ldb_from_lcdif2>; 1934 }; 1935 }; 1936 }; 1937 1938 media_blk_ctrl: blk-ctrl@32ec0000 { 1939 compatible = "fsl,imx8mp-media-blk-ctrl", 1940 "syscon"; 1941 reg = <0x32ec0000 0x10000>; 1942 #address-cells = <1>; 1943 #size-cells = <1>; 1944 power-domains = <&pgc_mediamix>, 1945 <&pgc_mipi_phy1>, 1946 <&pgc_mipi_phy1>, 1947 <&pgc_mediamix>, 1948 <&pgc_mediamix>, 1949 <&pgc_mipi_phy2>, 1950 <&pgc_mediamix>, 1951 <&pgc_ispdwp>, 1952 <&pgc_ispdwp>, 1953 <&pgc_mipi_phy2>; 1954 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1", 1955 "lcdif1", "isi", "mipi-csi2", 1956 "lcdif2", "isp", "dwe", 1957 "mipi-dsi2"; 1958 interconnects = 1959 <&noc IMX8MP_ICM_LCDIF_RD &noc IMX8MP_ICN_MEDIA>, 1960 <&noc IMX8MP_ICM_LCDIF_WR &noc IMX8MP_ICN_MEDIA>, 1961 <&noc IMX8MP_ICM_ISI0 &noc IMX8MP_ICN_MEDIA>, 1962 <&noc IMX8MP_ICM_ISI1 &noc IMX8MP_ICN_MEDIA>, 1963 <&noc IMX8MP_ICM_ISI2 &noc IMX8MP_ICN_MEDIA>, 1964 <&noc IMX8MP_ICM_ISP0 &noc IMX8MP_ICN_MEDIA>, 1965 <&noc IMX8MP_ICM_ISP1 &noc IMX8MP_ICN_MEDIA>, 1966 <&noc IMX8MP_ICM_DWE &noc IMX8MP_ICN_MEDIA>; 1967 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0", 1968 "isi1", "isi2", "isp0", "isp1", 1969 "dwe"; 1970 clocks = <&clk IMX8MP_CLK_MEDIA_APB_ROOT>, 1971 <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>, 1972 <&clk IMX8MP_CLK_MEDIA_CAM1_PIX_ROOT>, 1973 <&clk IMX8MP_CLK_MEDIA_CAM2_PIX_ROOT>, 1974 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX_ROOT>, 1975 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX_ROOT>, 1976 <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>, 1977 <&clk IMX8MP_CLK_MEDIA_MIPI_PHY1_REF_ROOT>; 1978 clock-names = "apb", "axi", "cam1", "cam2", 1979 "disp1", "disp2", "isp", "phy"; 1980 1981 /* 1982 * The ISP maximum frequency is 400MHz in normal mode 1983 * and 500MHz in overdrive mode. The 400MHz operating 1984 * point hasn't been successfully tested yet, so set 1985 * IMX8MP_CLK_MEDIA_ISP to 500MHz for the time being. 1986 */ 1987 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>, 1988 <&clk IMX8MP_CLK_MEDIA_APB>, 1989 <&clk IMX8MP_CLK_MEDIA_DISP1_PIX>, 1990 <&clk IMX8MP_CLK_MEDIA_DISP2_PIX>, 1991 <&clk IMX8MP_CLK_MEDIA_ISP>, 1992 <&clk IMX8MP_VIDEO_PLL1>; 1993 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 1994 <&clk IMX8MP_SYS_PLL1_800M>, 1995 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1996 <&clk IMX8MP_VIDEO_PLL1_OUT>, 1997 <&clk IMX8MP_SYS_PLL2_500M>; 1998 assigned-clock-rates = <500000000>, <200000000>, 1999 <0>, <0>, <500000000>, 2000 <1039500000>; 2001 #power-domain-cells = <1>; 2002 2003 lvds_bridge: bridge@5c { 2004 compatible = "fsl,imx8mp-ldb"; 2005 reg = <0x5c 0x4>, <0x128 0x4>; 2006 reg-names = "ldb", "lvds"; 2007 clocks = <&clk IMX8MP_CLK_MEDIA_LDB_ROOT>; 2008 clock-names = "ldb"; 2009 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>; 2010 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; 2011 status = "disabled"; 2012 2013 ports { 2014 #address-cells = <1>; 2015 #size-cells = <0>; 2016 2017 port@0 { 2018 reg = <0>; 2019 2020 ldb_from_lcdif2: endpoint { 2021 remote-endpoint = <&lcdif2_to_ldb>; 2022 }; 2023 }; 2024 2025 port@1 { 2026 reg = <1>; 2027 2028 ldb_lvds_ch0: endpoint { 2029 }; 2030 }; 2031 2032 port@2 { 2033 reg = <2>; 2034 2035 ldb_lvds_ch1: endpoint { 2036 }; 2037 }; 2038 }; 2039 }; 2040 }; 2041 2042 pcie_phy: pcie-phy@32f00000 { 2043 compatible = "fsl,imx8mp-pcie-phy"; 2044 reg = <0x32f00000 0x10000>; 2045 resets = <&src IMX8MP_RESET_PCIEPHY>, 2046 <&src IMX8MP_RESET_PCIEPHY_PERST>; 2047 reset-names = "pciephy", "perst"; 2048 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>; 2049 #phy-cells = <0>; 2050 status = "disabled"; 2051 }; 2052 2053 hsio_blk_ctrl: blk-ctrl@32f10000 { 2054 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon"; 2055 reg = <0x32f10000 0x24>; 2056 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2057 <&clk IMX8MP_CLK_PCIE_ROOT>; 2058 clock-names = "usb", "pcie"; 2059 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>, 2060 <&pgc_usb1_phy>, <&pgc_usb2_phy>, 2061 <&pgc_hsiomix>, <&pgc_pcie_phy>; 2062 power-domain-names = "bus", "usb", "usb-phy1", 2063 "usb-phy2", "pcie", "pcie-phy"; 2064 interconnects = <&noc IMX8MP_ICM_NOC_PCIE &noc IMX8MP_ICN_HSIO>, 2065 <&noc IMX8MP_ICM_USB1 &noc IMX8MP_ICN_HSIO>, 2066 <&noc IMX8MP_ICM_USB2 &noc IMX8MP_ICN_HSIO>, 2067 <&noc IMX8MP_ICM_PCIE &noc IMX8MP_ICN_HSIO>; 2068 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie"; 2069 #power-domain-cells = <1>; 2070 #clock-cells = <0>; 2071 }; 2072 2073 hdmi_blk_ctrl: blk-ctrl@32fc0000 { 2074 compatible = "fsl,imx8mp-hdmi-blk-ctrl", "syscon"; 2075 reg = <0x32fc0000 0x1000>; 2076 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2077 <&clk IMX8MP_CLK_HDMI_ROOT>, 2078 <&clk IMX8MP_CLK_HDMI_REF_266M>, 2079 <&clk IMX8MP_CLK_HDMI_24M>, 2080 <&clk IMX8MP_CLK_HDMI_FDCC_TST>; 2081 clock-names = "apb", "axi", "ref_266m", "ref_24m", "fdcc"; 2082 power-domains = <&pgc_hdmimix>, <&pgc_hdmimix>, 2083 <&pgc_hdmimix>, <&pgc_hdmimix>, 2084 <&pgc_hdmimix>, <&pgc_hdmimix>, 2085 <&pgc_hdmimix>, <&pgc_hdmi_phy>, 2086 <&pgc_hdmimix>, <&pgc_hdmimix>; 2087 power-domain-names = "bus", "irqsteer", "lcdif", 2088 "pai", "pvi", "trng", 2089 "hdmi-tx", "hdmi-tx-phy", 2090 "hdcp", "hrv"; 2091 interconnects = <&noc IMX8MP_ICM_HRV &noc IMX8MP_ICN_HDMI>, 2092 <&noc IMX8MP_ICM_LCDIF_HDMI &noc IMX8MP_ICN_HDMI>, 2093 <&noc IMX8MP_ICM_HDCP &noc IMX8MP_ICN_HDMI>; 2094 interconnect-names = "hrv", "lcdif-hdmi", "hdcp"; 2095 #power-domain-cells = <1>; 2096 }; 2097 2098 irqsteer_hdmi: interrupt-controller@32fc2000 { 2099 compatible = "fsl,imx8mp-irqsteer", "fsl,imx-irqsteer"; 2100 reg = <0x32fc2000 0x1000>; 2101 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 2102 interrupt-controller; 2103 #interrupt-cells = <1>; 2104 fsl,channel = <1>; 2105 fsl,num-irqs = <64>; 2106 clocks = <&clk IMX8MP_CLK_HDMI_APB>; 2107 clock-names = "ipg"; 2108 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_IRQSTEER>; 2109 }; 2110 2111 hdmi_pvi: display-bridge@32fc4000 { 2112 compatible = "fsl,imx8mp-hdmi-pvi"; 2113 reg = <0x32fc4000 0x800>; 2114 interrupt-parent = <&irqsteer_hdmi>; 2115 interrupts = <12>; 2116 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PVI>; 2117 status = "disabled"; 2118 2119 ports { 2120 #address-cells = <1>; 2121 #size-cells = <0>; 2122 2123 port@0 { 2124 reg = <0>; 2125 pvi_from_lcdif3: endpoint { 2126 remote-endpoint = <&lcdif3_to_pvi>; 2127 }; 2128 }; 2129 2130 port@1 { 2131 reg = <1>; 2132 pvi_to_hdmi_tx: endpoint { 2133 remote-endpoint = <&hdmi_tx_from_pvi>; 2134 }; 2135 }; 2136 }; 2137 }; 2138 2139 hdmi_pai: audio-bridge@32fc4800 { 2140 compatible = "fsl,imx8mp-hdmi-pai"; 2141 reg = <0x32fc4800 0x800>; 2142 interrupt-parent = <&irqsteer_hdmi>; 2143 interrupts = <14>; 2144 clocks = <&clk IMX8MP_CLK_HDMI_APB>; 2145 clock-names = "apb"; 2146 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PAI>; 2147 status = "disabled"; 2148 2149 port { 2150 pai_to_hdmi_tx: endpoint { 2151 remote-endpoint = <&hdmi_tx_from_pai>; 2152 }; 2153 }; 2154 }; 2155 2156 lcdif3: display-controller@32fc6000 { 2157 compatible = "fsl,imx8mp-lcdif"; 2158 reg = <0x32fc6000 0x1000>; 2159 interrupt-parent = <&irqsteer_hdmi>; 2160 interrupts = <8>; 2161 clocks = <&hdmi_tx_phy>, 2162 <&clk IMX8MP_CLK_HDMI_APB>, 2163 <&clk IMX8MP_CLK_HDMI_ROOT>; 2164 clock-names = "pix", "axi", "disp_axi"; 2165 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_LCDIF>; 2166 status = "disabled"; 2167 2168 port { 2169 lcdif3_to_pvi: endpoint { 2170 remote-endpoint = <&pvi_from_lcdif3>; 2171 }; 2172 }; 2173 }; 2174 2175 hdmi_tx: hdmi@32fd8000 { 2176 compatible = "fsl,imx8mp-hdmi-tx"; 2177 reg = <0x32fd8000 0x7eff>; 2178 interrupt-parent = <&irqsteer_hdmi>; 2179 interrupts = <0>; 2180 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2181 <&clk IMX8MP_CLK_HDMI_REF_266M>, 2182 <&clk IMX8MP_CLK_32K>, 2183 <&hdmi_tx_phy>; 2184 clock-names = "iahb", "isfr", "cec", "pix"; 2185 assigned-clocks = <&clk IMX8MP_CLK_HDMI_REF_266M>; 2186 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>; 2187 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX>; 2188 reg-io-width = <1>; 2189 status = "disabled"; 2190 2191 ports { 2192 #address-cells = <1>; 2193 #size-cells = <0>; 2194 2195 port@0 { 2196 reg = <0>; 2197 2198 hdmi_tx_from_pvi: endpoint { 2199 remote-endpoint = <&pvi_to_hdmi_tx>; 2200 }; 2201 }; 2202 2203 port@1 { 2204 reg = <1>; 2205 /* Point endpoint to the HDMI connector */ 2206 }; 2207 2208 port@2 { 2209 reg = <2>; 2210 2211 hdmi_tx_from_pai: endpoint { 2212 remote-endpoint = <&pai_to_hdmi_tx>; 2213 }; 2214 }; 2215 }; 2216 }; 2217 2218 hdmi_tx_phy: phy@32fdff00 { 2219 compatible = "fsl,imx8mp-hdmi-phy"; 2220 reg = <0x32fdff00 0x100>; 2221 clocks = <&clk IMX8MP_CLK_HDMI_APB>, 2222 <&clk IMX8MP_CLK_HDMI_24M>; 2223 clock-names = "apb", "ref"; 2224 assigned-clocks = <&clk IMX8MP_CLK_HDMI_24M>; 2225 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2226 power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_HDMI_TX_PHY>; 2227 #clock-cells = <0>; 2228 #phy-cells = <0>; 2229 status = "disabled"; 2230 }; 2231 }; 2232 2233 pcie0: pcie: pcie@33800000 { 2234 compatible = "fsl,imx8mp-pcie"; 2235 reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>; 2236 reg-names = "dbi", "config"; 2237 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2238 <&clk IMX8MP_CLK_HSIO_AXI>, 2239 <&clk IMX8MP_CLK_PCIE_ROOT>; 2240 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2241 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2242 assigned-clock-rates = <10000000>; 2243 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2244 #address-cells = <3>; 2245 #size-cells = <2>; 2246 device_type = "pci"; 2247 bus-range = <0x00 0xff>; 2248 ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000>, /* downstream I/O 64KB */ 2249 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */ 2250 num-lanes = <1>; 2251 num-viewport = <4>; 2252 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2253 interrupt-names = "msi"; 2254 #interrupt-cells = <1>; 2255 interrupt-map-mask = <0 0 0 0x7>; 2256 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 2257 <0 0 0 2 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 2258 <0 0 0 3 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 2259 <0 0 0 4 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; 2260 fsl,max-link-speed = <3>; 2261 linux,pci-domain = <0>; 2262 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2263 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2264 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2265 reset-names = "apps", "turnoff"; 2266 phys = <&pcie_phy>; 2267 phy-names = "pcie-phy"; 2268 status = "disabled"; 2269 }; 2270 2271 pcie0_ep: pcie_ep: pcie-ep@33800000 { 2272 compatible = "fsl,imx8mp-pcie-ep"; 2273 reg = <0x33800000 0x100000>, 2274 <0x18000000 0x8000000>, 2275 <0x33900000 0x100000>, 2276 <0x33b00000 0x100000>; 2277 reg-names = "dbi", "addr_space", "dbi2", "atu"; 2278 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2279 <&clk IMX8MP_CLK_HSIO_AXI>, 2280 <&clk IMX8MP_CLK_PCIE_ROOT>; 2281 clock-names = "pcie", "pcie_bus", "pcie_aux"; 2282 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>; 2283 assigned-clock-rates = <10000000>; 2284 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>; 2285 num-lanes = <1>; 2286 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */ 2287 interrupt-names = "dma"; 2288 fsl,max-link-speed = <3>; 2289 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>; 2290 resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>, 2291 <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>; 2292 reset-names = "apps", "turnoff"; 2293 phys = <&pcie_phy>; 2294 phy-names = "pcie-phy"; 2295 num-ib-windows = <4>; 2296 num-ob-windows = <4>; 2297 status = "disabled"; 2298 }; 2299 2300 gpu3d: gpu@38000000 { 2301 compatible = "vivante,gc"; 2302 reg = <0x38000000 0x8000>; 2303 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 2304 clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>, 2305 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>, 2306 <&clk IMX8MP_CLK_GPU_ROOT>, 2307 <&clk IMX8MP_CLK_GPU_AHB>; 2308 clock-names = "core", "shader", "bus", "reg"; 2309 #cooling-cells = <2>; 2310 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>, 2311 <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>; 2312 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>, 2313 <&clk IMX8MP_SYS_PLL2_1000M>; 2314 assigned-clock-rates = <1000000000>, <1000000000>; 2315 power-domains = <&pgc_gpu3d>; 2316 }; 2317 2318 gpu2d: gpu@38008000 { 2319 compatible = "vivante,gc"; 2320 reg = <0x38008000 0x8000>; 2321 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2322 clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>, 2323 <&clk IMX8MP_CLK_GPU_ROOT>, 2324 <&clk IMX8MP_CLK_GPU_AHB>; 2325 clock-names = "core", "bus", "reg"; 2326 #cooling-cells = <2>; 2327 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>; 2328 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>; 2329 assigned-clock-rates = <1000000000>; 2330 power-domains = <&pgc_gpu2d>; 2331 }; 2332 2333 vpu_g1: video-codec@38300000 { 2334 compatible = "nxp,imx8mm-vpu-g1"; 2335 reg = <0x38300000 0x10000>; 2336 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 2337 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>; 2338 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>; 2339 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 2340 assigned-clock-rates = <800000000>; 2341 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>; 2342 }; 2343 2344 vpu_g2: video-codec@38310000 { 2345 compatible = "nxp,imx8mq-vpu-g2"; 2346 reg = <0x38310000 0x10000>; 2347 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 2348 clocks = <&clk IMX8MP_CLK_VPU_G2_ROOT>; 2349 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>, <&clk IMX8MP_VPU_PLL_OUT>; 2350 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>; 2351 assigned-clock-rates = <700000000>, <700000000>; 2352 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>; 2353 }; 2354 2355 vpumix_blk_ctrl: blk-ctrl@38330000 { 2356 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon"; 2357 reg = <0x38330000 0x100>; 2358 #power-domain-cells = <1>; 2359 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>, 2360 <&pgc_vpu_g2>, <&pgc_vpu_vc8000e>; 2361 power-domain-names = "bus", "g1", "g2", "vc8000e"; 2362 clocks = <&clk IMX8MP_CLK_VPU_G1_ROOT>, 2363 <&clk IMX8MP_CLK_VPU_G2_ROOT>, 2364 <&clk IMX8MP_CLK_VPU_VC8KE_ROOT>; 2365 clock-names = "g1", "g2", "vc8000e"; 2366 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>; 2367 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>; 2368 assigned-clock-rates = <800000000>; 2369 interconnects = <&noc IMX8MP_ICM_VPU_G1 &noc IMX8MP_ICN_VIDEO>, 2370 <&noc IMX8MP_ICM_VPU_G2 &noc IMX8MP_ICN_VIDEO>, 2371 <&noc IMX8MP_ICM_VPU_H1 &noc IMX8MP_ICN_VIDEO>; 2372 interconnect-names = "g1", "g2", "vc8000e"; 2373 }; 2374 2375 npu: npu@38500000 { 2376 compatible = "vivante,gc"; 2377 reg = <0x38500000 0x200000>; 2378 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 2379 clocks = <&clk IMX8MP_CLK_NPU_ROOT>, 2380 <&clk IMX8MP_CLK_NPU_ROOT>, 2381 <&clk IMX8MP_CLK_ML_AXI>, 2382 <&clk IMX8MP_CLK_ML_AHB>; 2383 clock-names = "core", "shader", "bus", "reg"; 2384 #cooling-cells = <2>; 2385 power-domains = <&pgc_mlmix>; 2386 }; 2387 2388 gic: interrupt-controller@38800000 { 2389 compatible = "arm,gic-v3"; 2390 reg = <0x38800000 0x10000>, 2391 <0x38880000 0xc0000>; 2392 #address-cells = <0>; 2393 #interrupt-cells = <3>; 2394 interrupt-controller; 2395 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 2396 interrupt-parent = <&gic>; 2397 }; 2398 2399 edacmc: memory-controller@3d400000 { 2400 compatible = "snps,ddrc-3.80a"; 2401 reg = <0x3d400000 0x400000>; 2402 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 2403 }; 2404 2405 ddr-pmu@3d800000 { 2406 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu"; 2407 reg = <0x3d800000 0x400000>; 2408 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 2409 }; 2410 2411 usb3_phy0: usb-phy@381f0040 { 2412 compatible = "fsl,imx8mp-usb-phy"; 2413 reg = <0x381f0040 0x40>; 2414 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2415 clock-names = "phy"; 2416 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2417 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2418 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>; 2419 #phy-cells = <0>; 2420 status = "disabled"; 2421 }; 2422 2423 usb3_0: usb@32f10100 { 2424 compatible = "fsl,imx8mp-dwc3"; 2425 reg = <0x32f10100 0x8>, 2426 <0x381f0000 0x20>; 2427 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2428 <&clk IMX8MP_CLK_USB_SUSP>; 2429 clock-names = "hsio", "suspend"; 2430 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 2431 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2432 #address-cells = <1>; 2433 #size-cells = <1>; 2434 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2435 ranges; 2436 status = "disabled"; 2437 2438 usb_dwc3_0: usb@38100000 { 2439 compatible = "snps,dwc3"; 2440 reg = <0x38100000 0x10000>; 2441 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2442 <&clk IMX8MP_CLK_USB_CORE_REF>, 2443 <&clk IMX8MP_CLK_USB_SUSP>; 2444 clock-names = "bus_early", "ref", "suspend"; 2445 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 2446 phys = <&usb3_phy0>, <&usb3_phy0>; 2447 phy-names = "usb2-phy", "usb3-phy"; 2448 snps,gfladj-refclk-lpm-sel-quirk; 2449 snps,parkmode-disable-ss-quirk; 2450 }; 2451 2452 }; 2453 2454 usb3_phy1: usb-phy@382f0040 { 2455 compatible = "fsl,imx8mp-usb-phy"; 2456 reg = <0x382f0040 0x40>; 2457 clocks = <&clk IMX8MP_CLK_USB_PHY_ROOT>; 2458 clock-names = "phy"; 2459 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>; 2460 assigned-clock-parents = <&clk IMX8MP_CLK_24M>; 2461 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>; 2462 #phy-cells = <0>; 2463 status = "disabled"; 2464 }; 2465 2466 usb3_1: usb@32f10108 { 2467 compatible = "fsl,imx8mp-dwc3"; 2468 reg = <0x32f10108 0x8>, 2469 <0x382f0000 0x20>; 2470 clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, 2471 <&clk IMX8MP_CLK_USB_SUSP>; 2472 clock-names = "hsio", "suspend"; 2473 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 2474 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>; 2475 #address-cells = <1>; 2476 #size-cells = <1>; 2477 dma-ranges = <0x40000000 0x40000000 0xc0000000>; 2478 ranges; 2479 status = "disabled"; 2480 2481 usb_dwc3_1: usb@38200000 { 2482 compatible = "snps,dwc3"; 2483 reg = <0x38200000 0x10000>; 2484 clocks = <&clk IMX8MP_CLK_USB_ROOT>, 2485 <&clk IMX8MP_CLK_USB_CORE_REF>, 2486 <&clk IMX8MP_CLK_USB_SUSP>; 2487 clock-names = "bus_early", "ref", "suspend"; 2488 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 2489 phys = <&usb3_phy1>, <&usb3_phy1>; 2490 phy-names = "usb2-phy", "usb3-phy"; 2491 snps,gfladj-refclk-lpm-sel-quirk; 2492 snps,parkmode-disable-ss-quirk; 2493 }; 2494 }; 2495 2496 dsp: dsp@3b6e8000 { 2497 compatible = "fsl,imx8mp-hifi4"; 2498 reg = <0x3b6e8000 0x88000>; 2499 clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, 2500 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_OCRAMA_IPG>, 2501 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSP_ROOT>, 2502 <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_DSPDBG_ROOT>; 2503 clock-names = "ipg", "ocram", "core", "debug"; 2504 power-domains = <&pgc_audio>; 2505 mbox-names = "tx", "rx", "rxdb"; 2506 mboxes = <&mu2 0 0>, <&mu2 1 0>, <&mu2 3 0>; 2507 firmware-name = "imx/dsp/hifi4.bin"; 2508 resets = <&audio_blk_ctrl IMX8MP_AUDIOMIX_DSP_RUNSTALL>; 2509 reset-names = "runstall"; 2510 access-controllers = <&aips5 2511 IMX8MP_AIPSTZ_HIFI4 2512 IMX8MP_AIPSTZ_MASTER 2513 (IMX8MP_AIPSTZ_MPL | IMX8MP_AIPSTZ_MTW | IMX8MP_AIPSTZ_MTR) 2514 >; 2515 status = "disabled"; 2516 }; 2517 }; 2518};
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